WO2015100859A1 - 阵列基板及其制造方法和显示装置 - Google Patents

阵列基板及其制造方法和显示装置 Download PDF

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Publication number
WO2015100859A1
WO2015100859A1 PCT/CN2014/074032 CN2014074032W WO2015100859A1 WO 2015100859 A1 WO2015100859 A1 WO 2015100859A1 CN 2014074032 W CN2014074032 W CN 2014074032W WO 2015100859 A1 WO2015100859 A1 WO 2015100859A1
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Prior art keywords
gate insulating
film
insulating layer
layer
thin film
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PCT/CN2014/074032
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English (en)
French (fr)
Inventor
袁广才
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/422,321 priority Critical patent/US9812541B2/en
Publication of WO2015100859A1 publication Critical patent/WO2015100859A1/zh

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Definitions

  • Embodiments of the present invention relate to the field of display technologies, and in particular, to an array substrate, a manufacturing method thereof, and a display device. Background technique
  • display technology has been rapidly developed, such as the development of thin film transistor technology from the original a-Si (amorphous silicon) thin film transistor to the current LTPS (low temperature polysilicon) thin film transistor, MILC (metal induced lateral crystallization) thin film transistor, Oxide (oxide) thin film transistor, etc.
  • the light-emitting technology has also evolved from the original LCD (liquid crystal display), PDP (plasma display) to the current OLED (organic light-emitting diode), AMOLED (active matrix organic light-emitting diode) and so on.
  • Organic light-emitting displays are a new generation of display devices.
  • liquid crystal displays Compared with liquid crystal displays, they have many advantages, such as spontaneous light, fast response, wide viewing angle, etc., which can be used for flexible display, transparent display, 3D (3D stereo) display, etc.
  • the liquid crystal display or the organic light emitting display it is necessary to provide each of the pixels with a switching device for controlling the pixel, so that each pixel can be independently controlled by the driving circuit without causing crosstalk to other pixels. And so on.
  • Oxide thin film transistors using an oxide semiconductor as an active layer have advantages of high mobility, high on-state current, and superior switching characteristics, and are therefore widely used in applications requiring fast response and large current, such as high frequency, high resolution. Rate, large size display, and organic light emitting display.
  • the existing Oxide thin film transistor fabrication method generally includes six patterning processes for forming a gate line and a gate, a gate insulating layer, an active layer, an etch stop layer, a source drain, a passivation layer, and a pass. hole.
  • the six-time mask exposure process results in unstable performance of the thin film transistor, a long fabrication cycle, and a corresponding increase in manufacturing cost. Summary of the invention
  • Embodiments of the present invention provide an array substrate capable of effectively reducing cost, simplifying processes, and improving stability of a thin film transistor, a manufacturing method thereof, and a display device.
  • an array substrate that includes a first thin film transistor and an image Prime electrode, the method includes:
  • An active layer film, a source/drain metal film, and a transparent electrode layer are deposited on the substrate on which the buffer layer is formed, and a pattern of the active layer, the source and drain electrodes, and the pixel electrode in the first thin film transistor is formed by one patterning process.
  • an array substrate prepared by the above manufacturing method comprising: a substrate, wherein the substrate is provided with a buffer layer, an active layer, a source/drain electrode, a pixel electrode, a gate insulating layer, and a gate a layer; the source/drain electrode and the pixel electrode are in direct contact.
  • a display device comprising the above array substrate.
  • 1 to 9 are steps of a method for fabricating an array substrate according to an embodiment of the present invention, which is illustrated by cutting the array substrate along lines A-A and B-B of FIG. 10;
  • FIG. 10 is a schematic plan view showing the structure of an array substrate according to an embodiment of the present invention.
  • Figure 11 is an equivalent circuit diagram of the array substrate of Figure 10. detailed description
  • Embodiments of the present invention provide a method for fabricating an array substrate, which includes a thin film crystal Tube and pixel electrodes, including:
  • a semiconductor material, a source/drain metal material, and a transparent electrode layer are deposited on the buffer layer substrate, and a pattern of the active layer, the source and drain electrodes, and the pixel electrode in the thin film transistor is formed by one patterning process.
  • the active layer, the source and drain electrodes and the pixel electrode are completed by one patterning process, which can greatly shorten the fabrication cycle of the thin film transistor, and at the same time, the stability and reliability of the thin film transistor can be effectively improved due to the relatively small number of process steps, so that the film
  • the threshold voltage of the transistor does not drift greatly, and the yield of the product can be improved, the manufacturing cost can be reduced, and the lifetime of the device can be made longer.
  • the array substrate produced by this manufacturing method is suitable for a top gate type LCD display device.
  • an embodiment of the present invention further provides a method for fabricating an array substrate suitable for a top gate type OLED structure.
  • an OLED (Organic Light Emitting Diode) array substrate includes two thin film transistors to illustrate a method for fabricating the array substrate.
  • the array substrate includes a first thin film transistor, a second thin film transistor, and a pixel electrode.
  • the active layer and the source/drain electrodes in both the first thin film transistor and the second thin film transistor are formed by one patterning process.
  • the patterning process referred to in the present invention includes processes such as photoresist coating, exposure, etching, and photoresist stripping.
  • the photoresist is exemplified by a positive photoresist.
  • Embodiments of the present invention provide a method for fabricating a top gate array substrate, including:
  • Step 1 A buffer layer 322 is formed on the substrate 321 , and the buffer layer 322 can effectively prevent adverse effects on the device due to direct contact between the glass substrate and the semiconductor layer.
  • Step 2 depositing an active layer film, a source/drain metal film, and a transparent electrode layer on the substrate on which the above steps are performed, forming an active layer, a source/drain electrode, and a pixel electrode in the first thin film transistor by one patterning process pattern.
  • the pattern of the active layer includes a pattern of the intrinsic semiconductor layer and/or a pattern of the doped semiconductor layer, and the active layer includes the pattern of the intrinsic semiconductor layer and the doped semiconductor layer in the drawing showing the present step.
  • the pattern of the two is taken as an example.
  • step 2 may further include: Step 201, depositing an intrinsic semiconductor material layer 323, a doped semiconductor material layer 324 (the intrinsic semiconductor layer 323, the doped semiconductor layer 324 constitutes an active layer film), a source/drain metal film 325, and a transparent layer on the substrate on which the step 1 is completed. Electrode layer 326, see Figure 1.
  • Step 202 coating a photoresist 327 on the transparent electrode layer 326.
  • Step 203 Exposing and developing the photoresist by a two-tone mask process to form a photoresist completely reserved region, a photoresist portion remaining region, and a photoresist completely removed region, wherein the first thin film transistor drain and a connection region of the gate of the second thin film transistor (see the A region in FIG. 9), a data line and a power supply line region (not shown;), source and drain electrodes of the first thin film transistor and the second thin film transistor (see FIG. 9 The B region) and the pixel electrode region (see the D region in FIG. 9) are completely reserved regions of the photoresist;
  • the first channel region of the first thin film transistor and the second channel region of the second thin film transistor are portions of the resist portion reserved;
  • Step 204 removing the transparent electrode layer, the source/drain metal film, and the active layer film corresponding to the completely removed region of the photoresist by the first etching process, that is, etching to the buffer layer 322; refer to FIG.
  • Step 205 removing the photoresist corresponding to the partially reserved region by an ashing process to form a first channel region and a second channel region; refer to FIG. 5.
  • Step 206 Remove the pixel electrode layer 326 and the source/drain metal film 325 and the doped semiconductor layer 324 corresponding to the remaining portion of the photoresist portion by a second etching process.
  • the active layer is only one layer in actual production, that is, only the intrinsic semiconductor layer 323 is included, only the pixel electrode layer 326 and the source/drain metal film 325 need to be removed, refer to FIG. 5.
  • Step 207 stripping the residual photoresist, forming a pattern of a connection region of the drain of the first thin film transistor and the gate of the second thin film transistor, a pattern of the data line and the power line region, and source and drain of the first thin film transistor and the second thin film transistor.
  • the pattern of the poles and the pattern of the pixel electrode regions; continue to refer to FIG.
  • the intrinsic semiconductor layer can be, for example, IGZO, ITZO, IZO, Cu20, GZO, AZO, HfIZO,
  • the doped semiconductor layer may be, for example, one or more of amorphous silicon, polycrystalline silicon, and microcrystalline silicon materials.
  • the oxide semiconductor when the active layer is made of an oxide semiconductor material, the oxide semiconductor may be subjected to plasma treatment of different atmospheres, such as oxygen, argon, nitrogen monoxide, hydrogen; or may be oxidized a gas whose surface is modified by a semiconductor, such as a hydrogen plasma The semiconductor material is etched in the air.
  • different atmospheres such as oxygen, argon, nitrogen monoxide, hydrogen
  • a semiconductor such as a hydrogen plasma
  • the oxide semiconductor layer may be annealed, and the annealing temperature is
  • the annealing environment is air, oxygen, nitrogen, air containing 1-10% water vapor or oxygen containing 1-10% water vapor.
  • Step 3 Form a gate insulating layer 328 on the substrate on which the step 2 is completed, and form a via hole by a patterning process; refer to FIG.
  • the gate insulating layer may be, for example, a layer, and the gate insulating layer may be a silicon oxide film, an aluminum oxide film, a titanium oxide film, a zirconia film, a hafnium oxide film, a barium titanate film, a hafnium oxide film, or a silicon oxynitride film. a film, an aluminum oxynitride film, a zirconium oxynitride film, a hafnium oxynitride film, a hafnium oxynitride film, a silicon nitride film, an aluminum nitride film, a zirconium nitride film, and a tantalum nitride film;
  • the gate insulating layer is two layers, that is, includes a first gate insulating layer and a second gate insulating layer, the first gate insulating layer is adjacent to the gate layer, and the second gate insulating layer is adjacent to the active layer
  • the first gate insulating layer pattern is made of a silicon oxynitride film, an aluminum oxynitride film, a zirconium oxynitride film, a hafnium oxynitride film, a hafnium oxynitride film, a silicon nitride film, an aluminum nitride film, or a zirconium nitride film.
  • the second gate insulating layer using a silicon oxide film, an aluminum oxide film, a titanium oxide film, a silicon oxynitride film, a zirconia film, a hafnium oxide film, a barium titanate film, and oxidation One of the enamel films; or
  • the gate insulating layer is three layers, including a third gate insulating layer, a fourth gate insulating layer and a fifth gate insulating layer, the third gate insulating layer is adjacent to the gate layer, and the fifth gate insulating layer
  • the layer is adjacent to the active layer
  • the fourth gate insulating layer is located between the third gate insulating layer and the fifth gate insulating layer
  • the third gate insulating layer is made of a silicon nitride film, an aluminum nitride film, and a zirconium nitride
  • the fourth gate insulating layer is one of a silicon oxynitride film, an aluminum oxynitride film, a zirconium oxynitride film, a hafnium oxynitride film, and a hafnium oxynitride film
  • the fifth gate insulating layer pattern is one of a silicon oxide film, an aluminum oxide film,
  • the gate insulating layer of the different layers may be subjected to an annealing process, and the specific annealing process includes: adding a nitrogen or air to the heating chamber of the PECVD device to perform a dehydrogenation process on the first gate insulating layer;
  • the heating chamber temperature is 200 ° C ⁇ 350 ° C, and the annealing time is 15 minutes - 90 minutes.
  • Step 4 forming a first thin film transistor and a second thin film transistor by one patterning process The pattern of the gate and gate lines.
  • a gate metal material 329 is deposited on the substrate on which the step 3 is completed, and gate lines and gate lines of the first thin film transistor and the second thin film transistor are formed by a patterning process.
  • the pixel is removed.
  • the gate above the electrode region prevents the gate from being short-circuited with the pixel electrode, thereby completing the main structure of the array substrate.
  • a gate electrode protection layer 330 may be formed on the substrate of the step 4, and the gate electrode protection layer 330 is generally coated with a corrosion-resistant, anti-friction conductive film, such as germanium, germanium. , ⁇ and other films and conductive films similar in nature.
  • a corrosion-resistant, anti-friction conductive film such as germanium, germanium. , ⁇ and other films and conductive films similar in nature.
  • the gate metal is made of a relatively wear-resistant, hard metal film, the gate electrode protection layer 330 can be omitted.
  • the etching process involved in the above steps may be wet etching, dry etching or dry wet bonding etching.
  • FIG. 10 is a schematic plan view showing the structure of an array substrate according to an embodiment of the present invention, which reflects the structure of one pixel unit
  • FIG. 11 is an equivalent circuit diagram of the array substrate of FIG. 10, and FIG.
  • a cross-sectional view of the array substrate along the ⁇ - ⁇ line and the ⁇ - ⁇ line in 10 (the left-hand side is along the ⁇ - ⁇ line, and the right-hand side is along the ⁇ - ⁇ line).
  • This embodiment takes an OLED (Organic Light Emitting Diode) array substrate as an example.
  • the array substrate includes an active layer, a data line 14, a power line 12 and a gate line 11, a data line 14 and a power line 12 and a gate line.
  • a first thin film transistor also referred to as a switching thin film transistor
  • a control unit for controlling the organic light emitting diode is further included.
  • a second thin film transistor also called a driving thin film transistor
  • a pixel electrode is perpendicular, and defines a pixel area together with two adjacent gate lines, wherein a first thin film transistor (also referred to as a switching thin film transistor) as an address element is formed in the pixel area, and a control unit for controlling the organic light emitting diode.
  • a second thin film transistor also called a driving thin film transistor
  • pixel electrode also called a driving thin film transistor
  • the first thin film transistor is located at a point where the gate line 11 and the data line 14 intersect, and the second thin film transistor is located at a position where the gate line 11 and the power line 12 intersect, wherein the first drain 151 and the second gate of the first thin film transistor 162 connected.
  • the array substrate includes, for example, a substrate having a pattern of a buffer layer, an active layer, a source/drain electrode, a pixel electrode layer, a gate insulating layer, and a gate electrode, and the source/drain electrode layer and the pixel electrode layer are in direct contact.
  • the active layer includes a first active layer 171 of the first thin film transistor and a second active layer 172 of the second thin film transistor.
  • the source/drain electrode layer includes a first source 152 of the first thin film transistor, a first drain 151, and a second source 153 and a second drain 154 of the second thin film transistor.
  • a via hole is formed in the gate insulating layer, and the first drain electrode 151 of the first thin film transistor is connected to the second gate electrode 162 of the second thin film transistor through the via hole.
  • a gate layer is disposed on the gate insulating layer, the gate layer includes a first gate 161 of the first thin film transistor and a second gate 162 of the second thin film transistor; the first gate 161 and the second gate 162, the gate Line 11 is completed by a patterning process.
  • the first gate 161 is connected to the gate line 11, and the second gate 162 is not connected to the gate line 11, and the first gate 161 and the second gate 162 are not connected to each other.
  • the gate metal material layer and the source/drain metal layer in this embodiment are both single layers, and the material thereof may be a metal or an alloy such as at least one of Cu, Mo, Al, Nd, Ti and alloys thereof.
  • the source and the drain of the thin film transistor vary depending on the direction in which the current flows.
  • the drain connected to the pixel electrode is referred to as a drain.
  • the channel region is a void region between the source electrode and the drain electrode.
  • the gate insulating layer may be, for example, a layer, and the specific material is the same as that in the first embodiment.
  • the gate insulating layer may be annealed (ie, the gate insulating layer). For the insulating layer treated by the annealing process, the effect of the complex of hydrogen and hydrogen in the gate insulating layer on the characteristics of the oxide semiconductor is reduced.
  • the gate insulating layer may be two layers, that is, including a first gate insulating layer and a second gate insulating layer, the first gate insulating layer being close to the gate, and the second gate insulating layer being close to the active layer.
  • the specific materials of the first and second gate insulating layers are the same as those in the first embodiment.
  • the first gate insulating layer and/or the second gate insulating layer is an insulating layer treated by an annealing process.
  • the first gate insulating material can well contain the adverse effects of the gate electrode, especially when copper or copper alloy is used.
  • the function of the second gate insulating layer is to achieve a good match with the oxide semiconductor to improve the performance of the device.
  • the material of the second gate insulating layer is mostly an oxide insulating layer, its ability to prevent diffusion of H+, OH- and the like is relatively poor, so when the first gate insulating layer is formed, it is preferably required.
  • the annealing process is performed to reduce the breakage that may occur in the first gate insulating layer due to the diffusion of groups such as H+, OH-, etc., thereby achieving the effect of improving device stability.
  • the gate insulating layer is three layers, that is, includes a third gate insulating layer, a fourth gate insulating layer, and a fifth gate insulating layer, wherein the third gate insulating layer is adjacent to the gate, and the fifth gate insulating layer Adjacent to the active layer, the fourth gate insulating layer is between the third gate insulating layer and the fifth gate insulating layer.
  • Second, third, fourth grid The specific material of the insulating layer is the same as that in the first embodiment.
  • the third gate insulating layer is made of an inorganic insulating material such as a silicon nitride film. Since the material directly contacts the oxide semiconductor layer, the performance of the oxide semiconductor layer is lowered, but it can be better. The containment is inconsistent with the contact of the gate metal (especially when copper and its alloy are used as the gate), so that the first gate insulating layer is disposed in close contact with the gate and away from the active layer.
  • the fourth gate insulating layer is disposed on the intermediate layer, and the fourth gate insulating layer made of an inorganic insulating material such as a silicon oxynitride film itself has less H+, OH-, etc.
  • the fifth gate insulating layer is closely adhered to the oxide semiconductor, so that the matching with the oxide semiconductor can be better achieved, thereby improving the stability of the device.
  • the method for fabricating two thin film transistors in this embodiment is also applicable to a method of fabricating only one thin film transistor or a plurality of thin film transistor array substrates.
  • Embodiments of the present invention also provide a display device including the above array substrate.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any display product or component.
  • the fabrication cycle of the thin film transistor is greatly shortened, the stability of the thin film transistor is improved, and the threshold voltage of the thin film transistor is not greatly drifted. Improve product yield and extend device life.

Abstract

一种阵列基板的制作方法，所述阵列基板包括第一薄膜晶体管和像素电极，该方法包括：在基板（321）上形成缓冲层（322），在形成有缓冲层（322）的基板（321）上沉积有源层薄膜（323，324）和透明电极层（326），并且通过一次构图工艺形成所述第一薄膜晶体管中有源层（171）、源漏电极（152，151）以及像素电极的图案。利用该制造方法制备的阵列基板及其显示装置。通过上述制作方法，大大缩短了薄膜晶体管的制作周期，提高了薄膜晶体管的稳定性，使得薄膜晶体管的阈值电压不会发生较大的漂移，同时可提高产品的良率，延长了器件的使用寿命。

Description

阵列基板及其制造方法和显示装置 技术领域
本发明实施例涉及显示技术领域， 尤其涉及一种阵列基板及其制作方法 和显示装置。 背景技术
近年来，显示技术得到快速的发展，如薄膜晶体管技术由原来的 a-Si (非 晶硅）薄膜晶体管发展到现在的 LTPS (低温多晶硅）薄膜晶体管、 MILC (金 属诱导横向晶化）薄膜晶体管、 Oxide (氧化物）薄膜晶体管等。 而发光技术 也由原来的 LCD (液晶显示器）、 PDP (等离子显示屏）发展为现在的 OLED (有机发光二极管）、 AMOLED (主动式矩阵有机发光二极管）等。 有机发 光显示器是新一代的显示器件， 与液晶显示器相比， 具有很多优点， 如自发 光， 响应速度快， 宽视角等等， 可以用于柔性显示， 透明显示， 3D (三维立 体）显示等。 但无论液晶显示还是有机发光显示， 都需要为它们中的每一个 像素配备用于控制该像素的开关装置一薄膜晶体管， 从而可以通过驱动电路 独立控制每一个像素， 而不会对其他像素造成串扰等影响。
釆用氧化物半导体作为有源层的 Oxide薄膜晶体管具有迁移率大、 开态 电流高、 开关特性更优的优点， 因此广泛应用于需要快速响应和较大电流的 应用， 如高频、 高分辨率、 大尺寸的显示器以及有机发光显示器等。
然而， 现有 Oxide薄膜晶体管的制作方法通常包括六次构图工艺， 分别 用于形成栅线及栅极， 栅极绝缘层、 有源层， 刻蚀阻挡层， 源漏极， 钝化层 及过孔。 通过六次 mask曝光工艺会导致薄膜晶体管性能不稳定、 制作周期 较长， 并且导致制作成本相应增加。 发明内容
本发明实施例提供了一种能够有效降低成本、 简化工艺并且提高薄膜晶 体管的稳定性的阵列基板及其制作方法和显示装置。
根据本发明的一方面， 提供一种所述阵列基板包括第一薄膜晶体管和像 素电极， 该方法包括：
在基板上形成緩冲层； 以及
在形成有緩冲层的基板上沉积有源层薄膜、源漏金属薄膜和透明电极层， 并且通过一次构图工艺形成所述第一薄膜晶体管中有源层、 源漏电极以及像 素电极的图案。
根据本发明的再一方面， 还提供一种上述制造方法制备的阵列基板， 包 括基板， 所述基板上设有緩冲层、 有源层、 源漏电极、 像素电极、 栅绝缘层、 栅极层； 所述源漏电极和像素电极直接接触。
根据本发明的又一方面， 还提供一种显示装置， 包括上述的阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1~9为以沿图 10中 A-A线和 B-B线剖切阵列基板的方式所示意的本 发明实施例的阵列基板制作方法的各个步骤；
图 10为本发明实施例阵列基板结构的平面示意图；
图 11为图 10阵列基板的等效电路图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图， 对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一"、 "第二" 以及类似的词语并不表示任何顺序、 数 量或者重要性， 而只是用来区分不同的组成部分。
本发明实施例提供一种阵列基板的制作方法， 该阵列基板包括薄膜晶体 管和像素电极， 包括：
在基板上形成緩冲层； 以及
在形成有緩冲层基板上沉积半导体材料、 源漏金属材料和透明电极层， 并且通过一次构图工艺形成所述薄膜晶体管中有源层、 源漏电极以及像素电 极的图案。
将有源层、 源漏电极和像素电极釆用一次构图工艺完成， 可大大缩短薄 膜晶体管的制作周期， 同时由于经历比较少的工艺步骤， 可以有效提高薄膜 晶体管的稳定性和可靠性，使得薄膜晶体管的阔值电压不会发生较大的漂移， 同时可提高产品的良率， 降低制造成本， 使器件的使用寿命更长。 通过该制 作方法制作出的阵列基板适用于顶栅型的 LCD显示器件。
另外， 本发明实施例还提供一种适用于顶栅型 OLED结构的阵列基板的 制作方法。
下面结合附图及实施例对本发明进行如下详细说明。
实施例一
本实施例以 OLED ( Organic Light Emitting Diode, 有机发光二极管） 阵 列基板包括两个薄膜晶体管举例说明该阵列基板的制作方法， 例如该阵列基 板包括第一薄膜晶体管、 第二薄膜晶体管以及像素电极， 其中， 第一薄膜晶 体管和第二薄膜晶体管二者中的有源层和源漏电极通过一次构图工艺形成。 本发明所称的构图工艺包括光刻胶涂覆、 曝光、 刻蚀和光刻胶剥离等工艺， 光刻胶以正性光刻胶为例。
本发明实施例提供一种顶栅型阵列基板的制作方法， 包括：
步骤 1、在基板 321上形成緩冲层 322，该緩冲层 322可有效防止因玻璃 基板与半导体层直接接触而对器件造成的不利影响。
步骤 2、 在完成上述步骤的基板上， 沉积有源层薄膜、 源漏金属薄膜和 透明电极层， 通过一次构图工艺形成所述第一薄膜晶体管中有源层和源漏电 极的以及像素电极的图案。
例如，该有源层的图案包括本征半导体层的图案和 /或掺杂半导体层的图 案， 在示出本步骤的附图中以有源层包括本征半导体层的图案和掺杂半导体 层二者的图案为例说明。
在一个示例中， 步骤 2可进一步包括： 步骤 201、在完成步骤 1的基板上沉积本征半导体材料层 323、掺杂半导 体材料层 324 (本征半导体层 323、 掺杂半导体层 324构成有源层薄膜）、 源 漏金属薄膜 325和透明电极层 326， 参考图 1。
步骤 202、 在透明电极层 326上涂覆光刻胶 327。
步骤 203、 釆用双色调掩膜工艺对光刻胶进行曝光、 显影以形成光刻胶 完全保留区域、 光刻胶部分保留区域和光刻胶完全去除区域， 其中， 第一薄 膜晶体管漏极与第二薄膜晶体管栅极的连接区域（见图 9中的 A区域）、 数 据线和电源线区域（图未示；)、第一薄膜晶体管和第二薄膜晶体管的源漏电极 (参见图 9中的 B区域）以及像素电极区域（见图 9中 D区域）为光刻胶完 全保留区域；
第一薄膜晶体管的第一沟道区域和第二薄膜晶体管的第二沟道区域 (参 见图 9中的 C区域)为光刻胶部分保留区域；
上述区域之外区域为光刻胶完全去除区域； 参考图 2和图 3。
步骤 204、 通过第一次刻蚀工艺， 去除光刻胶完全去除区域对应的透明 电极层、 源漏金属薄膜以及有源层薄膜， 即刻蚀至緩冲层 322; 参考图 4。
步骤 205、 通过灰化工艺除去所述部分保留区域对应的光刻胶， 形成第 一沟道区域和第二沟道区域； 参考图 5。
步骤 206、 通过第二次刻蚀工艺， 去除光刻胶部分保留区域对应的像素 电极层 326和源漏金属薄膜 325以及掺杂半导体层 324。
需要说明的是， 若在实际生产中有源层仅为一层， 即仅包括本征半导体 层 323， 则只需要去除像素电极层 326和源漏金属薄膜 325即可， 参考图 5。
步骤 207、 剥离剩余光刻胶， 形成第一薄膜晶体管漏极与第二薄膜晶体 管栅极的连接区域的图案、 数据线和电源线区域的图案、 第一薄膜晶体管和 第二薄膜晶体管的源漏电极的图案以及像素电极区域的图案；继续参考图 5。
本征半导体层例如可釆用 IGZO、 ITZO、 IZO、 Cu20、 GZO、 AZO、 HfIZO、
ZnON材料中的一种或多种， 掺杂半导体层例如可釆用非晶硅、 多晶硅、 微 晶硅材料中的一种或多种。
可选地， 当有源层釆用氧化物半导体材料制作时， 可对氧化物半导体进 行不同气氛的等离子体处理， 该气氛例如可以为氧气、 氩气、 一氧化氮、 氢 气； 或可以对氧化物半导体进行表面改性的气体， 例如可釆用氢等离子体在 空气中对半导体材料进行腐蚀处理。
可选地， 还可以对氧化物半导体层进行退火处理， 所述退火温度为
200-500 °C , 退火环境为空气， 氧气， 氮气、含有摩尔百分比为 1-10%水汽的 空气或含有摩尔百分比为 1-10%水汽的氧气。
步骤 3、在完成步骤 2的基板上形成栅绝缘层 328，通过构图工艺形成过 孔； 参考图 6。
该栅绝缘层例如可以为一层， 所述栅绝缘层可釆用氧化硅薄膜、 氧化铝 薄膜， 氧化钛薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜、 氧化钕薄膜、 氮氧化硅薄膜、 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜、 氮氧化钕薄 膜、 氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜和氮化钽薄膜中的一种；
可替代地，所述栅绝缘层为两层， 即包括第一栅绝缘层和第二栅绝缘层， 所述第一栅绝缘层贴近栅极层， 所述第二栅绝缘层贴近有源层， 所述第一栅 绝缘层图案釆用氮氧化硅薄膜、 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄 膜、 氮氧化钕薄膜、 氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜和氮化钽薄膜中 的一种； 所述第二栅绝缘层釆用氧化硅薄膜， 氧化铝薄膜， 氧化钛薄膜、 氮 氧化硅薄膜、氧化锆薄膜、 氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜中的一种； 或者
可替代地， 所述栅绝缘层为三层， 包括第三栅绝缘层、 第四栅绝缘层和 第五栅绝缘层， 所述第三栅绝缘层贴近栅极层， 所述第五栅绝缘层贴近有源 层， 所述第四栅绝缘层位于第三栅绝缘层和第五栅绝缘层之间， 所述第三栅 绝缘层釆用氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜和氮化钽薄膜中的一种； 所述第四栅绝缘层釆用氮氧化硅薄膜、 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧 化钽薄膜和氮氧化钕薄膜中的一种；所述第五栅绝缘层图案釆用氧化硅薄膜， 氧化铝薄膜， 氧化钛薄膜、 氮氧化硅薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸 钡薄膜和氧化钕薄膜中的一种。
进一步地， 可对以上不同层数的栅绝缘层进行退火工艺处理， 具体退火 工艺包括： 在 PECVD设备的加热腔室中加入氮气或空气， 对第一栅极绝缘 层进行脱氢工艺； 其中， 加热腔室温度为 200°C~350°C， 退火时间为 15分钟 -90分钟。
步骤 4、 通过一次构图工艺形成包括第一薄膜晶体管和第二薄膜晶体管 的栅极、 栅线的图案。
参考图 8，在完成步骤 3的基板上沉积栅金属材料 329，通过构图工艺形 成第一薄膜晶体管和第二薄膜晶体管的栅极、 栅线， 在形成栅极的过程中， 需要刻除位于像素电极区域上方的栅极， 避免该栅极与像素电极发生短路， 进而完成阵列基板的主体结构， 参考图 9。
可选的， 为了进一步保护位于顶处的栅电极， 可在步骤 4的基板上形成 栅电极保护层 330， 该栅电极保护层 330通常釆用抗腐蚀、 抗摩擦的导电薄 膜， 如 ΙΤΟ， ΙΖΟ, ΤΖΟ等薄膜以及与其性质相似的导电薄膜。 当然， 当栅 极金属选用比较耐磨的、 坚硬的金属薄膜时， 可以省去栅电极保护层 330。
上述步骤中涉及到的刻蚀工艺可以为湿法刻蚀、 干法刻蚀或干法湿法结 合刻蚀。
实施例二
基于实施例一中所釆用的阵列基板制作方法， 本发明实施例提供一种顶 栅型阵列基板。 图 10为本发明实施例阵列基板结构的平面示意图，所反映的 是一个像素单元的结构， 图 11为图 10阵列基板的等效电路图， 图 9包括图
10中阵列基板沿 Β-Β线和 Α-Α线的剖面图 （左手边为沿 Β-Β线， 右手边为 沿 Α-Α线）。 本实施例以 OLED ( Organic Light Emitting Diode, 有机发光二 极管） 阵列基板为例， 该阵列基板包括有源层、 数据线 14、 电源线 12和栅 线 11， 数据线 14和电源线 12与栅线 11垂直， 并与二个相邻的栅线一起限 定了像素区域， 像素区域内分别形成有作为寻址元件的第一薄膜晶体管 （也 称开关薄膜晶体管），还包括用于控制有机发光二极管的第二薄膜晶体管（也 称驱动薄膜晶体管）和像素电极。
第一薄膜晶体管位于栅线 11与数据线 14交叉点的位置， 第二薄膜晶体 管位于栅线 11与电源线 12交叉点的位置， 其中第一薄膜晶体管的第一漏极 151与第二栅极 162相连接。
该阵列基板例如包括基板， 所述基板上设有緩冲层、有源层、 源漏电极、 像素电极层、 栅绝缘层和栅电极的图案， 该源漏电极层和像素电极层直接接 触。
有源层包括第一薄膜晶体管的第一有源层 171和第二薄膜晶体管的第二 有源层 172。 所述源漏电极层包括第一薄膜晶体管的第一源极 152、 第一漏极 151以 及第二薄膜晶体管的第二源极 153、 第二漏极 154。
栅绝缘层中设有过孔， 第一薄膜晶体管的第一漏极 151通过过孔与第二 薄膜晶体管的第二栅极 162连接。
在栅绝缘层上设有栅极层， 栅极层包括第一薄膜晶体管的第一栅极 161 和第二薄膜晶体管的第二栅极 162; 第一栅极 161和第二栅极 162、 栅线 11 通过一次构图工艺完成。第一栅极 161与栅线 11连接，第二栅极 162不与栅 线 11相连， 同时第一栅极 161与第二栅极 162互不相连。
本实施例中的栅金属材料层和源漏金属层均为单层， 其材料可以为金属 或合金， 例如 Cu、 Mo、 Al、 Nd 、 Ti及其合金中的至少一种。
需要说明的是， 薄膜晶体管的源极和漏极因其中电流的流动方向不同而 异， 在本发明实施例中， 为了方便描述， 称与像素电极相连接的为漏极。 所 述沟道区域为源电极和漏电极之间的空隙区域。
栅绝缘层例如可以为一层， 其具体材料与实施例一中的相同为了保证更 好的器件特性， 在本实施例中， 可以对该栅极绝缘层进行退火工艺 （即该栅 极绝缘层为经过退火工艺处理的绝缘层），来降低栅极绝缘层中氢元素及氢的 复合物对氧化物半导体特性的影响。
可选地，该栅绝缘层可以为两层， 即包括第一栅绝缘层和第二栅绝缘层， 所述第一栅绝缘层贴近栅极， 所述第二栅绝缘层贴近有源层。 第一、 第二栅 绝缘层的具体材料与实施例一中的相同。优选地， 第一栅绝缘层和 /或第二栅 绝缘层为经过退火工艺处理的绝缘层。 第一栅极绝缘的材料可以很好地遏制 栅电极（尤其当釆用铜或铜合金时）产生的不利影响。 第二栅极绝缘层的作 用是可以很好的实现与氧化物半导体的匹配， 达到提高器件性能的作用。 由 于第二栅极绝缘层的材料多为氧化物绝缘层， 其对 H+、 OH-等基团的防扩散 的能力比较差， 所以在制作完第一栅极绝缘层时， 优选地需要对其进行退火 工艺处理，从而降低因 H+、 OH-等基团的扩散而在第一栅极绝缘层中可能发 生的断裂， 进而达到了提升器件稳定性的作用。
可选地， 该栅绝缘层为三层， 即包括第三栅绝缘层、 第四栅绝缘层和第 五栅绝缘层， 所述第三栅绝缘层贴近栅极， 所述第五栅绝缘层贴近有源层， 第四栅绝缘层位于第三栅绝缘层和第五栅绝缘层之间。 第二、 第三、 第四栅 绝缘层的具体材料与实施例一中的相同。
本实施例中， 第三栅极绝缘层釆用氮化硅薄膜等无机绝缘材料， 由于该 材料直接与氧化物半导体层接触时会造成氧化物半导体层的性能下降， 但它 却可以较好地遏制与栅极金属（尤其是当釆用铜及其合金作为栅极时）接触 产生不良现象， 因此设置该第一栅极绝缘层紧贴栅极， 并远离有源层。 将第 四栅极绝缘层设置在中间层， 由于由氮氧化硅薄膜等无机绝缘材料制成的第 四栅极绝缘层自身含有的 H+、 OH-等基团比较少， 同时对 H+、 OH-等基团 具有一定的防渗透能力， 可以很好的遏制 H+、 OH-等基团向氧化物半导体层 进行扩散，达到了提高器件稳定性的目的。为了最大程度的提高器件的特性， 将第五栅极绝缘层与氧化物半导体紧贴， 从而可以较好地实现与氧化物半导 体的匹配， 达到提高器件稳定性的作用。
需要说明的是， 本实施例中釆用两个薄膜晶体管的制作方法同样适用于 只有一个薄膜晶体管或多个薄膜晶体管阵列基板的制作方法。
实施例三
本发明实施例还提供一种显示器件， 其包括上述阵列基板。 所述显示器 件可以为： 液晶面板、 电子纸、 OLED面板、 手机、 平板电脑、 电视机、 显 示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能的产品或部件。
在上述实施例中， 通过对阵列基板制作工艺流程的改进， 大大缩短了薄 膜晶体管的制作周期， 提高了薄膜晶体管的稳定性， 使得薄膜晶体管的阔值 电压不会发生较大的漂移， 同时可提高产品的良率，延长了器件的使用寿命。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种阵列基板的制作方法，所述阵列基板包括第一薄膜晶体管和像素 电极， 该方法包括：
在基板上形成緩冲层； 以及
在形成有緩冲层的基板上沉积有源层薄膜、源漏金属薄膜和透明电极层， 并且通过一次构图工艺形成所述第一薄膜晶体管中有源层、 源漏电极以及像 素电极的图案。
2、如权利要求 1所述的阵列基板的制作方法，其中所述阵列基板还包括 第二薄膜晶体管， 所述第一薄膜晶体管和第二薄膜晶体管二者中的有源层、 源漏电极层以及像素电极层通过同一次构图工艺形成。
3、如权利要求 2所述的阵列基板的制作方法， 在形成有源层、 源漏电极 以及像素电极的图案之后还包括：
在基板上形成栅绝缘层的图案及过孔；
在栅绝缘层上形成第一薄膜晶体管和第二薄膜晶体管二者的栅极以及栅 线的图案。
4、如权利要求 3所述的阵列基板的制作方法，还包括在栅极及栅线上形 成栅极保护层。
5、如权利要求 2所述的阵列基板的制作方法，其中所述第一薄膜晶体管 和第二薄膜晶体管二者中的有源层、 源漏电极层以及像素电极层通过同一次 构图工艺形成包括：
沉积有源层薄膜、 源漏金属薄膜和透明电极层；
涂覆光刻胶；
釆用双色调掩膜工艺对光刻胶进行曝光、 显影以形成光刻胶完全保留区 域、 光刻胶部分保留区域和光刻胶完全去除区域，
其中， 第一薄膜晶体管漏极与第二薄膜晶体管栅极的连接区域、 数据线 和电源线区域、 第一薄膜晶体管和第二薄膜晶体管二者的源漏电极区域以及 像素电极区域为光刻胶完全保留区域；
第一薄膜晶体管的第一沟道区域和第二薄膜晶体管的第二沟道区域为光 刻胶部分保留区域； 上述区域之外区域为光刻胶完全去除区域；
通过第一次刻蚀工艺， 去除光刻胶完全去除区域对应的透明电极层、 源 漏金属薄膜以及有源层薄膜，
通过灰化工艺除去所述部分保留区域对应的光刻胶， 形成第一沟道区域 和第二沟道区域；
通过第二次刻蚀工艺， 去除光刻胶部分保留区域对应的像素电极层和源 漏金属层；
剥离剩余光刻胶， 形成第一薄膜晶体管漏极与第二薄膜晶体管栅极的连 接区域的图案、 数据线和电源线区域的图案、 第一薄膜晶体管和第二薄膜晶 体管二者的源漏电极区域的图案以及像素电极的图案。
6、如权利要求 3所述的阵列基板的制作方法，其中在栅绝缘层上形成第 一薄膜晶体管和第二薄膜晶体管二者的栅极以及栅线的图案包括：
沉积栅金属层， 通过构图工艺形成第一薄膜晶体管和第二薄膜晶体管二 者的栅极以及栅线， 刻除位于像素电极区域上方的栅极。
7、如权利要求 3所述的阵列基板的制作方法，其中所述栅绝缘层经过退 火工艺处理。
8、如权利要求 7所述的阵列基板的制作方法，其中所述栅绝缘层为一层， 所述栅绝缘层釆用氧化硅薄膜、 氧化铝薄膜， 氧化钛薄膜、 氧化锆薄膜、 氧 化钽薄膜、 钛酸钡薄膜或氧化钕薄膜、 氮氧化硅薄膜、 氮氧化铝薄膜、 氮氧 化锆薄膜、 氮氧化钽薄膜、 氮氧化钕薄膜、 氮化硅薄膜、 氮化铝薄膜、 氮化 锆薄膜和氮化钽薄膜中的一种； 或者
所述栅绝缘层包括第一栅绝缘层和第二栅绝缘层， 所述第一栅绝缘层贴 近栅极层， 所述第二栅绝缘层贴近有源层， 所述第一栅绝缘层图案釆用氮氧 化硅薄膜、 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜、 氮氧化钕薄膜、 氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜和氮化钽薄膜中的一种； 所述第二栅 绝缘层釆用氧化硅薄膜， 氧化铝薄膜， 氧化钛薄膜、 氮氧化硅薄膜、 氧化锆 薄膜、 氧化钽薄膜、 钛酸钡薄膜和氧化钕薄膜中的一种； 或者
所述栅绝缘层包括第三栅绝缘层、 第四栅绝缘层和第五栅绝缘层， 所述 第三栅绝缘层贴近栅极层， 所述第五栅绝缘层贴近有源层， 所述第四栅绝缘 层位于第三栅绝缘层和第五栅绝缘层之间， 所述第三栅绝缘层釆用氮化硅薄 膜、 氮化铝薄膜、 氮化锆薄膜和氮化钽薄膜中的一种； 所述第四栅绝缘层釆 用氮氧化硅薄膜、 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜和氮氧化钕 薄膜中的一种； 所述第五栅绝缘层图案釆用氧化硅薄膜， 氧化铝薄膜， 氧化 钛薄膜、 氮氧化硅薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜和氧化钕薄 膜中的一种。
9、如权利要求 1所述的阵列基板的制造方法，其中所述有源层包括本征 半导体层和掺杂半导体层中的至少一个， 其中， 本征半导体层釆用 IGZO、 ITZO、 IZO、 Cu20、 GZO、 AZO、 HfIZO、 ZnON材料中的一种或多种， 掺 杂半导体层釆用非晶硅、 多晶硅、 微晶硅材料中的一种或多种。
10、 如权利要求 9所述的阵列基板的制造方法， 其中有源层釆用氧化物 半导体材料时， 对氧化物半导体进行等离子体处理。
11、 如权利要求 9所述的阵列基板的制造方法， 其中有源层釆用氧化物 半导体材料时，对氧化物半导体层进行退火处理， 所述退火温度为 200~500°C， 退火环境为空气、 氧气或氮气。
12、 一种利用权利要求 1-11任一项所述的制造方法制备的阵列基板， 包 括基板， 所述基板上设有緩冲层、 有源层、 源漏电极、 像素电极、 栅绝缘层、 栅极层； 所述源漏电极和像素电极直接接触。
13、 如权利要求 12所述的阵列基板，
其中所述栅极层包括第一薄膜晶体管的第一栅极和第二薄膜晶体管的第 二栅极；
所述有源层包括第一薄膜晶体管的第一有源层和第二薄膜晶体管的第二 有源层；
所述源漏电极层包括第一薄膜晶体管的第一源极、 第一漏极以及第二薄 膜晶体管的第二源极、 第二漏极。
14、 如权利要求 12或 13所述的阵列基板，
其中所述栅绝缘层经过退火工艺处理。
15、如权利要求 14所述的阵列基板， 其中所述栅绝缘层为一层， 所述栅 绝缘层釆用氧化硅薄膜、 氧化铝薄膜， 氧化钛薄膜、 氧化锆薄膜、 氧化钽薄 膜、 钛酸钡薄膜或氧化钕薄膜、 氮氧化硅薄膜、 氮氧化铝薄膜、 氮氧化锆薄 膜、 氮氧化钽薄膜、 氮氧化钕薄膜、 氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜 和氮化钽薄膜中的一种； 或者，
所述栅绝缘层包括第一栅绝缘层和第二栅绝缘层， 所述第一栅绝缘层贴 近栅极层， 所述第二栅绝缘层贴近有源层， 所述第一栅绝缘层图案釆用氮氧 化硅薄膜、 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜、 氮氧化钕薄膜、 氮化硅薄膜、 氮化铝薄膜、 氮化锆薄膜和氮化钽薄膜中的一种； 所述第二栅 绝缘层釆用氧化硅薄膜， 氧化铝薄膜， 氧化钛薄膜、 氮氧化硅薄膜、 氧化锆 薄膜、 氧化钽薄膜、 钛酸钡薄膜和氧化钕薄膜中的一种； 或者，
所述栅绝缘层包括第三栅绝缘层、 第四栅绝缘层和第五栅绝缘层， 所述 第三栅绝缘层贴近栅极层， 所述第五栅绝缘层贴近有源层， 所述第四栅绝缘 层位于第三栅绝缘层和第五栅绝缘层之间， 所述第三栅绝缘层釆用氮化硅薄 膜、 氮化铝薄膜、 氮化锆薄膜和氮化钽薄膜中的一种； 所述第四栅绝缘层釆 用氮氧化硅薄膜、 氮氧化铝薄膜、 氮氧化锆薄膜、 氮氧化钽薄膜和氮氧化钕 薄膜中的一种； 所述第五栅绝缘层图案釆用氧化硅薄膜， 氧化铝薄膜， 氧化 钛薄膜、 氮氧化硅薄膜、 氧化锆薄膜、 氧化钽薄膜、 钛酸钡薄膜和氧化钕薄 膜中的一种。
16、如权利要求 12所述的阵列基板，其中所述有源层包括本征半导体层 和掺杂半导体层中的至少一个，其中，本征半导体层釆用 IGZO、 ΙΤΖΟ、 ΙΖΟ、 Cu20、 GZO、 AZO、 HfIZO、 ZnON材料中的一种或多种， 掺杂半导体层釆 用非晶硅、 多晶硅、 微晶硅材料中的一种或多种。
17、 一种显示装置， 包括如权利要求 12-16任一权利要求所述的阵列基 板。
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