CN105977206B - 一种阵列基板的制造方法及阵列基板 - Google Patents

一种阵列基板的制造方法及阵列基板 Download PDF

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CN105977206B
CN105977206B CN201610479540.1A CN201610479540A CN105977206B CN 105977206 B CN105977206 B CN 105977206B CN 201610479540 A CN201610479540 A CN 201610479540A CN 105977206 B CN105977206 B CN 105977206B
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source electrode
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buffer layer
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CN105977206A (zh
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周志超
夏慧
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Abstract

本发明公开一种阵列基板及其制造方法，其中制造方法包括以下步骤：基板；在基板上形成缓冲层；在缓冲层内形成源极和数据线，同时在缓冲层上形成栅极和栅极线，其中缓冲层至少部分外露源极和数据线的远离基板的一侧；在源极、数据线、栅极以及栅极线上形成绝缘层，其中绝缘层至少部分外露源极和栅极线的远离基板的一侧；在源极上形成半导体层，其中半导体层与源极的外露部分电性连接且与栅极之间由绝缘层电性绝缘；在绝缘层上形成第一像素电极和第二像素电极，其中第一像素电极与半导体层的远离基板的一侧电性连接，第二像素电极与栅极线的外露部分电性连接。本发明阵列基板的制造过程高效且节能。

Description

一种阵列基板的制造方法及阵列基板
技术领域
本发明涉及液晶面板技术领域，特别是涉及一种阵列基板的制造方法及阵列基板。
背景技术
在液晶面板工业中，通过阵列基板来控制液晶的排列，从而实现不同灰度光线的显示。阵列基板为液晶面板中的重要部分，其生产也属于液晶面板制造过程中的重要工艺步骤。
当前阵列基板的制造生产中，基于其结构设计，通常会将漏极和栅极分开沉积刻蚀，而漏极和栅极一般采用同一种金属，因此分开沉积降低了生产效率且增大了生产成本。
发明内容
本发明的目的在于提供一种阵列基板的制造方法及阵列基板，以解决现有技术中阵列基板的生产效率较低成本较高的问题。
为解决上述问题，本发明提出一种阵列基板的制造方法，包括以下步骤：基板；在基板上形成缓冲层；在缓冲层内形成源极和数据线，同时在缓冲层上形成栅极和栅极线，其中缓冲层至少部分外露源极和数据线的远离基板的一侧；在源极、数据线、栅极以及栅极线上形成绝缘层，其中绝缘层至少部分外露源极和栅极线的远离基板的一侧；在源极上形成半导体层，其中半导体层与源极的外露部分电性连接且与栅极之间由绝缘层电性绝缘；在绝缘层上形成第一像素电极和第二像素电极，其中第一像素电极与半导体层的远离基板的一侧电性连接，第二像素电极与栅极线的外露部分电性连接。
其中，在缓冲层内形成源极和数据线，同时在缓冲层上形成栅极和栅极线的步骤包括：在基板上形成缓冲层并进行图案化处理，以在缓冲层上形成与源极和数据线对应的沟槽；在缓冲层上形成一导电层并进行图案化处理，以在沟槽内形成数据线和源极，并且在缓冲层上形成栅极和栅极线。
其中，栅极包括第一栅极和第二栅极，第一栅极和第二栅极均与源极平行设置。
其中，栅极线包括第一栅极线和第二栅极线，第二像素电极分别与第一栅极线的外露部分和第二栅极线的外露部分电性连接。
其中，源极与数据线电性连接，第一栅极和第二栅极均与第二栅极线电性连接。
为解决上述问题，本发明还提供一种阵列基板，其包括基板；缓冲层，形成在基板上；源极和数据线，形成在缓冲层内，缓冲层至少部分外露源极和数据线的远离基板的一侧；栅极和栅极线，形成在缓冲层上；绝缘层，形成在源极、数据线、栅极以及栅极线上，绝缘层至少部分外露源极和栅极线的远离基板的一侧；半导体层，形成在源极上，半导体层与源极的外露部分电性连接且与栅极之间由绝缘层电性绝缘；第一像素电极和第二像素电极，形成在绝缘层上，其中第一像素电极与半导体层的远离基板的一侧电性连接，第二像素电极与栅极线的外露部分电性连接。
其中，缓冲层为图案化缓冲层，图案化缓冲层上包括与源极和数据线对应的沟槽；源极和数据线形成于沟槽内，栅极和栅极线形成在缓冲层上。
其中，栅极包括第一栅极和第二栅极，第一栅极和第二栅极均与源极平行设置。
其中，栅极线包括第一栅极线和第二栅极线，第二像素电极分别与第一栅极线的外露部分和第二栅极线的外露部分电性连接。
其中，源极与数据线电性连接，第一栅极和第二栅极均与第二栅极线电性连接。
本发明阵列基板的制造方法包括以下步骤：基板，在基板上形成缓冲层，在缓冲层内形成源极和数据线，同时在缓冲层上形成栅极和栅极线，其中缓冲层至少部分外露源极和数据线的远离基板的一侧；在源极、数据线、栅极以及栅极线上形成绝缘层，其中绝缘层至少部分外露源极和栅极线的远离基板的一侧；在源极上形成半导体层，其中半导体层与源极的外露部分电性连接且与栅极之间由绝缘层电性绝缘；在绝缘层上形成第一像素电极和第二像素电极，其中第一像素电极与半导体层的远离基板的一侧电性连接，第二像素电极与栅极线的外露部分电性连接。本发明中同时形成源极、数据线和栅极、栅极线，减少了工艺步骤，提高生产效率，减小生产成本。
附图说明
图1是本发明阵列基板的制造方法一实施方式的流程示意图；
图2是图1所示阵列基板的制造方法中同时形成源极、数据线、栅极和栅极线的步骤所对应的结构示意图；
图3是图1所示阵列基板的制造方法中形成绝缘层的步骤所对应的结构示意图；
图4是图1所示阵列基板的制造方法中形成半导体层的步骤所对应的结构示意图；
图5是图1所示阵列基板的制造方法中形成第一像素电极和第二像素电极的步骤所对应的结构示意图；
图6是本发明阵列基板一实施方式的结构示意图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对发明所提供的一种阵列基板的制造方法及阵列基板做进一步详细描述。
参阅图1，图1是本发明阵列基板的制造方法一实施方式的流程示意图，本实施方式制造方法包括以下步骤。
S101：在基板上形成缓冲层。
请参阅图2，图2是图1所示阵列基板的制造方法中同时形成源极、数据线、栅极和栅极线的步骤所对应的结构示意图，图2中的上图为阵列基板的俯视图，下图为阵列基板A-A方向的剖视图，图3、4、5与图2类似，上图为俯视图，下图为A-A方向的剖视图。
本步骤中首先在基板11上形成的缓冲层12，该缓冲层12经过化学气相沉积及干法刻蚀的光罩制程实现图案化，图案化的缓冲层12中具有沟槽121，该沟槽121与后续步骤S102中形成的源极13和数据线14相对应，具体关系在步骤S102中再做描述。
S102：在缓冲层内形成源极和数据线，同时在缓冲层上形成栅极和栅极线。
请再次参阅图2，源极13和数据线14形成在缓冲层12内，并且缓冲层12至少部分外露源极13和数据线14的远离基板11的一侧；即源极13和数据线14并不是完全形成在缓冲层12内部而没有外露部分，其远离基板11的一侧是部分外露于缓冲层12的。形成源极13和数据线14的同时在缓冲层12上形成栅极15和栅极线16。
具体来说，步骤S101中的缓冲层12为图案化，具有沟槽121；上述源极13和数据线14则形成在沟槽121内，而栅极15和栅极线16则形成在缓冲层12上。
该步骤S102中首先在图案化的缓冲层12上物理气相沉积一导电层，利用湿法刻蚀的光罩制程对该导电层进行图案化处理，从而在沟槽内形成数据线14和源极13，并且在缓冲层上形成栅极15和栅极线16，其中数据线14和源极13电性连接。
所形成的栅极15分为第一栅极151和第二栅极152，栅极线16分为第一栅极线161和第二栅极线162。其中第一栅极151和第二栅极152均与源极13平行设置，并且都与第二栅极线162电性连接。
在本步骤S102中，源极13、数据线14、栅极15以及栅极线16采用同一金属材料制成，因此能够通过同一工艺同时制得，相比分两个工艺分别制作源极、数据线和栅极、栅极线，节省了时间，并且节约了湿法刻蚀中需要采用的铜酸，节约成本及减少工业污染。
S103：在源极、数据线、栅极以及栅极线上形成绝缘层。
请参阅图3，图3是图1所示阵列基板的制造方法中形成绝缘层的步骤所对应的结构示意图。本步骤S103中所形成的绝缘层17至少部分外露源极13和栅极线16的远离基板11的一侧。
同样，首先使用化学气相沉积一绝缘层，然后采用干法刻蚀的光罩制程进行图案化处理，使得源极13和栅极线16远离基板11的一侧有部分外露于绝缘层17。
S104：在源极上形成半导体层。
请参阅图4，图4是图1所示阵列基板的制造方法中形成半导体层的步骤所对应的结构示意图。本步骤S104所形成的半导体层18与源极13的外露部分电性连接且与栅极15之间由绝缘层17电性绝缘。
在步骤S103中，绝缘层17已将栅极15完全覆盖，因此所形成的半导体层18与栅极15之间能够由绝缘层17电性绝缘，且半导体层18为非晶硅或铟镓锌氧化物(IGZO)等有源层材料。本步骤中半导体层18主要采用了化学气相沉积和干法刻蚀工艺。
S105：在绝缘层上形成第一像素电极和第二像素电极。
请参阅图5，图5是图1所示阵列基板的制造方法中形成第一像素电极和第二像素电极的步骤所对应的结构示意图。本步骤S105中采用物理气相沉积及湿法刻蚀工艺得到图案化的像素电极层，包括第一像素电极191和第二像素电极192，完成本步骤后得到阵列基板100。
其中，第一像素电极191与半导体层18的远离基板的一侧电性连接，第二像素电极192与栅极线16的外露部分电性连接，具体的第二像素电极192分别与第一栅极线161的外露部分和第二栅极线162的外露部分电性连接，第一栅极线161和第二栅极线162通过第二像素电极192连接。
本发明阵列基板的制造方法包括以下步骤：基板，在基板上形成缓冲层，在缓冲层内形成源极和数据线，同时在缓冲层上形成栅极和栅极线，其中缓冲层至少部分外露源极和数据线的远离基板的一侧；在源极、数据线、栅极以及栅极线上形成绝缘层，其中绝缘层至少部分外露源极和栅极线的远离基板的一侧；在源极上形成半导体层，其中半导体层与源极的外露部分电性连接且与栅极之间由绝缘层电性绝缘；在绝缘层上形成第一像素电极和第二像素电极，其中第一像素电极与半导体层的远离基板的一侧电性连接，第二像素电极与栅极线的外露部分电性连接。本发明中同时形成源极、数据线和栅极、栅极线，减少了工艺步骤，提高生产效率，减小生产成本。
请参阅图6，图6是本发明阵列基板一实施方式的结构示意图。本实施方式阵列基板600包括基板61、缓冲层62、源极63、数据线64、栅极65、栅极线66、绝缘层67、半导体层68、第一像素电极691和第二像素电极692。
其中，缓冲层62形成在基板61上；缓冲层62为图案化缓冲层，其包括与源极63和数据线64对应的沟槽621。
源极63和数据线64电性连接，且形成在缓冲层62内，缓冲层62至少部分外露源极63和数据线64的远离基板的一侧。
栅极65和栅极线66，形成在缓冲层62上，栅极65包括第一栅极651和第二栅极652，第一栅极651和第二栅极652均与源极63平行设置。栅极线66包括第一栅极线661和第二栅极线662，第一栅极651和第二栅极652均与第二栅极线662电性连接。
绝缘层67，形成在源极63、数据线64、栅极65以及栅极线66上，绝缘层67至少部分外露源极63和栅极线66的远离基板61的一侧。
半导体层68，形成在源极63上，半导体层68与源极63的外露部分电性连接且与栅极65之间由绝缘层67电性绝缘。
第一像素电极691和第二像素电极692，形成在绝缘层67上，其中第一像素电极691与半导体层68的远离基板61的一侧电性连接，第二像素电极692与栅极线66的外露部分电性连接，第二像素电极692分别与第一栅极线661的外露部分和第二栅极线662的外露部分电性连接。
本实施方式阵列基板600与上述通过制造方法得到的阵列基板100类似，具体不再赘述。
本发明阵列基板基于其本身的结构能够实现在制造过程中同一工艺同时形成源极、数据线、栅极以及栅极线，因此本发明的阵列基板便于生产，且成本较低。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (9)

1.一种阵列基板的制造方法，其特征在于，所述制造方法包括以下步骤：
基板；
在所述基板上形成缓冲层；
在所述缓冲层内形成源极和数据线，同时在所述缓冲层上形成栅极和栅极线，其中所述缓冲层至少部分外露所述源极和所述数据线的远离所述基板的一侧；
在所述源极、所述数据线、所述栅极以及所述栅极线上形成绝缘层，其中所述绝缘层至少部分外露所述源极和所述栅极线的远离所述基板的一侧；
在所述源极上形成半导体层，其中所述半导体层与所述源极的外露部分电性连接且与所述栅极之间由所述绝缘层电性绝缘；
在所述绝缘层上形成第一像素电极和第二像素电极，其中所述第一像素电极与所述半导体层的远离所述基板的一侧电性连接，所述第二像素电极与所述栅极线的外露部分电性连接。
2.根据权利要求1所述的制造方法，其特征在于，所述在所述缓冲层内形成源极和数据线，同时在所述缓冲层上形成栅极和栅极线的步骤包括：
在所述基板上形成所述缓冲层并进行图案化处理，以在所述缓冲层上形成与所述源极和所述数据线对应的沟槽；
在所述缓冲层上形成一导电层并进行图案化处理，以在所述沟槽内形成所述数据线和所述源极，并且在所述缓冲层上形成所述栅极和所述栅极线。
3.根据权利要求1所述的制造方法，其特征在于，所述栅极包括第一栅极和第二栅极，所述第一栅极和所述第二栅极均与所述源极平行设置。
4.根据权利要求3所述的制造方法，其特征在于，所述栅极线包括第一栅极线和第二栅极线，所述第二像素电极分别与所述第一栅极线的外露部分和所述第二栅极线的外露部分电性连接。
5.根据权利要求4所述的制造方法，其特征在于，所述源极与所述数据线电性连接，所述第一栅极和所述第二栅极均与所述第二栅极线电性连接。
6.一种阵列基板，其特征在于，所述阵列基板包括：
基板；
缓冲层，形成在所述基板上；
源极和数据线，形成在所述缓冲层内，所述缓冲层至少部分外露所述源极和所述数据线的远离所述基板的一侧；
栅极和栅极线，形成在所述缓冲层上；
绝缘层，形成在所述源极、所述数据线、所述栅极以及所述栅极线上，所述绝缘层至少部分外露源极和所述栅极线的远离所述基板的一侧；
半导体层，形成在所述源极上，所述半导体层与所述源极的外露部分电性连接且与所述栅极之间由所述绝缘层电性绝缘；
第一像素电极和第二像素电极，形成在所述绝缘层上，其中所述第一像素电极与所述半导体层的远离所述基板的一侧电性连接，所述第二像素电极与所述栅极线的外露部分电性连接；
所述栅极包括第一栅极和第二栅极，所述第一栅极和所述第二栅极均与所述源极平行设置。
7.根据权利要求6所述的阵列基板，其特征在于，所述缓冲层为图案化缓冲层，所述图案化缓冲层上包括与所述源极和所述数据线对应的沟槽；所述源极和所述数据线形成于所述沟槽内，所述栅极和所述栅极线形成在所述缓冲层上。
8.根据权利要求6所述的阵列基板，其特征在于，所述栅极线包括第一栅极线和第二栅极线，所述第二像素电极分别与所述第一栅极线的外露部分和所述第二栅极线的外露部分电性连接。
9.根据权利要求8所述的阵列基板，其特征在于，所述源极与所述数据线电性连接，所述第一栅极和所述第二栅极均与所述第二栅极线电性连接。
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