WO2018000477A1 - 一种阵列基板的制造方法及阵列基板 - Google Patents

一种阵列基板的制造方法及阵列基板 Download PDF

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Publication number
WO2018000477A1
WO2018000477A1 PCT/CN2016/090583 CN2016090583W WO2018000477A1 WO 2018000477 A1 WO2018000477 A1 WO 2018000477A1 CN 2016090583 W CN2016090583 W CN 2016090583W WO 2018000477 A1 WO2018000477 A1 WO 2018000477A1
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Prior art keywords
gate
source
line
buffer layer
substrate
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PCT/CN2016/090583
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English (en)
French (fr)
Inventor
周志超
夏慧
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深圳市华星光电技术有限公司
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Priority to US15/117,446 priority Critical patent/US10249648B2/en
Publication of WO2018000477A1 publication Critical patent/WO2018000477A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the present invention relates to the field of liquid crystal panel technology, and in particular, to a method for fabricating an array substrate and an array substrate.
  • the arrangement of liquid crystals is controlled by an array substrate to realize display of different gray scale lights.
  • the array substrate is an important part in the liquid crystal panel, and its production is also an important process step in the manufacturing process of the liquid crystal panel.
  • the drain and gate are usually deposited and etched separately, while the drain and gate are generally made of the same metal, so separate deposition reduces production efficiency and increases production. cost.
  • An object of the present invention is to provide a method for fabricating an array substrate and an array substrate to solve the problem of low production cost and high cost of the array substrate in the prior art.
  • the present invention provides a method for fabricating an array substrate, comprising the steps of: forming a buffer layer on a substrate and performing a patterning process to form a trench corresponding to the source and the data line on the buffer layer; Forming a conductive layer on the buffer layer and performing a patterning process to form a data line and a source in the trench, and forming a gate and a gate line on the buffer layer, wherein the buffer layer at least partially exposes the source and the data a side of the line away from the substrate; the gate includes a first gate and a second gate, the first gate and the second gate are both disposed in parallel with the source; at the source, the data line, the gate, and the gate line Forming an insulating layer thereon, wherein the insulating layer at least partially exposes a side of the source and the gate line away from the substrate; forming a semiconductor layer on the source, wherein the semiconductor layer is electrically connected to the exposed portion of the source and between the gate Electrically insulating
  • the gate line includes a first gate line and a second gate line, and the second pixel electrode is electrically connected to the exposed portion of the first gate line and the exposed portion of the second gate line, respectively.
  • the source is electrically connected to the data line, and the first gate and the second gate are electrically connected to the second gate line.
  • the present invention provides a method for fabricating an array substrate, comprising the steps of: forming a buffer layer on a substrate; forming a source and a data line in the buffer layer, and forming a gate and a gate on the buffer layer; a pole line, wherein the buffer layer at least partially exposes a side of the source and the data line away from the substrate; forming an insulating layer on the source, the data line, the gate, and the gate line, wherein the insulating layer at least partially exposes the source and the gate a side of the line away from the substrate; forming a semiconductor layer on the source, wherein the semiconductor layer is electrically connected to the exposed portion of the source and electrically insulated from the gate by an insulating layer; forming a first pixel electrode on the insulating layer And a second pixel electrode, wherein the first pixel electrode is electrically connected to a side of the semiconductor layer remote from the substrate, and the second pixel electrode is electrically connected to the exposed portion of the gate line
  • the step of forming a source and a data line in the buffer layer while forming a gate and a gate line on the buffer layer includes: forming a buffer layer on the substrate and performing a patterning process to form a source on the buffer layer a trench corresponding to the data line; forming a conductive layer on the buffer layer and performing a patterning process to form a data line and a source in the trench, and forming a gate and a gate line on the buffer layer.
  • the gate includes a first gate and a second gate, and the first gate and the second gate are both disposed in parallel with the source.
  • the gate line includes a first gate line and a second gate line, and the second pixel electrode is electrically connected to the exposed portion of the first gate line and the exposed portion of the second gate line, respectively.
  • the source is electrically connected to the data line, and the first gate and the second gate are electrically connected to the second gate line.
  • the present invention further provides an array substrate including a substrate; a buffer layer formed on the substrate; a source and a data line formed in the buffer layer, the buffer layer being at least partially exposed away from the source and the data line a side of the substrate; a gate and a gate line formed on the buffer layer; an insulating layer formed on the source, the data line, the gate, and the gate line, the insulating layer being at least partially exposed away from the source and the gate line a semiconductor layer formed on the source, the semiconductor layer and the exposed portion of the source are electrically connected and electrically insulated from the gate by an insulating layer; the first pixel electrode and the second pixel electrode are formed on On the insulating layer, the first pixel electrode is electrically connected to a side of the semiconductor layer remote from the substrate, and the second pixel electrode is electrically connected to the exposed portion of the gate line.
  • the buffer layer is a patterned buffer layer, and the patterned buffer layer includes a trench corresponding to the source and the data line; the source and the data line are formed in the trench, and the gate and the gate line are formed on the buffer layer.
  • the gate includes a first gate and a second gate, and the first gate and the second gate are both disposed in parallel with the source.
  • the gate line includes a first gate line and a second gate line, and the second pixel electrode is electrically connected to the exposed portion of the first gate line and the exposed portion of the second gate line, respectively.
  • the source is electrically connected to the data line, and the first gate and the second gate are electrically connected to the second gate line.
  • the manufacturing method of the array substrate of the present invention comprises the steps of: forming a buffer layer on the substrate, forming a source and a data line in the buffer layer, and forming a gate and a gate line on the buffer layer, wherein the buffer layer is at least partially exposed a side of the source and the data line away from the substrate; forming an insulating layer on the source, the data line, the gate, and the gate line, wherein the insulating layer at least partially exposes a side of the source and the gate line away from the substrate; Forming a semiconductor layer on the source, wherein the semiconductor layer is electrically connected to the exposed portion of the source and electrically insulated from the gate by the insulating layer; forming a first pixel electrode and a second pixel electrode on the insulating layer, wherein the first layer The pixel electrode is electrically connected to a side of the semiconductor layer remote from the substrate, and the second pixel electrode is electrically connected to the exposed portion of the gate line.
  • FIG. 1 is a schematic flow chart of an embodiment of a method for fabricating an array substrate of the present invention
  • FIG. 2 is a schematic structural view corresponding to a step of simultaneously forming a source, a data line, a gate, and a gate line in the method of fabricating the array substrate shown in FIG. 1;
  • FIG. 3 is a schematic structural view corresponding to a step of forming an insulating layer in the method for fabricating the array substrate shown in FIG. 1;
  • FIG. 4 is a schematic structural view corresponding to a step of forming a semiconductor layer in the method of fabricating the array substrate shown in FIG. 1;
  • FIG. 5 is a schematic structural view corresponding to a step of forming a first pixel electrode and a second pixel electrode in the method of fabricating the array substrate shown in FIG. 1;
  • FIG. 6 is a schematic structural view of an embodiment of an array substrate of the present invention.
  • FIG. 1 is a schematic flow chart of an embodiment of a method for fabricating an array substrate according to the present invention.
  • the manufacturing method of the present embodiment includes the following steps.
  • FIG. 2 is a schematic structural diagram corresponding to the steps of simultaneously forming a source, a data line, a gate and a gate line in the method for fabricating the array substrate shown in FIG. 1.
  • the upper view in FIG. 2 is an array substrate.
  • the top view is a cross-sectional view of the array substrate AA direction, and FIGS. 3, 4, and 5 are similar to FIG. 2, the top view is a top view, and the lower view is a cross-sectional view in the AA direction.
  • a buffer layer 12 is first formed on the substrate 11.
  • the buffer layer 12 is patterned by a photomask process of dry vapor deposition and dry etching.
  • the patterned buffer layer 12 has a trench 121 therein. 121 corresponds to the source 13 and the data line 14 formed in the subsequent step S102, and the specific relationship is further described in step S102.
  • S102 forming a source and a data line in the buffer layer while forming a gate and a gate line on the buffer layer.
  • the source 13 and the data line 14 are formed in the buffer layer 12, and the buffer layer 12 at least partially exposes the side of the source 13 and the data line 14 away from the substrate 11; that is, the source 13 and the data line 14 It is not completely formed inside the buffer layer 12 without an exposed portion, and the side away from the substrate 11 is partially exposed to the buffer layer 12.
  • the gate electrode 15 and the gate line 16 are formed on the buffer layer 12 while the source electrode 13 and the data line 14 are formed.
  • the buffer layer 12 in step S101 is patterned and has a trench 121; the source 13 and the data line 14 are formed in the trench 121, and the gate 15 and the gate line 16 are formed in the buffer layer. 12 on.
  • a conductive layer is first physically vapor deposited on the patterned buffer layer 12, and the conductive layer is patterned by a wet etch mask process to form a data line 14 and a source in the trench. 13, and a gate electrode 15 and a gate line 16 are formed on the buffer layer, wherein the data line 14 and the source electrode 13 are electrically connected.
  • the formed gate electrode 15 is divided into a first gate electrode 151 and a second gate electrode 152, and the gate line 16 is divided into a first gate line 161 and a second gate line 162.
  • the first gate 151 and the second gate 152 are both disposed in parallel with the source 13 and are electrically connected to the second gate line 162.
  • the source 13 , the data line 14 , the gate 15 and the gate line 16 are made of the same metal material, and thus can be simultaneously produced by the same process, and the source and the data line are separately produced by two processes. And the gate and gate lines save time and save the copper acid needed in wet etching, saving cost and reducing industrial pollution.
  • S103 forming an insulating layer on the source, the data line, the gate, and the gate line.
  • FIG. 3 is a schematic structural view corresponding to the step of forming an insulating layer in the method for fabricating the array substrate shown in FIG. 1.
  • the insulating layer 17 formed in this step S103 at least partially exposes the source 13 and the side of the gate line 16 away from the substrate 11.
  • an insulating layer is first deposited using chemical vapor deposition, and then patterned by a dry etching reticle process such that a portion of the source 13 and the gate line 16 away from the substrate 11 is partially exposed to the insulating layer 17.
  • FIG. 4 is a schematic structural view corresponding to the step of forming a semiconductor layer in the method for fabricating the array substrate shown in FIG. 1.
  • the semiconductor layer 18 formed in this step S104 is electrically connected to the exposed portion of the source 13 and electrically insulated from the gate 15 by the insulating layer 17.
  • step S103 the insulating layer 17 has completely covered the gate electrode 15, so that the formed semiconductor layer 18 and the gate electrode 15 can be electrically insulated by the insulating layer 17, and the semiconductor layer 18 is amorphous silicon or indium gallium zinc. Active layer material such as oxide (IGZO).
  • the semiconductor layer 18 mainly adopts a chemical vapor deposition and a dry etching process.
  • S105 forming a first pixel electrode and a second pixel electrode on the insulating layer.
  • FIG. 5 is a schematic structural diagram corresponding to the step of forming a first pixel electrode and a second pixel electrode in the method for fabricating the array substrate shown in FIG. 1.
  • the patterned pixel electrode layer is obtained by the physical vapor deposition and the wet etching process, and includes the first pixel electrode 191 and the second pixel electrode 192.
  • the array substrate 100 is obtained.
  • the first pixel electrode 191 is electrically connected to a side of the semiconductor layer 18 away from the substrate, and the second pixel electrode 192 is electrically connected to the exposed portion of the gate line 16.
  • the specific second pixel electrode 192 and the first gate are respectively
  • the exposed portion of the pole line 161 is electrically connected to the exposed portion of the second gate line 162, and the first gate line 161 and the second gate line 162 are connected by the second pixel electrode 192.
  • the manufacturing method of the array substrate of the present invention comprises the steps of: forming a buffer layer on the substrate, forming a source and a data line in the buffer layer, and forming a gate and a gate line on the buffer layer, wherein the buffer layer is at least partially exposed a side of the source and the data line away from the substrate; forming an insulating layer on the source, the data line, the gate, and the gate line, wherein the insulating layer at least partially exposes a side of the source and the gate line away from the substrate; Forming a semiconductor layer on the source, wherein the semiconductor layer is electrically connected to the exposed portion of the source and electrically insulated from the gate by the insulating layer; forming a first pixel electrode and a second pixel electrode on the insulating layer, wherein the first layer The pixel electrode is electrically connected to a side of the semiconductor layer remote from the substrate, and the second pixel electrode is electrically connected to the exposed portion of the gate line.
  • FIG. 6 is a schematic structural view of an embodiment of an array substrate of the present invention.
  • the array substrate 600 of the present embodiment includes a substrate 61, a buffer layer 62, a source 63, a data line 64, a gate 65, a gate line 66, an insulating layer 67, a semiconductor layer 68, a first pixel electrode 691, and a second pixel electrode 692. .
  • the buffer layer 62 is formed on the substrate 61; the buffer layer 62 is a patterned buffer layer including a trench 621 corresponding to the source 63 and the data line 64.
  • the source 63 and the data line 64 are electrically connected and formed in the buffer layer 62.
  • the buffer layer 62 at least partially exposes the side of the source 63 and the data line 64 away from the substrate.
  • a gate 65 and a gate line 66 are formed on the buffer layer 62.
  • the gate 65 includes a first gate 651 and a second gate 652.
  • the first gate 651 and the second gate 652 are both disposed in parallel with the source 63.
  • the gate line 66 includes a first gate line 661 and a second gate line 662.
  • the first gate 651 and the second gate 652 are both electrically connected to the second gate line 662.
  • the insulating layer 67 is formed on the source 63, the data line 64, the gate 65, and the gate line 66.
  • the insulating layer 67 at least partially exposes the side of the source 63 and the gate line 66 away from the substrate 61.
  • the semiconductor layer 68 is formed on the source 63, and the semiconductor layer 68 is electrically connected to the exposed portion of the source 63 and electrically insulated from the gate 65 by the insulating layer 67.
  • the first pixel electrode 691 and the second pixel electrode 692 are formed on the insulating layer 67, wherein the first pixel electrode 691 is electrically connected to a side of the semiconductor layer 68 remote from the substrate 61, and the second pixel electrode 692 and the gate line 66 are electrically connected.
  • the exposed portions are electrically connected, and the second pixel electrodes 692 are electrically connected to the exposed portions of the first gate lines 661 and the exposed portions of the second gate lines 662, respectively.
  • the array substrate 600 of the present embodiment is similar to the array substrate 100 obtained by the above manufacturing method, and details are not described herein again.
  • the array substrate of the present invention can realize the simultaneous formation of the source, the data line, the gate and the gate line in the same process in the manufacturing process based on its own structure. Therefore, the array substrate of the present invention is easy to produce and has a low cost.

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Abstract

一种阵列基板及其制造方法，其中制造方法包括以下步骤：基板（11）；（S101）在基板（11）上形成缓冲层（12）；（S102）在缓冲层（12）内形成源极（13）和数据线（14），同时在缓冲层（12）上形成栅极（15）和栅极线（16），其中缓冲层（12）至少部分外露源极（13）和数据线（14）的远离基板（11）的一侧；（S103）在源极（13）、数据线（14）、栅极（15）以及栅极线（16）上形成绝缘层（17），其中绝缘层（17）至少部分外露源极（13）和栅极线（16）的远离基板（11）的一侧；（S104）在源极（13）上形成半导体层（18），其中半导体层（18）与源极（13）的外露部分电性连接且与栅极（15）之间由绝缘层（17）电性绝缘；（S105）在绝缘层（17）上形成第一像素电极（191）和第二像素电极（192），其中第一像素电极（191）与半导体层（18）的远离基板（11）的一侧电性连接，第二像素电极（192）与栅极线（16）的外露部分电性连接。

Description

一种阵列基板的制造方法及阵列基板
【技术领域】
本发明涉及液晶面板技术领域，特别是涉及一种阵列基板的制造方法及阵列基板。
【背景技术】
在液晶面板工业中，通过阵列基板来控制液晶的排列，从而实现不同灰度光线的显示。阵列基板为液晶面板中的重要部分，其生产也属于液晶面板制造过程中的重要工艺步骤。
当前阵列基板的制造生产中，基于其结构设计，通常会将漏极和栅极分开沉积刻蚀，而漏极和栅极一般采用同一种金属，因此分开沉积降低了生产效率且增大了生产成本。
【发明内容】
本发明的目的在于提供一种阵列基板的制造方法及阵列基板，以解决现有技术中阵列基板的生产效率较低成本较高的问题。
为解决上述问题，本发明提出一种阵列基板的制造方法，包括以下步骤：基板；在基板上形成缓冲层并进行图案化处理，以在缓冲层上形成与源极和数据线对应的沟槽；在缓冲层上形成一导电层并进行图案化处理，以在沟槽内形成数据线和源极，并且在缓冲层上形成栅极和栅极线，其中缓冲层至少部分外露源极和数据线的远离基板的一侧；栅极包括第一栅极和第二栅极，第一栅极和第二栅极均与源极平行设置；在源极、数据线、栅极以及栅极线上形成绝缘层，其中绝缘层至少部分外露源极和栅极线的远离基板的一侧；在源极上形成半导体层，其中半导体层与源极的外露部分电性连接且与栅极之间由绝缘层电性绝缘；在绝缘层上形成第一像素电极和第二像素电极，其中第一像素电极与半导体层的远离基板的一侧电性连接，第二像素电极与栅极线的外露部分电性连接。
其中，栅极线包括第一栅极线和第二栅极线，第二像素电极分别与第一栅极线的外露部分和第二栅极线的外露部分电性连接。
其中，源极与数据线电性连接，第一栅极和第二栅极均与第二栅极线电性连接。
为解决上述问题，本发明提出一种阵列基板的制造方法，包括以下步骤：基板；在基板上形成缓冲层；在缓冲层内形成源极和数据线，同时在缓冲层上形成栅极和栅极线，其中缓冲层至少部分外露源极和数据线的远离基板的一侧；在源极、数据线、栅极以及栅极线上形成绝缘层，其中绝缘层至少部分外露源极和栅极线的远离基板的一侧；在源极上形成半导体层，其中半导体层与源极的外露部分电性连接且与栅极之间由绝缘层电性绝缘；在绝缘层上形成第一像素电极和第二像素电极，其中第一像素电极与半导体层的远离基板的一侧电性连接，第二像素电极与栅极线的外露部分电性连接。
其中，在缓冲层内形成源极和数据线，同时在缓冲层上形成栅极和栅极线的步骤包括：在基板上形成缓冲层并进行图案化处理，以在缓冲层上形成与源极和数据线对应的沟槽；在缓冲层上形成一导电层并进行图案化处理，以在沟槽内形成数据线和源极，并且在缓冲层上形成栅极和栅极线。
其中，栅极包括第一栅极和第二栅极，第一栅极和第二栅极均与源极平行设置。
其中，栅极线包括第一栅极线和第二栅极线，第二像素电极分别与第一栅极线的外露部分和第二栅极线的外露部分电性连接。
其中，源极与数据线电性连接，第一栅极和第二栅极均与第二栅极线电性连接。
为解决上述问题，本发明还提供一种阵列基板，其包括基板；缓冲层，形成在基板上；源极和数据线，形成在缓冲层内，缓冲层至少部分外露源极和数据线的远离基板的一侧；栅极和栅极线，形成在缓冲层上；绝缘层，形成在源极、数据线、栅极以及栅极线上，绝缘层至少部分外露源极和栅极线的远离基板的一侧；半导体层，形成在源极上，半导体层与源极的外露部分电性连接且与栅极之间由绝缘层电性绝缘；第一像素电极和第二像素电极，形成在绝缘层上，其中第一像素电极与半导体层的远离基板的一侧电性连接，第二像素电极与栅极线的外露部分电性连接。
其中，缓冲层为图案化缓冲层，图案化缓冲层上包括与源极和数据线对应的沟槽；源极和数据线形成于沟槽内，栅极和栅极线形成在缓冲层上。
其中，栅极包括第一栅极和第二栅极，第一栅极和第二栅极均与源极平行设置。
其中，栅极线包括第一栅极线和第二栅极线，第二像素电极分别与第一栅极线的外露部分和第二栅极线的外露部分电性连接。
其中，源极与数据线电性连接，第一栅极和第二栅极均与第二栅极线电性连接。
本发明阵列基板的制造方法包括以下步骤：基板，在基板上形成缓冲层，在缓冲层内形成源极和数据线，同时在缓冲层上形成栅极和栅极线，其中缓冲层至少部分外露源极和数据线的远离基板的一侧；在源极、数据线、栅极以及栅极线上形成绝缘层，其中绝缘层至少部分外露源极和栅极线的远离基板的一侧；在源极上形成半导体层，其中半导体层与源极的外露部分电性连接且与栅极之间由绝缘层电性绝缘；在绝缘层上形成第一像素电极和第二像素电极，其中第一像素电极与半导体层的远离基板的一侧电性连接，第二像素电极与栅极线的外露部分电性连接。本发明中同时形成源极、数据线和栅极、栅极线，减少了工艺步骤，提高生产效率，减小生产成本。
【附图说明】
图1是本发明阵列基板的制造方法一实施方式的流程示意图；
图2是图1所示阵列基板的制造方法中同时形成源极、数据线、栅极和栅极线的步骤所对应的结构示意图；
图3是图1所示阵列基板的制造方法中形成绝缘层的步骤所对应的结构示意图；
图4是图1所示阵列基板的制造方法中形成半导体层的步骤所对应的结构示意图；
图5是图1所示阵列基板的制造方法中形成第一像素电极和第二像素电极的步骤所对应的结构示意图；
图6是本发明阵列基板一实施方式的结构示意图。
【具体实施方式】
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对发明所提供的一种阵列基板的制造方法及阵列基板做进一步详细描述。
参阅图1，图1是本发明阵列基板的制造方法一实施方式的流程示意图，本实施方式制造方法包括以下步骤。
S101：在基板上形成缓冲层。
请参阅图2，图2是图1所示阵列基板的制造方法中同时形成源极、数据线、栅极和栅极线的步骤所对应的结构示意图，图2中的上图为阵列基板的俯视图，下图为阵列基板A-A方向的剖视图，图3、4、5与图2类似，上图为俯视图，下图为A-A方向的剖视图。
本步骤中首先在基板11上形成的缓冲层12，该缓冲层12经过化学气相沉积及干法刻蚀的光罩制程实现图案化，图案化的缓冲层12中具有沟槽121，该沟槽121与后续步骤S102中形成的源极13和数据线14相对应，具体关系在步骤S102中再做描述。
S102：在缓冲层内形成源极和数据线，同时在缓冲层上形成栅极和栅极线。
请再次参阅图2，源极13和数据线14形成在缓冲层12内，并且缓冲层12至少部分外露源极13和数据线14的远离基板11的一侧；即源极13和数据线14并不是完全形成在缓冲层12内部而没有外露部分，其远离基板11的一侧是部分外露于缓冲层12的。形成源极13和数据线14的同时在缓冲层12上形成栅极15和栅极线16。
具体来说，步骤S101中的缓冲层12为图案化，具有沟槽121；上述源极13和数据线14则形成在沟槽121内，而栅极15和栅极线16则形成在缓冲层12上。
该步骤S102中首先在图案化的缓冲层12上物理气相沉积一导电层，利用湿法刻蚀的光罩制程对该导电层进行图案化处理，从而在沟槽内形成数据线14和源极13，并且在缓冲层上形成栅极15和栅极线16，其中数据线14和源极13电性连接。
所形成的栅极15分为第一栅极151和第二栅极152，栅极线16分为第一栅极线161和第二栅极线162。其中第一栅极151和第二栅极152均与源极13平行设置，并且都与第二栅极线162电性连接。
在本步骤S102中，源极13、数据线14、栅极15以及栅极线16采用同一金属材料制成，因此能够通过同一工艺同时制得，相比分两个工艺分别制作源极、数据线和栅极、栅极线，节省了时间，并且节约了湿法刻蚀中需要采用的铜酸，节约成本及减少工业污染。
S103：在源极、数据线、栅极以及栅极线上形成绝缘层。
请参阅图3，图3是图1所示阵列基板的制造方法中形成绝缘层的步骤所对应的结构示意图。本步骤S103中所形成的绝缘层17至少部分外露源极13和栅极线16的远离基板11的一侧。
同样，首先使用化学气相沉积一绝缘层，然后采用干法刻蚀的光罩制程进行图案化处理，使得源极13和栅极线16远离基板11的一侧有部分外露于绝缘层17。
S104：在源极上形成半导体层。
请参阅图4，图4是图1所示阵列基板的制造方法中形成半导体层的步骤所对应的结构示意图。本步骤S104所形成的半导体层18与源极13的外露部分电性连接且与栅极15之间由绝缘层17电性绝缘。
在步骤S103中，绝缘层17已将栅极15完全覆盖，因此所形成的半导体层18与栅极15之间能够由绝缘层17电性绝缘，且半导体层18为非晶硅或铟镓锌氧化物（IGZO）等有源层材料。本步骤中半导体层18主要采用了化学气相沉积和干法刻蚀工艺。
S105：在绝缘层上形成第一像素电极和第二像素电极。
请参阅图5，图5是图1所示阵列基板的制造方法中形成第一像素电极和第二像素电极的步骤所对应的结构示意图。本步骤S105中采用物理气相沉积及湿法刻蚀工艺得到图案化的像素电极层，包括第一像素电极191和第二像素电极192，完成本步骤后得到阵列基板100。
其中，第一像素电极191与半导体层18的远离基板的一侧电性连接，第二像素电极192与栅极线16的外露部分电性连接，具体的第二像素电极192分别与第一栅极线161的外露部分和第二栅极线162的外露部分电性连接，第一栅极线161和第二栅极线162通过第二像素电极192连接。
本发明阵列基板的制造方法包括以下步骤：基板，在基板上形成缓冲层，在缓冲层内形成源极和数据线，同时在缓冲层上形成栅极和栅极线，其中缓冲层至少部分外露源极和数据线的远离基板的一侧；在源极、数据线、栅极以及栅极线上形成绝缘层，其中绝缘层至少部分外露源极和栅极线的远离基板的一侧；在源极上形成半导体层，其中半导体层与源极的外露部分电性连接且与栅极之间由绝缘层电性绝缘；在绝缘层上形成第一像素电极和第二像素电极，其中第一像素电极与半导体层的远离基板的一侧电性连接，第二像素电极与栅极线的外露部分电性连接。本发明中同时形成源极、数据线和栅极、栅极线，减少了工艺步骤，提高生产效率，减小生产成本。
请参阅图6，图6是本发明阵列基板一实施方式的结构示意图。本实施方式阵列基板600包括基板61、缓冲层62、源极63、数据线64、栅极65、栅极线66、绝缘层67、半导体层68、第一像素电极691和第二像素电极692。
其中，缓冲层62形成在基板61上；缓冲层62为图案化缓冲层，其包括与源极63和数据线64对应的沟槽621。
源极63和数据线64电性连接，且形成在缓冲层62内，缓冲层62至少部分外露源极63和数据线64的远离基板的一侧。
栅极65和栅极线66，形成在缓冲层62上，栅极65包括第一栅极651和第二栅极652，第一栅极651和第二栅极652均与源极63平行设置。栅极线66包括第一栅极线661和第二栅极线662，第一栅极651和第二栅极652均与第二栅极线662电性连接。
绝缘层67，形成在源极63、数据线64、栅极65以及栅极线66上，绝缘层67至少部分外露源极63和栅极线66的远离基板61的一侧。
半导体层68，形成在源极63上，半导体层68与源极63的外露部分电性连接且与栅极65之间由绝缘层67电性绝缘。
第一像素电极691和第二像素电极692，形成在绝缘层67上，其中第一像素电极691与半导体层68的远离基板61的一侧电性连接，第二像素电极692与栅极线66的外露部分电性连接，第二像素电极692分别与第一栅极线661的外露部分和第二栅极线662的外露部分电性连接。
本实施方式阵列基板600与上述通过制造方法得到的阵列基板100类似，具体不再赘述。
本发明阵列基板基于其本身的结构能够实现在制造过程中同一工艺同时形成源极、数据线、栅极以及栅极线，因此本发明的阵列基板便于生产，且成本较低。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种阵列基板的制造方法，其中，所述制造方法包括以下步骤：
    基板；
    在所述基板上形成所述缓冲层并进行图案化处理，以在所述缓冲层上形成与所述源极和所述数据线对应的沟槽；
    在所述缓冲层上形成一导电层并进行图案化处理，以在所述沟槽内形成所述数据线和所述源极，并且在所述缓冲层上形成所述栅极和所述栅极线，其中所述缓冲层至少部分外露所述源极和所述数据线的远离所述基板的一侧；
    所述栅极包括第一栅极和第二栅极，所述第一栅极和所述第二栅极均与所述源极平行设置；
    在所述源极、所述数据线、所述栅极以及所述栅极线上形成绝缘层，其中所述绝缘层至少部分外露所述源极和所述栅极线的远离所述基板的一侧；
    在所述源极上形成半导体层，其中所述半导体层与所述源极的外露部分电性连接且与所述栅极之间由所述绝缘层电性绝缘；
    在所述绝缘层上形成第一像素电极和第二像素电极，其中所述第一像素电极与所述半导体层的远离所述基板的一侧电性连接，所述第二像素电极与所述栅极线的外露部分电性连接。
  2. 根据权利要求1所述的制造方法，其中，所述栅极线包括第一栅极线和第二栅极线，所述第二像素电极分别与所述第一栅极线的外露部分和所述第二栅极线的外露部分电性连接。
  3. 根据权利要求2所述的制造方法，其中，所述源极与所述数据线电性连接，所述第一栅极和所述第二栅极均与所述第二栅极线电性连接。
  4. 一种阵列基板的制造方法，其中，所述制造方法包括以下步骤：
    基板；
    在所述基板上形成缓冲层；
    在所述缓冲层内形成源极和数据线，同时在所述缓冲层上形成栅极和栅极线，其中所述缓冲层至少部分外露所述源极和所述数据线的远离所述基板的一侧；
    在所述源极、所述数据线、所述栅极以及所述栅极线上形成绝缘层，其中所述绝缘层至少部分外露所述源极和所述栅极线的远离所述基板的一侧；
    在所述源极上形成半导体层，其中所述半导体层与所述源极的外露部分电性连接且与所述栅极之间由所述绝缘层电性绝缘；
    在所述绝缘层上形成第一像素电极和第二像素电极，其中所述第一像素电极与所述半导体层的远离所述基板的一侧电性连接，所述第二像素电极与所述栅极线的外露部分电性连接。
  5. 根据权利要求4所述的制造方法，其中，所述在所述缓冲层内形成源极和数据线，同时在所述缓冲层上形成栅极和栅极线的步骤包括：
    在所述基板上形成所述缓冲层并进行图案化处理，以在所述缓冲层上形成与所述源极和所述数据线对应的沟槽；
    在所述缓冲层上形成一导电层并进行图案化处理，以在所述沟槽内形成所述数据线和所述源极，并且在所述缓冲层上形成所述栅极和所述栅极线。
  6. 根据权利要求4所述的制造方法，其中，所述栅极包括第一栅极和第二栅极，所述第一栅极和所述第二栅极均与所述源极平行设置。
  7. 根据权利要求6所述的制造方法，其中，所述栅极线包括第一栅极线和第二栅极线，所述第二像素电极分别与所述第一栅极线的外露部分和所述第二栅极线的外露部分电性连接。
  8. 根据权利要求7所述的制造方法，其中，所述源极与所述数据线电性连接，所述第一栅极和所述第二栅极均与所述第二栅极线电性连接。
  9. 一种阵列基板，其中，所述阵列基板包括：
    基板；
    缓冲层，形成在所述基板上；
    源极和数据线，形成在所述缓冲层内，所述缓冲层至少部分外露所述源极和所述数据线的远离所述基板的一侧；
    栅极和栅极线，形成在所述缓冲层上；
    绝缘层，形成在所述源极、所述数据线、所述栅极以及所述栅极线上，所述绝缘层至少部分外露源极和所述栅极线的远离所述基板的一侧；
    半导体层，形成在所述源极上，所述半导体层与所述源极的外露部分电性连接且与所述栅极之间由所述绝缘层电性绝缘；
    第一像素电极和第二像素电极，形成在所述绝缘层上，其中所述第一像素电极与所述半导体层的远离所述基板的一侧电性连接，所述第二像素电极与所述栅极线的外露部分电性连接。
  10. 根据权利要求9所述的阵列基板，其中，所述缓冲层为图案化缓冲层，所述图案化缓冲层上包括与所述源极和所述数据线对应的沟槽；所述源极和所述数据线形成于所述沟槽内，所述栅极和所述栅极线形成在所述缓冲层上。
  11. 根据权利要求9所述的阵列基板，其中，所述栅极包括第一栅极和第二栅极，所述第一栅极和所述第二栅极均与所述源极平行设置。
  12. 根据权利要求11所述的阵列基板，其中，所述栅极线包括第一栅极线和第二栅极线，所述第二像素电极分别与所述第一栅极线的外露部分和所述第二栅极线的外露部分电性连接。
  13. 根据权利要求12所述的阵列基板，其中，所述源极与所述数据线电性连接，所述第一栅极和所述第二栅极均与所述第二栅极线电性连接。
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