WO2017024605A1 - 一种ffs阵列基板的制造方法 - Google Patents

一种ffs阵列基板的制造方法 Download PDF

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Publication number
WO2017024605A1
WO2017024605A1 PCT/CN2015/087379 CN2015087379W WO2017024605A1 WO 2017024605 A1 WO2017024605 A1 WO 2017024605A1 CN 2015087379 W CN2015087379 W CN 2015087379W WO 2017024605 A1 WO2017024605 A1 WO 2017024605A1
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layer
semiconductor active
active layer
precursor
pixel electrode
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PCT/CN2015/087379
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English (en)
French (fr)
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葛世民
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深圳市华星光电技术有限公司
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Priority to US14/891,904 priority Critical patent/US20180188618A1/en
Publication of WO2017024605A1 publication Critical patent/WO2017024605A1/zh

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    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
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Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a method for fabricating an FFS array substrate.
  • Fringe Field Switch (Fringe Field Switching (FFS) technology is a current liquid crystal display technology, which is a wide viewing angle technology developed by the liquid crystal industry to solve large-size, high-definition desktop displays and LCD TV applications.
  • the FFS liquid crystal panel has the advantages of fast response time, high light transmittance, wide viewing angle and low color shift.
  • amorphous silicon (a-Si) and polycrystalline silicon (p-Si) are thin film transistors (Thin Film).
  • Transistor, TFT is a mainstream semiconductor material in which amorphous silicon is the most widely used, but amorphous silicon has problems such as low electron mobility and poor light stability.
  • polycrystalline silicon is better than amorphous silicon in terms of electron mobility, it has problems such as complicated structure, large leakage current, and poor uniformity of film quality.
  • people have put forward higher and higher requirements for the performance of TFTs.
  • Amorphous silicon and polysilicon have not fully met these requirements.
  • the pixel electrode is generally made of transparent indium tin oxide (Indium Tin) Oxide, ITO) material, in the fabrication of the semiconductor active layer of the TFT and the pixel electrode, it is necessary to use two mask processes to separately fabricate the semiconductor active layer and the pixel electrode of the TFT, which would require more use. More reticle, as well as more complex manufacturing processes, reduce production efficiency.
  • ITO transparent indium tin oxide
  • An object of the present invention is to provide a method of manufacturing an FFS array substrate which can reduce the number of masks and improve the manufacturing efficiency of the FFS array substrate.
  • a method of manufacturing an FFS array substrate comprising the steps of:
  • a passivation layer is formed on the source, the drain, the semiconductor active layer, and the pixel electrode.
  • the gate electrode and the common electrode are formed by sequentially depositing an ITO layer and a metal layer on the glass substrate, and then performing a patterning process on the ITO layer and the metal layer. Forming the gate and the common electrode.
  • the material of the transparent metal oxide semiconductor is IGZO.
  • the material of the transparent metal oxide semiconductor is ITZO.
  • the ion implantation is performed by plasma processing both ends of the semiconductor active layer precursor and the pixel electrode precursor.
  • the ion is a H ion.
  • the ion is an Ar ion.
  • the method before the forming a source and a drain on the semiconductor active layer, the method further includes the steps of: forming an etch stop layer on the semiconductor active layer and the pixel electrode, and A corresponding via hole is formed on both ends of the semiconductor active layer and on one end of the pixel electrode adjacent to the semiconductor active layer, so that both ends of the semiconductor active layer and the semiconductor are adjacent to the semiconductor One end of the pixel electrode of the active layer is exposed.
  • the material for forming the etch barrier layer is silicon oxide.
  • a method of manufacturing an FFS array substrate comprising the steps of:
  • a source and a drain are formed on the semiconductor active layer.
  • the step further includes forming a passivation layer on the source, the drain, the semiconductor active layer, and the pixel electrode.
  • the gate electrode and the common electrode are formed by sequentially depositing an ITO layer and a metal layer on the glass substrate, and then performing a patterning process on the ITO layer and the metal layer. Forming the gate and the common electrode.
  • the material of the transparent metal oxide semiconductor is IGZO.
  • the material of the transparent metal oxide semiconductor is ITZO.
  • the ion implantation is performed by plasma processing both ends of the semiconductor active layer precursor and the pixel electrode precursor.
  • the ions are H ions.
  • the ions are Ar ions.
  • the method further includes the steps of: forming an etch stop layer on the semiconductor active layer and the pixel electrode, and A corresponding via hole is formed on both ends of the semiconductor active layer and on one end of the pixel electrode adjacent to the semiconductor active layer, so that both ends of the semiconductor active layer and the semiconductor are One end of the pixel electrode of the source layer is exposed.
  • the gate insulating layer is made of silicon oxide.
  • the gate insulating layer is made of a two-layer film of silicon oxide and silicon nitride.
  • the method for manufacturing an FFS array substrate of the present invention can simultaneously manufacture a semiconductor active layer and a pixel electrode through a photomask by simultaneously manufacturing a gate electrode and a common electrode through a photomask, thereby reducing the number of masks, reducing the manufacturing cost, and improving the manufacturing cost.
  • the manufacturing efficiency of the FFS array substrate, and the replacement of amorphous silicon and polycrystalline silicon by the metal oxide semiconductor as the semiconductor material of the thin film transistor, the electron mobility and the aperture ratio of the semiconductor active layer are higher, the light stability and the light transmittance. better.
  • Embodiment 1 is a flow chart showing a manufacturing method of Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural view showing formation of a gate electrode and a common electrode on a substrate according to Embodiment 1 of the present invention
  • FIG. 3 is a schematic structural view showing formation of a gate insulating layer on a substrate according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic view showing a semiconductor active layer precursor and a pixel electrode precursor covered by a photoresist layer in a process of patterning a metal oxide semiconductor on a substrate according to Embodiment 1 of the present invention
  • FIG. 5 is a schematic view showing a photoresist layer covering a middle portion of a semiconductor active layer precursor on a substrate of Embodiment 1 of the present invention
  • FIG. 6 is a schematic view showing a semiconductor active layer precursor and a pixel electrode precursor on a substrate of Example 1 after being ion-implanted to form a semiconductor active layer and a pixel electrode, respectively;
  • FIG. 7 is a schematic view showing a source and a drain formed on a semiconductor active layer on a substrate of Embodiment 1 of the present invention.
  • FIG. 8 is a schematic view of the substrate, the drain electrode, and the pixel electrode covered with a passivation layer on the substrate of Embodiment 1 of the present invention
  • FIG. 9 is a schematic view of the semiconductor active layer and the pixel electrode covered with an etch stop layer on the substrate of Embodiment 2 of the present invention.
  • FIG. 10 is a schematic view showing a source and a drain formed on an etch barrier layer on a substrate according to Embodiment 2 of the present invention.
  • Figure 11 is a schematic view showing a passivation layer formed on a source, a drain, and an etch barrier layer on a substrate of Example 2 of the present invention.
  • FIG. 1 is a flowchart of a method for fabricating an FFS array substrate according to the embodiment
  • FIG. 2 to FIG. 8 are sequence diagrams of fabricating an FFS array substrate according to the embodiment.
  • the method for manufacturing an FFS array substrate of the embodiment includes the following steps:
  • a gate electrode 3 and a common electrode 2 are formed on the glass substrate 1, and the gate electrode 3 is formed on a portion of the common electrode 2.
  • the specific fabrication process is as follows: an ITO layer is deposited on the glass substrate 1, and a metal layer is deposited on the ITO layer. The material of the metal layer may be copper or aluminum, or may be other metals. Then, the ITO layer and the metal layer are patterned once, that is, through a mask process, including photoresist coating, exposure, development, etching, and photoresist removal to form the gate. 3 and the common electrode 2.
  • the common electrode 2 and the gate electrode 3 are formed, and the gate electrode 3 is provided on a portion of the ITO layer, which is separated from the common electrode 2.
  • the gate electrode 3 is usually formed on the glass substrate 1 , then the gate insulating layer 4 is formed on the gate electrode 3 , and then the common electrode 2 is formed on the gate insulating layer 4 .
  • Two reticle processes are required to separately manufacture, and this step reduces the manufacturing process of a reticle process and reduces the manufacturing cost compared with the prior art.
  • FIG. 3 is a schematic structural view of forming a gate insulating layer on the substrate of the embodiment.
  • a gate insulating layer 4 is formed on the gate 3 and the common electrode 2.
  • the material of the gate insulating layer 4 may be silicon oxide or silicon nitride.
  • This step is preferably a double film of silicon oxide or silicon oxide and silicon nitride, and may be other suitable materials.
  • the gate insulating layer 4 is plasma enhanced chemical vapor deposition (Plasma) Enhanced Chemical Vapor Deposition (PECVD) method for deposition.
  • S103 depositing a transparent metal oxide semiconductor layer on the gate insulating layer 4.
  • the material of the transparent metal oxide semiconductor is indium gallium zinc oxide (Indium Gallium) Zinc Oxide, IGZO) or Indium Tin Zinc Oxide (ITZO), in this embodiment, indium gallium zinc oxide is preferred.
  • S104 performing a patterning process on the transparent metal oxide semiconductor layer, that is, on the indium gallium zinc oxide layer, to form the semiconductor active layer precursor 5 and the pixel electrode precursor 6, and only making the semiconductor active
  • a photoresist layer 7 is formed on the intermediate portion of the layer precursor 5.
  • the patterning process includes processes such as photoresist coating, exposure, development, etching, and photoresist removal layer 7.
  • a special feature of this embodiment is that, when the photoresist layer 7 is removed, the photoresist layer 7 on the pixel electrode precursor 6 is completely removed, and for the semiconductor active layer precursor 5, only the upper two are removed.
  • the photoresist layer 7 at the end retains the photoresist layer 7 above the intermediate portion thereof, and the photoresist layer 7 on the intermediate portion of the semiconductor active layer precursor 5 serves as a protective layer for the ion implantation process of the next step.
  • the semiconductor active layer precursor 5 and the pixel electrode precursor 6 are covered by the photoresist layer 7 during patterning of the metal oxide semiconductor on the glass substrate 1 of the present embodiment, as shown in FIG. 5.
  • the upper portion of the intermediate portion of the semiconductor active layer precursor 5 on the glass substrate 1 of the present embodiment is covered with a photoresist layer 7.
  • the ion implantation method of this embodiment is: performing plasma treatment on both ends of the semiconductor active layer precursor 5 and the pixel electrode precursor 6, in this step, due to the middle portion of the semiconductor active layer precursor 5
  • the upper portion is protected by the photoresist layer 7, so that during the ion implantation, the intermediate portion of the semiconductor active layer precursor 5 is not damaged by the ion implantation, and remains as a semiconductor, and the semiconductor active layer precursor 5 is
  • the terminals and the pixel electrode precursor 6 are all replaced by conductors without the protection of the photoresist layer 7.
  • the ions are H ions or Ar ions.
  • the semiconductor active layer precursor 5 and the pixel electrode precursor 6 on the glass substrate 1 of the present embodiment are subjected to ion implantation treatment to form a semiconductor active layer 8 and a pixel electrode 9, respectively.
  • the present embodiment uses a metal oxide semiconductor, that is, indium gallium zinc oxide instead of the conventional amorphous silicon or polycrystalline silicon, as the material of the TFT semiconductor active layer 8, the electron mobility and the aperture ratio of the semiconductor active layer 8 are made more. High, light stability and light transmission are better.
  • the pixel electrode 9 is generally processed by an ITO process, and the semiconductor active layer 8 and the pixel electrode 9 are required to be completed by two separate photomask processes, and the effect is not as good as the embodiment.
  • S106 Forming the source 10 and the drain 11 on the semiconductor active layer 8. As shown in FIG. 7, a schematic view of the source substrate 10 and the drain electrode 11 formed on the semiconductor active layer 8 on the glass substrate 1 of the present embodiment.
  • the embodiment further includes forming a passivation layer 12 on the source 10, the drain 11, the semiconductor active layer 8, and the pixel electrode 9.
  • a schematic view of the glass substrate 1 of the first embodiment of the present invention in which the passivation layer 12 is covered on the source 10, the drain 11, and the pixel electrode 9 is shown.
  • the front portion of this embodiment is the same as S101 to S105 of Embodiment 1, except that after S105, before the source 10 and the drain 11 are formed on the semiconductor active layer 8, the method further includes the steps of: An etch stop layer 13 is formed on the semiconductor active layer 8 and the pixel electrode 9.
  • the etch stop layer 13 is made of silicon oxide. Further, at least one end of the semiconductor active layer 8 and the corresponding etch stop layer 13 on one end of the pixel electrode 9 adjacent to the semiconductor active layer 8 form a via hole to make the semiconductor active Both ends of the layer 8 and one end of the pixel electrode 9 adjacent to the semiconductor active layer 8 are exposed to prepare the source 10 and the drain 11 for the next step.
  • the source 10 and the drain 11 are formed on the etch barrier layer 13 corresponding to the semiconductor active layer 8.
  • the semiconductor active layer 8 and the pixel electrode 9 have been covered with an etch stop layer 13, so that the semiconductor active layer 8 is not damaged during the formation of the source 10 and the drain 11.
  • the middle part is covered with a passivation layer 12 is overlaid on the source 10, the drain 11 and the etch stop layer 13, and all the fabrication processes are completed.

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Abstract

一种FFS阵列基板的制造方法，包括：在玻璃基板（1）上形成栅极（3）与公共电极（2），栅极（3）形成在公共电极（2）的一部分上面；形成一层栅极绝缘层（4）；形成半导体有源层前体（5）与像素电极前体（6）；对所述半导体有源层前体（5）的没留有光阻层（7）的两端及所述像素电极前体（6）进行离子注入处理以使它们形成透明导体；最后形成源极（10）与漏极（11）。

Description

一种FFS阵列基板的制造方法 技术领域
本发明涉及液晶显示器技术领域，特别涉及一种FFS阵列基板的制造方法。
 背景技术
边缘场开关（Fringe Field Switching，简称FFS）技术，是目前的一种液晶显示器技术，是液晶界为解决大尺寸，高清晰桌面显示器和液晶电视应用而开发的一种广视角技术。FFS液晶面板具有响应时间快、光透过率高，宽视角及较低的色偏等优点。
目前，非晶硅（a-Si）和多晶硅（p-Si）是薄膜晶体管（Thin Film Transistor，TFT）主流的半导体材料，其中非晶硅应用最为广泛，但是非晶硅具有电子迁移率低、光照稳定性差等问题。多晶硅在电子迁移率方面虽然比非晶硅好，但是具有构造复杂、漏电流大，膜质均一性差等问题。总的来说，随着显示技术的飞快发展，人们对TFT的性能提出了越来越高的要求，非晶硅和多晶硅已经不能完全满足这些要求。
另外，像素电极一般由透明的氧化铟锡（Indium Tin Oxide，ITO）材料制成，在制作TFT的半导体有源层和像素电极时，需要采用两道光罩（mask）制程，以分别制作TFT的半导体有源层和像素电极，这样做会需要使用更多的光罩，以及更复杂的制作工艺，降低了生产效率。
 技术问题
本发明的目的在于提供一种FFS阵列基板的制造方法，该制造方法能够减少光罩次数，提高FFS阵列基板的制造效率。
 技术解决方案
一种FFS阵列基板的制造方法，其包括以下步骤：
在玻璃基板上形成栅极与公共电极，所述栅极形成在所述公共电极的一部分上面；
在所述栅极与所述公共电极上形成一层栅极绝缘层；
在所述栅极绝缘层上沉淀一层透明金属氧化物半导体层；
对所述透明金属氧化物半导体层进行一次图案化处理，以形成半导体有源层前体与像素电极前体，并仅使所述半导体有源层前体的中间部分上面有光阻层；
对所述半导体有源层前体的没有所述光阻层的两端及所述像素电极前体进行离子注入处理，以将它们变成透明导体，使所述半导体有源层前体变为半导体有源层，并使所述像素电极前体变为像素电极；
在所述半导体有源层上形成源极与漏极；以及
在所述源极、漏极、半导体有源层以及像素电极上形成一层钝化层。
优选地，其中所述栅极与公共电极的制作过程为：在所述玻璃基板上依次沉淀一层ITO层与一层金属层，再对所述ITO层与所述金属层进行一次图案化处理，以形成所述栅极与所述公共电极。
优选地，其中所述透明金属氧化物半导体的材料为IGZO。
优选地，其中所述透明金属氧化物半导体的材料为ITZO。
优选地，其中所述离子注入的方式为：对所述半导体有源层前体两端与所述像素电极前体进行等离子体处理。
优选地，其中所述离子为H离子。
优选地，其中所述离子为Ar离子。
优选地，其中所述的在所述半导体有源层上形成源极与漏极之前，还包括步骤：在所述半导体有源层及所述像素电极上形成一层刻蚀阻挡层，并在所述半导体有源层两端及靠近所述半导体有源层的所述像素电极的一端上对应的所述刻蚀阻挡层形成过孔，使所述半导体有源层两端及靠近所述半导体有源层的所述像素电极的一端暴露出来。
优选地，其中所述刻蚀阻挡层的制作材料为氧化硅。
一种FFS阵列基板的制造方法，其包括以下步骤：
在玻璃基板上形成栅极与公共电极，所述栅极形成在所述公共电极的一部分上面；
在所述栅极与所述公共电极上形成一层栅极绝缘层；
在所述栅极绝缘层上沉淀一层透明金属氧化物半导体层；
对所述透明金属氧化物半导体层进行一次图案化处理，以形成半导体有源层前体与像素电极前体，并仅使所述半导体有源层前体的中间部分上面有光阻层；
对所述半导体有源层前体的没有所述光阻层的两端及所述像素电极前体进行离子注入处理，以将它们变成透明导体，使所述半导体有源层前体变为半导体有源层，并使所述像素电极前体变为像素电极；以及
在所述半导体有源层上形成源极与漏极。
优选地，所述步骤还包括，在所述源极、漏极、半导体有源层以及像素电极上形成一层钝化层。
优选地，所述栅极与公共电极的制作过程为：在所述玻璃基板上依次沉淀一层ITO层与一层金属层，再对所述ITO层与所述金属层进行一次图案化处理，以形成所述栅极与所述公共电极。
优选地，所述透明金属氧化物半导体的材料为IGZO。
优选地，所述透明金属氧化物半导体的材料为ITZO。
优选地，所述离子注入的方式为：对所述半导体有源层前体两端与所述像素电极前体进行等离子体处理。
优选地，所述离子为H离子。
优选地，所述离子为Ar离子。
优选地，所述的在所述半导体有源层上形成源极与漏极之前，还包括步骤：在所述半导体有源层及所述像素电极上形成一层刻蚀阻挡层，并在所述半导体有源层两端及靠近所述半导体有源层的所述像素电极的一端上对应的所述刻蚀阻挡层形成过孔，使所述半导体有源层两端及靠近所述半导体有源层的所述像素电极的一端暴露出来。
优选地，所述栅极绝缘层的制作材料为氧化硅。
优选地，所述栅极绝缘层的制作材料为氧化硅与氮化硅的双层膜。
 有益效果
本发明的一种FFS阵列基板的制造方法，通过一道光罩同时制造栅极和公共电极，通过一道光罩同时制造半导体有源层和像素电极，能够减少光罩次数，降低了制作成本，提高FFS阵列基板的制造效率，并且用金属氧化物半导体替代非晶硅和多晶硅作为薄膜晶体管的半导体材料，会使得半导体有源层的电子迁移率和开口率更高，光照稳定性以及光透过性更好。
 附图说明
图1为本发明的实施例1的制造方法流程图；
图2为本发明的实施例1的基板上的形成栅极与公共电极的结构示意图；
图3为本发明的实施例1的基板上的形成栅极绝缘层的结构示意图；
图4为本发明的实施例1的基板上的对金属氧化物半导体进行图案化过程中半导体有源层前体和像素电极前体被光阻层覆盖示意图；
图5为本发明的实施例1的基板上的半导体有源层前体中间部分上面覆盖光阻层示意图；
图6为本发明的实施例1的基板上的半导体有源层前体和像素电极前体被离子注入处理后分别形成半导体有源层和像素电极后的示意图；
图7为本发明的实施例1的基板上的在半导体有源层上形成源极和漏极后的示意图；
图8为本发明的实施例1的基板上的在源极、漏极和像素电极上覆盖钝化层后的示意图；
图9为本发明的实施例2的基板上的在半导体有源层和像素电极上覆盖一层刻蚀阻挡层后的示意图；
图10为本发明的实施例2的基板上的在刻蚀阻挡层上形成源极和漏极后的示意图；
图11为本发明的实施例2的基板上的在源极、漏极和刻蚀阻挡层上形成钝化层后的示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
实施例1
如图1所示为本实施例的一种FFS阵列基板的制造方法的流程图，图2至图8为本实施例制作FFS阵列基板的顺序图。
从图1可以看出，本实施例的一种FFS阵列基板的制造方法，包括以下几个步骤：
S101：如图2所示，在玻璃基板1上形成栅极3与公共电极2，所述栅极3形成在所述公共电极2的一部分上面。具体制作过程为：现在玻璃基板1上沉淀一层ITO层，再在该ITO层上沉淀一层金属层，该金属层的材料可以是铜或铝，也可以是其它金属。然后再对所述ITO层与所述金属层进行一次图案化处理，即通过一道光罩工艺，包括光阻涂布、曝光、显影、刻蚀和去光阻等工序，以形成所述栅极3与所述公共电极2。本步骤中，为了只用一道光罩工艺，就形成公共电极2和栅极3，将栅极3设在了ITO层的一部分上，该部分ITO层与公共电极2相隔开。在现有技术中，通常是先在玻璃基板1上形成栅极3，接着在栅极3上形成栅极绝缘层4，然后才在栅极绝缘层4上形成公共电极2，这种制作方法需要两道光罩工艺分别制作才能完成，本步骤相对于现有技术来说，减少了一道光罩工艺制程，降低了制作成本。
S102：如图3所示，为本实施例的基板上的形成栅极绝缘层的结构示意图。本步骤是在所述栅极3与所述公共电极2上形成一层栅极绝缘层4。该栅极绝缘层4的制作材料可以为氧化硅或者氮化硅，本步骤优选为氧化硅或氧化硅与氮化硅的双层膜，也可以是其它合适的材料。该栅极绝缘层4是通过等离子体增强化学气相沉积（Plasma Enhanced Chemical Vapor Deposition,PECVD）方法沉积形成的。
S103：在所述栅极绝缘层4上沉淀一层透明金属氧化物半导体层。该透明金属氧化物半导体的材料为铟镓锌氧化物（Indium Gallium Zinc Oxide，IGZO）或者铟锡锌氧化物（Indium Tin Zinc Oxide，ITZO），本实施例优选铟镓锌氧化物。
S104：对所述透明金属氧化物半导体层，即对铟镓锌氧化物层进行一次图案化处理，以形成半导体有源层前体5与像素电极前体6，并仅使所述半导体有源层前体5的中间部分上面有光阻层7。其中，所述图案化处理包括光阻涂布、曝光、显影、刻蚀和去光阻层7等工序。本实施例的一个特别之处就是，在去光阻层7的时候，把像素电极前体6上面的光阻层7全部去掉，而对于半导体有源层前体5，则只是去除它上面两端的光阻层7，保留其中间部分上面的光阻层7，半导体有源层前体5中间部分上面的光阻层7作为下一步骤的离子注入处理的保护层。如图4所示，为本实施例的玻璃基板1上的对金属氧化物半导体进行图案化过程中半导体有源层前体5和像素电极前体6被光阻层7覆盖示意图，如图5所示，为本实施例的玻璃基板1上的半导体有源层前体5中间部分上面覆盖光阻层7示意图。
S105：对所述半导体有源层前体5的没有所述光阻层7的两端及所述像素电极前体6进行离子注入处理，以将它们变成透明导体，使所述半导体有源层前体5变为半导体有源层8，并使所述像素电极前体6变为像素电极9。本实施例的离子注入的方式为：对所述半导体有源层前体5两端与所述像素电极前体6进行等离子体处理，在本步骤中，由于半导体有源层前体5中间部分的上面有光阻层7保护，所以在离子注入的过程中，半导体有源层前体5中间部分不会受到离子注入的影响破坏，仍然维持为半导体，而半导体有源层前体5的两端以及像素电极前体6，由于没有了光阻层7的保护，全部变为导体。另外本实施例优选所述离子为H离子或Ar离子。如图6所示，为本实施例的玻璃基板1上的半导体有源层前体5和像素电极前体6被离子注入处理后分别形成半导体有源层8和像素电极9后的示意图。
从S104和S105这两个步骤可以看出，本实施例在制作半导体有源层8和像素电极9时，只需要一道光罩工艺制程。另外由于本实施例使用金属氧化物半导体即铟镓锌氧化物替代传统的非晶硅或多晶硅，作为TFT半导体有源层8的材料，会使得半导体有源层8的电子迁移率和开口率更高，光照稳定性以及光透过性更好。而在现有技术中，像素电极9一般由ITO制程，半导体有源层8和像素电极9需要两道独立的光罩工艺制程来完成，而且效果没有本实施例好。
S106：在所述半导体有源层8上形成源极10与漏极11。如图7所示，为本实施例的玻璃基板1上的在半导体有源层8上形成源极10和漏极11后的示意图。
除了以上制作步骤外，本实施例还包括，在所述源极10、漏极11、半导体有源层8以及像素电极9上形成一层钝化层12。如图8所示，为本发明的实施例1的玻璃基板1上的在源极10、漏极11和像素电极9上覆盖钝化层12后的示意图。
实施例2
本实施例的前面部分与实施例1的S101～S105相同，所不同的是在S105之后，在所述半导体有源层8上形成源极10与漏极11之前，还包括步骤：在所述半导体有源层8及所述像素电极9上形成一层刻蚀阻挡层13，本实施例优选所述刻蚀阻挡层13的制作材料为氧化硅。另外还在所述半导体有源层8两端，以及靠近所述半导体有源层8的所述像素电极9的一端上对应的所述刻蚀阻挡层13形成过孔，使所述半导体有源层8两端及靠近所述半导体有源层8的所述像素电极9的一端暴露出来，为下一步骤形成源极10和漏极11做准备。
接下来就是在所述半导体有源层8对应的刻蚀阻挡层13上形成源极10和漏极11。在上一步骤中，已经在半导体有源层8和像素电极9上覆盖了一层刻蚀阻挡层13，因此在形成源极10和漏极11的过程中不会损伤到半导体有源层8的中间部分。最后再在源极10、漏极11和刻蚀阻挡层13上面覆盖一层钝化层12，至此所有制作工艺全部完成。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种FFS阵列基板的制造方法，其包括以下步骤：
    在玻璃基板上形成栅极与公共电极，所述栅极形成在所述公共电极的一部分上面；
    在所述栅极与所述公共电极上形成一层栅极绝缘层；
    在所述栅极绝缘层上沉淀一层透明金属氧化物半导体层；
    对所述透明金属氧化物半导体层进行一次图案化处理，以形成半导体有源层前体与像素电极前体，并仅使所述半导体有源层前体的中间部分上面有光阻层；
    对所述半导体有源层前体的没有所述光阻层的两端及所述像素电极前体进行离子注入处理，以将它们变成透明导体，使所述半导体有源层前体变为半导体有源层，并使所述像素电极前体变为像素电极；
    在所述半导体有源层上形成源极与漏极；以及
    在所述源极、漏极、半导体有源层以及像素电极上形成一层钝化层。
  2. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述栅极与公共电极的制作过程为：在所述玻璃基板上依次沉淀一层ITO层与一层金属层，再对所述ITO层与所述金属层进行一次图案化处理，以形成所述栅极与所述公共电极。
  3. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述透明金属氧化物半导体的材料为IGZO。
  4. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述透明金属氧化物半导体的材料为ITZO。
  5. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述离子注入的方式为：对所述半导体有源层前体两端与所述像素电极前体进行等离子体处理。
  6. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述离子为H离子。
  7. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述离子为Ar离子。
  8. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述的在所述半导体有源层上形成源极与漏极之前，还包括步骤：在所述半导体有源层及所述像素电极上形成一层刻蚀阻挡层，并在所述半导体有源层两端及靠近所述半导体有源层的所述像素电极的一端上对应的所述刻蚀阻挡层形成过孔，使所述半导体有源层两端及靠近所述半导体有源层的所述像素电极的一端暴露出来。
  9. 根据权利要求1所述的FFS阵列基板的制造方法，其中所述刻蚀阻挡层的制作材料为氧化硅。
  10. 一种FFS阵列基板的制造方法，其其包括以下步骤：
    在玻璃基板上形成栅极与公共电极，所述栅极形成在所述公共电极的一部分上面；
    在所述栅极与所述公共电极上形成一层栅极绝缘层；
    在所述栅极绝缘层上沉淀一层透明金属氧化物半导体层；
    对所述透明金属氧化物半导体层进行一次图案化处理，以形成半导体有源层前体与像素电极前体，并仅使所述半导体有源层前体的中间部分上面有光阻层；
    对所述半导体有源层前体的没有所述光阻层的两端及所述像素电极前体进行离子注入处理，以将它们变成透明导体，使所述半导体有源层前体变为半导体有源层，并使所述像素电极前体变为像素电极；以及
    在所述半导体有源层上形成源极与漏极。
  11. 根据权利要求10所述的FFS阵列基板的制造方法，其中所述步骤还包括，在所述源极、漏极、半导体有源层以及像素电极上形成一层钝化层。
  12. 根据权利要求10所述的FFS阵列基板的制造方法，其中所述栅极与公共电极的制作过程为：在所述玻璃基板上依次沉淀一层ITO层与一层金属层，再对所述ITO层与所述金属层进行一次图案化处理，以形成所述栅极与所述公共电极。
  13. 根据权利要求10所述的FFS阵列基板的制造方法，其中所述透明金属氧化物半导体的材料为IGZO。
  14. 根据权利要求10所述的FFS阵列基板的制造方法，其中所述透明金属氧化物半导体的材料为ITZO。
  15. 根据权利要求10所述的FFS阵列基板的制造方法，其中所述离子注入的方式为：对所述半导体有源层前体两端与所述像素电极前体进行等离子体处理。
  16. 根据权利要求10所述的FFS阵列基板的制造方法，其中所述离子为H离子。
  17. 根据权利要求10所述的FFS阵列基板的制造方法，其中所述离子为Ar离子。
  18. 根据权利要求10所述的FFS阵列基板的制造方法，其中所述的在所述半导体有源层上形成源极与漏极之前，还包括步骤：在所述半导体有源层及所述像素电极上形成一层刻蚀阻挡层，并在所述半导体有源层两端及靠近所述半导体有源层的所述像素电极的一端上对应的所述刻蚀阻挡层形成过孔，使所述半导体有源层两端及靠近所述半导体有源层的所述像素电极的一端暴露出来。
  19. 根据权利要求10所述的FFS阵列基板的制造方法，其中所述栅极绝缘层的制作材料为氧化硅。
  20. 根据权利要求1所述的FFS阵列基板的制造方法，其特征在于，所述栅极绝缘层的制作材料为氧化硅与氮化硅的双层膜。
PCT/CN2015/087379 2015-08-12 2015-08-18 一种ffs阵列基板的制造方法 WO2017024605A1 (zh)

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