WO2017152522A1 - 金属氧化物薄膜晶体管及其制作方法、阵列基板 - Google Patents

金属氧化物薄膜晶体管及其制作方法、阵列基板 Download PDF

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Publication number
WO2017152522A1
WO2017152522A1 PCT/CN2016/084762 CN2016084762W WO2017152522A1 WO 2017152522 A1 WO2017152522 A1 WO 2017152522A1 CN 2016084762 W CN2016084762 W CN 2016084762W WO 2017152522 A1 WO2017152522 A1 WO 2017152522A1
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barrier layer
metal oxide
drain
source
layer
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PCT/CN2016/084762
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English (en)
French (fr)
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姚江波
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深圳市华星光电技术有限公司
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Priority to US15/120,753 priority Critical patent/US9634036B1/en
Publication of WO2017152522A1 publication Critical patent/WO2017152522A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure

Definitions

  • the present invention relates to the field of displays, and in particular to a metal oxide thin film transistor, a method of fabricating the same, and an array substrate.
  • the metal oxide TFT process generally uses copper as an electrode because of its excellent electrical conductivity.
  • copper since copper has a certain diffusibility, when the thin film transistor is turned on, copper may diffuse to the metal oxide active layer, affecting the electrical conductivity of the metal oxide active layer. Therefore, in the prior art, copper is not used alone, but a multilayer structure including a diffusion barrier layer and a copper layer is employed.
  • the barrier layer is generally formed by using Mo and Ti to block the diffusion of copper to the active layer of the metal oxide.
  • the thicker the diffusion barrier layer the better the effect of blocking the diffusion of copper to the metal oxide active layer, but the manufacturer has strict requirements on cost and device thickness, and the diffusion barrier layer cannot be done too much. Thickness; at the same time, in order to improve the performance of the device, the thin film transistor is annealed after it is formed. The annealing process needs to be realized in a high temperature environment, and the copper diffusion is intensified at a high temperature, which causes the diffusion barrier to prevent copper diffusion. The effect is poor, which in turn affects the electrical conductivity of the active layer of the metal oxide, thereby affecting the performance of the thin film transistor.
  • An object of the present invention is to provide a metal oxide thin film transistor, a method for fabricating the same, and an array substrate; and to solve the technical problem that the effect of the diffusion barrier of the conventional diffusion barrier layer is poor.
  • a metal oxide thin film transistor comprising:
  • a gate insulating layer disposed on the gate and the glass substrate;
  • a metal oxide active layer disposed on the gate insulating layer
  • a diffusion barrier layer comprising a source barrier layer and a drain barrier layer, the source barrier layer and the drain barrier layer being respectively disposed in the source via and the drain via, and in contact with the metal oxide active layer,
  • the diffusion barrier layer is doped with a predetermined concentration of boron ions and/or phosphorus ions;
  • drain disposed on the drain barrier layer.
  • the diffusion barrier layer comprises a molybdenum metal and a titanium metal.
  • the metal oxide active layer is an indium gallium zinc oxide active layer.
  • the diffusion barrier layer has a thickness of from 100 angstroms to 500 angstroms.
  • the diffusion barrier layer is doped with boron ions and phosphorus ions, and the doping concentration of boron ions and phosphorus ions is 10% to 90%.
  • the doping concentration is successively decreased from the side of the diffusion barrier layer close to the source and the drain to the side close to the metal oxide active layer.
  • the present invention also provides an array substrate comprising the metal oxide thin film transistor according to any of the above.
  • the invention also provides a method for fabricating a metal oxide thin film transistor, comprising the following steps:
  • a gate electrode Forming a gate electrode, a gate insulating layer, a metal oxide active layer, and an etch barrier layer on the glass substrate, wherein the etch barrier layer is provided with a source via hole and a drain via hole;
  • the diffusion barrier layer includes a source barrier layer and a drain barrier layer, the source barrier layer and the drain barrier layer being respectively disposed on the source via and the drain via And in contact with the metal oxide active layer;
  • a source is formed on the source barrier layer, and a drain is formed on the drain barrier layer.
  • the diffusion barrier layer is doped with boron ions and phosphorus ions, and the doping concentration of boron ions and phosphorus ions is 10% to 90%.
  • doping from a side of the diffusion barrier layer close to the source and the drain to a side close to the metal oxide active layer The concentration is decreasing in turn.
  • the metal oxide thin film transistor of the preferred embodiment of the present invention employs boron ions and/or phosphorus ions in the diffusion barrier layer to improve the barrier property of the diffusion barrier layer to the copper ion diffusion of the source and the drain.
  • the diffusion of copper ions at the source and the drain of the high temperature process to the active layer of the metal oxide can be prevented from affecting the conductivity of the active layer of the metal oxide.
  • FIG. 1 is a schematic structural view of a metal oxide thin film transistor in a preferred embodiment of the present invention
  • FIG. 2 is a flow chart showing a method of fabricating a metal oxide thin film transistor in a preferred embodiment of the present invention
  • 3A-3E are schematic views showing the fabrication of a metal oxide thin film transistor in a preferred embodiment of the present invention.
  • FIG. 1 is a schematic structural view of a preferred embodiment of a metal oxide thin film transistor of the present invention.
  • the metal oxide thin film transistor includes: a glass substrate 10, a gate electrode 20, a gate insulating layer 30, a metal oxide active layer 40, an etch barrier layer 50, a diffusion barrier layer (not labeled), a source electrode 80, and a drain electrode. Extreme 90.
  • the gate electrode 20 is disposed on the glass substrate 10; the gate insulating layer 30 is disposed on the gate electrode 20 and the glass substrate 10; the metal oxide active layer 40 is disposed on the gate insulating layer 30; and the etch barrier layer 50 is disposed.
  • the etch barrier layer 50 is provided with a source via and a drain via; the diffusion barrier layer includes a source barrier layer 60 and a drain barrier layer 70.
  • the source blocking layer 60 and the drain blocking layer 70 are respectively disposed in the source via and the drain pass, and are in contact with the metal oxide active layer 40.
  • the diffusion barrier layer 70 is doped with a predetermined concentration of boron ions and/or phosphorus ions.
  • the source 80 is disposed on the source barrier layer; the drain 90 is disposed on the drain barrier layer 70, and the source 80 and the drain 90 are both formed of metal copper.
  • the diffusion barrier layer 70 comprises molybdenum metal and/or titanium metal, which is formed by physical vapor deposition.
  • the metal oxide active layer 40 is an indium gallium zinc oxide active layer which is formed by physical vapor deposition.
  • the diffusion barrier layer has a thickness of from 100 angstroms to 500 angstroms.
  • the diffusion barrier layer is doped with boron ions and phosphorus ions, and the doping concentration of boron ions and phosphorus ions is 10% to 90%.
  • the doping concentration is successively decreased from the side of the diffusion barrier layer adjacent to the source 80 and the drain 90 to the side close to the metal oxide active layer 40.
  • the doping concentration is successively decreased from the side of the diffusion barrier layer adjacent to the source 80 and the drain 90 to the side close to the metal oxide active layer 40.
  • the metal oxide thin film transistor of the preferred embodiment of the present invention employs boron ions and/or phosphorus ions in the diffusion barrier layer to improve the barrier property of the diffusion barrier layer to diffuse the copper ions of the source and the drain, thereby preventing the high temperature.
  • the diffusion of copper ions from the source and drain of the process to the active layer of the metal oxide affects the conductivity of the active layer of the metal oxide.
  • the present invention also provides an array substrate comprising the metal oxide thin film transistor of the above embodiment.
  • FIG. 2 is a schematic structural view of a preferred embodiment of a method for fabricating a metal oxide thin film transistor of the present invention. The method includes the following steps:
  • the diffusion barrier layer includes a source barrier layer and a drain barrier layer; the source barrier layer and the drain barrier layer are respectively disposed on the source via and the drain In the via hole and in contact with the metal oxide active layer;
  • the gate electrode 20 is formed by a stack of one or more of molybdenum, titanium, aluminum, and copper, which is formed by physical vapor deposition.
  • the gate insulating layer 30 is made of silicon dioxide or silicon nitride, which is formed by chemical vapor deposition.
  • the metal oxide active layer 40 is an indium gallium zinc oxide active layer.
  • a source via 51 and a drain via 52 are formed on the etch barrier layer 50. As shown in FIG. 3A, the process goes to step S202.
  • the diffusion barrier layer is made of molybdenum metal and/or titanium metal, which is formed by physical vapor deposition and has a thickness of 100 angstroms to 500 angstroms. .
  • the diffusion barrier layer includes a source barrier layer 60 and a drain barrier layer 70. As shown in FIG. 3B, the process proceeds to step S203.
  • step S203 before the doping of the diffusion barrier layer, the etch barrier layer is subjected to a yellow light process, and the region where the ion implantation is required, that is, the source barrier layer and the drain barrier layer are partially leaked, and the other portions are used.
  • the photoresist layer 100 is covered to prevent damage during ion implantation.
  • boron ions or phosphorus ions may be used, and boron ions and phosphorus ions may be used for mixed doping.
  • the doping concentration ranges from 10% to 90%.
  • the diffusion barrier layer has a decreasing doping concentration from a side close to the source 80 and the drain 90 to a side close to the metal oxide active layer 40. Thereby, not only the energy of ion implantation but also the effect of ion diffusion blocking can be improved. As shown in FIG. 3C, the process goes to step S204.
  • step S204 the following steps are specifically included:
  • a first metal layer 200 is deposited on the photoresist layer 100, the source barrier layer 60, and the drain barrier layer 70, as shown in FIG. 3D.
  • the material of the first metal layer 200 is metallic copper, which is formed by physical vapor deposition.
  • the method for fabricating a metal oxide thin film transistor employs a boron barrier and/or a phosphorus ion in the diffusion barrier layer to improve the barrier property of the diffusion barrier layer to the copper ion diffusion of the source and the drain. Preventing the diffusion of copper ions from the source and drain of the high temperature process to the metal oxide active layer affects the conductivity of the metal oxide active layer.

Abstract

一种金属氧化物薄膜晶体管及其制作方法、阵列基板，金属氧化物薄膜晶体管包括：玻璃基板(10)、栅极(20)、栅极绝缘层(30)、金属氧化物有源层(40)、刻蚀阻挡层(50)，刻蚀阻挡层设置有源极通孔以及漏极通孔；扩散阻挡层，包括源极阻挡层(60)和漏极阻挡层(70)，扩散阻挡层中掺杂有预定浓度的硼离子和/或磷离子；源极(80)以及漏极(90)。

Description

金属氧化物薄膜晶体管及其制作方法、阵列基板 技术领域
本发明涉及显示器领域，特别是涉及一种金属氧化物薄膜晶体管及其制作方法、阵列基板。
 背景技术
目前金属氧化物TFT工艺过程一般选用铜作为电极，因其有较优良的导电特性。但由于铜具有一定的扩散性，当薄膜晶体管导通时，铜会扩散到金属氧化物有源层，影响金属氧化物有源层的导电性能。因此，现有技术中，铜不单独使用，而是采用多层结构，包括扩散阻挡层和铜层。其中，阻挡层一般采用Mo、Ti形成，用来阻挡铜向金属氧化物有源层扩散。
但是现有技术中至少存在如下问题：扩散阻挡层越厚则阻挡铜向金属氧化物有源层扩散的效果越好，但是厂家对于成本及器件厚度有着严格要求，扩散阻挡层不可能做的太厚；同时为了提高器件性能，在形成薄膜晶体管后会对其进行退火工艺处理，退火工艺需要在高温环境中实现，而铜在高温下扩散加剧，这两方面原因导致扩散阻挡层防止铜扩散的效果差，进而影响金属氧化物有源层的导电性能，从而影响薄膜晶体管的性能。
因此，现有技术存在缺陷，急需改进。
 技术问题
本发明的目的在于提供一种金属氧化物薄膜晶体管及其制作方法、阵列基板；以解决现有的扩散阻挡层的阻挡扩散的效果差的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
提供一种金属氧化物薄膜晶体管，包括：
一玻璃基板；
栅极，其设置于玻璃基板上；
栅极绝缘层，其设置于栅极以及玻璃基板上；
金属氧化物有源层，其设置于栅极绝缘层上；
刻蚀阻挡层，其设置于金属氧化物有源层以及栅极绝缘层上，该刻蚀阻挡层设置有源极通孔以及漏极通孔；
扩散阻挡层，其包括源极阻挡层和漏极阻挡层，该源极阻挡层和漏极阻挡层分别设置于源极通孔以及漏极通中，并与该金属氧化物有源层接触，所述扩散阻挡层中掺杂有预定浓度的硼离子和/或磷离子；
源极，其设置于所述源极阻挡层上；
漏极，其设置于所述漏极阻挡层上。
在本发明所述的金属氧化物薄膜晶体中，所述扩散阻挡层包括钼金属和钛金属。
在本发明所述的金属氧化物薄膜晶体中，所述金属氧化物有源层为铟镓锌氧化物有源层。
在本发明所述的金属氧化物薄膜晶体中，所述扩散阻挡层的厚度为100埃米-500埃米。
在本发明所述的金属氧化物薄膜晶体中，所述扩散阻挡层中掺杂有硼离子和磷离子，硼离子和磷离子的掺杂浓度为10%-90%。
在本发明所述的金属氧化物薄膜晶体中，从所述扩散阻挡层的靠近所述源极以及漏极的一侧到靠近所述金属氧化物有源层的一侧，掺杂浓度依次递减。
本发明还提供了一种阵列基板，包括上述任一项所述的金属氧化物薄膜晶体管。
本发明还提供了一种金属氧化物薄膜晶体管的制作方法，包括以下步骤：
在玻璃基板上依次形成栅极、栅极绝缘层、金属氧化物有源层以及刻蚀阻挡层，该刻蚀阻挡层设置有源极通孔以及漏极通孔；
在金属氧化物有源层上形成扩散阻挡层，该扩散阻挡层包括源极阻挡层和漏极阻挡层，该源极阻挡层和漏极阻挡层分别设置于源极通孔以及漏极通孔中并分别与金属氧化物有源层接触；
采用预定浓度的硼离子和/或磷离子对扩散阻挡层进行掺杂；
在该源极阻挡层上形成源极，在该漏极阻挡层上形成漏极。
在本发明所述的金属氧化物薄膜晶体管的制作方法中，所述扩散阻挡层中掺杂有硼离子和磷离子，硼离子和磷离子的掺杂浓度为10%-90%。
在本发明所述的金属氧化物薄膜晶体管的制作方法中，从所述扩散阻挡层的靠近所述源极以及漏极的一侧到靠近所述金属氧化物有源层的一侧，掺杂浓度依次递减。
 有益效果
相对于现有技术，本发明优选实施例的金属氧化物薄膜晶体管采用在扩散阻挡层掺入硼离子和/或磷离子，提高了扩散阻挡层对源极以及漏极的铜离子扩散的阻挡能力，可以防止在高温过程源极以及漏极的铜离子扩散到金属氧化物有源层影响该金属氧化物有源层的导电性能力。
 附图说明
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
图1为本发明一优选实施例中的金属氧化物薄膜晶体管的结构示意图；
图2为本发明一优选实施例中的金属氧化物薄膜晶体管的制作方法的流程图；
图3A-图3E是本发明一优选实施例中的金属氧化物薄膜晶体管的制作方法的制作示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图1，图1为本发明的金属氧化物薄膜晶体管的优选实施例的结构示意图。该金属氧化物薄膜晶体管包括：玻璃基板10、栅极20、栅极绝缘层30、金属氧化物有源层40、刻蚀阻挡层50、扩散阻挡层（图未标号）、源极80以及漏极90。
其中，栅极20设置于玻璃基板10上；栅极绝缘层30设置于栅极20以及玻璃基板10上；金属氧化物有源层40设置于栅极绝缘层30上；刻蚀阻挡层50设置于金属氧化物有源层40以及栅极绝缘层30上，该刻蚀阻挡层50设置有源极通孔以及漏极通孔；扩散阻挡层包括源极阻挡层60和漏极阻挡层70。该源极阻挡层60和漏极阻挡层70分别设置于源极通孔以及漏极通中，并与该金属氧化物有源层40接触。扩散阻挡层70中掺杂有预定浓度的硼离子和/或磷离子。源极80设置于源极阻挡层上；漏极90设置于漏极阻挡层70上，源极80和漏极90均为金属铜沉积而成。
其中，扩散阻挡层70包括钼金属和/或钛金属，其采用物理气相沉淀制成。金属氧化物有源层40为铟镓锌氧化物有源层，其采用物理气相沉淀制成。扩散阻挡层的厚度为100埃米-500埃米。扩散阻挡层中掺杂有硼离子和磷离子，硼离子和磷离子的掺杂浓度为10%-90%。
优选地，从扩散阻挡层的靠近源极80以及漏极90的一侧到靠近金属氧化物有源层40的一侧，掺杂浓度依次递减。从而不仅可以节约离子注入的能量，还可以提高离子扩散阻挡的效果。
在本发明优选实施例的金属氧化物薄膜晶体管采用在扩散阻挡层掺入硼离子和/或磷离子，提高了扩散阻挡层对源极以及漏极的铜离子扩散的阻挡能力，可以防止在高温过程源极以及漏极的铜离子扩散到金属氧化物有源层影响该金属氧化物有源层的导电性能力。
本发明还提供了一种阵列基板，包括上述实施例中的金属氧化物薄膜晶体管。
请参照图2，图2为本发明的金属氧化物薄膜晶体管的制作方法的优选实施例的结构示意图。该方法包括以下步骤：
S201，在玻璃基板上依次形成栅极、栅极绝缘层、金属氧化物有源层以及刻蚀阻挡层，该刻蚀阻挡层设置有源极通孔以及漏极通孔；
S202，在金属氧化物有源层上形成扩散阻挡层，该扩散阻挡层包括源极阻挡层和漏极阻挡层；该源极阻挡层和漏极阻挡层分别设置于源极通孔以及漏极通孔中，并与该金属氧化物有源层接触；
S203，采用预定浓度的硼离子和/或磷离子对扩散阻挡层进行掺杂；
S204，在该源极阻挡层上形成源极，在该漏极阻挡层上形成漏极。
下面结合图3A-图3E对该金属氧化物薄膜晶体管的制作方法的各个步骤进行详细说明。
在步骤S201中，该栅极20采用材料为钼、钛、铝、铜中的一种或多种的堆栈组合，其采用物理气相沉积法沉积形成。该栅极绝缘层30采用二氧化硅或者氮化硅，其采用化学气相沉淀制成。该金属氧化物有源层40为铟镓锌氧化物有源层。刻蚀阻挡层50上形成有源极通孔51以及漏极通孔52。如图3A所示，转至步骤S202。
在步骤S202中，在金属氧化物有源层40上形成扩散阻挡层时，该扩散阻挡层采用钼金属和/或钛金属，其采用物理气相沉淀形成，其厚度为100埃米-500埃米。该扩散阻挡层包括源极阻挡层60和漏极阻挡层70。如图3B所示，转至步骤S203。
在步骤S203中，对扩散阻挡层进行掺杂前，对刻蚀阻挡层进行黄光制程，将需要进行离子注入的区域也即是源极阻挡层和漏极阻挡层部分漏出，将其他部分采用光阻层100覆盖，防止离子注入时的损伤。然后，进行掺杂时，可以采用硼离子，也可以采用磷离子，还可以采用硼离子和磷离子进行混合掺杂。其中，掺杂浓度的范围为10%-90%。优选地，该扩散阻挡层从靠近源极80以及漏极90的一侧到靠近金属氧化物有源层40的一侧的掺杂浓度依次递减。从而不仅可以节约离子注入的能量，还可以提高离子扩散阻挡的效果。如图3C所示，转至步骤S204。
在步骤S204中，具体包括以下步骤：
A，在光阻层100、源极阻挡层60以及漏极阻挡层70上沉积第一金属层200，如图3D所示。该第一金属层200的材料为金属铜，采用物理气相沉淀而成。
B，进行光阻剥离，以将光阻层100去除，同时，第一金属层200的位于光阻层100上的部分也随之去除；从而在该源极阻挡层60上形成源极80，在该漏极阻挡层70上形成漏极90。如图3E所示。
在本发明优选实施例的金属氧化物薄膜晶体管的制作方法采用在扩散阻挡层掺入硼离子和/或磷离子，提高了扩散阻挡层对源极以及漏极的铜离子扩散的阻挡能力，可以防止在高温过程源极以及漏极的铜离子扩散到金属氧化物有源层影响该金属氧化物有源层的导电性能力。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种金属氧化物薄膜晶体管，其中，包括：
    一玻璃基板；
    栅极，其设置于玻璃基板上；
    栅极绝缘层，其设置于栅极以及玻璃基板上；
    金属氧化物有源层，其设置于栅极绝缘层上；
    刻蚀阻挡层，其设置于金属氧化物有源层以及栅极绝缘层上，该刻蚀阻挡层设置有源极通孔以及漏极通孔；
    扩散阻挡层，其包括源极阻挡层和漏极阻挡层，该源极阻挡层和漏极阻挡层分别设置于源极通孔以及漏极通中，并与该金属氧化物有源层接触，所述扩散阻挡层中掺杂有预定浓度的硼离子和/或磷离子；
    源极，其设置于所述源极阻挡层上；
    漏极，其设置于所述漏极阻挡层上。
  2. 根据权利要求1所述的金属氧化物薄膜晶体管，其中，所述扩散阻挡层包括钼金属和钛金属。
  3. 根据权利要求1所述的金属氧化物薄膜晶体管，其中，所述金属氧化物有源层为铟镓锌氧化物有源层。
  4. 根据权利要求1所述的金属氧化物薄膜晶体管，其中，所述扩散阻挡层的厚度为100埃米-500埃米。
  5. 根据权利要求1所述的金属氧化物薄膜晶体管，其中，所述扩散阻挡层中掺杂有硼离子和磷离子，硼离子和磷离子的掺杂浓度为10%-90%。
  6. 根据权利要求1所述的金属氧化物薄膜晶体管，其中，从所述扩散阻挡层的靠近所述源极以及漏极的一侧到靠近所述金属氧化物有源层的一侧，掺杂浓度依次递减。
  7. 一种阵列基板，其包括金属氧化物薄膜晶体管，该金属氧化物薄膜晶体管包括：
    一玻璃基板；
    栅极，其设置于玻璃基板上；
    栅极绝缘层，其设置于栅极以及玻璃基板上；
    金属氧化物有源层，其设置于栅极绝缘层上；
    刻蚀阻挡层，其设置于金属氧化物有源层以及栅极绝缘层上，该刻蚀阻挡层设置有源极通孔以及漏极通孔；
    扩散阻挡层，其包括源极阻挡层和漏极阻挡层，该源极阻挡层和漏极阻挡层分别设置于源极通孔以及漏极通中，并与该金属氧化物有源层接触，所述扩散阻挡层中掺杂有预定浓度的硼离子和/或磷离子；
    源极，其设置于所述源极阻挡层上；
    漏极，其设置于所述漏极阻挡层上。
  8. 根据权利要求7所述的阵列基板，其中，所述扩散阻挡层包括钼金属和钛金属。
  9. 根据权利要求7所述的阵列基板，其中，所述金属氧化物有源层为铟镓锌氧化物有源层。
  10. 根据权利要求7所述的阵列基板，其中，所述扩散阻挡层的厚度为100埃米-500埃米。
  11. 根据权利要求7所述的阵列基板，其中，所述扩散阻挡层中掺杂有硼离子和磷离子，硼离子和磷离子的掺杂浓度为10%-90%。
  12. 根据权利要求7所述的阵列基板，其中，从所述扩散阻挡层的靠近所述源极以及漏极的一侧到靠近所述金属氧化物有源层的一侧，掺杂浓度依次递减。
  13. 根据权利要求7所述的阵列基板，其中，所述扩散阻挡层包括钼金属和钛金属；
    所述金属氧化物有源层为铟镓锌氧化物有源层；
    所述扩散阻挡层的厚度为100埃米-500埃米；
    所述扩散阻挡层中掺杂有硼离子和磷离子，硼离子和磷离子的掺杂浓度为10%-90%；
    从所述扩散阻挡层的靠近所述源极以及漏极的一侧到靠近所述金属氧化物有源层的一侧，掺杂浓度依次递减。
  14. 一种金属氧化物薄膜晶体管的制作方法，其包括以下步骤：
    在玻璃基板上依次形成栅极、栅极绝缘层、金属氧化物有源层以及刻蚀阻挡层，该刻蚀阻挡层设置有源极通孔以及漏极通孔；
    在金属氧化物有源层上形成扩散阻挡层，该扩散阻挡层包括源极阻挡层和漏极阻挡层，该源极阻挡层和漏极阻挡层分别设置于源极通孔以及漏极通孔中并分别与金属氧化物有源层接触；
    采用预定浓度的硼离子和/或磷离子对扩散阻挡层进行掺杂；
    在该源极阻挡层上形成源极，在该漏极阻挡层上形成漏极。
  15. 根据权利要求14所述的金属氧化物薄膜晶体管的制作方法，其中，所述扩散阻挡层中掺杂有硼离子和磷离子，硼离子和磷离子的掺杂浓度为10%-90%。
  16. 根据权利要求14所述的金属氧化物薄膜晶体管，其中，从所述扩散阻挡层的靠近所述源极以及漏极的一侧到靠近所述金属氧化物有源层的一侧，掺杂浓度依次递减。
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