WO2016201751A1 - 一种阵列基板及其制成方法、显示面板 - Google Patents

一种阵列基板及其制成方法、显示面板 Download PDF

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Publication number
WO2016201751A1
WO2016201751A1 PCT/CN2015/083744 CN2015083744W WO2016201751A1 WO 2016201751 A1 WO2016201751 A1 WO 2016201751A1 CN 2015083744 W CN2015083744 W CN 2015083744W WO 2016201751 A1 WO2016201751 A1 WO 2016201751A1
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channel layer
layer
gate
gate insulating
insulating layer
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PCT/CN2015/083744
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English (en)
French (fr)
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王质武
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深圳市华星光电技术有限公司
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Priority to US14/768,008 priority Critical patent/US20170141204A1/en
Publication of WO2016201751A1 publication Critical patent/WO2016201751A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present application relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display panel.
  • GI Insulator
  • SiO silicon monoxide
  • SiN silicon nitride
  • SiN/SiO double layer structure Since a hydrogen-containing reaction gas is required in both the preparation of SiO and SiN, hydrogen is inevitably included in the reaction product, that is, the gate insulating layer contains hydrogen.
  • the TFT when the display panel is in operation, the TFT is applied with a positive or negative bias to be in a normally open or normally closed state, and the H ion of the gate insulating/channel layer (English: GI/Channel) interface is used as a An interface defect state that traps or de-traps electrons during work. Therefore, as the operating time of the display panel increases and the electrons of the GI/Channel interface accumulate or are released to a certain extent, the threshold voltage (also referred to as the turn-on voltage) of the TFT may drift positively or negatively, thereby affecting the TFT. stability.
  • the present invention provides an array substrate, a method for fabricating the same, and a display panel, which can prevent the threshold voltage of the TFT from drifting and ensure the stability of the TFT.
  • a first aspect of the present application provides an array substrate including a substrate and a plurality of thin film transistors including a gate, a gate insulating layer, a channel layer, a source, and a drain disposed on the substrate, a gate insulating layer is disposed between the gate and the channel layer to insulate the gate and the channel layer, the source and the drain being respectively disposed on the channel layer; wherein the gate
  • the insulating layer is an aluminum nitride AlN film.
  • the AlN film is fabricated by using a magnetron sputtering device in an aluminum case
  • the chamber is formed by sputtering with nitrogen gas or a mixed gas including argon gas and nitrogen gas.
  • the ratio of the argon gas to the nitrogen gas is 0-90%.
  • the channel layer is composed of a metal oxide.
  • the thin film transistor further includes an etch barrier layer disposed on the channel layer and a passivation layer overlying the source and drain electrodes, and the etch stop layer is disposed at the source Between the drain and the drain.
  • a second aspect of the present invention provides a method of fabricating an array substrate, the method comprising: forming a gate, a gate insulating layer, and a channel layer on a substrate, wherein the gate insulating layer is stacked on the substrate Between the gate and the channel layer, and the gate insulating layer is an aluminum nitride AlN film; a source and a drain are formed on the channel layer.
  • the forming of the gate insulating layer specifically comprises: using a magnetron sputtering device in an aluminum box Al A nitrogen gas or a mixed gas including argon gas and nitrogen gas is introduced into the chamber to form an AlN film by sputtering on the gate electrode.
  • the ratio of the argon gas to the nitrogen gas is 0-90%.
  • the temperature of the substrate is 25 degrees Celsius to 300 degrees Celsius.
  • a third aspect of the present disclosure provides a display panel including an array substrate, the array substrate including a substrate and a plurality of thin film transistors, the thin film transistor including a gate, a gate insulating layer, a channel layer, and a channel layer disposed on the substrate a source and a drain, the gate insulating layer is disposed between the gate and the channel layer to insulate the gate and the channel layer, and the source and the drain are respectively disposed in the channel On the layer; wherein the gate insulating layer is an aluminum nitride AlN film; wherein the channel layer is composed of a metal oxide, and the AlN film is formed by a magnetron sputtering device in an aluminum case
  • the chamber is formed by sputtering with nitrogen gas or a mixed gas including argon gas and nitrogen gas.
  • the ratio of the argon gas to the nitrogen gas is 0-90%.
  • the thin film transistor further includes an etch barrier layer disposed on the channel layer and a passivation layer overlying the source and drain electrodes, and the etch stop layer is disposed at the source Between the drain and the drain.
  • the AlN film is used as the gate insulating layer of the TFT of the array substrate. Since the AlN film does not contain hydrogen, the gate insulating layer can be prevented from capturing or releasing electrons when the array substrate is operated, so that the threshold voltage of the TFT is positive or Negative drift, thus ensuring the stability of the TFT.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate of the present application.
  • FIG. 2 is a schematic structural view of an embodiment of a display panel of the present application.
  • FIG. 3 is a flow chart of an embodiment of a method of fabricating an array substrate of the present application.
  • FIG. 1 is a schematic structural diagram of an embodiment of an array substrate of the present application.
  • the array substrate 100 includes a substrate 110 and a plurality of TFTs. 120 (FIG. 1 exemplarily shows one TFT 120 on the substrate 110 for explanation).
  • the substrate 110 may be a transparent substrate made of a glass substrate or other insulating material.
  • TFT 120 includes a gate electrode 121, a gate insulating layer 122, a channel layer 123, a source electrode 124, and a drain electrode 125 disposed on the substrate 110.
  • the gate insulating layer 122 is stacked between the gate electrode 121 and the channel layer 123 to insulate the gate electrode 121 and the channel layer 123, and the source electrode 124 and the drain electrode 125 are located on the same layer, and They are respectively disposed on the channel layer 123 and are not in direct contact.
  • the gate 121 obtains a voltage greater than or equal to the turn-on voltage
  • the channel layer 123 induces electrons to turn on the source 124 and the drain 125.
  • the gate insulating layer 122 is an aluminum nitride (chemical formula: AlN) film.
  • the AlN film is a good insulating material, so that the gate electrode 121 and the channel layer 122 can be well insulated.
  • the AlN film has a high breakdown field strength (such as 1.2-1.8 MV/cm for AlN crystal), high thermal conductivity, high chemical and thermal stability, and a transmittance of more than 90% in the visible range. .
  • Due to AlN The film does not contain hydrogen, so that when the array substrate is in operation, the gate insulating layer contains hydrogen to capture or release electrons, so that the threshold voltage of the TFT is positively or negatively drifted, thereby ensuring the stability of the TFT.
  • the channel layer 123 may be composed of a metal oxide, such as indium gallium zinc oxide (English: indium gallium) Zinc oxide, referred to as: IGZO).
  • IGZO indium gallium zinc oxide
  • IGZO indium gallium Zinc oxide
  • TFT 120 may further include an etch barrier layer 126 disposed on the channel layer 123 and a passivation layer 127 overlying the source and drain electrodes 124 and 125, and the etch stop layer 126 is disposed on the Between the source 124 and the drain 125.
  • a silicide layer may be disposed between the source, the drain, and the passivation layer to prevent Cu ions of the source and drain from diffusing to the passivation layer.
  • the gate electrode 121, the channel layer 123, the source electrode 124, and the drain electrode 125 may be physically vapor deposited (English: Physical: Vapor Deposition (PVD) generation, the etch stop layer 126 and the passivation layer 127 may be plasma enhanced chemical vapor deposition (Plasma Enhanced) Chemical Vapor Deposition, referred to as: PECVD).
  • PVD Physical: Vapor Deposition
  • the etch stop layer 126 and the passivation layer 127 may be plasma enhanced chemical vapor deposition (Plasma Enhanced) Chemical Vapor Deposition, referred to as: PECVD).
  • the above-mentioned gate insulating layer 122 that is, the AlN film, may be etched by an inductively coupled plasma (abbreviation: ICP) device or by PVD such as magnetron sputtering.
  • ICP inductively coupled plasma
  • PVD magnetron sputtering
  • the AlN film is prepared using a magnetron sputtering apparatus.
  • a magnetron sputtering apparatus for example, in an aluminum case (English: Al
  • the chamber is formed by sputtering with nitrogen gas or a mixed gas including argon gas and nitrogen gas.
  • the ratio of the argon gas to the nitrogen gas is 0-90%, for example, the ratio is 0%, 45% or 90%.
  • the temperature of the substrate is 25 degrees Celsius to 300 degrees Celsius, for example, specifically 25, 85 or 300 degrees Celsius. Therefore, since the AlN film is prepared by magnetron sputtering, high temperature is not required, and it can be carried out at normal temperature, and no oxidizing gas participates in the reaction during the film formation of the AlN film, so that the gate insulating layer can be prevented from causing gate oxidation.
  • the etch stop layer 126 may also be an AlN film, which is formed in the same manner as the above-mentioned gate insulating layer. Due to AlN The film does not contain hydrogen, so that when the etching barrier film is formed, even if the temperature is too high or too low, the channel layer is not reduced or the etching barrier layer is formed with holes, thereby ensuring the quality of the TFT, and When the AlN film is formed into a film, it is not required to be subjected to temperature limitation, the film formation requirement is lowered, and the film formation rate can be improved.
  • the array substrate may further include a plurality of data lines, a plurality of scan lines, and a plurality of pixel electrodes (not shown) disposed on the substrate, the data lines and a source of the TFT The pole is connected, the scan line is connected to the gate of the TFT, and the pixel electrode is connected to the drain of the TFT.
  • the scan line inputs a voltage greater than or equal to the startup voltage to the gate of the TFT, the source and the drain of the TFT are turned on, that is, the data line and the pixel electrode are connected, and the pixel electrode obtains the voltage input from the data line.
  • the source, the drain and the pixel electrode may have an integral structure and are composed of a transparent conductive film.
  • FIG. 2 is a schematic structural diagram of an embodiment of a display panel of the present application.
  • the display panel includes an array substrate 210, a color filter substrate 220, and a liquid crystal 230 interposed between the array substrate 210 and the color filter substrate 220.
  • the array substrate 210 is the array substrate described in the above embodiment, and the color filter substrate 220 may include a substrate, and a black matrix and a color filter layer respectively disposed on the substrate (English: Color Filter, referred to as: CF), protective layer and ITO Membrane.
  • CF Color Filter
  • the pixel electrode of the array substrate acquires the display voltage input from the data line, an electric field is formed between the pixel electrode and the ITO film of the color filter substrate, thereby driving the liquid crystal 230 to be deflected to form a display image.
  • FIG. 3 is a flow chart of an embodiment of a method for fabricating an array substrate of the present application. The method includes:
  • a gate electrode, a gate insulating layer, and a channel layer on the substrate wherein the gate insulating layer is stacked between the gate electrode and the channel layer, and the gate insulating layer is an AlN film.
  • a gate electrode is formed on a substrate, an AlN thin film is covered on the gate electrode as a gate insulating layer, and a channel layer is formed on the gate insulating layer.
  • the gate and the channel layer can be generated by PVD.
  • the AlN film can be etched by an ICP device or prepared by PVD such as magnetron sputtering.
  • the AlN film is formed by sputtering using a magnetron sputtering apparatus by introducing nitrogen gas or a mixed gas including argon gas and nitrogen gas into an aluminum tank.
  • the ratio of the argon gas to the nitrogen gas may be 0-90%, for example, the ratio is 0%, 45% or 90%.
  • the temperature of the substrate is 25 degrees Celsius to 300 degrees Celsius, for example, specifically 25, 85 or 300 degrees Celsius.
  • the AlN film is prepared by magnetron sputtering, high temperature is not required, and it can be carried out at normal temperature, and no oxidizing gas participates in the reaction during the film formation of the AlN film, so that the gate insulating layer can be prevented from causing gate oxidation.
  • 320 forming a source and a drain on the channel layer.
  • a source and a drain are respectively formed on the channel layer, wherein the source and the drain are not in direct contact.
  • an etch stop layer may be formed on the source and drain electrodes on the channel layer, and the etch stop layer is disposed between the source and the drain; and/or formed on the source and the drain, respectively. Passivation layer.
  • the source and the drain may be formed by PVD, and the etch barrier layer and the passivation layer may be formed by PECVD.
  • the etch stop layer may be formed of an AlN film.
  • the etch stop layer may be formed by a PVD film formation similar to the above-mentioned 310 gate insulating layer.
  • the method of fabricating further includes forming a plurality of scan lines, a plurality of data lines, and a plurality of pixel electrodes on the substrate.
  • the data line is in electrical contact with a source of the TFT
  • the scan line is in electrical contact with a gate of the TFT
  • the pixel electrode is in electrical contact with a drain of the TFT.
  • the AlN film is used as the gate insulating layer of the TFT of the array substrate. Since the AlN film does not contain hydrogen, the gate insulating layer can be prevented from capturing or releasing electrons when the array substrate is operated, so that the threshold voltage of the TFT is positive or Negative drift, thus ensuring the stability of the TFT.

Abstract

一种阵列基板及其制成方法、显示面板，其中，阵列基板（100）包括基板（110）和多个TFT（120），TFT（120）包括设置在基板（110）上的栅极（121）、栅绝缘层（122）、沟道层（123）、源极（124）和漏极（125），栅绝缘层（122）叠置在栅极（121）和沟道层（123）之间，以将栅极（121）和沟道层（123）绝缘，源极（124）和漏极（125）分别设置在沟道层（123）上；其中，栅绝缘层（122）为AlN薄膜。能够避免TFT的阈值电压出现漂移，保证TFT的稳定性。

Description

一种阵列基板及其制成方法、显示面板
【技术领域】
本申请涉及显示技术领域，特别是涉及一种阵列基板及其制成方法、显示面板。
【背景技术】
目前，主流显示面板的薄膜晶体管（英文：thin film transistor，简称：TFT）的栅绝缘层（英文：gate insulator，简称：GI）通常采用一氧化硅（分子式：SiO）、氮化硅（分子式：SiN）或者SiN/SiO双层结构构成。由于在制备SiO和SiN时均需使用含氢的反应气体，故反应生成物中必然包括氢，也即栅绝缘层中含有氢。
然而，在显示面板工作时，TFT会被施加正偏压或负偏压使其处于常开或者常关的状态，栅绝缘层/沟道层（英文：GI/Channel）界面的H离子作为一种界面缺陷态，在工作过程中会捕捉或者释放（trapping/de-trapping）电子。因此，随着显示面板工作时间的增加，GI/Channel界面的电子积累或释放到一定程度时，TFT的阈值电压（也称为开启电压）则会出现正向或者负向漂移，从而影响TFT的稳定性。
【发明内容】
本申请提供一种阵列基板及其制成方法、显示面板，能够避免TFT的阈值电压出现漂移，保证TFT的稳定性。
本申请第一方面提供一种阵列基板，包括基板和多个薄膜晶体管，所述薄膜晶体管包括设置在所述基板上的栅极、栅绝缘层、沟道层、源极和漏极，所述栅绝缘层叠置在所述栅极和沟道层之间，以将所述栅极和沟道层绝缘，所述源极和漏极分别设置在所述沟道层上；其中，所述栅绝缘层为氮化铝AlN薄膜。
其中，所述AlN薄膜是利用磁控溅射设备，在铝箱Al Chamber中通入氮气、或包括氩气和氮气的混合气体，溅射形成的。
其中，所述氩气与氮气的比值为0-90%。
其中，所述沟道层由金属氧化物构成。
其中，所述薄膜晶体管还包括设置在所述沟道层上的刻蚀阻挡层和覆盖在所述源极和漏极上的钝化层，且所述刻蚀阻挡层设置在所述源极和漏极之间。
本申请第二方面提供一种阵列基板的制成方法，其特征在于，所述方法包括：在基板上形成栅极、栅绝缘层、沟道层，其中，所述栅绝缘层叠置在所述栅极和沟道层之间，且所述栅绝缘层为氮化铝AlN薄膜；在所述沟道层上形成源极和漏极。
其中，所述栅绝缘层的形成具体包括：利用磁控溅射设备，在铝箱Al Chamber中通入氮气、或包括氩气和氮气的混合气体，以在所述栅极上溅射形成AlN薄膜。
其中，所述氩气与氮气的比值为0-90%。
其中，在AlN薄膜成膜时，所述基板的温度为25摄氏度-300摄氏度。
本申请第三方面提供一种显示面板，包括阵列基板，所述阵列基板包括基板和多个薄膜晶体管，所述薄膜晶体管包括设置在所述基板上的栅极、栅绝缘层、沟道层、源极和漏极，所述栅绝缘层叠置在所述栅极和沟道层之间，以将所述栅极和沟道层绝缘，所述源极和漏极分别设置在所述沟道层上；其中，所述栅绝缘层为氮化铝AlN薄膜；其中，所述沟道层由金属氧化物构成，所述AlN薄膜是利用磁控溅射设备，在铝箱Al Chamber中通入氮气、或包括氩气和氮气的混合气体，溅射形成的。
其中，所述氩气与氮气的比值为0-90%。
其中，所述薄膜晶体管还包括设置在所述沟道层上的刻蚀阻挡层和覆盖在所述源极和漏极上的钝化层，且所述刻蚀阻挡层设置在所述源极和漏极之间。
上述方案中，采用AlN薄膜作为阵列基板的TFT的栅绝缘层，由于AlN薄膜不含氢，故可避免在阵列基板工作时，栅绝缘层捕捉或释放电子，使得TFT的阈值电压出现正向或负向漂移，从而保证了TFT的稳定性。
【附图说明】
图1是本申请阵列基板一实施方式的结构示意图；
图2是本申请显示面板一实施方式的结构示意图；
图3是本申请阵列基板的制成方法一实施方式的流程图。
【具体实施方式】
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、接口、技术之类的具体细节，以便透彻理解本申请。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施方式中也可以实现本申请。在其它情况中，省略对众所周知的装置、电路以及方法的详细说明，以免不必要的细节妨碍本申请的描述。
请参阅图1，图1是本申请阵列基板一实施方式的结构示意图。本实施方式中，阵列基板100包括基板110和多个TFT 120（图1仅示范性示出基板110上的一个TFT120进行说明）。其中，所述基板110可以为玻璃基板或其他绝缘材料构成的透明基板。TFT 120包括设置在所述基板110上的栅极121、栅绝缘层122、沟道层123、源极124、漏极125。所述栅绝缘层122叠置在所述栅极121和沟道层123之间，以将所述栅极121和沟道层123绝缘，所述源极124和漏极125位于同一层，并分别设置在所述沟道层123上且不直接接触。当栅极121获得大于或等于开启电压的电压时，沟道层123感应出电子，使源极124和漏极125导通。
其中，所述栅绝缘层122为氮化铝（化学式：AlN）薄膜。AlN薄膜为良好的绝缘材料，故可对栅极121和沟道层122起到很好的绝缘作用。而且，AlN薄膜具有高的击穿场强（如AlN晶体为1.2-1.8MV/cm）、高热导率、高化学和热稳定性、以及在可见光范围可具备90%以上的穿透率等特点。另外，由于AlN 薄膜不含氢，故可避免在阵列基板工作时，栅绝缘层含氢而捕捉或释放电子，使得TFT的阈值电压出现正向或负向漂移，从而保证了TFT的稳定性。
在本实施方式中，所述沟道层123可由金属氧化物构成，例如为铟镓锌氧化物（英文：indium gallium zinc oxide，简称：IGZO）。
TFT 120还可包括设置在所述沟道层123上的刻蚀阻挡层126和覆盖在所述源极124和漏极125上的钝化层127，且所述刻蚀阻挡层126设置在所述源极124和漏极125之间。
在其他实施方式中，在源极、漏极与钝化层之间还可设置硅化物层，以防止源极、漏极的Cu离子扩散到钝化层。
在上述结构中，所述栅极121、沟道层123、源极124和漏极125可采用物理气相沉积（英文：Physical Vapor Deposition，简称：PVD）生成，上述刻蚀阻挡层126和钝化层127可采用等离子体增强化学气相沉积法（英文：Plasma Enhanced Chemical Vapor Deposition，简称：PECVD）生成。
上述栅绝缘层122即AlN薄膜可以由感应耦合等离子体（简称：ICP）设备进行刻蚀、或采用PVD如磁控溅射法制备得到。
在另一实施方式中，AlN薄膜利用磁控溅射设备制备得到。例如，在铝箱（英文：Al Chamber）中通入氮气、或包括氩气和氮气的混合气体，溅射形成的。其中，在通入混合气体的实施方式中，所述氩气与氮气的比值为0-90%，例如比值为0%、45%或90%。
在磁控溅射成膜过程中，基板的温度为25摄氏度-300摄氏度，例如具体为25、85或300摄氏度。故由于制备AlN薄膜如采用磁控溅射制备，无需高温，可在常温下进行，且AlN薄膜成膜过程中没有氧化性的气体参与反应，故可避免沉积栅绝缘层是造成栅极氧化。
当然，刻蚀阻挡层126也可以为AlN薄膜，其成膜方式类同于上述栅绝缘层。由于AlN 薄膜不含氢，故在刻蚀阻挡层成膜时，即使温度过高或过低，也不会导致沟道层还原或者刻蚀阻挡层出现孔洞的情况，进而保证了TFT的质量，而且，在AlN薄膜成膜时无需受到温度限制，降低了成膜要求，且可提高成膜速率。
在再一实施方式中，阵列基板还可包括设置在所述基板上的多条数据线、多条扫描线和多个像素电极（图未示出），所述数据线与所述TFT的源极连接，所述扫描线与所述TFT的栅极连接，像素电极与所述TFT的漏极连接。当扫描线向TFT的栅极输入大于或等于启动电压的电压时，TFT的源极和漏极导通，即数据线和像素电极连接，像素电极获得数据线输入的电压。
其中，为增加像素电极的开口率，源极、漏极和像素电极可是一体结构，由透明导电薄膜构成。
请参阅图2，图2是本申请显示面板一实施方式的结构示意图。本实施方式中，显示面板包括阵列基板210、彩膜基板220和夹置在阵列基板210、彩膜基板220之间的液晶230。其中，所述阵列基板210为上面实施方式描述的阵列基板，彩膜基板220可包括基板，以及分别设置在基板上的黑矩阵、彩色滤光层（英文：Color Filter ，简称：CF）、保护层及 ITO 膜。阵列基板的像素电极获取数据线输入的显示电压时，与彩膜基板的ITO膜之间形成电场，从而驱动液晶230发生偏转，形成显示图像。
请参阅图3，图3是本申请阵列基板的制成方法一实施方式的流程图。所述方法包括：
310：在基板上形成栅极、栅绝缘层、沟道层，其中，所述栅绝缘层叠置在所述栅极和沟道层之间，且所述栅绝缘层为AlN薄膜。
本实施方式中，在基板上形成栅极，在栅极上覆盖AlN薄膜作为栅绝缘层，再在栅绝缘层上形成沟道层。其中，所述栅极、沟道层可采用PVD生成。
AlN薄膜可以由ICP设备进行刻蚀、或采用PVD如磁控溅射法制备得到。例如，AlN薄膜利用磁控溅射设备，在铝箱中通入氮气、或包括氩气和氮气的混合气体，溅射形成的。其中，在通入混合气体的实施方式中，所述氩气与氮气的比值可为0-90%，例如比值为0%、45%或90%。在磁控溅射成膜过程中，基板的温度为25摄氏度-300摄氏度，例如具体为25、85或300摄氏度。故由于制备AlN薄膜如采用磁控溅射制备，无需高温，可在常温下进行，且AlN薄膜成膜过程中没有氧化性的气体参与反应，故可避免沉积栅绝缘层是造成栅极氧化。
320：在所述沟道层上形成源极和漏极。
在形成沟道层后，在沟道层上分别形成源极和漏极，其中，源极和漏极不直接接触。在其他实施方式中，还可在沟道层上的源极和漏极形成刻蚀阻挡层，且刻蚀阻挡层设置源极和漏极之间；和/或分别源极和漏极上形成钝化层。
具体地，所述源极和漏极可采用PVD生成，上述刻蚀阻挡层和钝化层可采用PECVD生成。或者，上述刻蚀阻挡层可由AlN薄膜形成，此时，刻蚀阻挡层可不由PECVD生成，而是采用类同上述310中栅绝缘层的PVD成膜方式。
在另一实施方式中，所述制成方法还包括在基板上形成多条扫描线、多条数据线和多个像素电极。其中，所述数据线与所述TFT的源极电接触，所述扫描线与所述TFT的栅极电接触，像素电极与所述TFT的漏极电接触。
上述方案中，采用AlN薄膜作为阵列基板的TFT的栅绝缘层，由于AlN薄膜不含氢，故可避免在阵列基板工作时，栅绝缘层捕捉或释放电子，使得TFT的阈值电压出现正向或负向漂移，从而保证了TFT的稳定性。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (12)

  1. 一种显示面板，其中，包括阵列基板，所述阵列基板包括基板和多个薄膜晶体管，所述薄膜晶体管包括设置在所述基板上的栅极、栅绝缘层、沟道层、源极和漏极，所述栅绝缘层叠置在所述栅极和沟道层之间，以将所述栅极和沟道层绝缘，所述源极和漏极分别设置在所述沟道层上；其中，所述栅绝缘层为氮化铝AlN薄膜；
    其中，所述沟道层由金属氧化物构成，所述AlN薄膜是利用磁控溅射设备，在铝箱Al Chamber中通入氮气、或包括氩气和氮气的混合气体，溅射形成的。
  2. 根据权利要求1所述的显示面板，其中，所述氩气与氮气的比值为0-90%。
  3. 根据权利要求1所述的显示面板，其中，所述薄膜晶体管还包括设置在所述沟道层上的刻蚀阻挡层和覆盖在所述源极和漏极上的钝化层，且所述刻蚀阻挡层设置在所述源极和漏极之间。
  4. 一种阵列基板，其中，包括基板和多个薄膜晶体管，所述薄膜晶体管包括设置在所述基板上的栅极、栅绝缘层、沟道层、源极和漏极，所述栅绝缘层叠置在所述栅极和沟道层之间，以将所述栅极和沟道层绝缘，所述源极和漏极分别设置在所述沟道层上；其中，所述栅绝缘层为氮化铝AlN薄膜。
  5. 根据权利要求4所述的阵列基板，其中，所述AlN薄膜是利用磁控溅射设备，在铝箱Al Chamber中通入氮气、或包括氩气和氮气的混合气体，溅射形成的。
  6. 根据权利要求5所述的阵列基板，其中，所述氩气与氮气的比值为0-90%。
  7. 根据权利要求4所述的阵列基板，其中，所述沟道层由金属氧化物构成。
  8. 根据权利要求4所述的阵列基板，其中，所述薄膜晶体管还包括设置在所述沟道层上的刻蚀阻挡层和覆盖在所述源极和漏极上的钝化层，且所述刻蚀阻挡层设置在所述源极和漏极之间。
  9. 一种阵列基板的制成方法，其中，所述方法包括：
    在基板上形成栅极、栅绝缘层、沟道层，其中，所述栅绝缘层叠置在所述栅极和沟道层之间，且所述栅绝缘层为氮化铝AlN薄膜；
    在所述沟道层上形成源极和漏极。
  10. 根据权利要求9所述的方法，其中，所述栅绝缘层的形成具体包括：
    利用磁控溅射设备，在铝箱Al Chamber中通入氮气、或包括氩气和氮气的混合气体，以在所述栅极上溅射形成AlN薄膜。
  11. 根据权利要求10所述的方法，其中，所述氩气与氮气的比值为0-90%。
  12. 根据权利要求10所述的方法，其中，在AlN薄膜成膜时，所述基板的温度为25摄氏度-300摄氏度。
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