CN110148601A - 一种阵列基板、其制作方法及显示装置 - Google Patents

一种阵列基板、其制作方法及显示装置 Download PDF

Info

Publication number
CN110148601A
CN110148601A CN201910468906.9A CN201910468906A CN110148601A CN 110148601 A CN110148601 A CN 110148601A CN 201910468906 A CN201910468906 A CN 201910468906A CN 110148601 A CN110148601 A CN 110148601A
Authority
CN
China
Prior art keywords
layer
grid
region
array substrate
grid line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910468906.9A
Other languages
English (en)
Other versions
CN110148601B (zh
Inventor
刘军
闫梁臣
周斌
梁亚东
刘宁
程磊磊
方金钢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Hefei Xinsheng Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201910468906.9A priority Critical patent/CN110148601B/zh
Publication of CN110148601A publication Critical patent/CN110148601A/zh
Priority to PCT/CN2020/090315 priority patent/WO2020238640A1/zh
Priority to US17/265,789 priority patent/US11961848B2/en
Application granted granted Critical
Publication of CN110148601B publication Critical patent/CN110148601B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/4757—After-treatment
    • H01L21/47573—Etching the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
    • H01L21/47635—After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors

Abstract

本发明公开了一种阵列基板、其制作方法及显示装置，该阵列基板包括：衬底基板，位于衬底基板上依次层叠设置的遮光金属层、缓冲层、有源层、栅极绝缘层、栅极、层间绝缘层、源漏极和钝化层；栅极所在的第一金属膜层还包括栅线，源漏极所在的第二金属膜层还包括数据线；栅线在与数据线相对区域的表面具有氧化物金属层。本发明通过在与数据线具有相对区域的栅线的表面设置氧化物金属层，由于氧化物金属层的介电常数和击穿电压较高，可以极大的降低栅线和数据线在交叠区域发生短路的可能性。因此采用本发明实施例提供的阵列基板能够解决相关技术中栅线和数据线之间的交叠区域易发生短路，而造成面板良率下降的问题。

Description

一种阵列基板、其制作方法及显示装置
技术领域
本发明涉及显示技术领域，特别涉及一种阵列基板、其制作方法及显示装置。
背景技术
目前，薄膜晶体管(Thin Film Transistor，TFT)是液晶显示器和有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)的主要驱动元件。在TFT制作过程中，由于工艺的原因会导致栅线和数据线之间的交叠区域发生短路，使得面板发生亮线，造成面板良率下降。
发明内容
本发明实施例提供一种阵列基板、其制作方法及显示装置，用以解决相关技术中栅线和数据线之间的交叠区域易发生短路，而造成面板良率下降的问题。
因此，本发明实施例提供了一种阵列基板，包括：衬底基板，位于所述衬底基板上依次层叠设置的遮光金属层、缓冲层、有源层、栅极绝缘层、栅极、层间绝缘层、源漏极和钝化层；所述栅极所在的第一金属膜层还包括栅线，所述源漏极所在的第二金属膜层还包括数据线；
所述栅线在与所述数据线相对区域的表面具有氧化物金属层。
可选地，在具体实施时，在本发明实施例提供的上述阵列基板中，所述相对区域包括：所述栅线和所述数据线的交叠区域，以及沿所述栅线延伸方向超出所述交叠区域的两个对称的第一区域。
可选地，在具体实施时，在本发明实施例提供的上述阵列基板中，所述第一区域沿所述栅线延伸方向的宽度为2μm-3um。
可选地，在具体实施时，在本发明实施例提供的上述阵列基板中，所述第一金属膜层包括位于所述栅极绝缘层背向所述衬底基板一侧依次层叠设置的第一钼金属层、铜金属层、铝金属层和第二钼金属层，所述相对区域包括所述第一钼金属层、所述铜金属层和部分所述铝金属层，所述氧化物金属层为所述铝金属层的表面经过氧化后形成的氧化铝层。
相应地，本发明实施例还提供了一种显示装置，包括本发明实施例提供的上述任一项阵列基板。
相应地，本发明实施例还提供了一种本发明实施例提供的上述任一项阵列基板的制作方法，包括：
在衬底基板上依次形成层叠设置的遮光金属层、缓冲层、有源层和栅极绝缘层；
在所述栅极绝缘层上形成第一金属膜层，对所述第一金属膜层进行构图形成栅极和栅线的图案；
在所述栅线与将要形成的数据线相对区域的表面形成氧化物金属层；
在所述氧化物金属层上依次形成层间绝缘层、第二金属膜层和钝化层，所述第二金属膜层包括数据线和源漏极的图案。
可选地，在具体实施时，在本发明实施例提供的上述阵列基板的制作方法中，在所述栅极绝缘层上形成第一金属膜层，具体包括：
在所述栅极绝缘层上依次沉积第一钼金属层、铜金属层、铝金属层和第二钼金属层；
对所述第一金属膜层进行构图形成栅极和栅线的图案，具体包括：
在所述第二钼金属层上形成光刻胶层；
对所述光刻胶层进行图案化处理，形成光刻胶图案；所述光刻胶图案包括部分保留区域、完全保留区域和完全去除区域；其中，所述部分保留区域覆盖所述相对区域，所述完全保留区域覆盖所述栅极所在区域，所述完全去除区域覆盖其它区域；
以所述光刻胶图案作为遮挡，对暴露出的所述第一钼金属层、所述铜金属层、所述铝金属层和所述第二钼金属层进行湿法刻蚀处理，形成所述栅极和所述栅线的图案。
可选地，在具体实施时，在本发明实施例提供的上述阵列基板的制作方法中，在所述栅线与将要形成的数据线相对区域的表面形成氧化物金属层，具体包括：
采用灰化工艺去除所述部分保留区域的光刻胶层；
对所述栅极绝缘层进行干法刻蚀处理的同时，刻蚀掉所述部分保留区域的第二金属钼层；
采用包含O2的等离子体对所述相对区域的铝金属层进行氧化处理，形成氧化铝层。
可选地，在具体实施时，在本发明实施例提供的上述阵列基板的制作方法中，在采用包含O2的等离子体对所述相对区域的铝金属层进行氧化处理之前，还包括：
对所述栅极绝缘层进行干法刻蚀处理后暴露出的所述有源层进行导体化处理。
可选地，在具体实施时，在本发明实施例提供的上述阵列基板的制作方法中，对所述光刻胶层进行图案化处理，具体包括：
采用半色调掩膜版对所述光刻胶层进行图案化处理；其中，所述半色调掩膜版包括：与所述完全去除区域对应的完全透光区域，与所述部分保留区域对应的部分透光区域，以及与所述完全保留区域对应的不透光区域；所述部分透光区域的透光量为所述完全透光区域的透光量的75％-85％。
可选地，在具体实施时，在本发明实施例提供的上述阵列基板的制作方法中，所述光刻胶层的厚度为2.0μm-2.2μm，所述部分保留区域的光刻胶图案的厚度为0.3μm-0.5μm。
可选地，在具体实施时，在本发明实施例提供的上述阵列基板的制作方法中，对所述栅极绝缘层进行干法刻蚀处理，具体包括：
采用O2和CF4的组合气体对所述栅极绝缘层进行干法刻蚀处理，所述O2的流量为1000sccm～1500sccm，CF4的流量为2000sccm～2500sccm。
本发明实施例的有益效果：
本发明实施例提供的阵列基板、其制作方法及显示装置，该阵列基板包括：衬底基板，位于衬底基板上依次层叠设置的遮光金属层、缓冲层、有源层、栅极绝缘层、栅极、层间绝缘层、源漏极和钝化层；栅极所在的第一金属膜层还包括栅线，源漏极所在的第二金属膜层还包括数据线；栅线在与数据线相对区域的表面具有氧化物金属层。本发明通过在与数据线具有相对区域的栅线的表面设置氧化物金属层，由于氧化物金属层的介电常数和击穿电压较高，可以极大的降低栅线和数据线在交叠区域发生短路的可能性。因此采用本发明实施例提供的阵列基板能够解决相关技术中栅线和数据线之间的交叠区域易发生短路，而造成面板良率下降的问题。
附图说明
图1为相关技术中提供的阵列基板的结构示意图；
图2为本发明实施例提供的阵列基板的结构示意图；
图3为图2所示的阵列基板的部分膜层的俯视结构示意图；
图4为本发明实施例提供的阵列基板的制作方法的流程图之一；
图5为本发明实施例提供的阵列基板的制作方法的流程图之二；
图6为本发明实施例提供的阵列基板的制作方法的流程图之三；
图7为本发明实施例提供的阵列基板的制作方法的流程图之四；
图8A至图8N为本发明实施例提供的阵列基板的制作方法中执行各步骤之后的剖面示意图。
具体实施方式
为了使本发明的目的，技术方案和优点更加清楚，下面结合附图，对本发明实施例提供的阵列基板、其制作方法及显示装置的具体实施方式进行详细地说明。
附图中各层薄膜厚度和形状不反映阵列基板的真实比例，目的只是示意说明本发明内容。
顶栅结构的TFT相比底栅结构的TFT具有高的开态电流、更高开口率和更好的TFT稳定性而受到关注。
如图1所示，相关技术中采用顶栅结构的TFT的阵列基板包括衬底基板1，以及依次设置在衬底基板1上的遮光金属层2、缓冲层3、有源层4、栅极绝缘层5、栅极金属层6、层间绝缘层7，形成在层间绝缘层7上的源漏金属层8，以及覆盖源漏金属层8的钝化层9。栅极金属层6包括栅极61和栅线62，源漏金属层8包括源极81、漏极82和数据线83。其中源极81和漏极82分别通过贯穿层间绝缘层7的过孔与有源层4电连接。
在制备采用顶栅结构的TFT的阵列基板的过程中，栅极金属层6和源漏金属层8均使用铜，且栅极金属层6使用铜的厚度可达到400nm以上，源漏金属层8使用铜的厚度可达到500nm以上。因沉积铜厚度较厚，湿刻后铜角度(栅线62的侧面和底面之间的夹角θ)难以改善，且该夹角θ通常在60度以上，这样在后续采用沉积工艺在栅极金属层6上沉积层间绝缘层7时，因夹角θ的原因，栅线62的边缘较陡，沉积的层间绝缘层7在栅线62的边缘会变薄，无法完全阻止栅线62和数据线83短路，另外铜在高温沉积或刻蚀工艺时针对层间绝缘层7(SiO材料)具有热扩散性，故而在栅线62和数据线83的交叠区域(图1中虚线框所示)较易发生栅线62和数据线83短路，使得显示面板产生亮线，造成显示面板良率下降。
有鉴于此，为了解决上述问题，本发明实施例提供了一种阵列基板，如图2和图3所示，图2为该阵列基板的剖面结构示意图，图3为图2中部分膜层的俯视结构示意图，该阵列基板包括：衬底基板1，位于衬底基板1上依次层叠设置的遮光金属层2、缓冲层3、有源层4、栅极绝缘层5、栅极61、层间绝缘层7、源漏极(源极81和漏极82)和钝化层9；栅极61所在的第一金属膜层还包括栅线62，源漏极(源极81和漏极82)所在的第二金属膜层还包括数据线83；
栅线62在与数据线83相对区域的表面具有氧化物金属层10。
本发明实施例提供的阵列基板包括：衬底基板，位于衬底基板上依次层叠设置的遮光金属层、缓冲层、有源层、栅极绝缘层、栅极、层间绝缘层、源漏极和钝化层；栅极所在的第一金属膜层还包括栅线，源漏极所在的第二金属膜层还包括数据线；栅线在与数据线相对区域的表面具有氧化物金属层。本发明通过在与数据线具有相对区域的栅线的表面设置氧化物金属层，由于氧化物金属层的介电常数和击穿电压较高，可以极大的降低栅线和数据线在交叠区域发生短路的可能性。因此采用本发明实施例提供的阵列基板能够解决相关技术中栅线和数据线之间的交叠区域易发生短路，而造成面板良率下降的问题。
进一步地，在具体实施时，在本发明实施例提供的上述阵列基板中，如图3所示，相对区域包括：栅线62和数据线83的交叠区域(图3中黑色虚线框所示)，以及沿栅线62延伸方向超出交叠区域的两个对称的第一区域A。即氧化物金属层10覆盖栅线62和数据线83的交叠区域(图3中黑色虚线框所示)，以及覆盖沿栅线62延伸方向超出交叠区域的两个对称的第一区域A。
进一步地，在具体实施时，为了保证氧化物金属层完全覆盖栅线侧面以及栅线与数据线的交叠区域，在本发明实施例提供的上述阵列基板中，如图3所示，第一区域A沿栅线62延伸方向的宽度为2μm-3um。
进一步地，在具体实施时，在本发明实施例提供的上述阵列基板中，如图2所示，第一金属膜层包括位于栅极绝缘层7背向衬底基板1一侧依次层叠设置的第一钼金属层、铜金属层、铝金属层和第二钼金属层，即本发明实施例中栅极61是由层叠设置的第一钼金属层、铜金属层、铝金属层和第二钼金属层构成；相对区域包括第一钼金属层、铜金属层和部分铝金属层，即本发明实施例中栅线62是由层叠设置的第一钼金属层、铜金属层和部分铝金属层构成；氧化物金属层10为铝金属层的表面经过氧化后形成的氧化铝层。由于氧化铝的介电常数和击穿电压较高，因此可以极大的降低栅线和数据线在交叠区域发生短路的可能性。
进一步地，在具体实施时，在本发明实施例提供的上述阵列基板中，如图2所示，该阵列基板具有TFT区域B，电容区域C，以及栅线62和数据线83的交叠区域D。
需要说明的是，本发明实施例提供的阵列基板可以应用于液晶显示面板(LiquidCrystal Display，LCD)和有机电致发光二极管(Organic Light Emitting Diode，OLED)显示面板。
当阵列基板应用于液晶显示面板时，该阵列基板还可以包括与TFT的漏极电连接的像素电极；进一步地，还可以包括公共电极。
当阵列基板应用于OLED显示面板时，该阵列基板还可以包括与TFT的漏极电连接的阳极、阴极以及位于阳极和阴极之间的有机功能层。
基于同一发明构思，本发明实施例还提供了一种阵列基板的制作方法，如图4所示，包括：
S401、在衬底基板上依次形成层叠设置的遮光金属层、缓冲层、有源层和栅极绝缘层；
S402、在栅极绝缘层上形成第一金属膜层，对第一金属膜层进行构图形成栅极和栅线的图案；
S403、在栅线与将要形成的数据线相对区域的表面形成氧化物金属层；
S404、在氧化物金属层上依次形成层间绝缘层、第二金属膜层和钝化层，第二金属膜层包括数据线和源漏极的图案。
本发明实施例提供的阵列基板的制作方法，通过在与数据线具有相对区域的栅线的表面形成氧化物金属层，由于氧化物金属层的介电常数和击穿电压较高，可以极大的降低栅线和数据线在交叠区域发生短路的可能性。因此采用本发明实施例提供的制作方法制得的阵列基板能够解决相关技术中栅线和数据线之间的交叠区域易发生短路，而造成面板良率下降的问题。
进一步地，在具体实施时，在本发明实施例提供的上述阵列基板的制作方法中，在栅极绝缘层上形成第一金属膜层，具体可以包括：
在栅极绝缘层上依次沉积第一钼金属层、铜金属层、铝金属层和第二钼金属层；
如图5所示，对第一金属膜层进行构图形成栅极和栅线的图案，具体可以包括：
S501、在第二钼金属层上形成光刻胶层；
S502、对光刻胶层进行图案化处理，形成光刻胶图案；光刻胶图案包括部分保留区域、完全保留区域和完全去除区域；其中，部分保留区域覆盖相对区域，光刻胶完全保留区域覆盖栅极所在区域，完全去除区域覆盖其它区域；
S503、以光刻胶图案作为遮挡，对暴露出的第一钼金属层、铜金属层、铝金属层和第二钼金属层进行湿法刻蚀处理，形成栅极和栅线的图案。
进一步地，在具体实施时，在本发明实施例提供的上述阵列基板的制作方法中，如图6所示，在栅线与将要形成的数据线相对区域的表面形成氧化物金属层，具体可以包括：
S601、采用灰化工艺去除部分保留区域的光刻胶层；
S602、对栅极绝缘层进行干法刻蚀处理的同时，刻蚀掉部分保留区域的第二金属钼层；
S603、采用包含O2的等离子体对相对区域的铝金属层进行氧化处理，形成氧化铝层。
进一步地，在具体实施时，在本发明实施例提供的上述阵列基板的制作方法中，如图7所示，在采用包含O2的等离子体对相对区域的铝金属层进行氧化处理之前，还包括：
S603’、对栅极绝缘层进行干法刻蚀处理后暴露出的有源层进行导体化处理。
进一步地，在具体实施时，在本发明实施例提供的上述阵列基板的制作方法中，对光刻胶层进行图案化处理，具体包括：
采用半色调掩膜版对光刻胶层进行图案化处理；其中，半色调掩膜版包括：与完全去除区域对应的完全透光区域，与部分保留区域对应的部分透光区域，以及与完全保留区域对应的不透光区域；部分透光区域的透光量为完全透光区域的透光量的75％-85％。
进一步地，在具体实施时，在本发明实施例提供的上述阵列基板的制作方法中，光刻胶层的厚度可以为2.0μm-2.2μm，部分保留区域的光刻胶图案的厚度可以为0.3μm-0.5μm。
进一步地，在具体实施时，在本发明实施例提供的上述阵列基板的制作方法中，对栅极绝缘层进行干法刻蚀处理，具体可以包括：
采用O2和CF4的组合气体对栅极绝缘层进行干法刻蚀处理，O2的流量为1000sccm～1500sccm，CF4的流量为2000sccm～2500sccm。
下面通过具体实施例对本发明实施例提供的阵列基板的制作方法进行详细说明。
(1)可以利用化学气相沉积法在衬底基板1上沉积一层遮光金属薄膜，遮光金属薄膜可以为钼或钼铌合金等金属，厚度可以为0.10μm～0.15μm，紧接着通过曝光、显影和湿法刻蚀后形成遮光金属层2，如图8A所示；具体地，湿法刻蚀遮光金属薄膜可采用混酸进行刻蚀。
(2)可以利用化学气相沉积法或者磁控溅射的方法在衬底基板1上沉积一层缓冲层3，如图8B所示；具体地，该缓冲层3的材料可以为氧化硅，厚度可以为0.3μm～0.5μm。
(3)可以利用化学气相沉积法在缓冲层3上沉积金属氧化物半导体薄膜，然后对金属氧化物半导体薄膜进行一次构图工艺形成有源层4，如图8C所示，即在光刻胶涂覆后，用普通的掩膜板对光刻胶进行曝光、显影、刻蚀形成有源层4。具体地，有源层4的材料可以为氧化铟锡(IGZO)，厚度可以为0.05μm～0.1μm。
(4)可以利用化学气相沉积法或者磁控溅射的方法在衬底基板1上沉积一层栅极绝缘薄膜01，如图8D所示；具体地，该栅极绝缘薄膜01的材料可以为氧化硅，厚度为0.1μm～0.2μm。
(5)可以利用磁控溅射的方法在衬底基板1上沉积一层第一金属膜层，具体地，可以在栅极绝缘薄膜01上依次沉积由第一钼金属层001、铜金属层002、铝金属层003和第二钼金属层004构成的第一金属膜层，如图8E所示；具体地，第一钼金属层001的厚度可以为0.03μm～0.04μm，铜金属层002的厚度可以为0.4μm～0.5μm，铝金属层003的厚度可以为0.06μm～0.08μm，第二钼金属层004的厚度可以为0.05μm。
(6)在第二钼金属层004上形成光刻胶层，然后利用半色调掩膜板对光刻胶层进行曝光、显影和刻蚀，形成光刻胶图案，如图8F所示；具体地，光刻胶图案包括部分保留区域021、完全保留区域022和完全去除区域；其中，部分保留区域021覆盖相对区域(即将形成的栅线62区域)，完全保留区域022覆盖栅极61所在区域，完全去除区域覆盖其它区域。具体地，光刻胶层为正性光刻胶，其厚度可以为2.0μm～2.2μm，部分保留区域021的光刻胶厚度可以为0.3μm～0.5μm。
(7)以光刻胶图案(021和022)作为遮挡，对暴露出的第一钼金属层001、铜金属层002、铝金属层003和第二钼金属层004进行湿法刻蚀处理，形成栅极61和栅线62的图案，如图8G所示；具体地，湿法刻蚀上述四个金属层可采用混酸进行刻蚀，例如一定配比的硝酸、醋酸和磷酸。
(8)采用灰化工艺去除部分保留区域021的光刻胶层，如图8H所示；具体地，采用流量为10000sccm～12000sccm的O2、控制相应时间以及采用高源功率和高偏置功率进行灰化掉部分保留区域02的0.3μm～0.5μm的光刻胶。
(9)保留栅极61上方的栅极掩膜(即光刻胶图案022)对栅极绝缘薄膜01进行干法刻蚀处理，形成栅极绝缘层5，在对栅极绝缘薄膜02进行干法刻蚀处理的同时，刻蚀掉相对区域的第二金属钼层004，如图8I所示；具体地，采用流量为2000sccm～2500sccm的CF4和流量为1000sccm～1500sccm的O2混合气体对无光刻胶保护的栅极绝缘薄膜02进行干法刻蚀，特别的栅极绝缘薄膜02在干法刻蚀的同时，可以将图栅线62最上方的第二金属钼层004刻蚀掉。
(10)继续保留栅极61上方的栅极掩膜(即光刻胶图案022)对在栅极绝缘层进行干法刻蚀处理后暴露出的有源层4进行导体化处理。由于有源层4包括被栅极绝缘层5覆盖的沟道区以及分别位于沟道区两侧的源极接触区域漏极接触区，因此，通过对源极接触区和漏极接触区进行导体化处理，能够降低即将形成的源极61、漏极61和有源层4的接触电阻，提高导电性。具体地，可以采用氨气(NH3)或者氦气(He)进行导体化处理。
(11)采用包含O2的等离子体对相对区域的铝金属层003的表面进行氧化处理，使铝金属层003的表面形成氧化物金属层10，即氧化铝层，如图8J所示；具体地，可以采用流量为10000sccm～12000sccm的O2，由于栅极绝缘薄膜02在干刻时使完全保留区域022的光刻胶的表面生成了表面硬化光阻，该氧化处理过程中不仅可以将光刻胶表面生成的硬化光阻去掉，而且可以对相对区域的铝金属层003的表面进行氧化使其转变为氧化铝。
(12)对完全保留区域022的光刻胶进行湿法剥离，如图8K所示。
(13)在氧化物金属层10上形成层间绝缘层7，如图8L所示。具体地，层间绝缘层7的材料可以为氧化硅，厚度可以为0.45μm～0.6μm。
(14)采用和制作栅极61、栅线62类似的方法，在层间绝缘层7上沉积一层第二金属膜层，通过构图工艺形成源极81、漏极82和数据线83，如图8M所示。具体地，如沉积一层金属铜，厚度可以为0.5μm～0.6μm，随后进行光刻掩膜，源漏极掩膜光刻胶的厚度可以为1.5μm～1.8μm，所用光刻胶为正性光刻胶，利用此掩膜先进行数据线湿刻，铜湿刻可采用双氧水(H2O2)药液进行，湿刻完成后进行光阻剥离，光阻剥离完成后数据线83的线宽应为10μm以下。
(15)最后沉积一层钝化层9，如图8N所示。具体地，钝化层9的材料可以为氧化硅，厚度可以为0.3μm～0.5μm。
通过上述步骤(1)至步骤(15)后即可在栅线62和数据线83的相对区域即交叉区域形成氧化铝层，由于氧化铝的介电常数和击穿电压更高，故而可极大降低栅线62与数据线83短路的可能性。
基于同一发明构思，本发明实施例还提供了一种显示装置，包括本发明实施例提供的上述阵列基板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述阵列基板的实施例，重复之处不再赘述。
本发明实施例提供的阵列基板、其制作方法及显示装置，该阵列基板包括：衬底基板，位于衬底基板上依次层叠设置的遮光金属层、缓冲层、有源层、栅极绝缘层、栅极、层间绝缘层、源漏极和钝化层；栅极所在的第一金属膜层还包括栅线，源漏极所在的第二金属膜层还包括数据线；栅线在与数据线相对区域的表面具有氧化物金属层。本发明通过在与数据线具有相对区域的栅线的表面设置氧化物金属层，由于氧化物金属层的介电常数和击穿电压较高，可以极大的降低栅线和数据线在交叠区域发生短路的可能性。因此采用本发明实施例提供的阵列基板能够解决相关技术中栅线和数据线之间的交叠区域易发生短路，而造成面板良率下降的问题。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (12)

1.一种阵列基板，其特征在于，包括：衬底基板，位于所述衬底基板上依次层叠设置的遮光金属层、缓冲层、有源层、栅极绝缘层、栅极、层间绝缘层、源漏极和钝化层；所述栅极所在的第一金属膜层还包括栅线，所述源漏极所在的第二金属膜层还包括数据线；
所述栅线在与所述数据线相对区域的表面具有氧化物金属层。
2.如权利要求1所述的阵列基板，其特征在于，所述相对区域包括：所述栅线和所述数据线的交叠区域，以及沿所述栅线延伸方向超出所述交叠区域的两个对称的第一区域。
3.如权利要求1所述的阵列基板，其特征在于，所述第一区域沿所述栅线延伸方向的宽度为2μm-3um。
4.如权利要求1所述的阵列基板，其特征在于，所述第一金属膜层包括位于所述栅极绝缘层背向所述衬底基板一侧依次层叠设置的第一钼金属层、铜金属层、铝金属层和第二钼金属层，所述相对区域包括所述第一钼金属层、所述铜金属层和部分所述铝金属层，所述氧化物金属层为所述铝金属层的表面经过氧化后形成的氧化铝层。
5.一种显示装置，其特征在于，包括如权利要1-4任一项所述的阵列基板。
6.一种如权利要求1-4任一项所述的阵列基板的制作方法，其特征在于，包括：
在衬底基板上依次形成层叠设置的遮光金属层、缓冲层、有源层和栅极绝缘层；
在所述栅极绝缘层上形成第一金属膜层，对所述第一金属膜层进行构图形成栅极和栅线的图案；
在所述栅线与将要形成的数据线相对区域的表面形成氧化物金属层；
在所述氧化物金属层上依次形成层间绝缘层、第二金属膜层和钝化层，所述第二金属膜层包括数据线和源漏极的图案。
7.如权利要求6所述的阵列基板的制作方法，其特征在于，在所述栅极绝缘层上形成第一金属膜层，具体包括：
在所述栅极绝缘层上依次沉积第一钼金属层、铜金属层、铝金属层和第二钼金属层；
对所述第一金属膜层进行构图形成栅极和栅线的图案，具体包括：
在所述第二钼金属层上形成光刻胶层；
对所述光刻胶层进行图案化处理，形成光刻胶图案；所述光刻胶图案包括部分保留区域、完全保留区域和完全去除区域；其中，所述部分保留区域覆盖所述相对区域，所述完全保留区域覆盖所述栅极所在区域，所述完全去除区域覆盖其它区域；
以所述光刻胶图案作为遮挡，对暴露出的所述第一钼金属层、所述铜金属层、所述铝金属层和所述第二钼金属层进行湿法刻蚀处理，形成所述栅极和所述栅线的图案。
8.如权利要求6所述的阵列基板的制作方法，其特征在于，在所述栅线与将要形成的数据线相对区域的表面形成氧化物金属层，具体包括：
采用灰化工艺去除所述部分保留区域的光刻胶层；
对所述栅极绝缘层进行干法刻蚀处理的同时，刻蚀掉所述部分保留区域的第二金属钼层；
采用包含O2的等离子体对所述相对区域的铝金属层进行氧化处理，形成氧化铝层。
9.如权利要求8所述的阵列基板的制作方法，其特征在于，在采用包含O2的等离子体对所述相对区域的铝金属层进行氧化处理之前，还包括：
对所述栅极绝缘层进行干法刻蚀处理后暴露出的所述有源层进行导体化处理。
10.如权利要求7所述的阵列基板的制作方法，其特征在于，对所述光刻胶层进行图案化处理，具体包括：
采用半色调掩膜版对所述光刻胶层进行图案化处理；其中，所述半色调掩膜版包括：与所述完全去除区域对应的完全透光区域，与所述部分保留区域对应的部分透光区域，以及与所述完全保留区域对应的不透光区域；所述部分透光区域的透光量为所述完全透光区域的透光量的75％-85％。
11.如权利要求10所述的阵列基板的制作方法，其特征在于，所述光刻胶层的厚度为2.0μm-2.2μm，所述部分保留区域的光刻胶图案的厚度为0.3μm-0.5μm。
12.如权利要求8所述的阵列基板的制作方法，其特征在于，对所述栅极绝缘层进行干法刻蚀处理，具体包括：
采用O2和CF4的组合气体对所述栅极绝缘层进行干法刻蚀处理，所述O2的流量为1000sccm～1500sccm，CF4的流量为2000sccm～2500sccm。
CN201910468906.9A 2019-05-31 2019-05-31 一种阵列基板、其制作方法及显示装置 Active CN110148601B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201910468906.9A CN110148601B (zh) 2019-05-31 2019-05-31 一种阵列基板、其制作方法及显示装置
PCT/CN2020/090315 WO2020238640A1 (zh) 2019-05-31 2020-05-14 一种显示基板及其制作方法、显示装置
US17/265,789 US11961848B2 (en) 2019-05-31 2020-05-14 Display substrate and manufacturing method therefor, and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910468906.9A CN110148601B (zh) 2019-05-31 2019-05-31 一种阵列基板、其制作方法及显示装置

Publications (2)

Publication Number Publication Date
CN110148601A true CN110148601A (zh) 2019-08-20
CN110148601B CN110148601B (zh) 2022-12-20

Family

ID=67589944

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910468906.9A Active CN110148601B (zh) 2019-05-31 2019-05-31 一种阵列基板、其制作方法及显示装置

Country Status (3)

Country Link
US (1) US11961848B2 (zh)
CN (1) CN110148601B (zh)
WO (1) WO2020238640A1 (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110908199A (zh) * 2019-11-15 2020-03-24 武汉华星光电技术有限公司 阵列基板及液晶显示面板
CN111244115A (zh) * 2020-03-09 2020-06-05 合肥鑫晟光电科技有限公司 一种显示用基板及其制备方法、显示装置
WO2020238640A1 (zh) * 2019-05-31 2020-12-03 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置
CN113675222A (zh) * 2021-08-24 2021-11-19 京东方科技集团股份有限公司 一种tft基板、电子纸显示屏、显示设备及其制备方法
WO2021248605A1 (zh) * 2020-06-10 2021-12-16 深圳市华星光电半导体显示技术有限公司 阵列基板及显示面板
WO2023206071A1 (zh) * 2022-04-26 2023-11-02 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1447153A (zh) * 2002-03-22 2003-10-08 精工爱普生株式会社 电光装置及其制造方法以及电子机器
CN1615452A (zh) * 2002-01-15 2005-05-11 三星电子株式会社 显示器布线及其制造方法与包含该布线的薄膜晶体管阵列面板及其制造方法
US20070188671A1 (en) * 2001-07-07 2007-08-16 Hwang Kwang J Array substrate of liquid crystal display and fabricating method thereof
CN103367248A (zh) * 2013-07-01 2013-10-23 京东方科技集团股份有限公司 阵列基板、制备方法以及显示装置
CN103779360A (zh) * 2014-02-12 2014-05-07 鄂尔多斯市源盛光电有限责任公司 显示基板及其制作方法、显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3009438B2 (ja) * 1989-08-14 2000-02-14 株式会社日立製作所 液晶表示装置
JP2781706B2 (ja) * 1991-09-25 1998-07-30 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
JP3494720B2 (ja) 1994-11-01 2004-02-09 株式会社半導体エネルギー研究所 半導体装置及びその作製方法、ならびにアクティブマトリクス型の液晶ディスプレー及びイメージセンサー
CN101887893B (zh) * 2010-06-10 2012-01-11 深超光电（深圳）有限公司 一种薄膜晶体管阵列基板及其制造方法
CN102646632B (zh) * 2012-03-08 2014-04-02 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置
CN103400802B (zh) * 2013-07-30 2016-04-13 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置
CN104766802B (zh) * 2015-03-26 2019-05-03 深圳市华星光电技术有限公司 液晶显示面板、阵列基板及其薄膜晶体管的制造方法
CN110148601B (zh) 2019-05-31 2022-12-20 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070188671A1 (en) * 2001-07-07 2007-08-16 Hwang Kwang J Array substrate of liquid crystal display and fabricating method thereof
CN1615452A (zh) * 2002-01-15 2005-05-11 三星电子株式会社 显示器布线及其制造方法与包含该布线的薄膜晶体管阵列面板及其制造方法
CN1447153A (zh) * 2002-03-22 2003-10-08 精工爱普生株式会社 电光装置及其制造方法以及电子机器
CN103367248A (zh) * 2013-07-01 2013-10-23 京东方科技集团股份有限公司 阵列基板、制备方法以及显示装置
CN103779360A (zh) * 2014-02-12 2014-05-07 鄂尔多斯市源盛光电有限责任公司 显示基板及其制作方法、显示装置

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020238640A1 (zh) * 2019-05-31 2020-12-03 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置
US11961848B2 (en) 2019-05-31 2024-04-16 Hefei Xinsheng Optoelectronics Technology Co., Ltd. Display substrate and manufacturing method therefor, and display device
CN110908199A (zh) * 2019-11-15 2020-03-24 武汉华星光电技术有限公司 阵列基板及液晶显示面板
CN111244115A (zh) * 2020-03-09 2020-06-05 合肥鑫晟光电科技有限公司 一种显示用基板及其制备方法、显示装置
CN111244115B (zh) * 2020-03-09 2022-12-02 合肥鑫晟光电科技有限公司 一种显示用基板及其制备方法、显示装置
WO2021248605A1 (zh) * 2020-06-10 2021-12-16 深圳市华星光电半导体显示技术有限公司 阵列基板及显示面板
CN113675222A (zh) * 2021-08-24 2021-11-19 京东方科技集团股份有限公司 一种tft基板、电子纸显示屏、显示设备及其制备方法
WO2023206071A1 (zh) * 2022-04-26 2023-11-02 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置

Also Published As

Publication number Publication date
WO2020238640A1 (zh) 2020-12-03
US11961848B2 (en) 2024-04-16
US20210167098A1 (en) 2021-06-03
CN110148601B (zh) 2022-12-20

Similar Documents

Publication Publication Date Title
JP6129312B2 (ja) アレイ基板の製造方法、アレイ基板及び表示装置
CN110148601A (zh) 一种阵列基板、其制作方法及显示装置
KR101325053B1 (ko) 박막 트랜지스터 기판 및 이의 제조 방법
US9349760B2 (en) Method of manufacturing a TFT-LCD array substrate having light blocking layer on the surface treated semiconductor layer
CN103378164B (zh) 阵列基板及其制造方法
KR101019048B1 (ko) 어레이 기판 및 이의 제조방법
US10964790B1 (en) TFT substrate and manufacturing method thereof
US9761616B2 (en) Manufacturing method of array substrate with reduced number of patterning processes array substrate and display device
CN110164873B (zh) 阵列基板的制作方法、阵列基板、显示面板及显示装置
CN104282769A (zh) 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置
CN103069334A (zh) 显示装置用基板及其制造方法、显示装置
KR20100094817A (ko) 어레이 기판의 제조방법
JP2007157916A (ja) Ｔｆｔ基板及びｔｆｔ基板の製造方法
KR20100063493A (ko) 박막 트랜지스터 기판 및 그 제조 방법
KR20100075026A (ko) 박막 트랜지스터 기판 및 이의 제조 방법
KR20140010361A (ko) 박막 트랜지스터 어레이 기판, 그 제조 방법, 디스플레이 패널 및 디스플레이 장치
WO2015043069A1 (zh) 阵列基板及其制备方法、显示装置
US11204532B2 (en) Wiring structure, display substrate, display device and method for fabricating display substrate
US20160313622A1 (en) Display substrate, its manufacturing method, and display device
CN103500738A (zh) 含刻蚀阻挡层的半导体器件及其制造方法和应用
CN106847830A (zh) 阵列基板及其制作方法、显示面板
EP3261127B1 (en) Thin-film transistor and manufacturing method therefor, array substrate and display device
CN107799466A (zh) Tft基板及其制作方法
WO2022116313A1 (zh) 一种阵列基板、显示面板及其制备方法
KR20100123327A (ko) 어레이 기판의 제조방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant