WO2023206071A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2023206071A1
WO2023206071A1 PCT/CN2022/089268 CN2022089268W WO2023206071A1 WO 2023206071 A1 WO2023206071 A1 WO 2023206071A1 CN 2022089268 W CN2022089268 W CN 2022089268W WO 2023206071 A1 WO2023206071 A1 WO 2023206071A1
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WIPO (PCT)
Prior art keywords
signal line
orthographic projection
base substrate
isolation pattern
display substrate
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PCT/CN2022/089268
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English (en)
French (fr)
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WO2023206071A9 (zh
Inventor
宋子科
李梁梁
荣孟欣
王尖
唐辉
台运东
蔡双双
易小强
Original Assignee
京东方科技集团股份有限公司
成都京东方显示科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方显示科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000900.9A priority Critical patent/CN117597779A/zh
Priority to PCT/CN2022/089268 priority patent/WO2023206071A1/zh
Publication of WO2023206071A1 publication Critical patent/WO2023206071A1/zh
Publication of WO2023206071A9 publication Critical patent/WO2023206071A9/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a manufacturing method thereof, and a display device.
  • Cu is generally used to make signal lines of display substrates. Signal lines of different layers cross each other. At the intersection position, an insulating layer is provided between signal lines of different layers.
  • the signal lines are prone to Cu ion diffusion, and Cu Ions penetrating the insulating layer will cause short circuits between signal lines on different layers, affecting the product yield of the display substrate.
  • the technical problem to be solved by this disclosure is to provide a display substrate, a manufacturing method thereof, and a display device, which can ensure the product yield of the display substrate.
  • a display substrate including:
  • a first signal line located on the base substrate and extending along the first direction
  • a second signal line located on the base substrate and extending along a second direction, the second signal line and the first signal line are arranged in different layers, and the second direction intersects the first direction;
  • the first signal line includes a first portion, and a first orthographic projection of the first portion on the base substrate is located within an orthographic projection of the second signal line on the base substrate;
  • the display substrate also includes:
  • the isolation pattern is located on the side of the first signal line away from the base substrate, the isolation pattern is located on the side of the second signal line close to the base substrate, and the first orthographic projection is located on the isolation side.
  • the graphic is in a second orthographic projection on the base substrate.
  • the display substrate further includes:
  • the isolation pattern is located on a side of the insulating layer close to the base substrate;
  • the isolation pattern is located on a side of the insulating layer away from the base substrate.
  • the isolation pattern is made of semiconductor material.
  • the isolation pattern uses a metal oxide semiconductor.
  • the active layer of the thin film transistor of the display substrate and the isolation pattern are arranged in the same layer and made of the same material.
  • the first signal line includes a second part in addition to the first part, and the orthographic projection of the second part on the substrate is the same as the second signal line on the substrate. Orthographic projections on the base substrate do not overlap.
  • the boundary of the second orthographic projection exceeds the boundary of the first orthographic projection, and there is a gap between the boundary of the first orthographic projection and the boundary of the second orthographic projection.
  • the minimum distance is greater than 0.2 microns.
  • the boundary of the second orthographic projection exceeds the boundary of the first orthographic projection, and there is a gap between the boundary of the first orthographic projection and the boundary of the second orthographic projection.
  • the minimum distance is greater than 0.2 microns.
  • the first signal line includes a plurality of mutually independent first parts, each of the first parts corresponds to one of the isolation patterns, and the first part is on a first front surface of the substrate.
  • the projection falls into the second orthographic projection of the corresponding isolation pattern on the base substrate, and multiple isolation patterns corresponding to the same first signal line form an integrated structure.
  • the first signal line is a gate line
  • the second signal line is a data line
  • the first signal line is a first clock signal line
  • the second signal line is a second clock signal line.
  • An embodiment of the present disclosure provides a display device including the display substrate as described above.
  • Embodiments of the present disclosure provide a method for manufacturing a display substrate, including:
  • a second signal line extending along a second direction is formed on the base substrate.
  • the second signal line and the first signal line are arranged in different layers.
  • the second direction intersects the first direction.
  • the second signal line extends along a second direction.
  • a signal line includes a first portion, a first orthographic projection of the first portion on the base substrate is located within an orthographic projection of the second signal line on the base substrate;
  • An isolation pattern is formed on the side of the first signal line away from the base substrate, the isolation pattern is located on the side of the second signal line close to the base substrate, and the first orthographic projection is located on the side of the second signal line close to the base substrate.
  • the isolation pattern is in a second orthographic projection on the base substrate.
  • the manufacturing method specifically includes:
  • the active layer of the thin film transistor of the display substrate and the isolation pattern are formed through one patterning process.
  • an isolation pattern is set between the first signal line and the second signal line.
  • the isolation pattern can block the diffusion of metal ions between the first signal line and the second signal line, and slow down the metal ion diffusion between the cross metal signal lines due to the electric field. Ion diffusion and chemical reactions ensure the product yield of display substrates.
  • Figure 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure
  • Figure 2 is a schematic cross-sectional view of a display substrate in related technology
  • 3 and 4 are schematic cross-sectional views of the substrate in the AA direction according to embodiments of the present disclosure
  • FIG. 5-7 are schematic plan views of display substrates according to specific embodiments of the present disclosure.
  • Figures 8 and 9 are enlarged schematic views of the portion in the oval frame in Figure 7.
  • Embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device, which can ensure the product yield of the display substrate.
  • An embodiment of the present disclosure provides a display substrate, as shown in Figure 1, including:
  • a first signal line 01 located on the base substrate and extending along the first direction;
  • a second signal line 02 is located on the base substrate and extends along a second direction.
  • the second signal line 02 and the first signal line 01 are arranged in different layers.
  • the second direction and the first direction cross;
  • the first signal line 01 includes a first part (the part inside the dotted line frame), and the first orthographic projection of the first part on the substrate is located on the orthogonal projection of the second signal line 02 on the substrate. within projection;
  • the display substrate also includes:
  • the isolation pattern 03 is located on the side of the first signal line 01 away from the base substrate, the isolation pattern is located on the side of the second signal line 02 close to the base substrate, and the first orthographic projection is on The isolation pattern is in a second orthographic projection on the base substrate.
  • an isolation pattern is provided between the first signal line and the second signal line.
  • the isolation pattern can block the diffusion of metal ions between the first signal line and the second signal line, and slow down the electric field between the cross metal signal lines. Metal ion diffusion and chemical reactions ensure the product yield of display substrates.
  • Cu Since Cu has good electrical conductivity, Cu is generally used to make the signal lines of the display substrate, including the first signal line and the second signal line, as shown in Figure 2.
  • the first signal line 01 and the second signal line There is an insulating layer 03 between 02.
  • the insulating layer 03 is generally made of silicon oxide, silicon nitride or silicon oxynitride. Due to the manufacturing process, the thickness of the insulating layer 03 is relatively small.
  • the first signal line 01 and the second signal line 02 will cause metal ion diffusion, resulting in the risk of short circuit between the first signal line 01 and the second signal line 02 at the intersection of the first signal line 01 and the second signal line 02.
  • the signal line After a short circuit occurs, the signal line will The temperature at the intersection position increases, which in turn causes the insulation layer at the intersection position of the signal lines to be easily damaged, destroying the sealing performance of the display substrate. Water vapor can easily invade, corrode the signal lines, and cause chemical reactions. The water vapor will also spread along the direction of the signal lines. , reducing the product yield of display substrates.
  • an isolation pattern 03 is provided between the first signal line 01 and the second signal line 02.
  • the isolation pattern 03 has a certain thickness and can block the first signal line 01 and the second signal line 02. 02's metal ion diffusion slows down the metal ion diffusion and chemical reaction caused by the electric field between the cross metal signal lines, ensuring the product yield of the display substrate.
  • the first signal line includes a second part in addition to the first part, and the orthographic projection of the second part on the substrate is the same as the second signal line on the substrate.
  • Orthographic projections on the base substrate do not overlap. That is, the orthographic projection of the first signal line on the base substrate at the signal line intersection position is all located within the orthographic projection of the isolation pattern 03 on the base substrate.
  • the first part 011 (the part inside the dotted line frame)
  • the first orthographic projection on the base substrate is located within the orthographic projection of the isolation pattern 03 on the base substrate.
  • the area of the isolation pattern 03 is larger than the area of the first part 011.
  • the first signal line 01 After metal ion diffusion occurs, the metal ions are distributed on the isolation pattern 03. Since the area of the isolation pattern 03 is relatively large, the area directly facing the isolation pattern 03 and the first signal line 01 is relatively large (compared to the area between the second signal line 02 and the first signal line 01). The area facing the first signal line 01) can reduce the distribution density of metal ions and slow down the diffusion and chemical reaction of metal ions due to the electric field between the cross metal signal lines; in contrast, after the diffusion of metal ions occurs in the second signal line 02, Metal ions are distributed on the isolation pattern 03.
  • the area of the isolation pattern 03 is relatively large, the area of the isolation pattern 03 directly facing the second signal line 02 is relatively large (compared to the area directly facing the first signal line 01 and the first signal line 01 area), can reduce the distribution density of metal ions and slow down the diffusion of metal ions and chemical reactions caused by the electric field between the cross metal signal lines.
  • the isolation pattern 03 can be located between the insulating layer 04 and the second signal line 02; or, as shown in Figure 4, the isolation pattern 03 can be located between the insulating layer 04 and the first signal line 01, as long as the isolation It suffices that the pattern 03 is located between the first signal line 01 and the second signal line 02.
  • the isolation pattern 03 can be made of materials with good waterproof properties.
  • the isolation pattern 03 can be made of semiconductor material.
  • the semiconductor material has a certain electron mobility.
  • the isolation pattern 03 can be made of metal oxide semiconductor, amorphous silicon, polycrystalline silicon, etc.
  • the isolation pattern 03 is made of a metal oxide semiconductor, such as IGZO.
  • Metal oxide semiconductor has good electron mobility and can effectively reduce the intersection position of signal lines. the electric field density at .
  • the active layer of the thin film transistor of the display substrate can be provided in the same layer and with the same material as the isolation pattern 03, so that the active layer of the thin film transistor of the display substrate and the isolation pattern 03 can be formed through one patterning process. There is no need to use a special patterning process to produce the isolation pattern 03, which can reduce the number of patterning processes for producing the display substrate and reduce the production cost of the display substrate.
  • the thickness of the isolation pattern 03 can be the same as the thickness of the active layer of the thin film transistor, or the thickness of the isolation pattern 03 can be adjusted, and the thickness of the isolation pattern 03 is designed to be greater than the thickness of the active layer of the thin film transistor, so as to better To reduce the electric field density at the intersection of the signal lines, the thickness of the isolation pattern 03 should be no less than 100nm.
  • the boundary of the second orthographic projection exceeds the boundary of the first orthographic projection, and the first orthographic projection
  • the minimum distance d1 between the boundary of the orthographic projection and the boundary of the second orthographic projection is greater than 0.2 microns.
  • the isolation pattern 03 can spatially block the diffusion of metal ions between the first signal line 01 and the second signal line 02 .
  • d1 greater than 0.2 microns can change the water vapor diffusion path and reduce the possibility of water vapor intrusion.
  • d1 can be greater than a+0.2 microns, where a is the maximum fluctuation value of the critical dimensions of the first signal line 01 and the isolation pattern 03 during the manufacturing process. This can reduce the impact of the manufacturing process on the display substrate product yield.
  • the boundary of the second orthographic projection exceeds the boundary of the first orthographic projection, and the first orthographic projection
  • the minimum distance d2 between the boundary of the orthographic projection and the boundary of the second orthographic projection is greater than 0.2 microns.
  • the isolation pattern 03 can spatially block the diffusion of metal ions between the first signal line 01 and the second signal line 02 .
  • d1 greater than 0.2 microns can change the water vapor diffusion path and reduce the possibility of water vapor intrusion.
  • d2 can be greater than b+0.2 microns, where b is the maximum fluctuation value of the critical dimensions of the second signal line 02 and the isolation pattern 03 during the manufacturing process. This can reduce the impact of the manufacturing process on the display substrate product yield.
  • the signal lines can adopt various shapes.
  • the first signal line 01 and the second signal line 02 may be linear; as shown in Figure 5, the second signal line 02 may also include a plurality of hollow areas 021 at the intersection positions of the signal lines.
  • the first signal line can also include a plurality of hollow areas at the intersection positions of the signal lines, which can reduce the facing area between the signal lines, reduce the electric field density at the intersection positions of the signal lines, and slow down the occurrence of electric fields between the crossing metal signal lines.
  • the diffusion and chemical reaction of metal ions prevents corrosion at the intersection of signal lines, thereby preventing water vapor from diffusing along the signal lines and ensuring display product yield.
  • the second signal line 02 may also be in a serpentine shape.
  • the first signal line is a gate line
  • the second signal line is a data line
  • the first signal line is a first clock signal line
  • the second signal line is a second clock signal line. signal line.
  • the first signal line is not limited to the gate line and the first clock signal line
  • the second signal line is not limited to the data line and the second clock signal line, and may also be other signal lines.
  • gate lines and data lines intersect vertically and horizontally.
  • An isolation pattern 03 is set at the intersection of the gate lines and data lines, which can block the diffusion of metal ions between the gate lines and data lines and slow down the electric field between the crossing metal signal lines. Metal ion diffusion and chemical reactions ensure the product yield of display substrates.
  • the first clock signal line 07 and the second clock signal line 08 cross vertically and horizontally.
  • the first clock signal line 07 and the second clock signal line 08 pass through the via hole 06. connect.
  • an isolation pattern 03 is provided at the intersection of the first clock signal line 07 and the second clock signal line 08, which can block the diffusion of metal ions of the first clock signal line 07 and the second clock signal line 08. , slow down the metal ion diffusion and chemical reaction caused by the electric field between the cross metal signal lines, and ensure the product yield of the display substrate.
  • Figure 8 is an enlarged schematic diagram of the position of the oval frame in Figure 7.
  • the first clock signal line 07 can include a hollow area, and the hollow area connects the first clock signal
  • the line 07 is divided into two mutually independent first parts (the hollow area can also divide the first clock signal line 07 into three or more mutually independent first parts), and each of the first parts corresponds to one of the isolation patterns 03 , the first orthographic projection of the first part on the base substrate falls within the second orthographic projection of the corresponding isolation pattern on the base substrate.
  • isolation patterns corresponding to the same first signal line can be integrated into an integrated structure, as shown in FIG. 9 .
  • the minimum distance d1 between the boundary of the first orthographic projection and the boundary of the second orthographic projection may be 2.5-3.3 microns.
  • the minimum distance d2 between the boundary of the first orthographic projection and the boundary of the second orthographic projection may be 4.5-5.05 microns.
  • An embodiment of the present disclosure provides a display device including the display substrate as described above.
  • the display device includes but is not limited to: a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, a power supply and other components.
  • a radio frequency unit a radio frequency unit
  • a network module an audio output unit
  • an input unit a sensor
  • a display unit a user input unit
  • an interface unit a memory
  • a processor a power supply and other components.
  • display devices include but are not limited to monitors, mobile phones, tablet computers, televisions, wearable electronic devices, navigation display devices, and the like.
  • the display device may be any product or component with a display function such as a television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, etc.
  • the display device further includes a flexible circuit board, a printed circuit board and a backplane.
  • Embodiments of the present disclosure provide a method for manufacturing a display substrate, including:
  • a second signal line extending along a second direction is formed on the base substrate.
  • the second signal line and the first signal line are arranged in different layers.
  • the second direction intersects the first direction.
  • the second signal line extends along a second direction.
  • a signal line includes a first portion, a first orthographic projection of the first portion on the base substrate is located within an orthographic projection of the second signal line on the base substrate;
  • An isolation pattern is formed on the side of the first signal line away from the base substrate, the isolation pattern is located on the side of the second signal line close to the base substrate, and the first orthographic projection is located on the side of the second signal line close to the base substrate.
  • the isolation pattern is in a second orthographic projection on the base substrate.
  • an isolation pattern is provided between the first signal line and the second signal line.
  • the isolation pattern can block the diffusion of metal ions between the first signal line and the second signal line, and slow down the electric field between the cross metal signal lines. Metal ion diffusion and chemical reactions ensure the product yield of display substrates.
  • Cu Since Cu has good electrical conductivity, Cu is generally used to make the signal lines of the display substrate, including the first signal line and the second signal line, as shown in Figure 2.
  • the first signal line 01 and the second signal line There is an insulating layer 03 between 02.
  • the insulating layer 03 is generally made of silicon oxide, silicon nitride or silicon oxynitride. Due to the manufacturing process, the thickness of the insulating layer 03 is relatively small.
  • the first signal line 01 and the second signal line 02 will cause metal ion diffusion, resulting in the risk of short circuit between the first signal line 01 and the second signal line 02 at the intersection of the first signal line 01 and the second signal line 02.
  • the signal line After a short circuit occurs, the signal line will The temperature at the intersection position increases, which in turn causes the insulation layer at the intersection position of the signal lines to be easily damaged, destroying the sealing performance of the display substrate. Water vapor can easily invade, corrode the signal lines, and cause chemical reactions. The water vapor will also spread along the direction of the signal lines. , reducing the product yield of display substrates.
  • an isolation pattern 03 is provided between the first signal line 01 and the second signal line 02.
  • the isolation pattern 03 has a certain thickness and can block the first signal line 01 and the second signal line 02. 02's metal ion diffusion slows down the metal ion diffusion and chemical reaction caused by the electric field between the cross metal signal lines, ensuring the product yield of the display substrate.
  • the first signal line includes a second part in addition to the first part, and the orthographic projection of the second part on the substrate is the same as the second signal line on the substrate.
  • Orthographic projections on the base substrate do not overlap. That is, the orthographic projection of the first signal line on the base substrate at the signal line intersection position is all located within the orthographic projection of the isolation pattern 03 on the base substrate.
  • the first part 011 (the part inside the dotted line frame)
  • the first orthographic projection on the base substrate is located within the orthographic projection of the isolation pattern 03 on the base substrate.
  • the area of the isolation pattern 03 is larger than the area of the first part 011.
  • the first signal line 01 After metal ion diffusion occurs, the metal ions are distributed on the isolation pattern 03. Since the area of the isolation pattern 03 is relatively large, the area directly facing the isolation pattern 03 and the first signal line 01 is relatively large (compared to the area between the second signal line 02 and the first signal line 01). The area facing the first signal line 01) can reduce the distribution density of metal ions and slow down the diffusion and chemical reaction of metal ions due to the electric field between the cross metal signal lines; in contrast, after the diffusion of metal ions occurs in the second signal line 02, Metal ions are distributed on the isolation pattern 03.
  • the area of the isolation pattern 03 is relatively large, the area of the isolation pattern 03 directly facing the second signal line 02 is relatively large (compared to the area directly facing the first signal line 01 and the first signal line 01 area), can reduce the distribution density of metal ions and slow down the diffusion of metal ions and chemical reactions caused by the electric field between the cross metal signal lines.
  • the isolation pattern 03 can be located between the insulating layer 04 and the second signal line 02; or, as shown in Figure 4, the isolation pattern 03 can be located between the insulating layer 04 and the first signal line 01, as long as the isolation It suffices that the pattern 03 is located between the first signal line 01 and the second signal line 02.
  • the isolation pattern 03 can be made of materials with good waterproof properties.
  • the isolation pattern 03 can be made of semiconductor material.
  • the semiconductor material has a certain electron mobility.
  • the isolation pattern 03 can be made of metal oxide semiconductor, amorphous silicon, polycrystalline silicon, etc.
  • the isolation pattern 03 is made of a metal oxide semiconductor, such as IGZO.
  • Metal oxide semiconductor has good electron mobility and can effectively reduce the intersection position of signal lines. the electric field density at .
  • the active layer of the thin film transistor of the display substrate can be provided in the same layer and with the same material as the isolation pattern 03, so that the active layer of the thin film transistor of the display substrate and the isolation pattern 03 can be formed through one patterning process. There is no need to use a special patterning process to produce the isolation pattern 03, which can reduce the number of patterning processes for producing the display substrate and reduce the production cost of the display substrate.
  • the thickness of the isolation pattern 03 can be the same as the thickness of the active layer of the thin film transistor, or the thickness of the isolation pattern 03 can be adjusted, and the thickness of the isolation pattern 03 is designed to be greater than the thickness of the active layer of the thin film transistor, so as to better To reduce the electric field density at the intersection of the signal lines, the thickness of the isolation pattern 03 should be no less than 100nm.
  • the signal lines can adopt various shapes.
  • the first signal line 01 and the second signal line 02 may be linear; as shown in Figure 5, the second signal line 02 may also include a plurality of hollow areas 021 at the intersection positions of the signal lines.
  • the first signal line can also include a plurality of hollow areas at the intersection positions of the signal lines, which can reduce the facing area between the signal lines, reduce the electric field density at the intersection positions of the signal lines, and slow down the occurrence of electric fields between the crossing metal signal lines.
  • the diffusion and chemical reaction of metal ions prevents corrosion at the intersection of signal lines, thereby preventing water vapor from diffusing along the signal lines and ensuring display product yield.
  • the second signal line 02 may also be in a serpentine shape.
  • the first signal line is a gate line
  • the second signal line is a data line
  • the first signal line is a first clock signal line
  • the second signal line is a second clock signal line. signal line.
  • the first signal line is not limited to the gate line and the first clock signal line
  • the second signal line is not limited to the data line and the second clock signal line, and may also be other signal lines.
  • gate lines and data lines intersect vertically and horizontally.
  • An isolation pattern 03 is set at the intersection of the gate lines and data lines, which can block the diffusion of metal ions between the gate lines and data lines and slow down the electric field between the crossing metal signal lines. Metal ion diffusion and chemical reactions ensure the product yield of display substrates.
  • the first clock signal line 07 and the second clock signal line 08 cross vertically and horizontally.
  • the first clock signal line 07 and the second clock signal line 08 pass through the via hole 06. connect.
  • an isolation pattern 03 is provided at the intersection of the first clock signal line 07 and the second clock signal line 08, which can block the diffusion of metal ions of the first clock signal line 07 and the second clock signal line 08. , slow down the metal ion diffusion and chemical reaction caused by the electric field between the cross metal signal lines, and ensure the product yield of the display substrate.
  • Figure 8 is an enlarged schematic diagram of the position of the oval frame in Figure 7.
  • the first clock signal line 07 can include a hollow area, and the hollow area connects the first clock signal
  • the line 07 is divided into two mutually independent first parts (the hollow area can also divide the first clock signal line 07 into three or more mutually independent first parts), and each of the first parts corresponds to one of the isolation patterns 03 , the first orthographic projection of the first part on the base substrate falls within the second orthographic projection of the corresponding isolation pattern on the base substrate.
  • isolation patterns corresponding to the same first signal line can be integrated into an integrated structure, as shown in FIG. 9 .

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Abstract

本公开提供了一种显示基板及其制作方法、显示装置，属于显示技术领域。其中，显示基板包括：位于衬底基板上、沿第一方向延伸的第一信号线；位于所述衬底基板上、沿第二方向延伸的第二信号线，所述第二信号线与所述第一信号线异层设置，所述第二方向与所述第一方向交叉；所述第一信号线包括第一部分，所述第一部分在所述衬底基板上的第一正投影位于所述第二信号线在所述衬底基板上的正投影内；所述显示基板还包括：位于所述第一信号线远离所述衬底基板一侧的隔绝图形，所述隔绝图形位于所述第二信号线靠近所述衬底基板的一侧，所述第一正投影位于所述隔绝图形在所述衬底基板上的第二正投影内。本申请实施例能够提高显示基板的产品良率。

Description

显示基板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，特别是指一种显示基板及其制作方法、显示装置。
背景技术
相关技术中，一般采用Cu制作显示基板的信号线，不同层的信号线之间交叉，在交叉位置处，不同层的信号线之间设置有绝缘层，但信号线容易发生Cu离子扩散，Cu离子穿透绝缘层会导致不同层的信号线之间短路，影响显示基板的产品良率。
发明内容
本公开要解决的技术问题是提供一种显示基板及其制作方法、显示装置，能够保证显示基板的产品良率。
为解决上述技术问题，本公开的实施例提供技术方案如下：
一方面，提供一种显示基板，包括：
位于衬底基板上、沿第一方向延伸的第一信号线；
位于所述衬底基板上、沿第二方向延伸的第二信号线，所述第二信号线与所述第一信号线异层设置，所述第二方向与所述第一方向交叉；
所述第一信号线包括第一部分，所述第一部分在所述衬底基板上的第一正投影位于所述第二信号线在所述衬底基板上的正投影内；
所述显示基板还包括：
位于所述第一信号线远离所述衬底基板一侧的隔绝图形，所述隔绝图形位于所述第二信号线靠近所述衬底基板的一侧，所述第一正投影位于所述隔绝图形在所述衬底基板上的第二正投影内。
一些实施例中，所述显示基板还包括：
位于所述第一信号线和所述第二信号线之间的绝缘层；
其中，所述隔绝图形位于所述绝缘层靠近所述衬底基板的一侧；或
所述隔绝图形位于所述绝缘层远离所述衬底基板的一侧。
一些实施例中，所述隔绝图形采用半导体材料制作。
一些实施例中，所述隔绝图形采用金属氧化物半导体。
一些实施例中，所述显示基板的薄膜晶体管的有源层与所述隔绝图形同层同材料设置。
一些实施例中，所述第一信号线包括除所述第一部分之外的第二部分，所述第二部分在所述衬底基板上的正投影与所述第二信号线在所述衬底基板上的正投影不重叠。
一些实施例中，在所述第二方向上，所述第二正投影的边界超出所述第一正投影的边界，所述第一正投影的边界与所述第二正投影的边界之间的最小距离大于0.2微米。
一些实施例中，在所述第一方向上，所述第二正投影的边界超出所述第一正投影的边界，所述第一正投影的边界与所述第二正投影的边界之间的最小距离大于0.2微米。
一些实施例中，所述第一信号线包括多个相互独立的所述第一部分，每一所述第一部分对应一所述隔绝图形，所述第一部分在所述衬底基板上的第一正投影落入对应的隔绝图形在所述衬底基板上的第二正投影内，对应同一第一信号线的多个隔绝图形为一体结构。
一些实施例中，所述第一信号线为栅线，所述第二信号线为数据线；或
所述第一信号线为第一时钟信号线，所述第二信号线为第二时钟信号线。
本公开的实施例提供了一种显示装置，包括如上所述的显示基板。
本公开的实施例提供了一种显示基板的制作方法，包括：
在衬底基板上形成沿第一方向延伸的第一信号线；
在衬底基板上形成沿第二方向延伸的第二信号线，所述第二信号线与所述第一信号线异层设置，所述第二方向与所述第一方向交叉，所述第一信号线包括第一部分，所述第一部分在所述衬底基板上的第一正投影位于所述第二信号线在所述衬底基板上的正投影内；
在所述第一信号线远离所述衬底基板的一侧形成隔绝图形，所述隔绝图形位于所述第二信号线靠近所述衬底基板的一侧，所述第一正投影位于所述隔绝图形在所述衬底基板上的第二正投影内。
一些实施例中，所述制作方法具体包括：
通过一次构图工艺形成所述显示基板的薄膜晶体管的有源层和所述隔绝图形。
本公开的实施例具有以下有益效果：
上述方案中，在第一信号线和第二信号线之间设置隔绝图形，隔绝图形能够阻挡第一信号线和第二信号线的金属离子扩散，减缓交叉金属信号线间因电场作用发生的金属离子扩散及化学反应，保证显示基板的产品良率。
附图说明
图1为本公开实施例显示基板的平面示意图；
图2为相关技术显示基板的截面示意图；
图3和图4为本公开实施例显示基板在AA方向上的截面示意图；
图5-图7为本公开具体实施例显示基板的平面示意图；
图8和图9为图7中椭圆框中部分的放大示意图。
附图标记
01 第一信号线
011 第一部分
02 第二信号线
03 隔绝图形
021 镂空区域
04 绝缘层
06 过孔
07 第一时钟信号线
08 第二时钟信号线
具体实施方式
为使本公开的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
本公开的实施例提供一种显示基板及其制作方法、显示装置，能够保证显示基板的产品良率。
本公开的实施例提供一种显示基板，如图1所示，包括：
位于衬底基板上、沿第一方向延伸的第一信号线01；
位于所述衬底基板上、沿第二方向延伸的第二信号线02，所述第二信号线02与所述第一信号线01异层设置，所述第二方向与所述第一方向交叉；
所述第一信号线01包括第一部分(虚线框内部分)，所述第一部分在所述衬底基板上的第一正投影位于所述第二信号线02在所述衬底基板上的正投影内；
所述显示基板还包括：
位于所述第一信号线01远离所述衬底基板一侧的隔绝图形03，所述隔绝图形位于所述第二信号线02靠近所述衬底基板的一侧，所述第一正投影位于所述隔绝图形在所述衬底基板上的第二正投影内。
本实施例中，在第一信号线和第二信号线之间设置隔绝图形，隔绝图形能够阻挡第一信号线和第二信号线的金属离子扩散，减缓交叉金属信号线间因电场作用发生的金属离子扩散及化学反应，保证显示基板的产品良率。
由于Cu的导电性良好，一般采用Cu制作显示基板的信号线，包括第一信号线和第二信号线，如图2所示，现有技术中，在第一信号线01和第二信号线02之间设置有绝缘层03，绝缘层03一般采用氧化硅、氮化硅或氮氧化硅制作，受限于制作工艺，绝缘层03的厚度比较小，第一信号线01和第二信号线02会发生金属离子扩散，导致在第一信号线01和第二信号线02的交叉位置处，第一信号线01和第二信号线02存在发生短路的风险，发生短路后，会导致信号线交叉位置处的温度升高，进而导致信号线交叉位置处的绝缘层容易损坏，破坏显示基板的密封性能，水汽容易入侵，腐蚀信号线，出现化学反应，水汽还会沿着信号线的方向扩散，降低显示基板的产品良率。
如图3所示，本实施例中，在第一信号线01和第二信号线02之间设置隔绝图形03，隔绝图形03具有一定的厚度，能够阻挡第一信号线01和第二信号线02的金属离子扩散，减缓交叉金属信号线间因电场作用发生的金属离子扩散及化学反应，保证显示基板的产品良率。
一些实施例中，所述第一信号线包括除所述第一部分之外的第二部分，所述第二部分在所述衬底基板上的正投影与所述第二信号线在所述衬底基板上的正投影不重叠。即信号线交叉位置处的第一信号线在衬底基板上的正投影全都位于隔绝图形03在所述衬底基板上的正投影内，如图1所示，第一部分011(虚线框内部分)在衬底基板上的第一正投影位于隔绝图形03在所述衬底基板上的正投影内，隔绝图形03的面积大于第一部分011的面积，如图3所示，第一信号线01发生金属离子扩散后，金属离子分布在隔绝图形03上，由于隔绝图形03的面积比较大，隔绝图形03与第一信号线01正对的面积比较大(相比于第二信号线02与第一信号线01正对的面积)，能够降低金属离子的分布密度，减缓交叉金属信号线间因电场作用发生的金属离子扩散及化学反应；相对地，第二信号线02发生金属离子扩散后，金属离子分布在隔绝图形03上，由于隔绝图形03的面积比较大，隔绝图形03与第二信号线02正对的面积比较大(相比于第一信号线01与第一信号线01正对的面积)，能够降低金属离子的分布密度，减缓交叉金属信号线间因电场作用发生的金属离子扩散及化学反应。
如图3所示，隔绝图形03可以位于绝缘层04和第二信号线02之间；或者，如图4所示，隔绝图形03可以位于绝缘层04和第一信号线01之间，只要隔绝图形03位于第一信号线01和第二信号线02之间即可。
为了保证显示基板的防水性能，隔绝图形03可以采用防水性好的材料。本实施例中，所述隔绝图形03可以采用半导体材料制作，半导体材料具有一定的电子迁移率，在信号线扩散的金属离子到达隔绝图形03后，隔绝图形03作为半导体能够改变电场分布，减缓交叉金属信号线间因电场作用发生的金属离子扩散及化学反应，避免信号线交叉位置处发生腐蚀，进而避免水汽沿信号线进行扩散，保证显示产品良率。
隔绝图形03可以采用金属氧化物半导体、非晶硅、多晶硅等，优选地，隔绝图形03采用金属氧化物半导体，比如IGZO，金属氧化物半导体具有良好的电子迁移率，可以有效降低信号线交叉位置处的电场密度。
一些实施例中，所述显示基板的薄膜晶体管的有源层可以与所述隔绝图形03同层同材料设置，这样可以通过一次构图工艺形成显示基板的薄膜晶体管的有源层以及隔绝图形03，无需通过专门的构图工艺来制作隔绝图形03，能够减少制作显示基板的构图工艺的次数，降低显示基板的生产成本。隔绝图形03的厚度可以与薄膜晶体管的有源层的厚度相同，也可以对隔绝图形03的厚度进行调整，将隔绝图形03的厚度设计为大于薄膜晶体管的有源层的厚度，以更好地降低信号线交叉位置处的电场密度，隔绝图形03的厚度不小于100nm为宜。
为了更好地降低信号线交叉位置处的电场密度，如图1所示，在所述第二方向上，所述第二正投影的边界超出所述第一正投影的边界，所述第一正投影的边界与所述第二正投影的边界之间的最小距离d1大于0.2微米。这样隔绝图形03能够从空间上阻挡第一信号线01和第二信号线02之间的金属离子扩散。并且，由于在发生信号线腐蚀后，水汽会沿着信号线扩散，d1大于0.2微米能够使得水汽扩散路径发生改变，降低水汽入侵的可能性。
进一步地，d1可以大于a+0.2微米，其中，a为第一信号线01和隔绝图形03在制作工艺中关键尺寸的最大波动值，这样可以降低制作工艺对显示基板产品良率的影响。
为了更好地降低信号线交叉位置处的电场密度，如图1所示，在所述第一方向上，所述第二正投影的边界超出所述第一正投影的边界，所述第一正投影的边界与所述第二正投影的边界之间的最小距离d2大于0.2微米。这样隔绝图形03能够从空间上阻挡第一信号线01和第二信号线02之间的金属离子扩散。并且，由于在发生信号线腐蚀后，水汽会沿着信号线扩散，d1大于0.2微米能够使得水汽扩散路径发生改变，降低水汽入侵的可能性。
进一步地，d2可以大于b+0.2微米，其中，b为第二信号线02和隔绝图形03在制作工艺中关键尺寸的最大波动值，这样可以降低制作工艺对显示基 板产品良率的影响。
本实施例中，信号线可以采用多种形状。如图1所示，第一信号线01和第二信号线02可以为直线形；如图5所示，第二信号线02在信号线交叉位置处还可以包括多个镂空区域021，当然，第一信号线在信号线交叉位置处也可以包括多个镂空区域，这样能够减少信号线之间的正对面积，降低信号线交叉位置处的电场密度，减缓交叉金属信号线间因电场作用发生的金属离子扩散及化学反应，避免信号线交叉位置处发生腐蚀，进而避免水汽沿信号线进行扩散，保证显示产品良率。如图6所示，在信号线交叉位置处，第二信号线02还可以呈蛇形。
本实施例中，所述第一信号线为栅线，所述第二信号线为数据线；或，所述第一信号线为第一时钟信号线，所述第二信号线为第二时钟信号线。当然，第一信号线并不局限为栅线和第一时钟信号线，第二信号线并不局限为数据线和第二时钟信号线，还可以为其他信号线。
在显示区域，栅线和数据线纵横交叉，在栅线和数据线的交叉位置处设置隔绝图形03，能够阻挡栅线和数据线的金属离子扩散，减缓交叉金属信号线间因电场作用发生的金属离子扩散及化学反应，保证显示基板的产品良率。
在GOA区域，如图7所示，第一时钟信号线07和第二时钟信号线08纵横交叉，在过孔06位置处，第一时钟信号线07和第二时钟信号线08通过过孔06连接。除过孔06位置之外，在第一时钟信号线07和第二时钟信号线08的交叉位置处设置隔绝图形03，能够阻挡第一时钟信号线07和第二时钟信号线08的金属离子扩散，减缓交叉金属信号线间因电场作用发生的金属离子扩散及化学反应，保证显示基板的产品良率。
图8为图7中椭圆框位置的放大示意图，在第一时钟信号线07和第二时钟信号线08交叉位置处，第一时钟信号线07可以包括有镂空区域，镂空区域将第一时钟信号线07分为两个相互独立的所述第一部分(镂空区域还可以将第一时钟信号线07分为三个以上相互独立的第一部分)，每一所述第一部分对应一所述隔绝图形03，所述第一部分在所述衬底基板上的第一正投影落入对应的隔绝图形在所述衬底基板上的第二正投影内。
为了简化制作工艺，对应同一第一信号线的多个隔绝图形可以为一体结构，如图9所示。
一具体实施例中，在所述第二方向上，所述第一正投影的边界与所述第二正投影的边界之间的最小距离d1可以为2.5-3.3微米。在所述第一方向上，所述第一正投影的边界与所述第二正投影的边界之间的最小距离d2可以为4.5-5.05微米。在采用上述尺寸时，能够有效阻挡第一时钟信号线07和第二时钟信号线08的金属离子扩散，减缓交叉金属信号线间因电场作用发生的金属离子扩散及化学反应，保证显示基板的产品良率。
本公开的实施例提供了一种显示装置，包括如上所述的显示基板。
该显示装置包括但不限于：射频单元、网络模块、音频输出单元、输入单元、传感器、显示单元、用户输入单元、接口单元、存储器、处理器、以及电源等部件。本领域技术人员可以理解，上述显示装置的结构并不构成对显示装置的限定，显示装置可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。在本公开实施例中，显示装置包括但不限于显示器、手机、平板电脑、电视机、可穿戴电子设备、导航显示设备等。
所述显示装置可以为：电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
本公开的实施例提供了一种显示基板的制作方法，包括：
在衬底基板上形成沿第一方向延伸的第一信号线；
在衬底基板上形成沿第二方向延伸的第二信号线，所述第二信号线与所述第一信号线异层设置，所述第二方向与所述第一方向交叉，所述第一信号线包括第一部分，所述第一部分在所述衬底基板上的第一正投影位于所述第二信号线在所述衬底基板上的正投影内；
在所述第一信号线远离所述衬底基板的一侧形成隔绝图形，所述隔绝图形位于所述第二信号线靠近所述衬底基板的一侧，所述第一正投影位于所述隔绝图形在所述衬底基板上的第二正投影内。
本实施例中，在第一信号线和第二信号线之间设置隔绝图形，隔绝图形 能够阻挡第一信号线和第二信号线的金属离子扩散，减缓交叉金属信号线间因电场作用发生的金属离子扩散及化学反应，保证显示基板的产品良率。
由于Cu的导电性良好，一般采用Cu制作显示基板的信号线，包括第一信号线和第二信号线，如图2所示，现有技术中，在第一信号线01和第二信号线02之间设置有绝缘层03，绝缘层03一般采用氧化硅、氮化硅或氮氧化硅制作，受限于制作工艺，绝缘层03的厚度比较小，第一信号线01和第二信号线02会发生金属离子扩散，导致在第一信号线01和第二信号线02的交叉位置处，第一信号线01和第二信号线02存在发生短路的风险，发生短路后，会导致信号线交叉位置处的温度升高，进而导致信号线交叉位置处的绝缘层容易损坏，破坏显示基板的密封性能，水汽容易入侵，腐蚀信号线，出现化学反应，水汽还会沿着信号线的方向扩散，降低显示基板的产品良率。
如图3所示，本实施例中，在第一信号线01和第二信号线02之间设置隔绝图形03，隔绝图形03具有一定的厚度，能够阻挡第一信号线01和第二信号线02的金属离子扩散，减缓交叉金属信号线间因电场作用发生的金属离子扩散及化学反应，保证显示基板的产品良率。
一些实施例中，所述第一信号线包括除所述第一部分之外的第二部分，所述第二部分在所述衬底基板上的正投影与所述第二信号线在所述衬底基板上的正投影不重叠。即信号线交叉位置处的第一信号线在衬底基板上的正投影全都位于隔绝图形03在所述衬底基板上的正投影内，如图1所示，第一部分011(虚线框内部分)在衬底基板上的第一正投影位于隔绝图形03在所述衬底基板上的正投影内，隔绝图形03的面积大于第一部分011的面积，如图3所示，第一信号线01发生金属离子扩散后，金属离子分布在隔绝图形03上，由于隔绝图形03的面积比较大，隔绝图形03与第一信号线01正对的面积比较大(相比于第二信号线02与第一信号线01正对的面积)，能够降低金属离子的分布密度，减缓交叉金属信号线间因电场作用发生的金属离子扩散及化学反应；相对地，第二信号线02发生金属离子扩散后，金属离子分布在隔绝图形03上，由于隔绝图形03的面积比较大，隔绝图形03与第二信号线02正对的面积比较大(相比于第一信号线01与第一信号线01正对的面积)， 能够降低金属离子的分布密度，减缓交叉金属信号线间因电场作用发生的金属离子扩散及化学反应。
如图3所示，隔绝图形03可以位于绝缘层04和第二信号线02之间；或者，如图4所示，隔绝图形03可以位于绝缘层04和第一信号线01之间，只要隔绝图形03位于第一信号线01和第二信号线02之间即可。
为了保证显示基板的防水性能，隔绝图形03可以采用防水性好的材料。本实施例中，所述隔绝图形03可以采用半导体材料制作，半导体材料具有一定的电子迁移率，在信号线扩散的金属离子到达隔绝图形03后，隔绝图形03作为半导体能够改变电场分布，减缓交叉金属信号线间因电场作用发生的金属离子扩散及化学反应，避免信号线交叉位置处发生腐蚀，进而避免水汽沿信号线进行扩散，保证显示产品良率。
隔绝图形03可以采用金属氧化物半导体、非晶硅、多晶硅等，优选地，隔绝图形03采用金属氧化物半导体，比如IGZO，金属氧化物半导体具有良好的电子迁移率，可以有效降低信号线交叉位置处的电场密度。
一些实施例中，所述显示基板的薄膜晶体管的有源层可以与所述隔绝图形03同层同材料设置，这样可以通过一次构图工艺形成显示基板的薄膜晶体管的有源层以及隔绝图形03，无需通过专门的构图工艺来制作隔绝图形03，能够减少制作显示基板的构图工艺的次数，降低显示基板的生产成本。隔绝图形03的厚度可以与薄膜晶体管的有源层的厚度相同，也可以对隔绝图形03的厚度进行调整，将隔绝图形03的厚度设计为大于薄膜晶体管的有源层的厚度，以更好地降低信号线交叉位置处的电场密度，隔绝图形03的厚度不小于100nm为宜。
本实施例中，信号线可以采用多种形状。如图1所示，第一信号线01和第二信号线02可以为直线形；如图5所示，第二信号线02在信号线交叉位置处还可以包括多个镂空区域021，当然，第一信号线在信号线交叉位置处也可以包括多个镂空区域，这样能够减少信号线之间的正对面积，降低信号线交叉位置处的电场密度，减缓交叉金属信号线间因电场作用发生的金属离子扩散及化学反应，避免信号线交叉位置处发生腐蚀，进而避免水汽沿信号 线进行扩散，保证显示产品良率。如图6所示，在信号线交叉位置处，第二信号线02还可以呈蛇形。
本实施例中，所述第一信号线为栅线，所述第二信号线为数据线；或，所述第一信号线为第一时钟信号线，所述第二信号线为第二时钟信号线。当然，第一信号线并不局限为栅线和第一时钟信号线，第二信号线并不局限为数据线和第二时钟信号线，还可以为其他信号线。
在显示区域，栅线和数据线纵横交叉，在栅线和数据线的交叉位置处设置隔绝图形03，能够阻挡栅线和数据线的金属离子扩散，减缓交叉金属信号线间因电场作用发生的金属离子扩散及化学反应，保证显示基板的产品良率。
在GOA区域，如图7所示，第一时钟信号线07和第二时钟信号线08纵横交叉，在过孔06位置处，第一时钟信号线07和第二时钟信号线08通过过孔06连接。除过孔06位置之外，在第一时钟信号线07和第二时钟信号线08的交叉位置处设置隔绝图形03，能够阻挡第一时钟信号线07和第二时钟信号线08的金属离子扩散，减缓交叉金属信号线间因电场作用发生的金属离子扩散及化学反应，保证显示基板的产品良率。
图8为图7中椭圆框位置的放大示意图，在第一时钟信号线07和第二时钟信号线08交叉位置处，第一时钟信号线07可以包括有镂空区域，镂空区域将第一时钟信号线07分为两个相互独立的所述第一部分(镂空区域还可以将第一时钟信号线07分为三个以上相互独立的第一部分)，每一所述第一部分对应一所述隔绝图形03，所述第一部分在所述衬底基板上的第一正投影落入对应的隔绝图形在所述衬底基板上的第二正投影内。
为了简化制作工艺，对应同一第一信号线的多个隔绝图形可以为一体结构，如图9所示。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属 领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种显示基板，其特征在于，包括：
    位于衬底基板上、沿第一方向延伸的第一信号线；
    位于所述衬底基板上、沿第二方向延伸的第二信号线，所述第二信号线与所述第一信号线异层设置，所述第二方向与所述第一方向交叉；
    所述第一信号线包括第一部分，所述第一部分在所述衬底基板上的第一正投影位于所述第二信号线在所述衬底基板上的正投影内；
    所述显示基板还包括：
    位于所述第一信号线远离所述衬底基板一侧的隔绝图形，所述隔绝图形位于所述第二信号线靠近所述衬底基板的一侧，所述第一正投影位于所述隔绝图形在所述衬底基板上的第二正投影内。
  2. 根据权利要求1所述的显示基板，其特征在于，所述显示基板还包括：
    位于所述第一信号线和所述第二信号线之间的绝缘层；
    其中，所述隔绝图形位于所述绝缘层靠近所述衬底基板的一侧；或
    所述隔绝图形位于所述绝缘层远离所述衬底基板的一侧。
  3. 根据权利要求1所述的显示基板，其特征在于，所述隔绝图形采用半导体材料制作。
  4. 根据权利要求3所述的显示基板，其特征在于，所述隔绝图形采用金属氧化物半导体。
  5. 根据权利要求3所述的显示基板，其特征在于，所述显示基板的薄膜晶体管的有源层与所述隔绝图形同层同材料设置。
  6. 根据权利要求1所述的显示基板，其特征在于，所述第一信号线包括除所述第一部分之外的第二部分，所述第二部分在所述衬底基板上的正投影与所述第二信号线在所述衬底基板上的正投影不重叠。
  7. 根据权利要求1所述的显示基板，其特征在于，
    在所述第二方向上，所述第二正投影的边界超出所述第一正投影的边界，所述第一正投影的边界与所述第二正投影的边界之间的最小距离大于0.2微 米。
  8. 根据权利要求1所述的显示基板，其特征在于，
    在所述第一方向上，所述第二正投影的边界超出所述第一正投影的边界，所述第一正投影的边界与所述第二正投影的边界之间的最小距离大于0.2微米。
  9. 根据权利要求1所述的显示基板，其特征在于，
    所述第一信号线包括多个相互独立的所述第一部分，每一所述第一部分对应一所述隔绝图形，所述第一部分在所述衬底基板上的第一正投影落入对应的隔绝图形在所述衬底基板上的第二正投影内，对应同一第一信号线的多个隔绝图形为一体结构。
  10. 根据权利要求1所述的显示基板，其特征在于，
    所述第一信号线为栅线，所述第二信号线为数据线；
    或
    所述第一信号线为第一时钟信号线，所述第二信号线为第二时钟信号线。
  11. 一种显示装置，其特征在于，包括如权利要求1-10中任一项所述的显示基板。
  12. 一种显示基板的制作方法，其特征在于，包括：
    在衬底基板上形成沿第一方向延伸的第一信号线；
    在衬底基板上形成沿第二方向延伸的第二信号线，所述第二信号线与所述第一信号线异层设置，所述第二方向与所述第一方向交叉，所述第一信号线包括第一部分，所述第一部分在所述衬底基板上的第一正投影位于所述第二信号线在所述衬底基板上的正投影内；
    在所述第一信号线远离所述衬底基板的一侧形成隔绝图形，所述隔绝图形位于所述第二信号线靠近所述衬底基板的一侧，所述第一正投影位于所述隔绝图形在所述衬底基板上的第二正投影内。
  13. 根据权利要求12所述的显示基板的制作方法，其特征在于，所述制作方法具体包括：
    通过一次构图工艺形成所述显示基板的薄膜晶体管的有源层和所述隔绝 图形。
PCT/CN2022/089268 2022-04-26 2022-04-26 显示基板及其制作方法、显示装置 WO2023206071A1 (zh)

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CN101459028A (zh) * 2007-12-14 2009-06-17 佳能株式会社 图像显示装置
CN103178082A (zh) * 2011-12-21 2013-06-26 乐金显示有限公司 显示设备及其制造方法
CN107230661A (zh) * 2017-05-31 2017-10-03 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN110148601A (zh) * 2019-05-31 2019-08-20 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101459028A (zh) * 2007-12-14 2009-06-17 佳能株式会社 图像显示装置
CN103178082A (zh) * 2011-12-21 2013-06-26 乐金显示有限公司 显示设备及其制造方法
CN107230661A (zh) * 2017-05-31 2017-10-03 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
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