WO2024007434A1 - 显示面板及移动终端 - Google Patents

显示面板及移动终端 Download PDF

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Publication number
WO2024007434A1
WO2024007434A1 PCT/CN2022/115931 CN2022115931W WO2024007434A1 WO 2024007434 A1 WO2024007434 A1 WO 2024007434A1 CN 2022115931 W CN2022115931 W CN 2022115931W WO 2024007434 A1 WO2024007434 A1 WO 2024007434A1
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WIPO (PCT)
Prior art keywords
layer
via hole
display panel
substrate
insulating layer
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PCT/CN2022/115931
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English (en)
French (fr)
Inventor
艾飞
罗成志
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武汉华星光电技术有限公司
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Publication of WO2024007434A1 publication Critical patent/WO2024007434A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a mobile terminal.
  • via holes are usually opened in the insulating layer to achieve electrical connection between conductive components located in different film layers.
  • multiple conductive components located in the same film layer need to be located in other different layers. If the conductive components of the layer are electrically connected, the depth of the via holes that need to be etched and the number of film layers that the via holes pass through are different; in order to make the array substrate have ultra-high pixel density and sub-micron level Device size requires the line width, line spacing, and via hole size of the array device to be reduced as much as possible. At the same time, the thickness of the metal traces and the depth of the via holes need to be increased as much as possible.
  • the taper angle of the via hole is small, and both sides of the via hole are arc-shaped, resulting in the opening occupying a larger area on the insulating layer. , and the metal traces need to completely cover the vias, which causes the line width of the metal traces on the vias to become larger, which is not conducive to high PPI trace arrangement.
  • Embodiments of the present application provide a display panel to alleviate deficiencies in related technologies.
  • An embodiment of the present application provides a display panel, including a substrate and a thin film transistor layer provided on the substrate.
  • the thin film transistor layer includes a semiconductor layer, an insulating layer and a first metal layer that are stacked on the substrate.
  • the insulating layer is disposed on the base and the semiconductor layer and covers the semiconductor layer, and the first metal layer is disposed on the insulating layer;
  • the insulating layer includes at least one via hole
  • the first metal layer is connected to the semiconductor layer through the via hole
  • the angle between the side wall of the via hole and the bottom surface of the insulating layer is greater than or equal to 85 degrees, and less than or equal to 90 degrees.
  • the via hole includes a first opening on a side away from the substrate and a second opening on a side close to the substrate;
  • the ratio of the width of the first opening to the width of the second opening is greater than or equal to 0.9 and less than or equal to 1.1.
  • the substrate includes a substrate and a buffer layer disposed on the substrate, and the thickness of the insulating layer is greater than twice the thickness of the buffer layer.
  • the display panel further includes a conductive filling part disposed in the via hole, and the first metal layer is connected to the semiconductor layer through the conductive filling part.
  • the resistivity of the conductive filling part is less than 5.48 ⁇ 10 -6 ⁇ m.
  • the orthographic projection of the first metal layer on the substrate covers the orthographic projection of the conductive filling part on the substrate.
  • the display panel further includes a spacer layer located on the side of the insulating layer away from the substrate, and the spacer layer includes at least one slot penetrating the spacer layer.
  • the slot is connected to the via hole;
  • the first metal layer is disposed in the slot, and the angle between the side wall of the slot and the bottom surface of the spacer layer is greater than or equal to 85 degrees and less than or equal to 90 degrees.
  • the ratio of the depth of the groove to the width of the groove is greater than or equal to 0.2 and less than or equal to 1.
  • the display panel further includes a second metal layer
  • the thin film transistor layer includes a plurality of thin film transistors, the first metal layer includes source electrodes and drain electrodes of the thin film transistors, the semiconductor layer includes an active layer of the thin film transistors, and the second metal layer includes The gate electrode of the thin film transistor;
  • the insulating layer includes a plurality of via holes, the plurality of via holes include a first via hole and a second via hole located above the active layer, and the drain electrode is connected to the first via hole through the first via hole.
  • the active layer is connected, and the source is connected to the active layer through the second via hole.
  • the display panel further includes a conductive filling part.
  • the conductive filling part includes a first filling part provided in the first via hole, and a first filling part provided in the second via hole.
  • the drain electrode is connected to the active layer through the first filling part
  • the source electrode is connected to the active layer through the second filling part.
  • the spacer layer includes a plurality of the slots, and the plurality of slots include a first slot connected to the first via hole, and a first slot connected to the first via hole. A second slot connected by two vias;
  • the drain electrode is disposed in the first slot, and the source electrode is disposed in the second slot.
  • the semiconductor layer is located between the gate electrode and the substrate, and the insulating layer includes gate insulation disposed between the semiconductor layer and the gate electrode. layer, and an interlayer insulating layer disposed on the side of the gate insulating layer away from the gate;
  • the first via hole and the second via hole both pass through the interlayer insulating layer and the gate insulating layer;
  • the substrate includes a substrate and a buffer layer disposed on the substrate, and the thickness of the interlayer insulating layer is greater than twice the thickness of the buffer layer.
  • the gate is located between the semiconductor layer and the substrate, and the insulating layer includes a layer disposed between the semiconductor layer and the first metal layer.
  • An interlayer insulating layer, a gate insulating layer is provided on the side of the semiconductor layer away from the interlayer insulating layer;
  • the first via hole and the second via hole both pass through the interlayer insulating layer
  • the substrate includes a substrate and a buffer layer disposed on the substrate, and the thickness of the interlayer insulating layer is greater than twice the thickness of the buffer layer.
  • the display panel further includes a flat layer, a first electrode layer, a passivation layer and a second electrode layer stacked on the spacer layer;
  • a first connection via hole penetrating the flat layer and the passivation layer is provided in the display panel, and the first connection via hole is connected to the first slot;
  • the second electrode layer includes a first electrode connected to the drain electrode through the first connection via hole;
  • the angle between the side wall of the first connection via hole and the bottom surface of the flat layer is greater than or equal to 85 degrees and less than or equal to 90 degrees.
  • a second connection via hole penetrating the flat layer and the passivation layer and a third connection via hole penetrating the passivation layer are provided in the display panel.
  • the plurality of slots includes a third slot in communication with the second connection via hole, the second connection via hole is in communication with the third slot, and the first metal layer includes a
  • the first signal line in the three slots the first electrode layer includes a touch electrode, the second electrode layer includes a bridge segment, one end of the bridge segment passes through the second connection via hole and the first The signal line is connected, and the other end of the bridge section passes through the third connection via hole and is connected to the touch electrode;
  • the angle between the side wall of the second connection via hole and the bottom surface of the flat layer is greater than or equal to 85 degrees and less than or equal to 90 degrees
  • the side wall of the third connection via hole is between the side wall of the passivation layer and the passivation layer.
  • the angle between the bottom surfaces is greater than or equal to 85 degrees and less than or equal to 90 degrees.
  • the second metal layer further includes a second signal line arranged at a distance from the gate electrode, and the first metal layer includes a second signal line arranged opposite to the second signal line.
  • the thin film transistor layer includes a third via hole located above the second signal line, the conductive filling portion includes a third filling portion disposed in the third via hole, and the plurality of grooves include The fourth slot connected to the third via hole;
  • the third signal line is disposed in the fourth slot and connected to the second signal line through the third filling part; the distance between the side wall of the third via hole and the bottom surface of the insulating layer The angle is greater than or equal to 85 degrees and less than or equal to 90 degrees.
  • the third via hole includes a third opening on a side away from the substrate and a fourth opening on a side close to the substrate;
  • the ratio of the width of the third opening to the width of the fourth opening is greater than or equal to 0.9 and less than or equal to 1.1.
  • the semiconductor layer is located between the gate electrode and the substrate, and the insulating layer includes gate insulation disposed between the semiconductor layer and the gate electrode. layer, and an interlayer insulating layer disposed on the side of the gate insulating layer away from the gate;
  • the third via hole passes through the interlayer insulating layer, the gate insulating layer includes a first groove connected to the third via hole, and the second signal line is disposed in the first groove Inside.
  • the gate is located between the semiconductor layer and the substrate, and the insulating layer includes a layer disposed between the semiconductor layer and the first metal layer.
  • An interlayer insulating layer, a gate insulating layer is provided on the side of the semiconductor layer away from the interlayer insulating layer;
  • the third via hole passes through the interlayer insulating layer and the gate insulating layer.
  • the base includes a substrate and a buffer layer disposed on the substrate.
  • the buffer layer includes a through hole that penetrates the buffer layer. The fifth slot,
  • the second signal line is disposed in the fifth slot, and the angle between the side wall of the fifth slot and the bottom surface of the buffer layer is greater than or equal to 85 degrees and less than or equal to 90 degrees.
  • An embodiment of the present application provides a mobile terminal, including a terminal body and any one of the above display panels, and the terminal body and the display panel are combined into one body.
  • Embodiments of the present application provide a display panel.
  • the display panel includes a substrate and a thin film transistor layer provided on the substrate.
  • the thin film transistor layer includes a semiconductor layer, an insulating layer and a first layer that are stacked on the substrate.
  • a metal layer, the insulating layer is disposed on the base and the semiconductor layer and covers the semiconductor layer, the first metal layer is disposed on the insulating layer; by arranging the insulating layer to include at least one via hole, the The first metal layer is connected to the semiconductor layer through the via hole, and the angle between the side wall of the via hole and the bottom surface of the insulating layer is greater than or equal to 85 degrees and less than or equal to 90 degrees, thereby reducing the The area occupied by the via hole on the insulating layer further improves the aperture ratio of the display panel.
  • Figure 1 is a schematic structural diagram of an existing display panel
  • Figure 2 is a schematic cross-sectional view of the interlayer insulation layer of the existing display panel
  • Figure 3 is a schematic cross-sectional view of the drain electrode of an existing display panel
  • Figure 4 is a first cross-sectional schematic diagram of a display panel provided by an embodiment of the present application.
  • Figure 5 is a schematic cross-sectional view of the insulating layer provided by the embodiment of the present application.
  • Figure 6 is an enlarged view of point A in Figure 4.
  • Figure 7 is an enlarged view of B in Figure 4.
  • Figure 8 is a second schematic cross-sectional view of a display panel provided by an embodiment of the present application.
  • Figure 9 is a third schematic cross-sectional view of a display panel provided by an embodiment of the present application.
  • Figure 10 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present application.
  • FIGS. 11A to 11N are structural process flow diagrams for manufacturing the display panel in FIG. 10 .
  • An embodiment of the present application provides a display panel. Each is explained in detail below. It should be noted that the order of description of the following embodiments does not limit the preferred order of the embodiments.
  • the display panel includes a substrate 10 and a thin film transistor layer 20 disposed on the substrate 10.
  • the thin film transistor layer 20 includes a layer of The semiconductor layer 21, the insulating layer 30 and the first metal layer 40 on the substrate 10, the insulating layer 30 is disposed on the substrate 10 and the semiconductor layer 21 and covers the semiconductor layer 21, the first metal layer 40 disposed on the insulating layer 30;
  • the insulating layer 30 includes at least one via hole 31 , the first metal layer 40 is connected to the semiconductor layer 21 through the via hole 31 , and the side wall of the via hole 31 is in contact with the bottom surface of the insulating layer 30
  • the angle ⁇ is greater than or equal to 85 degrees and less than or equal to 90 degrees.
  • Figure 1 is a schematic structural diagram of an existing display panel; it should be noted that this embodiment does not specifically limit the structure of the existing display panel.
  • the existing display panel is only a liquid crystal display panel LiquidCrystalDisplay, LCD ) as an example.
  • the existing display panel includes a first substrate 100 and a second substrate (not shown in the figure) arranged oppositely, and a liquid crystal layer (not shown in the figure) arranged between the first substrate 100 and the second substrate.
  • the first substrate 100 is an array substrate, including a substrate 10 and a thin film transistor layer 20, a flat layer 30, a common electrode 40, a passivation layer 50 and a pixel electrode 60 that are sequentially stacked on the substrate 10, so
  • the substrate 10 includes a stacked substrate 11, a light-shielding layer 12, and a buffer layer 13.
  • the thin film transistor layer 20 includes an active layer 21, a gate insulating layer 22, and a gate 23 that are sequentially stacked on the substrate 10.
  • the thin film transistor layer 20 includes a plurality of thin film transistors 20A arranged in a matrix, and the thin film transistor 20A includes a plurality of thin film transistors 20A that penetrate the interlayer insulating layer 24 and the first via hole 26A and the second via hole 26B of the gate insulating layer 22 .
  • via holes 26 are usually opened in the active layer 21 to achieve electrical connection between conductive components located in different film layers.
  • a first via hole 26A and a second via hole 26B are provided through the interlayer insulating layer 24 and the gate insulating layer 22.
  • the source electrode 25A is connected to the active electrode through the first via hole 26A.
  • layer 21 is connected, and the drain electrode 25B is connected to the active layer 21 through the second via hole 26B.
  • the taper angle (Taper) of the hole is small. Specifically, please refer to FIG.
  • the taper angle ⁇ 1 of the first via hole 26A is less than 80 degrees. Both sides of a via hole 26A are arc-shaped, so that the first via hole 26A occupies a larger area on the interlayer insulating layer 24, resulting in a metal layer located on the first via hole 26A.
  • the larger area occupied by the second via hole 26B leads to a larger area of the metal layer located on the second via hole 26B, which in turn results in a larger size of the thin film transistor and is not conducive to the wiring arrangement of high PPI (pixel density).
  • Figure 4 is a first cross-sectional schematic diagram of the display panel provided by the embodiment of the present application
  • Figure 5 is a cross-sectional schematic diagram of the insulating layer provided by the embodiment of the present application.
  • Figure 6 is an enlarged view of point A in Figure 4
  • Figure 7 is an enlarged view of point B in Figure 4.
  • An embodiment of the present application provides a display panel, which includes but is not limited to one of a liquid crystal display panel (Liquid Crystal Display, LCD) and an organic light emitting diode (OLED) display panel. It should be noted that this embodiment uses The display panel is a liquid crystal display panel as an example to describe the technical solution of the present application.
  • LCD Liquid Crystal Display
  • OLED organic light emitting diode
  • the display panel includes a first substrate 100 and a second substrate (not shown in the figure) oppositely arranged, and a liquid crystal layer ( (not shown in the figure);
  • the first substrate 100 is an array substrate and the second substrate is a color filter substrate as an example to illustrate the technical solution of the present application.
  • the first substrate 100 includes a base 10 and a thin film transistor layer 20 disposed on the base 10 .
  • the base 10 includes a substrate 11 and a buffer layer 13 disposed on the substrate 11 .
  • the substrate 11 may include one of a rigid substrate or a flexible substrate, which is not specifically limited in this embodiment.
  • the thin film transistor layer 20 includes a semiconductor layer 21, an insulating layer 30 and a first metal layer 40 that are stacked on the substrate 10.
  • the insulating layer 30 is arranged on the substrate 10 and the semiconductor layer 21 and covers the Semiconductor layer 21, the first metal layer 40 is disposed on the insulating layer 30; it should be noted that the material of the semiconductor layer 21 includes but is not limited to one of polysilicon, amorphous silicon and oxide.
  • the embodiment takes the material of the semiconductor layer 21 as polysilicon as an example to illustrate the technical solution of the present application.
  • the insulating layer 30 includes at least one via hole 31 , the first metal layer 40 is connected to the semiconductor layer 21 through the via hole 31 , and the sidewalls of the via hole 31 are connected to the
  • the included angle ⁇ of the bottom surface of the insulating layer 30 is greater than or equal to 85 degrees and less than or equal to 90 degrees. It should be noted that the bottom surface of the insulating layer 30 is the side of the insulating layer 30 close to the substrate 10; preferably, In a direction perpendicular to the substrate 10 , the cross-section of the side wall of the via hole 31 is linear.
  • Table 1 is the design aperture and actual aperture of the via hole in the display panel provided by the embodiment of the present application, and the design aperture and actual aperture of the via hole in the existing display panel. data sheet.
  • the taper angle of the via hole 26 is usually less than 80 degrees, and both sides of the via hole 26 are arc-shaped. Therefore, as the The design diameter of the via hole 26 in the existing display panel is reduced. The actual diameter of the via hole 26 in the existing display panel is larger than the design diameter of the via hole 26.
  • the via hole 31 includes a side away from the substrate 10
  • the first opening 311 and the second opening 312 close to the side of the substrate 10, the ratio of the width of the first opening 311 to the width of the second opening 312 is greater than or equal to 0.9 and less than or equal to 1.1, Therefore, the actual aperture of the via hole 31 of the display panel is approximately equal to the design diameter of the via hole 31. Therefore, the use of the via hole 31 design provided in this embodiment is beneficial to the realization of the micro thin film transistor 20A. of production.
  • the via hole 26 in the above-mentioned existing display panel refers to the via hole 26 in the existing display panel that passes through the interlayer insulating layer 24 and the gate in the accompanying drawing 1. First via hole 26A and second via hole 26B of the insulating layer 22 .
  • the width D 1 of the first opening 311 ranges from 0.2 microns to 3.1 microns
  • the width D 2 of the second opening 312 ranges from 0.1 microns to 3.1 microns. 3 microns
  • this embodiment does not specifically limit this, wherein the shape of the first opening 311 and the shape of the second opening 312 are one of a circle, an ellipse, and a rectangle. Further, this embodiment The embodiment takes the shape of the first opening 311 as a circle and the shape of the second opening 312 as a circle to illustrate the technical solution of the present application.
  • the technical solution of the present application is exemplified by taking the hole depth of the via hole 31 to be 2000 nanometers.
  • the display panel provided in this embodiment has the same hole depth as the existing display panel.
  • the aspect ratio of the via hole 31 is positively related to the taper angle of the via hole 31 .
  • the thickness of the insulating layer 30 is greater than twice the thickness of the buffer layer 13.
  • the thickness of the insulating layer 30 ranges from 600 nanometers to 5000 nanometers.
  • the angle ⁇ between the side wall of the via hole 31 and the bottom surface of the insulation layer 30 is greater than or equal to 85 degrees and less than or equal to 90 degrees.
  • the actual aperture of the via hole 31 of the display panel is different from the through hole.
  • the design diameters of the holes 31 are approximately equal. Therefore, adopting the design of the via hole 31 provided in this embodiment is beneficial to providing a display panel with the via hole having a high aspect ratio.
  • the display panel further includes a conductive filling portion 23 disposed in the via hole 31 , and the first metal layer 40 is connected to the semiconductor layer 21 through the conductive filling portion 23 ;
  • the conductive filling portion 23 is made of a conductive material that has good contact with the semiconductor layer 21 and has a low resistivity; preferably, the resistivity of the conductive filling portion 23 is less than 5.48 ⁇ 10 -6 ⁇ m.
  • the material of the conductive filling portion 23 includes but is not limited to at least one of molybdenum (Mo), titanium (Ti), titanium nitride (TiN x ), and tungsten (W) or an alloy thereof.
  • the conductive filling portion 23 is disposed in the via hole 31 , and the first metal layer 40 is connected to the semiconductor layer 21 through the conductive filling portion 23 , thereby avoiding the problem due to The hole depth of the via hole 31 is too large.
  • the first metal layer 40 directly passes through the via hole 31 to connect to the semiconductor layer 21, the first metal layer 40 will have the risk of breaking; further , in this embodiment, the orthographic projection of the first metal layer 40 on the substrate 11 covers the orthographic projection of the conductive filling portion 23 on the substrate 11 , thereby increasing the size of the first metal layer.
  • the contact area between the layer 40 and the conductive filling portion 23 reduces the contact resistance and improves the stability of signal transmission.
  • the display panel also includes a spacer layer 50 located on the side of the insulating layer 30 away from the substrate 10.
  • the thickness of the spacer layer 50 ranges from 500 nanometers to 2000 nanometers.
  • the material of the spacer layer 50 is an inorganic material.
  • the inorganic material includes but is not limited to one of a single layer of silicon nitride ( SiN The embodiment does not specifically limit this. It can be understood that in this embodiment, by setting the material of the spacer layer 50 to be an inorganic material, compared with organic materials, the performance is more stable, the insulation is better, and the service life is extended.
  • the spacer layer 50 includes at least one groove 51 penetrating the spacer layer 50 , the groove 51 is connected with the via hole 31 ; wherein the first metal layer 40 is provided in the groove 51, the angle ⁇ between the side wall of the slot 51 and the bottom surface of the spacer layer 50 is greater than or equal to 85 degrees and less than or equal to 90 degrees. It should be noted that the bottom surface of the spacer layer 50 is the spacer The layer 50 is close to the side of the substrate 10; preferably, in the direction perpendicular to the substrate 10, the cross-section of the groove 51 of the via hole 31 is linear.
  • the ratio of the depth H 1 of the groove 51 to the width D 3 of the groove 51 is greater than or equal to 0.2 and less than or equal to 1; preferably, the depth H 1 of the groove 51
  • the width D3 of the groove 51 ranges from 500 nanometers to 2000 nanometers, and is not specifically limited in this embodiment.
  • the display panel further includes a second metal layer 22;
  • the thin film transistor layer 20 includes a plurality of thin film transistors 20A arranged in a matrix, and the first metal layer 40 includes the thin film transistors 20A.
  • the insulating layer 30 includes The plurality of via holes 31 includes a first via hole 31A and a second via hole 31B located above the active layer 21A.
  • the conductive filling portion 23 includes a plurality of via holes 31 disposed on the first via hole 31B.
  • the angle ⁇ 1 between the side wall of the first via hole 31A and the bottom surface of the gate insulation layer 32 is greater than or equal to 85 degrees and less than or equal to 90 degrees
  • the side wall of the second via hole 31B is between
  • the included angle ⁇ 2 of the bottom surface of the gate insulating layer 32 is greater than or equal to 85 degrees and less than or equal to 90 degrees.
  • the semiconductor layer 21 is located between the gate electrode 22A and the substrate 10
  • the insulating layer 30 includes a layer disposed between the semiconductor layer 21 and the gate electrode 22A.
  • the gate insulating layer 32 and the interlayer insulating layer 33 disposed on the side of the gate insulating layer 32 away from the gate 22A are taken as examples to illustrate the technical solution of the present application; wherein, the interlayer insulating layer 33
  • the thickness H 2 is greater than twice the thickness H 3 of the buffer layer 13 .
  • the first via hole 31A and the second via hole 31B both pass through the interlayer insulating layer 33 and the gate insulating layer 32;
  • the spacer layer 50 includes a plurality of Slots 51, the plurality of slots 51 include a first slot 51A connected to the first via hole 31A, and a second slot 51B connected to the second via hole 31B, wherein the leakage
  • the electrode 40B is disposed in the first slot 51A
  • the source electrode 40A is disposed in the second slot 51B
  • the orthographic projection of the drain electrode 40B on the substrate 11 covers the first filling
  • the orthographic projection of the portion 23A on the substrate 11 , and the orthographic projection of the source 40A on the substrate 11 covers the orthographic projection of the second filling portion 23B on the substrate 11 , thereby increasing the The contact area between the drain electrode 40B and the first filling part 23A is increased, and the contact area between the source electrode 40A and the second filling part 23B is increased, thereby reducing the contact resistance and improving the stability of signal transmission
  • the first filling part 23A is located in the first via hole 31A
  • the second filling part 23B is located in the second via hole 31B
  • the drain electrode 40B is provided in the first slot 51A and connected to the active layer 21A through the first via hole 31A and the first filling portion 23A, thereby preventing the first via hole 31A from being too deep.
  • the drain electrode 40B directly passes through the first via hole 31A and is connected to the active layer 21A, there is a risk of breakage; the source electrode 40A is disposed in the second slot 51B and passes through the first via hole 31A.
  • the two via holes 31B and the second filling portion 23B are connected to the active layer 21A, thereby preventing the source electrode 40A from directly passing through the second via hole due to the depth of the second via hole 31B being too large.
  • 31B is connected to the active layer 21A, there is a risk of breakage.
  • the angle ⁇ 1 between the side wall of the first slot 51A and the bottom surface of the spacer layer 50 is greater than or equal to 85 degrees and less than or equal to 90 degrees.
  • the ratio of the depth H 4 of 51A to the width D 4 of the first slot 51A is greater than or equal to 0.2 and less than or equal to 1;
  • the angle ⁇ 2 between the side wall of the second slot 51B and the bottom surface of the spacer layer 50 is greater than or equal to 85 degrees and less than or equal to 90 degrees, and the ratio of the depth H 5 of the second groove 51B to the width D 5 of the second groove 51B is greater than or equal to 0.2 and less than or equal to 1.
  • Figure 3 is a schematic cross-sectional view of the drain electrode of the existing display panel
  • Table 2 is the design width and actual width of the source electrode in the display panel provided by the embodiment of the present application, and Datasheet of designed and actual widths of drains in existing display panels.
  • the drain electrode 25B is located on a side of the interlayer insulating layer 24 away from the gate insulating layer 22. Due to limitations of exposure equipment and etching processes, the drain electrode 25B is The taper angle ⁇ of the electrode 25B is usually less than 70 degrees. Therefore, as the design width decreases, the actual width of the drain electrode 25B in the existing display panel is greater than the design width of the drain electrode 25B, resulting in the position of the drain electrode 25B.
  • the area of the drain electrode 25B becomes larger, which in turn results in a larger size of the thin film transistor 20A; and in this embodiment, by setting the angle between the side wall of the first slot 51A and the bottom surface of the spacer layer 50 ⁇ 1 is greater than or equal to 85 degrees and less than or equal to 90 degrees.
  • the drain electrode 40B is disposed in the first slot 51A.
  • the actual width of the drain electrode 40B can be determined by designing the first slot 51A.
  • the width of the drain electrode 40B is controlled so that the actual width of the drain electrode 40B of the display panel is approximately equal to the design width of the drain electrode 40B. Therefore, using the slotted design provided in this embodiment is conducive to realizing Fabrication of miniature thin film transistors.
  • the taper angle ⁇ of the drain electrode 25B, the interlayer insulating layer 24, the gate insulating layer 22 and the drain electrode 25B refers to the conventional display in FIG. 1
  • the thickness of the drain electrode 40B is 1500 nanometers to illustrate the technical solution of the present application.
  • the display panel provided by this embodiment has the same drain electrode 40B thickness.
  • the aspect ratio of the drain electrode 40B is positively related to the taper angle of the drain electrode 40B.
  • the angle ⁇ 1 between the side wall of the first slot 51A and the bottom surface of the spacer layer 50 is greater than or equal to 85 degrees and less than or equal to 90 degrees, the first slot 51A
  • the ratio of the depth H 4 to the width D 4 of the first groove 51A is greater than or equal to 0.2 and less than or equal to 1, so that the actual width of the drain electrode 40B of the display panel is equal to the design width of the drain electrode 40B Approximately equal.
  • this embodiment only takes the drain electrode 40B in the display panel and the drain electrode 25B in the existing display panel as an example to compare the design of the present application with the design of the prior art.
  • this embodiment there are no specific limitations on the number, size and position of the slots 51 and the number, type and position of the film layers included in the second metal layer 22 .
  • the taper angle of the first metal layer 40 located in the slot 51 can be controlled, thereby reducing the size of the taper angle.
  • the area size of the first metal layer 40 is small. Therefore, using the slot design provided in this embodiment is beneficial to providing a display panel with the metal layer having a high aspect ratio.
  • the display panel further includes a flat layer 60, a first electrode layer 70, a passivation layer 80 and a second electrode layer 90 stacked on the spacer layer 50; the display panel is provided with The first connection via hole 81A penetrates the flat layer 60 and the passivation layer 80, and the first connection via hole 81A is connected with the first slot 51A; the second electrode layer 90 includes The first electrode 91 is connected to the drain electrode 40B through the first connection via hole 81A; wherein the angle ⁇ 1 between the side wall of the first connection via hole 81A and the bottom surface of the flat layer 60 is greater than or equal to 85 degrees.
  • the angle ⁇ 1 between the side wall of the first connection via hole 81A and the bottom surface of the flat layer 60 is greater than or equal to 85 degrees, and less than Or equal to 90 degrees, thereby reducing the area occupied by the first connection via hole 81A on the passivation layer 80, thereby increasing the aperture ratio of the display panel, and thereby meeting the needs of high PPI display devices.
  • the first electrode 91 covers the side wall of the first connection via hole 81A and the bottom of the first connection via hole 81A.
  • the first connection via hole 81A is The depth of the hole 81A and the thickness of the first electrode 91 are not specifically limited.
  • the display panel is provided with a second connection via hole 81B penetrating the flat layer 60 and the passivation layer 80 and a third connection via hole 81C penetrating the passivation layer 80; a plurality of The slot 51 includes a third slot 51C connected to the second connection via hole 81B, the second connection via hole 81B communicates with the third slot 51C, and the first metal layer 40 includes a The first signal line 40C in the third slot 51C, the first electrode layer 70 includes a touch electrode 72, the second electrode layer 90 includes a bridge section 92, one end of the bridge section 92 passes through the The second connection via hole 81B is connected to the first signal line 40C, and the other end of the bridge section 92 passes through the third connection via hole 81C and is connected to the touch electrode 72; wherein, the second connection via hole 81B is connected to the first signal line 40C.
  • the angle ⁇ 2 between the side wall of the hole 81B and the bottom surface of the flat layer 60 is greater than or equal to 85 degrees and less than or equal to 90 degrees, thereby reducing the impact of the second connection via hole 81B on the passivation layer 80
  • the area occupied thereby increases the aperture ratio of the display panel
  • the angle ⁇ 3 between the side wall of the third connection via hole 81C and the bottom surface of the passivation layer 80 is greater than or equal to 85 degrees and less than or equal to 90 degrees. degree, thereby reducing the area occupied by the third connection via hole 81C on the passivation layer 80, thereby increasing the aperture ratio of the display panel, and meeting the needs of high PPI display devices.
  • the first connection via hole 81A, the second connection via hole 81B and the third connection via hole 81C each include two opposite openings (not labeled in the figure), wherein one The opening is provided on one side close to the base 10 , and the other opening is provided on a side far away from the base 10 .
  • the width of the opening on the side far away from the base 10 is the same as the width of the opening on the side close to the base 10 .
  • the ratio of the widths of the openings is greater than or equal to 0.9 and less than or equal to 1.1, so that the actual aperture of the first connection via hole 81A of the display panel is approximately equal to the design diameter of the first connection via hole 81A, so that The actual aperture diameter of the second connection via hole 81B of the display panel is approximately equal to the design diameter of the second connection via hole 81B, and the actual aperture diameter of the third connection via hole 81C of the display panel is equal to The design diameters of the third connection via holes 81C are approximately equal. Therefore, using the design of the connection via hole 31 provided in this embodiment is beneficial to realizing the first connection via hole 81A, the second connection via hole 81B and The third connection via hole 81C has a high aspect ratio.
  • the first electrode layer 70 includes a common electrode 71 and the touch electrode 72 arranged at intervals
  • the second electrode layer 90 includes a pixel electrode arranged at intervals and the bridge. Section 92, the pixel electrode passes through the first connection via hole 81A and is connected to the drain electrode 40B located in the first slot 51A, the first signal line 40C is a touch signal line, and the The touch electrode 72 is bridged with the touch signal line through the third connection via hole 81C, the bridge section 92 and the second connection via hole 81B.
  • the first signal line 40C is disposed in the third slot 51C.
  • the width of the third slot 51C can be controlled.
  • the taper angle of the first signal line 40C reduces the area size of the first signal line 40C, thereby reducing the wiring pressure in the display panel and promoting the development of the display panel to a higher PPI.
  • the second metal layer 22 further includes a second signal line 22B that is spaced apart from the gate electrode 22A, and the first metal layer 40 includes a third signal line 22B that is opposite to the second signal line 22B.
  • the thin film transistor layer 20 includes a third via hole 33A located above the second signal line 22B, and the conductive filling portion 23 includes a third filling portion disposed in the third via hole 33A.
  • the plurality of slots 51 include a fourth slot 51D connected to the third via hole 33A; wherein the third signal line 40C is disposed in the fourth slot 51D and passes through the third via hole 33A.
  • the three filling parts 23C are connected to the second signal line 22B; the angle ⁇ 3 between the side wall of the third via hole 33A and the bottom surface of the insulating layer 30 is greater than or equal to 85 degrees and less than or equal to 90 degrees; so The angle ⁇ 3 between the side wall of the fourth slot 51D and the bottom surface of the spacer layer 50 is greater than or equal to 85 degrees and less than or equal to 90 degrees; further, in this embodiment, the third via hole 33A Passing through the interlayer insulating layer 33 , the gate insulating layer 32 includes a first groove 32A connected to the third via hole 33A, and the second signal line 22B is disposed in the first groove 32A. Inside.
  • the third via hole 33A includes a third opening (not labeled in the figure) on a side away from the substrate 10 and a fourth opening (not labeled in the figure) close to the substrate 10 .
  • the third opening is The ratio of the width to the width of the fourth opening is greater than or equal to 0.9 and less than or equal to 1.1, so that the actual aperture diameter of the third via hole 33A of the display panel is equal to the design diameter of the third via hole 33A.
  • adopting the design of the third via hole 33A provided in this embodiment is beneficial to providing a display panel with the via hole having a high aspect ratio.
  • the third signal line 40C is disposed in the fourth slot 51D, and the angle ⁇ 3 between the side wall of the fourth slot 51D and the bottom surface of the spacer layer 50 is greater than or equal to 85 degrees, and less than or equal to 90 degrees. Therefore, the taper angle of the third signal line 40C located in the fourth slot 51D can be controlled by designing the width of the fourth slot 51D. This reduces the area size of the third signal line 40C, thereby reducing the wiring pressure in the display panel and promoting the development of the display panel to a higher PPI.
  • the second signal line 22B includes but is not limited to a scan line
  • the third signal line 40C includes but is not limited to a data line
  • the third signal line 40C includes a first signal sub-line. (not labeled in the figure) and a second signal sub-line (not labeled in the figure)
  • the extension direction of the first signal sub-line and the extension direction of the second signal sub-line are different
  • the first signal sub-line is provided in the third slot 51C and disconnected in the third slot 51C
  • the disconnected first signal sub-line passes through the third via hole 33A and the second signal line 22B
  • the two ends are electrically connected in the form of a bridge, thereby preventing the first signal sub-line and the second signal sub-line arranged on the same layer from being connected and causing a short circuit.
  • the gate insulating layer 32 also includes a second groove (not labeled in the figure), and the gate 22A is disposed in the second groove, so that the gate electrode 22A is disposed in the second groove.
  • the gate 22A plays the role of blocking water and oxygen and insulating;
  • the substrate 10 also includes a light-shielding layer 12 stacked between the substrate 11 and the buffer layer 13 , and the light-shielding layer 12 is on the substrate 10
  • the orthographic projection of the active layer 21A on the substrate 10 covers the orthographic projection of the active layer 21A on the substrate 10 .
  • the light shielding layer 12 can block the light directed to the active layer 21A, thereby reducing the risk of light irradiating the active layer 21A.
  • the leakage current caused by the photogenerated carriers generated in layer 21A increases, thereby maintaining the stability of the display panel during operation.
  • FIG. 8 is a second schematic cross-sectional view of a display panel provided by an embodiment of the present application.
  • the structure of the display panel is similar/identical to the structure of the display panel provided in the above-mentioned embodiment one.
  • the description of the display panel in the above-mentioned embodiment which will not be described again here. The difference between the two Just because:
  • the material of the semiconductor layer 21 is a metal oxide
  • the metal oxide includes but is not limited to Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO) ) or indium gallium zinc titanium oxide (Indium Gallium Zinc Tin Oxide, IGZTO);
  • the material of the semiconductor layer 21 is indium gallium zinc oxide as an example to illustrate the technical solution of the present application.
  • the gate 22A is located between the semiconductor layer 21 and the substrate 10 , and the insulating layer 30 includes a layer disposed between the semiconductor layer 21 and the first metal layer 40 Interlayer insulating layer 33, a gate insulating layer 32 is provided on the side of the semiconductor layer 21 away from the interlayer insulating layer 33; specifically, in this embodiment, the insulating layer 30 includes a gate insulating layer 32 provided between the semiconductor layer 21 and the interlayer insulating layer 33.
  • the interlayer insulating layer 33 between the first metal layers 40 is taken as an example to illustrate the technical solution of the present application.
  • the first via hole 31A and the second via hole 31B both pass through the interlayer insulating layer 33 ; wherein the thickness of the interlayer insulating layer 33 is greater than that of the buffer layer 13 twice the thickness; preferably, the thickness of the interlayer insulating layer 33 is 600 nanometers to 5000 nanometers.
  • the third via hole 33A passes through the interlayer insulating layer 33 and the gate insulating layer 32 , and the buffer layer 13 includes fifth slots 13A and sixth openings penetrating the buffer layer 13 .
  • slot 13B, the fifth slot 13A is connected to the third via hole 33A; wherein, the second signal line 22B is disposed in the fifth slot 13A, and the gate 22A is disposed in the third via hole 33A.
  • the angle between the side wall of the fifth slot 13A and the bottom surface of the buffer layer 13 is greater than or equal to 85 degrees, and The angle between the side wall of the sixth slot 13B and the bottom surface of the buffer layer 13 is greater than or equal to 85 degrees and less than or equal to 90 degrees.
  • the second signal line 22B is disposed in the fifth slot 13A; the side wall of the fifth slot 13A and the buffer layer 13
  • the included angle ⁇ 4 of the bottom surface is greater than or equal to 85 degrees and less than or equal to 90 degrees. Therefore, the width of the fifth groove 13A can be designed to control the width of the fifth groove 13A.
  • the taper angle of the second signal line 22B reduces the area size of the second signal line 22B, thereby further reducing the wiring pressure in the display panel and promoting the development of the display panel to a higher PPI.
  • the gate electrode 22A is located between the substrate 11 and the active layer 21A, and the orthographic projection of the active layer 21A on the substrate 10 is located at the gate electrode 22A.
  • the gate 22A functions as the light-shielding layer 12 in the above embodiment, thereby saving the engineering process and thereby reducing the manufacturing cost of the display panel.
  • FIG. 9 is a third schematic cross-sectional view of a display panel provided by an embodiment of the present application.
  • the structure of the display panel is similar/identical to the structure of the display panel provided in the above embodiment.
  • the description of the display panel in the above embodiment which will not be described in detail here. The only difference between the two is lies in:
  • the semiconductor layer 21 is an amorphous silicon semiconductor layer 21.
  • the semiconductor layer 21 includes a channel region 210 provided corresponding to the gate electrode 22A, and sources located on both sides of the channel region 210.
  • the electrode contact region 212 and the drain contact region 211 wherein the portion of the semiconductor layer 21 located in the channel region 210 includes a single crystal silicon layer, and the semiconductor layer 21 is located in the source contact region 212 and the drain contact region.
  • Parts of the region 211 include an undoped amorphous silicon layer 21B and an amorphous silicon doped layer 21C stacked on the substrate 10 , and the single crystal silicon layer of the channel region 210 is in contact with the source electrode.
  • the amorphous silicon doped layer of the contact region 212 and the drain contact region 211 is connected 21C.
  • the drain electrode 40B is disposed in the first groove 51A and passes through the first via hole 31A and the first filling portion 23A to communicate with the amorphous silicon.
  • the doped layer is connected.
  • the source 40A is disposed in the second slot 51B and connected to the second via hole 31B and the second filling portion 23B.
  • the amorphous silicon doped layer 21C is connected.
  • FIG. 10 is a flow chart of a method of producing a display panel according to an embodiment of the present application
  • Figure 11A Figure 11N is a structural process flow chart for manufacturing the display panel in Figure 10.
  • the manufacturing method of the display panel includes the following steps:
  • Step S100 Provide a substrate 10, including providing a substrate 11, and a light-shielding layer 12 and a buffer layer 13 sequentially formed on the substrate 11, as shown in FIG. 11A.
  • the material when the substrate 11 is a rigid substrate, the material may be metal or glass; when the substrate 11 is a flexible substrate, the material may include acrylic resin, methacrylic resin, polyisoprene, At least one of vinyl resin, epoxy resin, polyurethane resin, cellulose resin, silicone resin, polyimide-based resin, and polyamide-based resin.
  • the material of the light-shielding layer 12 includes but is not limited to metal materials, and the metal materials include but is not limited to one or more alloys of molybdenum (Mo), titanium (Ti), and nickel (Ni); the buffer layer 13 Materials include but are not limited to a single layer of silicon nitride (Si 3 N 4 ), a single layer of silicon dioxide (SiO 2 ), a single layer of silicon oxynitride (SiON x ), or a double-layer structure of the above layers.
  • the metal materials include but is not limited to one or more alloys of molybdenum (Mo), titanium (Ti), and nickel (Ni);
  • the buffer layer 13 Materials include but are not limited to a single layer of silicon nitride (Si 3 N 4 ), a single layer of silicon dioxide (SiO 2 ), a single layer of silicon oxynitride (SiON x ), or a double-layer structure of the above layers.
  • Step S200 Form a thin film transistor layer 20 on the substrate 10.
  • the thin film transistor layer 20 includes a semiconductor layer 21, an insulating layer 30 and a first metal layer 40 stacked on the substrate 10.
  • the insulating layer 30 The first metal layer 40 is disposed on the substrate 10 and the semiconductor layer 21 and covers the semiconductor layer 21 .
  • the first metal layer 40 is disposed on the insulating layer 30 .
  • the insulating layer 30 includes at least one via hole 31 .
  • the first metal layer 40 is connected to the semiconductor layer 21 through the via hole 31, and the angle ⁇ between the side wall of the via hole 31 and the bottom surface of the insulating layer 30 is greater than or equal to 85 degrees and less than or equal to 90 degrees. Spend.
  • step S200 includes the following steps:
  • Step S201 The semiconductor layer 21, the gate insulating layer 32, the second metal layer 22 and the interlayer insulating layer 33 are sequentially formed on the substrate 10, wherein the insulating layer 30 includes The gate insulating layer 32 between the gate electrode 22A and the interlayer insulating layer 33 disposed on the side of the gate insulating layer 32 away from the gate electrode 22A.
  • the second metal layer 22 includes corresponding The gate electrode 22A provided on the semiconductor layer 21 is as shown in FIG. 11B.
  • the material of the semiconductor layer 21 includes but is not limited to one of polysilicon, amorphous silicon and oxide.
  • the technical solution of the present application is illustrated by taking the material of the semiconductor layer 21 as polysilicon. .
  • the semiconductor layer 21 includes an active layer 21A located between the substrate 10 and the gate insulating layer 32 .
  • the active layer 21A includes a first conductor part and a second conductor part, and is located on the first conductor part.
  • An active section is between the conductor part and the second conductor part, and the gate 22A is arranged corresponding to the active section.
  • the gate insulating layer 32 is made of materials including but not limited to silicon oxide ( SiO groove, the gate 22A line is disposed in the second groove; the interlayer insulating layer 33 has strong water and oxygen barrier capabilities and insulation capabilities, and its materials include but are not limited to silicon oxide (SiO x ), nitride Silicon ( SiN It is 600 nanometers to 5000 nanometers.
  • Step S202 Form a first protective layer 101 and a photoresist material 103 sequentially on the interlayer insulating layer 33, as shown in FIG. 11C; wherein, the material of the first protective layer 101 is an organic material, and the first protective layer
  • the orthographic projection of layer 101 on the substrate 10 covers the orthographic projection of the interlayer insulating layer 33 on the substrate 10 .
  • Step S203 Use a first mask to expose and develop the photoresist material 103 to form a first photoresist layer 1031 located above the first protective layer 101.
  • the first photoresist layer 1031 includes a corresponding The first through hole 1031A provided in the first conductor segment and the second through hole 1031B provided corresponding to the second conductor segment are shown in FIG. 11D.
  • a mask plate with different transmittances can be used to perform a photomask process on the photoresist material 103.
  • the mask plate includes a first transmittance area Tr1 and a second transmittance area. Tr2, the first transmittance area Tr1 corresponds to the first through hole 1031A and the second through hole 1031B, the transmittance of the first transmittance area Tr1 is 100%, and the second through hole The transmittance area Tr2 corresponds to the remaining area and the third transmittance area is opaque.
  • the method of exposing the photoresist material 103 includes but is not limited to using masks with different transmittances; in this embodiment, using masks with different transmittances
  • the photomask process performed on the photoresist material 103 using a mask is only for illustration, and is not limited in this embodiment.
  • Step S204 Etch the first protective layer 101 that is not covered by the first photoresist layer 1031, and form a first opening 101A corresponding to the active layer 21A on the first protective layer 101.
  • the second opening 101B, the first opening 101A and the second opening 101B both pass through the first protective layer 101, as shown in FIG. 11E.
  • Step 205 Peel off the first photoresist layer 1031.
  • Step 206 Use the first protective layer 101 as a second mask to etch the insulating layer 30 to form the via hole 31 located above the active layer 21A, wherein the via hole 31 It includes a first via hole 31A and a second via hole 31B located above the active layer 21A.
  • the first via hole 31A is connected to the first opening 101A
  • the second via hole 31B is connected to the first via hole 101A.
  • the second opening 101B is provided in communication, and the first via hole 31A and the second via hole 31B both pass through the interlayer insulating layer 33 and the gate insulating layer 32 .
  • Step 207 Peel off the protective layer, as shown in Figure 11F.
  • the first protective layer 101 is formed on the interlayer insulating layer 33 , and the first protective layer 101 is used as a mask to separate the interlayer insulating layer 33 and the interlayer insulating layer 33 .
  • the gate insulating layer 32 is etched to form the first via hole 31A corresponding to the first opening 101A and the second via hole 31B corresponding to the second opening 101B, wherein the The angle ⁇ 1 between the side wall of the first via hole 31A and the bottom surface of the gate insulating layer 32 is greater than or equal to 85 degrees and less than or equal to 90 degrees.
  • the included angle ⁇ 2 of the bottom surface of the insulating layer 32 is greater than or equal to 85 degrees and less than or equal to 90 degrees, thereby reducing the area occupied by the via hole 31 on the insulating layer 30 and thereby improving the performance of the display panel.
  • the aperture ratio meets the requirements of high PPI display devices, and in this embodiment, the first via hole 31A and the second via hole 31B are made simultaneously through only one lighting process, which reduces the manufacturing cost of the display panel.
  • the via hole 31 includes a first opening 311 on a side away from the substrate 10 and a second opening 312 on a side close to the substrate 10.
  • the width D1 of the first opening 311 is the same as the width D1 of the first opening 311.
  • the ratio of the width D 2 of the two openings 312 is greater than or equal to 0.9 and less than or equal to 1.1, so that the actual aperture of the through hole 31 of the display panel is approximately equal to the design diameter of the through hole 31 . Therefore, using The design of the via hole 31 provided in this embodiment is conducive to the production of the micro thin film transistor 20A.
  • the manufacturing method of the display panel further includes the following steps:
  • Step S300 Form a conductive filling layer 230 on the side of the interlayer insulating layer 33 away from the substrate 10, as shown in FIG. 11G, where the conductive filling layer 230 fills the first via hole 31A and the For the second via hole 31B, the thickness of the conductive filling layer 230 is 500 nanometers to 5000 nanometers.
  • the conductive filling layer 230 is made of a conductive material that has good contact with the semiconductor layer 21 and has a low resistivity; preferably , the resistivity of the conductive filling layer 230 is less than 5.48 ⁇ 10 -6 ⁇ m, and the materials of the conductive filling layer 230 include but are not limited to molybdenum (Mo), titanium (Ti), titanium nitride (TiN x ) and At least one type of tungsten (W) or its alloy is not specifically limited in this embodiment.
  • Mo molybdenum
  • Ti titanium
  • TiN x titanium nitride
  • W tungsten
  • Step S400 Pattern the conductive filling layer 230 to form a conductive filling portion 23.
  • the conductive filling portion 23 includes a first filling portion 23A disposed in the first via hole 31A, and a first filling portion 23A disposed in the first via hole 31A.
  • the second filling portion 23B in the two via holes 31B is as shown in FIG. 11H.
  • Step S500 Form a spacer layer 50 on the side of the interlayer insulating layer 33 away from the substrate 10, as shown in FIG. 11I.
  • the thickness of the spacer layer 50 ranges from 500 nanometers to 2000 nanometers.
  • the material of layer 50 is an inorganic material, and the inorganic material includes but is not limited to one or more of a single layer of silicon nitride (SiN).
  • SiN silicon nitride
  • the double-layer structure of the film layer is not specifically limited in this embodiment. It can be understood that in this embodiment, by setting the material of the spacer layer 50 to be an inorganic material, compared with organic materials, the performance is more stable and the insulation is better. Better, extend service life.
  • Step S600 Pattern the spacer layer 50 to form at least one groove 51 penetrating the spacer layer 50.
  • the groove 51 is connected to the via hole 31, and the side walls of the groove 51 are connected to the via hole 31.
  • the angle ⁇ between the bottom surfaces of the spacer layer 50 is greater than or equal to 85 degrees and less than or equal to 90 degrees.
  • step S600 includes the following steps:
  • Step S601 Form a second protective layer 102 and a photoresist material 103 sequentially on the spacer layer 50, as shown in FIG. 11J; wherein the material of the second protective layer 102 is an organic material, and the second protective layer 102
  • the orthographic projection on the substrate 10 covers the orthographic projection of the spacer layer 50 on the substrate 10 .
  • Step S602 Use a third mask to expose and develop the photoresist material 103 to form a second photoresist layer 1032 located above the second protective layer 102.
  • the second photoresist layer 1032 includes a corresponding The third through hole 1032A provided in the first via hole 31A and the fourth through hole 1032B provided corresponding to the second via hole 31B are shown in FIG. 11K .
  • a mask plate with different transmittances may be used to perform a photomask process on the photoresist material 103.
  • the mask plate includes a first transmittance area Tr1 and a second transmittance area. Tr2, the first transmittance area Tr1 corresponds to the third through hole 1032A and the fourth through hole 1032B, the transmittance of the first transmittance area Tr1 is 100%, and the second through hole The transmittance area Tr2 corresponds to the remaining area and the third transmittance area is opaque.
  • the method of exposing the photoresist material 103 includes but is not limited to using masks with different transmittances; in this embodiment, using masks with different transmittances
  • the photomask process performed on the photoresist material 103 using a mask is only for illustration, and is not limited in this embodiment.
  • Step S603 Etch the second protective layer 102 that is not covered by the second photoresist layer 1032, and form a third opening 102A corresponding to the third through hole 1032A on the second protective layer 102. , and a fourth opening 102B provided corresponding to the fourth through hole 1032B. Both the third opening 102A and the fourth opening 102B pass through the second protective layer 102, as shown in FIG. 11L.
  • Step S604 Peel off the second photoresist layer 1032.
  • Step S605 Use the second protective layer 102 as a fourth mask to etch the spacer layer 50 to form the groove 51 penetrating the spacer layer 50, where the groove 51 includes The first slot 51A corresponding to the third opening 102A and the second slot 51B corresponding to the fourth opening 102B; specifically, the first slot 51A and the first through The hole 31A is connected, and the second slot 51B is connected with the second via hole 31B.
  • Step S606 Peel off the protective layer, as shown in Figure 11M.
  • the second protective layer 102 is formed on the spacer layer 50, and the second protective layer 102 is used as a mask to etch the spacer layer 50 to form a layer corresponding to the spacer layer 50.
  • the first slot 51A provided in the third opening 102A and the second slot 51B provided corresponding to the fourth opening 102B, wherein the distance between the side wall of the first slot 51A and the bottom surface of the spacer layer 50.
  • the included angle ⁇ 1 is greater than or equal to 85 degrees and less than or equal to 90 degrees.
  • the included angle ⁇ 2 between the side wall of the second slot 51B and the bottom surface of the spacer layer 50 is greater than or equal to 85 degrees and less than or equal to 90 degrees.
  • Step S700 Form the first metal layer 40 on the spacer layer 50, pattern the first metal layer 40 to form a drain electrode 40B located in the first groove 51A, and a drain electrode 40B located in the first groove 51A.
  • the source electrode 40A in the second slot 51B is shown in FIG. 11N.
  • the actual width of the drain electrode 40B can be controlled by designing the width of the first slot 51A, so that the actual width of the drain electrode 40B of the display panel Approximately equal to the design width of the drain electrode 40B, by setting the angle ⁇ 2 between the side wall of the second slot 51B and the bottom surface of the spacer layer 50 to be greater than or equal to 85 degrees and less than or equal to 90 degrees, so The source electrode 40A is disposed in the second slot 51B.
  • the actual width of the source electrode 40A can be controlled by designing the width of the second slot 51B, so that the source electrode of the display panel
  • the actual width of the drain electrode 40A is approximately equal to the designed width of the drain electrode 40B. Therefore, using the slot 51 design provided in this embodiment is beneficial to the production of the micro thin film transistor 20A.
  • Step S800 sequentially form the flat layer 60, the first electrode layer 70, the passivation layer 80 and the second electrode layer 90 on the spacer layer 50 to form the first substrate 100, as shown in FIG. 4 .
  • Step S900 Make a second substrate, assemble the second substrate and the first substrate, and inject liquid crystal between the first substrate and the second substrate.
  • This embodiment also provides a mobile terminal, which includes a terminal body and the display panel described in any of the above embodiments, and the terminal body and the display panel are combined into one body.
  • the mobile terminal can be a display screen of a smartphone, tablet computer, laptop, smart bracelet, smart watch, smart glasses, smart helmet, desktop computer, smart TV or digital camera, or even Applied to electronic devices with flexible displays.

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Abstract

本申请提供一种显示面板及移动终端，显示面板包括基底和薄膜晶体管层，薄膜晶体管层包括半导体层、绝缘层和第一金属层，绝缘层设置于基底和半导体层上且覆盖半导体层，第一金属层设置于绝缘层上：绝缘层包括至少一过孔，第一金属层通过过孔与半导体层连接，过孔的侧壁与绝缘层底面的夹角大于或等于85度，且小于或等于90度。

Description

显示面板及移动终端 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及移动终端。
背景技术
随着显示技术不断发展，消费者对显示面板的窄边框、高开口率、高亮度、高分辨率等参数提出了越来越高的要求，其中，特别是在新兴显示技术领域，例如：VR(VirtualRe ality)显示/AR(AugmentedReality)显示、面板系统集成等领域，需要阵列衬底具有超高像素密度(PixelsPerInch，PPI)和亚微米级别的器件尺寸。
在现有的阵列衬底工艺制程中，通常采用在绝缘层上开设过孔来实现位于不同膜层的导电部件进行电连接，其中，位于同一膜层的多个导电部件需要分别同位于其他不同层的导电部件进行电连接，则导致所需要刻蚀的过孔的深度和所述过孔穿过的膜层数目均不相同；而为使阵列衬底具有超高像素密度和亚微米级别的器件尺寸，要求阵列器件的线宽、线距、过孔的尺寸等都尽可能减小，同时，需要金属走线厚度和过孔的深度尽可能增加。
但由于受曝光设备和刻蚀工艺的限制，过孔的锥度角(taper)较小，过孔两侧呈圆弧形，从而导致所述开孔在所述绝缘层上所占据的面积较大，且金属走线需要完全覆盖过孔，这就导致过孔上的金属走线的线宽变大，进而不利于高PPI的走线排布。
技术问题
本申请实施例提供一种显示面板，用以缓解相关技术中的不足。
技术解决方案
为实现上述功能，本申请实施例提供的技术方案如下：
本申请实施例提供一种显示面板，包括基底和设置于所述基底上的薄膜晶体管层，所述薄膜晶体管层包括层叠设置于所述基底上的半导体层、绝缘层和第一金属层，所述绝缘层设置于所述基底和半导体层上且覆盖所述半导体层，所述第一金属层设置于所述绝缘层上；
其中，所述绝缘层包括至少一过孔，所述第一金属层通过所述过孔与所述半导体层连接，所述过孔的侧壁与所述绝缘层底面的夹角大于或等于85度，且小于或等于90度。
在本申请实施例所提供的显示面板中，所述过孔包括远离所述基底一侧的第一开口和靠近所述基底一侧的第二开口；
其中，所述第一开口的宽度与所述第二开口的宽度的比值大于或等于0.9，且小于或等于1.1。
在本申请实施例所提供的显示面板中，所述基底包括衬底和设置于所述衬底上缓冲层，所述绝缘层的厚度大于所述缓冲层的厚度的两倍。
在本申请实施例所提供的显示面板中，所述显示面板还包括设置于所述过孔内的导电填充部，所述第一金属层通过所述导电填充部与所述半导体层连接。
在本申请实施例所提供的显示面板中，所述导电填充部的电阻率小于5.48×10 -6Ω·m。
在本申请实施例所提供的显示面板中，所述第一金属层在所述衬底上的正投影覆盖所述导电填充部在所述衬底上的正投影。
在本申请实施例所提供的显示面板中，所述显示面板还包括位于所述绝缘层远离所述基底一侧的间隔层，所述间隔层包括贯穿所述间隔层的至少一开槽，所述开槽与所述过孔连通设置；
其中，所述第一金属层设置于所述开槽内，所述开槽的侧壁与所述间隔层底面的夹角大于或等于85度，且小于或等于90度。
在本申请实施例所提供的显示面板中，所述开槽的深度与所述开槽的宽度比值大于等于0.2，且小于等于1。
在本申请实施例所提供的显示面板中，所述显示面板还包括第二金属层；
所述薄膜晶体管层包括多个薄膜晶体管，所述第一金属层包括所述薄膜晶体管的源极和漏极，所述半导体层包括所述薄膜晶体管的有源层，所述第二金属层包括所述薄膜晶体管的栅极；
所述绝缘层包括多个所述过孔，多个所述过孔包括位于所述有源层上方的第一过孔和第二过孔，所述漏极通过所述第一过孔与所述有源层连接，所述源极通过所述第二过孔与所述有源层连接。
在本申请实施例所提供的显示面板中，所述显示面板还包括导电填充部，所述导电填充部包括设置于所述第一过孔内的第一填充部、及设置于所述第二过孔内的第二填充部，所述漏极通过所述第一填充部与所述有源层连接，所述源极通过所述第二填充部与所述有源层连接。
在本申请实施例所提供的显示面板中，所述间隔层包括多个所述开槽，多个所述开槽包括与所述第一过孔连通的第一开槽、及与所述第二过孔连通的第二开槽；
其中，所述漏极设置于所述第一开槽内，所述源极设置于所述第二开槽内。
在本申请实施例所提供的显示面板中，所述半导体层位于所述栅极和所述基底之间，所述绝缘层包括设置于所述半导体层和所述栅极之间的栅极绝缘层、及设置于所述栅极绝缘层远离所述栅极一侧的层间绝缘层；
所述第一过孔和所述第二过孔均穿过所述层间绝缘层和所述栅极绝缘层；
其中，所述基底包括衬底和设置于所述衬底上缓冲层，所述层间绝缘层的厚度大于所述缓冲层的厚度的两倍。
在本申请实施例所提供的显示面板中，所述栅极位于所述半导体层和所述基底之间，所述绝缘层包括设置于所述半导体层与所述第一金属层之间的层间绝缘层，所述半导体层远离所述层间绝缘层的一侧设置有栅极绝缘层；
所述第一过孔和所述第二过孔均穿过所述层间绝缘层；
其中，所述基底包括衬底和设置于所述衬底上缓冲层，所述层间绝缘层的厚度大于所述缓冲层的厚度的两倍。
在本申请实施例所提供的显示面板中，所述显示面板还包括层叠设置于所述间隔层上的平坦层、第一电极层、钝化层以及第二电极层；
所述显示面板内设置有贯穿所述平坦层和所述钝化层的第一连接过孔，所述第一连接过孔与所述第一开槽连通；
所述第二电极层包括穿过所述第一连接过孔与所述漏极连接的第一电极；
其中，所述第一连接过孔的侧壁与所述平坦层底面的夹角大于或等于85度，且小于或等于90度。
在本申请实施例所提供的显示面板中，所述显示面板内设置有贯穿所述平坦层和所述钝化层的第二连接过孔、及贯穿所述钝化层的第三连接过孔；
多个所述开槽包括与所述第二连接过孔连通的第三开槽，所述第二连接过孔与所述第三开槽连通，所述第一金属层包括设置于所述第三开槽内的第一信号线，所述第一电极层包括触控电极，所述第二电极层包括桥接段，所述桥接段一端穿过所述第二连接过孔与所述第一信号线连接，所述桥接段另一端穿过所述第三连接过孔与所述触控电极连接；
其中，所述第二连接过孔的侧壁与所述平坦层底面的夹角大于或等于85度，且小于或等于90度，所述第三连接过孔的侧壁与所述钝化层底面的夹角大于或等于85度，且小于或等于90度。
在本申请实施例所提供的显示面板中，所述第二金属层还包括与所述栅极间隔设置的第二信号线，所述第一金属层包括与所述第二信号线相对设置的第三信号线，
所述薄膜晶体管层包括位于所述第二信号线上方的第三过孔，所述导电填充部包括设置于所述第三过孔内的第三填充部，多个所述开槽包括与所述第三过孔连通的第四开槽；
其中，所述第三信号线设置于所述第四开槽内并通过所述第三填充部与所述第二信号线连接；所述第三过孔的侧壁与所述绝缘层底面的夹角大于或等于85度，且小于或等于90度。
在本申请实施例所提供的显示面板中，所述第三过孔包括远离所述基底一侧的第三开口和靠近所述基底一侧的第四开口；
其中，所述第三开口的宽度与所述第四开口的宽度的比值大于或等于0.9，且小于或等于1.1。
在本申请实施例所提供的显示面板中，所述半导体层位于所述栅极和所述基底之间， 所述绝缘层包括设置于所述半导体层和所述栅极之间的栅极绝缘层、及设置于所述栅极绝缘层远离所述栅极一侧的层间绝缘层；
所述第三过孔穿过所述层间绝缘层，所述栅极绝缘层包括与所述第三过孔连通的第一凹槽，所述第二信号线设置于所述第一凹槽内。
在本申请实施例所提供的显示面板中，所述栅极位于所述半导体层和所述基底之间，所述绝缘层包括设置于所述半导体层与所述第一金属层之间的层间绝缘层，所述半导体层远离所述层间绝缘层的一侧设置有栅极绝缘层；
所述第三过孔穿过所述层间绝缘层和所述栅极绝缘层，所述基底包括衬底和设置于所述衬底上缓冲层，所述缓冲层包括贯穿所述缓冲层的第五开槽，
其中，所述第二信号线设置于所述第五开槽内，所述第五开槽的侧壁与所述缓冲层底面的夹角大于或等于85度，且小于或等于90度。
本申请实施例提供一种移动终端，包括终端主体和上述任一所述的显示面板，所述终端主体与所述显示面板组合为一体
有益效果
本申请实施例提供一种显示面板，所述显示面板包括基底和设置于所述基底上的薄膜晶体管层，所述薄膜晶体管层包括层叠设置于所述基底上的半导体层、绝缘层和第一金属层，所述绝缘层设置于所述基底和半导体层上且覆盖所述半导体层，所述第一金属层设置于所述绝缘层上；通过设置所述绝缘层包括至少一过孔，所述第一金属层通过所述过孔与所述半导体层连接，所述过孔的侧壁与所述绝缘层底面的夹角大于或等于85度，且小于或等于90度，从而减小所述过孔的在所述绝缘层上所占据的面积，进而提升所述显示面板的开口率。
附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为现有显示面板的结构示意图；
图2为现有显示面板的层间绝缘层的截面示意图；
图3为现有显示面板的漏极的截面示意图；
图4为本申请实施例所提供的显示面板的第一种截面示意图；
图5为本申请实施例所提供的绝缘层的截面示意图；
图6为图4中A处的放大图；
图7为图4中B处的放大图；
图8为本申请实施例所提供的显示面板的第二种截面示意图；
图9为本申请实施例所提供的显示面板的第三种截面示意图；
图10为本申请实施例所提供显示面板的制作方法的流程图；
图11A至图11N为图10中显示面板制作的结构工艺流程图。
本发明的实施方式
本申请实施例提供一种显示面板。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
请参阅图4～图11N，本申请实施例提供一种显示面板，所述显示面板包括基底10和设置于所述基底10上的薄膜晶体管层20，所述薄膜晶体管层20包括层叠设置于所述基底10上的半导体层21、绝缘层30和第一金属层40，所述绝缘层30设置于所述基底10和半导体层21上且覆盖所述半导体层21，所述第一金属层40设置于所述绝缘层30上；
其中，所述绝缘层30包括至少一过孔31，所述第一金属层40通过所述过孔31与所述半导体层21连接，所述过孔31的侧壁与所述绝缘层30底面的夹角α大于或等于85度，且小于或等于90度。
请参阅图1，为现有显示面板的结构示意图；需要说明的是，本实施例对所述现有显示面板的结构不做具体限制，下文仅以现有显示面板为液晶显示面板LiquidCrystalDisplay，LCD)为例进行举例说明。
现有显示面板包括相对设置的第一基板100、第二基板(图中未画出)以及设置于所述第一基板100与所述第二基板之间的液晶层(图中未画出)，其中，所述第一基板100为阵列基板，包括基底10以及依次层叠设置与所述基底10上的薄膜晶体管层20、平坦层30、公共电极40、钝化层50以及像素电极60，所述基底10包括层叠设置的衬底11、遮光层12以及缓冲层13，所述薄膜晶体管层20包括依次层叠设置于所述基底10上的有源层21、栅极绝缘层22、栅极23、层间绝缘层24、源极25A和漏极25B；其中，所述薄膜晶体管层20包括呈矩阵式排布的多个薄膜晶体管20A，所述薄膜晶体管20A包括贯穿所述层间绝缘层24和所述栅极绝缘层22的第一过孔26A和第二过孔26B。
目前，在现有的阵列基板工艺制程中，通常采用在所述有源层21上开设过孔26来实现位于不同膜层的导电部件进行电连接，例如在图1中，所述显示面板内设有穿过所述层间绝缘层24和所述栅极绝缘层22的第一过孔26A和第二过孔26B，所述源极25A通过所述第一过孔26A与所述有源层21连接，所述漏极25B通过所述第二过孔26B与所述有源层21连接，但由于曝光设备和刻蚀工艺的限制，在现有阵列基板的工艺制程中，所述过孔的锥度角(Taper)较小，具体地，请结合图2为现有显示面板的层间绝缘层的截面示意图，所述第一过孔26A的锥度角β 1小于80度，所述第一过孔26A的两侧呈圆弧形,从而导致所述第一过孔26A在所述层间绝缘层24上所占据的面积较大，导致位于所述第一过孔26A 上的金属层面积变大；所述第二过孔26B的锥度角β 2小于80度，所述第二过孔26B的两侧呈圆弧形,所述第二过孔26B在所述层间绝缘层24上所占据的面积较大，导致位于所述第二过孔26B上的金属层面积变大，进而造成薄膜晶体管的尺寸较大，且不利于高PPI(像素密度)的走线排布。
现结合具体实施例对本申请的技术方案进行描述。
请结合图4、图5图6和图7，其中，图4为本申请实施例所提供的显示面板的第一种截面示意图；图5为本申请实施例所提供的绝缘层的截面示意图，图6为图4中A处的放大图，图7为图4中B处的放大图。
本申请实施例一种显示面板，所述显示面板包括但不限于液晶显示面板(LiquidCrystalDisplay，LCD)和有机发光二极管(OrganicLightEmittingDiode，OLED)显示面板中的一种；需要说明的是，本实施例以所述显示面板为液晶显示面板为例对本申请的技术方案进行描述。
在本实施例中，所述显示面板包括相对设置的第一基板100、第二基板(图中未画出)以及设置于所述第一基板100与所述第二基板之间的液晶层(图中未画出)；具体地，本实施例以所述第一基板100为阵列基板、所述第二基板为彩膜基板为例对本申请的技术方案进行举例说明。
在本实施例中，所述第一基板100包括基底10和设置于所述基底10上的薄膜晶体管层20，所述基底10包括衬底11和设置与所述衬底11上的缓冲层13，所述衬底11可以包括刚性衬底或柔性衬底中的一种，本实施例对此不做具体限制。
所述薄膜晶体管层20包括层叠设置于所述基底10上的半导体层21、绝缘层30和第一金属层40，所述绝缘层30设置于所述基底10和半导体层21上且覆盖所述半导体层21，所述第一金属层40设置于所述绝缘层30上；需要说明的是，所述半导体层21的材料包括但不限于多晶硅、非晶硅和氧化物中的一种，本实施例以所述半导体层21的材料为多晶硅为例对本申请的技术方案进行举例说明。
在本实施例中，所述绝缘层30包括至少一过孔31，所述第一金属层40通过所述过孔31与所述半导体层21连接，所述过孔31的侧壁与所述绝缘层30底面的夹角α大于或等于85度，且小于或等于90度，需要说明的是，所述绝缘层30底面为所述绝缘层30靠近所述基底10的一侧；优选地，在垂直于所述基底10的方向上，所述过孔31的侧壁的截面呈直线型。
请结合图2、图5和表一；其中，表一为本申请实施例所提供的显示面板中过孔的设计孔径和实际孔径、及现有显示面板中过孔的设计孔径和实际孔径的数据表。
Figure PCTCN2022115931-appb-000001
表一
在所述现有显示面板中，由于曝光设备和刻蚀工艺的限制，所述过孔26的锥度角通常小于80度，所述过孔26的两侧呈圆弧形，因此，随着所述现有显示面板中所述过孔26的设计孔径的减小，所述现有显示面板中的所述过孔26的实际孔径大于所述过孔26的设计直径，而在本实施例中通过设置所述过孔31的侧壁与所述绝缘层30底面的夹角α大于或等于85度，且小于或等于90度，进一步地，所述过孔31包括远离所述基底10一侧的第一开口311、及靠近所述基底10一侧的第二开口312，所述第一开口311的宽度与所述第二开口312的宽度的比值大于或等于0.9，且小于或等于1.1，从而使所述显示面板的所述过孔31的实际孔径与所述过孔31的设计直径近似相等，因此，采用本实施例所提供的所述过孔31设计，有利于实现微型薄膜晶体管20A的制作。
需要说明的是，上述所述现有显示面板中的所述过孔26，指的是附图1中，所述现有显示面板内设有穿过所述层间绝缘层24和所述栅极绝缘层22的第一过孔26A和第二过孔26B。
在本实施例中，在垂直于所述基底10的方向上，所述第一开口311的宽度D 1范围为0.2微米～3.1微米，所述第二开口312的宽度D 2范围为0.1微米～3微米，本实施例对此不做具体限制，其中，所述第一开口311的形状和所述第二开口312的形状均为圆形、椭圆形以及矩形中的一种，进一步地，本实施例以所述第一开口311的形状为圆形、所述第二开口312的形状为圆形为例对本申请的技术方案进行举例说明。
本实施例中以所述过孔31的孔深为2000纳米对本申请的技术方案进行举例说明；由表一可知，本实施例所提供的显示面板与现有显示面板相比，在相同的孔深条件下，所述过孔31的深宽比与所述过孔31的锥度角的大小正相关。
承上，在本实施例中，所述绝缘层30的厚度大于所述缓冲层13的厚度的两倍，优选地，所述绝缘层30的厚度范围为600纳米～5000纳米，本实施例通过设置所述过孔31的侧壁与所述绝缘层30底面的夹角α大于或等于85度，且小于或等于90度，所述显示面板 的所述过孔31的实际孔径与所述过孔31的设计直径近似相等，因此，采用本实施例所提供的所述过孔31设计，有利于提供一种具有高深宽比的所述过孔的显示面板。
进一步地，在本实施例中，所述显示面板还包括设置于所述过孔31内的导电填充部23，所述第一金属层40通过所述导电填充部23与所述半导体层21连接；具体地，所述导电填充部23选用与所述半导体层21具有良好接触、且电阻率较低的导电材料；优选地，所述导电填充部23的电阻率小于5.48×10 -6Ω·m，所述导电填充部23的材料包括但不限于钼(Mo)、钛(Ti)、氮化钛(TiN X)和钨(W)中的至少一种或其合金。
可以理解的是，本实施例通过设置所述导电填充部23设置于所述过孔31内，所述第一金属层40通过所述导电填充部23与所述半导体层21连接，从而避免由于所述过孔31的孔深太大，所述第一金属层40直接穿过所述过孔31与所述半导体层21连接时，所述第一金属层40会存在断裂的风险；进一步地，在本实施例中，所述第一金属层40在所述衬底11上的正投影覆盖所述导电填充部23在所述衬底11上的正投影，从而增大所述第一金属层40与所述导电填充部23的接触面积，降低其接触电阻，提高了信号传输的稳定性。
所述显示面板还包括位于所述绝缘层30远离所述基底10一侧的间隔层50，所述间隔层50的厚度范围为500纳米～2000纳米，所述间隔层50的材料为无机材料，所述无机材料包括但不限于单层氮化硅(SiN X)、单层氧化硅(SiO X)、单层氮氧化硅(SiON)中的一种或是以上膜层的双层结构，本实施例对此不做具体限制，可以理解的是，本实施例通过设置所述间隔层50的材料为无机材料，相比于有机材料，性能更加稳定，绝缘性更好，延长使用寿命。
其中，所述间隔层50包括贯穿所述间隔层50的至少一开槽51，所述开槽51与所述过孔31连通设置；其中，所述第一金属层40设置于所述开槽51内，所述开槽51的侧壁与所述间隔层50底面的夹角θ大于或等于85度，且小于或等于90度，需要说明的是，所述间隔层50底面为所述间隔层50靠近所述基底10的一侧；优选地，在垂直于所述基底10的方向上，所述过孔31的开槽51的截面呈直线型。
进一步地，在本实施例中，所述开槽51的深度H 1与所述开槽51的宽度D 3比值大于等于0.2，且小于等于1；优选地，所述开槽51的深度H 1范围为500纳米～2000纳米，所述开槽51的宽度D 3范围为200纳米～2600纳米，本实施例对此不做具体限制。
在本实施例中，所述显示面板还包括第二金属层22；所述薄膜晶体管层20包括呈矩阵式排布的多个薄膜晶体管20A，所述第一金属层40包括所述薄膜晶体管20A的源极40A和漏极40B，所述半导体层21包括所述薄膜晶体管20A的有源层21A，所述第二金属层22包括所述薄膜晶体管20A的栅极22A；所述绝缘层30包括多个所述过孔31，多个所述过孔31包括位于所述有源层21A上方的第一过孔31A和第二过孔31B，所述导电填充部23包括设置于所述第一过孔31A内的第一填充部23A、及设置于所述第二过孔31B内的第二填充部23B，所述漏极40B通过所述第一填充部23A与所述有源层21A连接，所述源极 40A通过所述第二填充部23B与所述有源层21A连接。
其中，所述第一过孔31A的侧壁与所述栅极绝缘层32底面的夹角α 1大于或等于85度，且小于或等于90度，所述第二过孔31B的侧壁与所述栅极绝缘层32底面的夹角α 2大于或等于85度，且小于或等于90度。
可以理解的是，本实施例以所述半导体层21位于所述栅极22A和所述基底10之间，所述绝缘层30包括设置于所述半导体层21和所述栅极22A之间的栅极绝缘层32、及设置于所述栅极绝缘层32远离所述栅极22A一侧的层间绝缘层33为例对本申请的技术方案进行举例说明；其中，所述层间绝缘层33的厚度H 2大于所述缓冲层13的厚度H 3的两倍。
在本实施例中，所述第一过孔31A和所述第二过孔31B均穿过所述层间绝缘层33和所述栅极绝缘层32；所述间隔层50包括多个所述开槽51，多个所述开槽51包括与所述第一过孔31A连通的第一开槽51A、及与所述第二过孔31B连通的第二开槽51B，其中，所述漏极40B设置于所述第一开槽51A内，所述源极40A设置于所述第二开槽51B内，所述漏极40B在所述衬底11上的正投影覆盖所述第一填充部23A在所述衬底11上的正投影，所述源极40A在所述衬底11上的正投影覆盖所述第二填充部23B在所述衬底11上的正投影，从而增大了所述漏极40B与所述第一填充部23A的接触面积、及增大了所述源极40A与所述第二填充部23B的接触面积，降低其接触电阻，提高了信号传输的稳定性。
可以理解的是，本实施例通过设置所述第一填充部23A位于所述第一过孔31A内，所述第二填充部23B位于所述第二过孔31B内，所述漏极40B设置于所述第一开槽51A内并通过所述第一过孔31A及所述第一填充部23A与所述有源层21A连接，从而避免由于所述第一过孔31A的深度太大，所述漏极40B直接穿过所述第一过孔31A与所述有源层21A连接时，存在断裂的风险；所述源极40A设置于所述第二开槽51B内并通过所述第二过孔31B及所述第二填充部23B与所述有源层21A连接，从而避免由于所述第二过孔31B的深度太大，所述源极40A直接穿过所述第二过孔31B与所述有源层21A连接时，存在断裂的风险。
进一步地，在本实施例中，所述第一开槽51A的侧壁与所述间隔层50底面的夹角θ 1大于或等于85度，且小于或等于90度，所述第一开槽51A的深度H 4与所述第一开槽51A的宽度D 4比值大于等于0.2，且小于等于1；所述第二开槽51B的侧壁与所述间隔层50底面的夹角θ 2大于或等于85度，且小于或等于90度，所述第二开槽51B的深度H 5与所述第二开槽51B的宽度D 5比值大于等于0.2，且小于等于1。
请结合图3、图6和表二；其中，图3为现有显示面板的漏极的截面示意图；表二为本申请实施例所提供的显示面板中源极的设计宽度和实际宽度、及现有显示面板中漏极的设计宽度和实际宽度的数据表。
Figure PCTCN2022115931-appb-000002
表二
可以理解的是，在现有显示面板中，所述漏极25B位于所述层间绝缘层24远离所述栅极绝缘层22的一侧，由于曝光设备和刻蚀工艺的限制，所述漏极25B的锥度角γ通常小于70度，因此，随着设计宽度的减小，所述现有显示面板中的所述漏极25B的实际宽度大于所述漏极25B的设计宽度，导致位于所述漏极25B的面积变大，进而导致所述薄膜晶体管20A的尺寸较大；而在本实施例中，通过设置所述第一开槽51A的侧壁与所述间隔层50底面的夹角θ 1大于或等于85度，且小于或等于90度，所述漏极40B设置于所述第一开槽51A内，所述漏极40B的实际宽度可以通过设计所述第一开槽51A的宽度而进行控制，从而使所述显示面板的所述漏极40B的实际宽度与所述漏极40B的设计宽度近似相等，因此，采用本实施例所提供的所述开槽设计，有利于实现微型薄膜晶体管的制作。
需要说明的是，上述所述漏极25B、所述层间绝缘层24、所述栅极绝缘层22以及所述漏极25B的锥度角γ指的是附图1中，所述现有显示面板的漏极、层间绝缘层、栅极绝缘层以及漏极的锥度角。
本实施例中以所述漏极40B的厚度为1500纳米对本申请的技术方案进行举例说明；由表二可知，本实施例所提供的显示面板与现有显示面板相比，在相同的漏极40B厚度条件下，所述漏极40B的深宽比与所述漏极40B的锥度角的大小正相关。
承上，本实施例通过设置所述第一开槽51A的侧壁与所述间隔层50底面的夹角θ 1大于或等于85度，且小于或等于90度，所述第一开槽51A的深度H 4与所述第一开槽51A的宽度D 4比值大于等于0.2，且小于等于1，从而使所述显示面板的所述漏极40B的实际宽度与所述漏极40B的设计宽度近似相等。
需要说明的是，本实施例仅以所述显示面板中的所述漏极40B和所述现有显示面板中的所述漏极25B为例，对本申请设计和现有技术的设计进行比较，本实施例对所述开槽51的数量、大小以及位置，所述第二金属层22包括的膜层数量、种类以及位置均不做具体限 制。
由上述实施例可知，在本实施例中，通过对所述开槽51的宽度进行设计，可以控制位于所述开槽51内的所述第一金属层40的锥度角大小，从而减小所述第一金属层40的面积大小，因此，采用本实施例所提供的所述开槽设计，有利于提供一种具有高深宽比的所述金属层的显示面板。
在本实施例中，所述显示面板还包括层叠设置于所述间隔层50上的平坦层60、第一电极层70、钝化层80以及第二电极层90；所述显示面板内设置有贯穿所述平坦层60和所述钝化层80的第一连接过孔81A，所述第一连接过孔81A与所述第一开槽51A连通；所述第二电极层90包括穿过所述第一连接过孔81A与所述漏极40B连接的第一电极91；其中，所述第一连接过孔81A的侧壁与所述平坦层60底面的夹角ω 1大于或等于85度，且小于或等于90度；可以理解的是，本申请实施例通过设置所述第一连接过孔81A的侧壁与所述平坦层60底面的夹角ω 1大于或等于85度，且小于或等于90度，从而减小所述第一连接过孔81A的在所述钝化层80上所占据的面积，进而提升所述显示面板的开口率，进而满足高PPI显示设备的需求。
进一步地，在本实施例中，所述第一电极91覆盖所述第一连接过孔81A的侧壁、及所述第一连接过孔81A的底部，本实施例对所述第一连接过孔81A的深度、及所述第一电极91的厚度均不做具体限制。
具体地，所述显示面板内设置有贯穿所述平坦层60和所述钝化层80的第二连接过孔81B、及贯穿所述钝化层80的第三连接过孔81C；多个所述开槽51包括与所述第二连接过孔81B连通的第三开槽51C，所述第二连接过孔81B与所述第三开槽51C连通，所述第一金属层40包括设置于所述第三开槽51C内的第一信号线40C，所述第一电极层70包括触控电极72，所述第二电极层90包括桥接段92，所述桥接段92一端穿过所述第二连接过孔81B与所述第一信号线40C连接，所述桥接段92另一端穿过所述第三连接过孔81C与所述触控电极72连接；其中，所述第二连接过孔81B的侧壁与所述平坦层60底面的夹角ω 2大于或等于85度，且小于或等于90度，从而减小所述第二连接过孔81B的在所述钝化层80上所占据的面积，进而提升所述显示面板的开口率；所述第三连接过孔81C的侧壁与所述钝化层80底面的夹角ω 3大于或等于85度，且小于或等于90度，从而减小所述第三连接过孔81C的在所述钝化层80上所占据的面积，进而提升所述显示面板的开口率，满足高PPI显示设备的需求。
在本实施例中，所述第一连接过孔81A、所述第二连接过孔81B以及所述第三连接过孔81C均包括相对设置的两个开口(图中未标记)，其中，一所述开口靠近所述基底10一侧设置，另一所述开口远离所述基底10一侧设置，远离所述基底10一侧的所述开口的宽度与靠近所述基底10一侧的所述开口的宽度的比值大于或等于0.9，且小于或等于1.1，从而使所述显示面板的所述第一连接过孔81A的实际孔径与所述第一连接过孔81A的设计直 径近似相等、使所述显示面板的所述第二连接过孔81B的实际孔径与所述第二连接过孔81B的设计直径近似相等、及使所述显示面板的所述第三连接过孔81C的实际孔径与所述第三连接过孔81C的设计直径近似相等，因此，采用本实施例所提供的连接过孔31设计，有利于实现所述第一连接过孔81A、所述第二连接过孔81B以及所述第三连接过孔81C具有高深宽比。
需要说明的是，在本实施例中，所述第一电极层70包括间隔设置的公共电极71和所述触控电极72，所述第二电极层90包括间隔设置的像素电极和所述桥接段92，所述像素电极穿过所述第一连接过孔81A与位于所述第一开槽51A内的所述漏极40B连接，所述第一信号线40C为触控信号线，所述触控电极72通过所述第三连接过孔81C、所述桥接段92以及所述第二连接过孔81B与所述触控信号线实现桥接。
承上，将所述第一信号线40C设置于所述第三开槽51C内，通过对所述第三开槽51C的宽度进行设计，可以控制位于所述第三开槽51C内的所述第一信号线40C的锥度角大小，从而减小所述第一信号线40C的面积大小，从而减轻所述显示面板中的布线压力，推动所述显示面板向更高PPI的发展。
在本实施例中，所述第二金属层22还包括与所述栅极22A间隔设置的第二信号线22B，所述第一金属层40包括与所述第二信号线22B相对设置的第三信号线40C，所述薄膜晶体管层20包括位于所述第二信号线22B上方的第三过孔33A，所述导电填充部23包括设置于所述第三过孔33A内的第三填充部23C，多个所述开槽51包括与所述第三过孔33A连通的第四开槽51D；其中，所述第三信号线40C设置于所述第四开槽51D内并通过所述第三填充部23C与所述第二信号线22B连接；所述第三过孔33A的侧壁与所述绝缘层30底面的夹角α 3大于或等于85度，且小于或等于90度；所述第四开槽51D的侧壁与所述间隔层50底面的夹角θ 3大于或等于85度，且小于或等于90度；进一步地，在本实施例中，所述第三过孔33A穿过所述层间绝缘层33，所述栅极绝缘层32包括与所述第三过孔33A连通的第一凹槽32A，所述第二信号线22B设置于所述第一凹槽32A内。
可以理解的是，在本实施例中通过设置所述第三过孔33A的侧壁与所述绝缘层30底面的夹角α 3大于或等于85度，且小于或等于90度，进一步地，所述第三过孔33A包括远离所述基底10一侧的第三开口(图中未标记)和靠近所述基底10一侧的第四开口(图中未标记)，所述第三开口的宽度与所述第四开口的宽度的比值大于或等于0.9，且小于或等于1.1，从而使所述显示面板的所述第三过孔33A的实际孔径与所述第三过孔33A的设计直径近似相等，因此，采用本实施例所提供的所述第三过孔33A设计，有利于提供一种具有高深宽比的所述过孔的显示面板。
并且，本实施例通过设置所述第三信号线40C设置于所述第四开槽51D内，所述第四开槽51D的侧壁与所述间隔层50底面的夹角θ 3大于或等于85度，且小于或等于90度，因此，可以通过对所述第四开槽51D的宽度进行设计，控制位于所述第四开槽51D内的所 述第三信号线40C的锥度角大小，从而减小所述第三信号线40C的面积大小，从而减轻所述显示面板中的布线压力，推动所述显示面板向更高PPI的发展。
承上，在本实施例中，所述第二信号线22B包括但不限于扫描线，所述第三信号线40C包括但不限于数据线，所述第三信号线40C包括第一信号子线(图中未标记)和第二信号子线(图中未标记)，所述第一信号子线的延伸方向和所述第二信号子线的延伸方向不同，所述第一信号子线设置于所述第三开槽51C内，并在所述第三开槽51C内断开，断开的所述第一信号子线通过所述第三过孔33A与所述第二信号线22B的两端以桥接的形式电连接，从而避免同层设置的所述第一信号子线与所述第二信号子线连接，造成线路短路。
需要说明的是，在本实施例中，所述栅极绝缘层32还包括第二凹槽(图中未标记)，所述栅极22A设置于所述第二凹槽内，从而对所述栅极22A起到阻隔水氧以及绝缘的作用；所述基底10还包括层叠设置于所述衬底11和所述缓冲层13之间的遮光层12，所述遮光层12在所述基底10上的正投影覆盖所述有源层21A在所述基底10上的正投影，所述遮光层12可以对射向所述有源层21A的光进行遮挡，从而减少因光照射所述有源层21A产生的光生载流子导致的漏电流增加，进而保持所述显示面板工作时的稳定性。
在另一实施例中，请参阅图8，为本申请实施例所提供的显示面板的第二种截面示意图。
在本实施例中，所述显示面板的结构与上述实施例一所提供的显示面板结构相似/相同，具体请参照上述实施例中的显示面板的描述，此处不再赘述，两者的区别仅在于：
在本实施例中，所述半导体层21的材料为金属氧化物，所述金属氧化包括但不限于氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)、氧化铟锡锌(Indium Tin Zinc Oxide，ITZO)或铟镓锌钛氧化物(Indium Gallium Zinc Tin Oxide，IGZTO)；优选地，本实施例以所述半导体层21的材料为氧化铟镓锌为例对本申请的技术方案进行举例说明。
在本实施例中，所述栅极22A位于所述半导体层21和所述基底10之间，所述绝缘层30包括设置于所述半导体层21与所述第一金属层40之间的层间绝缘层33，所述半导体层21远离所述层间绝缘层33的一侧设置有栅极绝缘层32；具体地；本实施例以所述绝缘层30包括设置于所述半导体层21与所述第一金属层40之间的层间绝缘层33为例对本申请的技术方案进行举例说明。
在本实施例中，所述第一过孔31A和所述第二过孔31B均穿过所述层间绝缘层33；其中，所述层间绝缘层33的厚度大于所述缓冲层13的厚度的两倍；优选地，所述层间绝缘层33的厚度为600纳米～5000纳米。
进一步地，所述第三过孔33A穿过所述层间绝缘层33和所述栅极绝缘层32，所述缓冲层13包括贯穿所述缓冲层13的第五开槽13A和第六开槽13B，所述第五开槽13A与所述第三过孔33A连通；其中，所述第二信号线22B设置于所述第五开槽13A内，所述栅极22A设置于所述第六开槽13B内，从而对所述栅极22A起到阻隔水氧以及绝缘的作用，所 述第五开槽13A的侧壁与所述缓冲层13底面的夹角大于或等于85度，且小于或等于90度，所述第六开槽13B的侧壁与所述缓冲层13底面的夹角大于或等于85度，且小于或等于90度。
可以理解的是，相对于上述实施例，本实施例通过设置所述第二信号线22B设置于所述第五开槽13A内；所述第五开槽13A的侧壁与所述缓冲层13底面的夹角θ 4大于或等于85度，且小于或等于90度，因此，可以通过对所述第五开槽13A的宽度进行设计，控制位于所述第五开槽13A内的所述第二信号线22B的锥度角大小，从而减小所述第二信号线22B的面积大小，从而进一步减轻所述显示面板中的布线压力，推动所述显示面板向更高PPI的发展。
并且，在本实施例中，所述栅极22A位于所述衬底11和所述有源层21A之间，所述有源层21A在所述基底10上的正投影位于所述栅极22A在所述基底10上的正投影内，从而使所述栅极22A起到上述实施例中所述遮光层12的作用，节省了工程流程，进而降低所述显示面板的制作成本。
在另一实施例中，请参阅图9，为本申请实施例所提供的显示面板的第三种截面示意图。
在本实施例中，所述显示面板的结构与上述实施例所提供的显示面板结构相似/相同，具体请参照上述实施例中的显示面板的描述，此处不再赘述，两者的区别仅在于：
在本实施例中，所述半导体层21为非晶硅半导体层21，所述半导体层21包括对应所述栅极22A设置的沟道区210、及位于所述沟道区210两侧的源极接触区212及漏极接触区211，其中，所述半导体层21位于所述沟道区210的部分包括单晶硅层，所述半导体层21位于所述源极接触区212及漏极接触区211的部分均包括层叠设置于所述基底10上的未掺杂的非晶硅层21B和非晶硅掺杂层21C，且所述沟道区210的单晶硅层与所述源极接触区212和漏极接触区211的非晶硅掺杂层相连21C。
其中，在所述漏极接触区211内，所述漏极40B设置于所述第一开槽51A内并通过所述第一过孔31A及所述第一填充部23A与所述非晶硅掺杂层连接，在所述源极接触区212内，所述源极40A设置于所述第二开槽51B内并通过所述第二过孔31B及所述第二填充部23B与所述非晶硅掺杂层21C连接。
本申请实施例还提供一种显示面板的制作方法，请结合图4、图10及图11A至图11N；其中，图10为本申请实施例所提供显示面板的制作方法的流程图；图11A至图11N为图10中显示面板制作的结构工艺流程图。
在本实施例中，所述显示面板的制作方法包括以下步骤：
步骤S100：提供一基底10，包括提供一衬底11，以及依次形成于所述衬底11上的遮光层12和缓冲层13，如图11A所示。
其中，当所述衬底11为刚性衬底时，材料可以是金属或玻璃，当所述衬底11为柔性 衬底时，材料可以包括丙烯酸树脂、甲基丙烯酸树脂、聚异戊二烯、乙烯基树脂、环氧基树脂、聚氨酯基树脂、纤维素树脂、硅氧烷树脂、聚酰亚胺基树脂、聚酰胺基树脂中的至少一种。
所述遮光层12的材料包括但不限于金属材料，所金属材料包括但不限于钼(Mo)、钛(Ti)、镍(Ni)其中的一种或多种合金；所述缓冲层13的材料包括但不限于单层氮化硅(Si 3N 4)、单层二氧化硅(SiO 2),单层氮氧化硅(SiON x)，或是以上膜层的双层结构。
步骤S200：在所述基底10上形成薄膜晶体管层20，所述薄膜晶体管层20包括层叠设置于所述基底10上的半导体层21、绝缘层30和第一金属层40，所述绝缘层30设置于所述基底10和半导体层21上且覆盖所述半导体层21，所述第一金属层40设置于所述绝缘层30上，其中，所述绝缘层30包括至少一过孔31，所述第一金属层40通过所述过孔31与所述半导体层21连接，所述过孔31的侧壁与所述绝缘层30底面的夹角α大于或等于85度，且小于或等于90度。
具体地，在本实施例中，所述步骤S200包括以下步骤：
步骤S201：在所述基底10上依次形成所述半导体层21、栅极绝缘层32、第二金属层22以及层间绝缘层33，其中，所述绝缘层30包括设置于所述半导体层21和所述栅极22A之间的栅极绝缘层32、及设置于所述栅极绝缘层32远离所述栅极22A一侧的层间绝缘层33，所述第二金属层22包括对应所述半导体层21设置的栅极22A，如图11B所示。
具体地，所述半导体层21的材料包括但不限于多晶硅、非晶硅和氧化物中的一种，本实施例以所述半导体层21的材料为多晶硅为例对本申请的技术方案进行举例说明。
所述半导体层21包括位于所述基底10和所述栅极绝缘层32之间的有源层21A，所述有源层21A包括第一导体部和第二导体部、及位于所述第一导体部和所述第二导体部之间的有源段，所述栅极22A对应所述有源段设置。
所述栅极绝缘层32的材料包括但不限于氧化硅(SiO X)、氮化硅(SiN X)、氮氧化硅(SiNO)等或其层叠，所述栅极绝缘层32包括第二凹槽，所述栅极22A线设置于所述第二凹槽内；所述层间绝缘层33具有强水氧阻隔能力和绝缘能力，其材料包括但不限于氧化硅(SiO X)、氮化硅(SiN X)、氮氧化硅(SiNO)等或其层叠，所述层间绝缘层33的厚度大于所述缓冲层13的厚度的两倍；优选地，所述层间绝缘层33的厚度为600纳米～5000纳米。
步骤S202：在所述层间绝缘层33上依次形成第一保护层101和光阻材料103，如图11C所示；其中，所述第一保护层101的材料为有机材料，所述第一保护层101在所述基底10上的正投影覆盖所述层间绝缘层33在所述基底10上的正投影。
步骤S203：采用第一道掩膜板对所述光阻材料103进行曝光和显影，形成位于所述第一保护层101上方的第一光阻层1031，所述第一光阻层1031包括对应所述第一导体段设置的第一通孔1031A、及对应所述第二导体段设置的第二通孔1031B，如图11D所示。
在所述步骤S203中，可以采用具有不同穿透率的掩膜板对所述光阻材料103进行光罩 制程，所述掩膜板包括第一穿透率区域Tr1和第二穿透率区域Tr2，所述第一穿透率区域Tr1对应所述第一通孔1031A和所述第二通孔1031B，所述第一穿透率区域Tr1的透过率为100％，所述第二穿透率区域Tr2对应剩余区域且所述第三穿透率区域不透光。
需要说明的是，在本实施例中，对所述光阻材料103进行曝光的方法包括但不限于采用具有不同穿透率的掩膜板；在本实施例中，采用具有不同穿透率的掩膜板对所述光阻材料103进行光罩制程仅用于举例说明，本实施例对此不做限制。
步骤S204：刻蚀未被所述第一光阻层1031覆盖的所述第一保护层101，在所述第一保护层101上形成对应所述有源层21A设置的第一开孔101A和第二开孔101B，所述第一开孔101A和所述第二开孔101B均穿过所述第一保护层101，如图11E所示。
步骤205：剥离所述第一光阻层1031。
步骤206：利用所述第一保护层101为第二道掩膜板对所述绝缘层30进行蚀刻，形成位于所述有源层21A上方的所述过孔31，其中，所述过孔31包括位于所述有源层21A上方的第一过孔31A和第二过孔31B，所述第一过孔31A与所述第一开孔101A连通设置，所述第二过孔31B与所述第二开孔101B连通设置，所述第一过孔31A和所述第二过孔31B均穿过所述层间绝缘层33和所述栅极绝缘层32。
步骤207：剥离所述一保护层，如图11F所示。
可以理解的是，本实施例通过在所述层间绝缘层33上形成所述第一保护层101，利用所述第一保护层101为掩膜板对所述层间绝缘层33和所述栅极绝缘层32进行蚀刻，形成对应所述第一开孔101A设置的所述第一过孔31A、及对应所述第二开孔101B设置的所述第二过孔31B，其中，所述第一过孔31A的侧壁与所述栅极绝缘层32底面的夹角α 1大于或等于85度，且小于或等于90度，所述第二过孔31B的侧壁与所述栅极绝缘层32底面的夹角α 2大于或等于85度，且小于或等于90度，从而减小所述过孔31的在所述绝缘层30上所占据的面积，进而提升所述显示面板的开口率，满足高PPI显示设备的需求，并且在本实施例中仅通过一道光照制程同时制作所述第一过孔31A和所述第二过孔31B，降低了所述显示面板的制作成本。
进一步地，所述过孔31包括远离所述基底10一侧的第一开口311、及靠近所述基底10一侧的第二开口312，所述第一开口311的宽度D 1与所述第二开口312的宽度D 2的比值大于或等于0.9，且小于或等于1.1，从而使所述显示面板的所述过孔31的实际孔径与所述过孔31的设计直径近似相等，因此，采用本实施例所提供的所述过孔31设计，有利于实现微型薄膜晶体管20A的制作
在本实施例中，所述显示面板的制作方法还包括以下步骤：
步骤S300：在所述层间绝缘层33远离所述基底10的一侧形成导电填充层230，如图11G所示，其中，所述导电填充层230填充所述第一过孔31A和所述第二过孔31B，所述导电填充层230的厚度为500纳米～5000纳米，所述导电填充层230选用与所述半导体层2 1具有良好接触、且电阻率较低的导电材料；优选地，所述导电填充层230的电阻率小于5.48×10 -6Ω·m，所述导电填充层230的材料包括但不限于钼(Mo)、钛(Ti)、氮化钛(TiN X)和钨(W)中的至少一种或其合金，本实施例对此不做具体限制。
步骤S400：对所述导电填充层230图案化处理，形成导电填充部23，所述导电填充部23包括设置于所述第一过孔31A内的第一填充部23A、及设置于所述第二过孔31B内的第二填充部23B，如图11H所示。
步骤S500：在所述层间绝缘层33远离所述基底10的一侧形成间隔层50，如图11I所示，其中，所述间隔层50的厚度范围为500纳米～2000纳米，所述间隔层50的材料为无机材料，所述无机材料包括但不限于单层氮化硅(SiN X)、单层氧化硅(SiO X)、单层氮氧化硅(SiON)中的一种或是以上膜层的双层结构，本实施例对此不做具体限制，可以理解的是，本实施例通过设置所述间隔层50的材料为无机材料，相比于有机材料，性能更加稳定，绝缘性更好，延长使用寿命。
步骤S600：对所述间隔层50图案化处理，形成贯穿所述间隔层50的至少一开槽51，所述开槽51与所述过孔31连通设置，所述开槽51的侧壁与所述间隔层50底面的夹角θ大于或等于85度，且小于或等于90度。
具体地，在本实施例中，所述步骤S600包括以下步骤：
步骤S601：在所述间隔层50上依次形成第二保护层102和光阻材料103，如图11J所示；其中，所述第二保护层102的材料为有机材料，所述第二保护层102在所述基底10上的正投影覆盖所述间隔层50在所述基底10上的正投影。
步骤S602：采用第三道掩膜板对所述光阻材料103进行曝光和显影，形成位于所述第二保护层102上方的第二光阻层1032，所述第二光阻层1032包括对应所述第一过孔31A设置的第三通孔1032A、及对应所述第二过孔31B设置的第四通孔1032B，如图11K所示。
在所述步骤S602中，可以采用具有不同穿透率的掩膜板对所述光阻材料103进行光罩制程，所述掩膜板包括第一穿透率区域Tr1和第二穿透率区域Tr2，所述第一穿透率区域Tr1对应所述第三通孔1032A和所述第四通孔1032B，所述第一穿透率区域Tr1的透过率为100％，所述第二穿透率区域Tr2对应剩余区域且所述第三穿透率区域不透光。
需要说明的是，在本实施例中，对所述光阻材料103进行曝光的方法包括但不限于采用具有不同穿透率的掩膜板；在本实施例中，采用具有不同穿透率的掩膜板对所述光阻材料103进行光罩制程仅用于举例说明，本实施例对此不做限制。
步骤S603：刻蚀未被所述第二光阻层1032覆盖的所述第二保护层102，在所述第二保护层102上形成对应所述第三通孔1032A设置的第三开孔102A、及对应所述第四通孔1032B设置的第四开孔102B，所述第三开孔102A和所述第四开孔102B均穿过所述第二保护层102，如图11L所示。
步骤S604：剥离所述第二光阻层1032。
步骤S605：利用所述第二保护层102为第四道掩膜板对所述间隔层50进行蚀刻，形成贯穿所述间隔层50的所述开槽51，其中，所述开槽51包括与所述第三开孔102A对应设置的第一开槽51A、及与所述第四开孔102B对应设置的第二开槽51B；具体地；所述第一开槽51A与所述第一过孔31A连通，所述第二开槽51B与所述第二过孔31B连通。
步骤S606：剥离所述一保护层，如图11M所示。
可以理解的是，本实施例通过在所述间隔层50上形成所述第二保护层102，利用所述第二保护层102为掩膜板对所述间隔层50进行蚀刻，形成对应所述第三开孔102A设置的第一开槽51A、及对应所述第四开孔102B设置的第二开槽51B，其中，所述第一开槽51A的侧壁与所述间隔层50底面的夹角θ 1大于或等于85度，且小于或等于90度，所述第二开槽51B的侧壁与所述间隔层50底面的夹角θ 2大于或等于85度，且小于或等于90度。
步骤S700：在所述间隔层50上形成所述第一金属层40，对所述第一金属层40图案化处理，形成位于所述第一开槽51A内的漏极40B、及位于所述第二开槽51B内的源极40A，如图11N所示。
可以理解的是，本实施例通过设置所述第一开槽51A的侧壁与所述间隔层50底面的夹角θ 1大于或等于85度，且小于或等于90度，所述漏极40B设置于所述第一开槽51A内，所述漏极40B的实际宽度可以通过设计所述第一开槽51A的宽度而进行控制，从而使所述显示面板的所述漏极40B的实际宽度与所述漏极40B的设计宽度近似相等，通过设置所述第二开槽51B的侧壁与所述间隔层50底面的夹角θ 2大于或等于85度，且小于或等于90度，所述源极40A设置于所述第二开槽51B内，所述源极40A的实际宽度可以通过设计所述第二开槽51B的宽度而进行控制，从而使所述显示面板的所述源极40A的实际宽度与所述漏极40B的设计宽度近似相等，因此，采用本实施例所提供的所述开槽51设计，有利于实现微型薄膜晶体管20A的制作。
步骤S800：在所述间隔层50上依次形成平坦层60、第一电极层70、钝化层80以及第二电极层90，从而形成第一基板100，如图4所示。
可以理解的是，所述平坦层60、所述第一电极层70、所述钝化层80以及所述第二电极层90已经在上述实施例中进行了详细的说明，在此不在重复说明。
步骤S900：制作第二基板，将所述第二基板与所述第一基板对盒，并在所述第一基板和所述第二基板之间注入液晶。
本实施例还提供一种移动终端，所述移动终端包括终端主体和上述任一实施例中所述的显示面板，所述终端主体与所述显示面板组合为一体。
可以理解的是，所述显示面板已经在上述实施例中进行了详细的说明，在此不在重复说明。
在具体应用时，所述移动终端可以为智能手机、平板电脑、笔记本电脑、智能手环、智能手表、智能眼镜、智能头盔、台式机电脑、智能电视或者数码相机等设备的显示屏， 甚至可以应用在具有柔性显示屏的电子设备上。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其中，包括基底和设置于所述基底上的薄膜晶体管层，所述薄膜晶体管层包括层叠设置于所述基底上的半导体层、绝缘层和第一金属层，所述绝缘层设置于所述基底和半导体层上且覆盖所述半导体层，所述第一金属层设置于所述绝缘层上；
    其中，所述绝缘层包括至少一过孔，所述第一金属层通过所述过孔与所述半导体层连接，所述过孔的侧壁与所述绝缘层底面的夹角大于或等于85度，且小于或等于90度。
  2. 根据权利要求1所述的显示面板，其中，所述过孔包括远离所述基底一侧的第一开口和靠近所述基底一侧的第二开口；
    其中，所述第一开口的宽度与所述第二开口的宽度的比值大于或等于0.9，且小于或等于1.1。
  3. 根据权利要求1所述的显示面板，其中，所述基底包括衬底和设置于所述衬底上缓冲层，所述绝缘层的厚度大于所述缓冲层的厚度的两倍。
  4. 根据权利要求1所述的显示面板，其中，所述显示面板还包括设置于所述过孔内的导电填充部，所述第一金属层通过所述导电填充部与所述半导体层连接。
  5. 根据权利要求4所述的显示面板，其中，所述导电填充部的电阻率小于5.48×10 -6Ω·m。
  6. 根据权利要求4所述的显示面板，其中，所述第一金属层在所述衬底上的正投影覆盖所述导电填充部在所述衬底上的正投影。
  7. 根据权利要求1所述的显示面板，其中，所述显示面板还包括位于所述绝缘层远离所述基底一侧的间隔层，所述间隔层包括贯穿所述间隔层的至少一开槽，所述开槽与所述过孔连通设置；
    其中，所述第一金属层设置于所述开槽内，所述开槽的侧壁与所述间隔层底面的夹角大于或等于85度，且小于或等于90度。
  8. 根据权利要求7所述的显示面板，其中，所述开槽的深度与所述开槽的宽度比值大于等于0.2，且小于等于1。
  9. 根据权利要求7所述的显示面板，其中，所述显示面板还包括第二金属层；
    所述薄膜晶体管层包括多个薄膜晶体管，所述第一金属层包括所述薄膜晶体管的源极和漏极，所述半导体层包括所述薄膜晶体管的有源层，所述第二金属层包括所述薄膜晶体管的栅极；
    所述绝缘层包括多个所述过孔，多个所述过孔包括位于所述有源层上方的第一过孔和第二过孔，所述漏极通过所述第一过孔与所述有源层连接，所述源极通过所述第二过孔与所述有源层连接。
  10. 根据权利要求9所述的显示面板，其中，所述显示面板还包括导电填充部，所述导电填充部包括设置于所述第一过孔内的第一填充部、及设置于所述第二过孔内的第二填充部，所述漏极通过所述第一填充部与所述有源层连接，所述源极通过所述第二填充部与 所述有源层连接。
  11. 根据权利要求9所述的显示面板，其中，所述间隔层包括多个所述开槽，多个所述开槽包括与所述第一过孔连通的第一开槽、及与所述第二过孔连通的第二开槽；
    其中，所述漏极设置于所述第一开槽内，所述源极设置于所述第二开槽内。
  12. 根据权利要求11所述的显示面板，其中，所述半导体层位于所述栅极和所述基底之间，所述绝缘层包括设置于所述半导体层和所述栅极之间的栅极绝缘层、及设置于所述栅极绝缘层远离所述栅极一侧的层间绝缘层；
    所述第一过孔和所述第二过孔均穿过所述层间绝缘层和所述栅极绝缘层；
    其中，所述基底包括衬底和设置于所述衬底上缓冲层，所述层间绝缘层的厚度大于所述缓冲层的厚度的两倍。
  13. 根据权利要求11所述的显示面板，其中，所述栅极位于所述半导体层和所述基底之间，所述绝缘层包括设置于所述半导体层与所述第一金属层之间的层间绝缘层，所述半导体层远离所述层间绝缘层的一侧设置有栅极绝缘层；
    所述第一过孔和所述第二过孔均穿过所述层间绝缘层；
    其中，所述基底包括衬底和设置于所述衬底上缓冲层，所述层间绝缘层的厚度大于所述缓冲层的厚度的两倍。
  14. 根据权利要求11所述的显示面板，其中，所述显示面板还包括层叠设置于所述间隔层上的平坦层、第一电极层、钝化层以及第二电极层；
    所述显示面板内设置有贯穿所述平坦层和所述钝化层的第一连接过孔，所述第一连接过孔与所述第一开槽连通；
    所述第二电极层包括穿过所述第一连接过孔与所述漏极连接的第一电极；
    其中，所述第一连接过孔的侧壁与所述平坦层底面的夹角大于或等于85度，且小于或等于90度。
  15. 根据权利要求14所述的显示面板，其中，所述显示面板内设置有贯穿所述平坦层和所述钝化层的第二连接过孔、及贯穿所述钝化层的第三连接过孔；
    多个所述开槽包括与所述第二连接过孔连通的第三开槽，所述第二连接过孔与所述第三开槽连通，所述第一金属层包括设置于所述第三开槽内的第一信号线，所述第一电极层包括触控电极，所述第二电极层包括桥接段，所述桥接段一端穿过所述第二连接过孔与所述第一信号线连接，所述桥接段另一端穿过所述第三连接过孔与所述触控电极连接；
    其中，所述第二连接过孔的侧壁与所述平坦层底面的夹角大于或等于85度，且小于或等于90度，所述第三连接过孔的侧壁与所述钝化层底面的夹角大于或等于85度，且小于或等于90度。
  16. 根据权利要求9所述的显示面板，其中，所述第二金属层还包括与所述栅极间隔设置的第二信号线，所述第一金属层包括与所述第二信号线相对设置的第三信号线，
    所述薄膜晶体管层包括位于所述第二信号线上方的第三过孔，所述导电填充部包括设置于所述第三过孔内的第三填充部，多个所述开槽包括与所述第三过孔连通的第四开槽；
    其中，所述第三信号线设置于所述第四开槽内并通过所述第三填充部与所述第二信号线连接；所述第三过孔的侧壁与所述绝缘层底面的夹角大于或等于85度，且小于或等于90度。
  17. 根据权利要求16所述的显示面板，其中，所述第三过孔包括远离所述基底一侧的第三开口和靠近所述基底一侧的第四开口；
    其中，所述第三开口的宽度与所述第四开口的宽度的比值大于或等于0.9，且小于或等于1.1。
  18. 根据权利要求16所述的显示面板，其中，所述半导体层位于所述栅极和所述基底之间，所述绝缘层包括设置于所述半导体层和所述栅极之间的栅极绝缘层、及设置于所述栅极绝缘层远离所述栅极一侧的层间绝缘层；
    所述第三过孔穿过所述层间绝缘层，所述栅极绝缘层包括与所述第三过孔连通的第一凹槽，所述第二信号线设置于所述第一凹槽内。
  19. 根据权利要求16所述的显示面板，其中，所述栅极位于所述半导体层和所述基底之间，所述绝缘层包括设置于所述半导体层与所述第一金属层之间的层间绝缘层，所述半导体层远离所述层间绝缘层的一侧设置有栅极绝缘层；
    所述第三过孔穿过所述层间绝缘层和所述栅极绝缘层，所述基底包括衬底和设置于所述衬底上缓冲层，所述缓冲层包括贯穿所述缓冲层的第五开槽，
    其中，所述第二信号线设置于所述第五开槽内，所述第五开槽的侧壁与所述缓冲层底面的夹角大于或等于85度，且小于或等于90度。
  20. 一种移动终端，其中，所述移动终端包括终端主体和如权利要求1中所述的显示面板，所述终端主体与所述显示面板组合为一体。
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