JP6359650B2 - アレイ基板、表示装置及びアレイ基板の製作方法 - Google Patents
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- 239000000758 substrate Substances 0.000 title claims description 100
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000010410 layer Substances 0.000 claims description 165
- 239000011241 protective layer Substances 0.000 claims description 76
- 239000010409 thin film Substances 0.000 claims description 40
- 238000000034 method Methods 0.000 claims description 29
- 238000000059 patterning Methods 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 18
- 230000005669 field effect Effects 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 16
- 238000002161 passivation Methods 0.000 claims description 14
- 229910005265 GaInZnO Inorganic materials 0.000 claims description 8
- 229910007717 ZnSnO Inorganic materials 0.000 claims description 8
- 238000005530 etching Methods 0.000 description 9
- 239000007769 metal material Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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Description
基板を提供し、基板上に薄膜電界効果トランジスターのゲート電極を形成し、ゲート電極が位置している第1金属層上にゲート絶縁層を形成するステップと、
提供された基板上に保護層の薄膜を形成し、パターニング工程によって前記保護層を含むパターンを形成するステップと、
前記保護層が形成された基板上に第2金属層の薄膜を形成し、パターニング工程によって前記保護層に直接接触するデータラインを含むパターンを形成するステップと、を含み、
前記薄膜電界効果トランジスターの活性層と前記保護層とが同一層に設けられ、且つ同じ材料で形成され、前記薄膜電界効果トランジスターのソース電極、ドレイン電極、および前記データラインが同一層に設けられ同期に完成される。
前記画素電極が形成された基板上にパッシベーション層を形成し、
前記パッシベーション層が形成された基板上に第2導電薄膜を形成し、パターニング工程によって共通電極を含むパターンを形成する。
基板を提供し、基板上に薄膜電界効果トランジスターのゲート電極を形成し、ゲート電極が位置する第1金属層の上にゲート絶縁層を形成するステップS101と、
提供された基板上に保護層の薄膜を形成し、パターニング工程によって保護層を含むパターンを形成するステップS102と、
保護層が形成された基板上に第2金属層の薄膜を形成し、パターニング工程によって保護層と直接接触するデータラインを含むパターンを形成するステップS103と、を含む。
ステップ1:基板を提供し、基板上に第1金属層の薄膜を蒸着し、1回のパターニング工程によってゲート電極およびゲートラインを含むパターンを形成する。
ステップ2:ステップ1を完了した基板上にゲート絶縁層を形成する。
ステップ3:ステップ2を完了した基板上に活性層および保護層を含む薄膜を形成し、パターニング工程によって活性層および保護層を含むパターンを形成する。
ステップ4:ステップ3を完了した基板上にストッパ層を形成する。
ステップ5:ステップ4を完了した基板上に第2金属層の薄膜を形成し、1回のパターニング工程によってソース電極、ドレイン電極、およびデータラインを含むパターンを形成する。
ステップ6:ステップ5を完了した基板上に画素電極層の薄膜を形成し、1回のパターニング工程によってドレイン電極と電気的に接続する画素電極を形成する。
ステップ7:ステップ6を完了した基板上にパッシベーション層を形成する。
ステップ8:ステップ7を完了した基板上に透明導電層の薄膜を形成し、1回のパターニング工程によって共通電極のパターンを形成する。
102 ゲート電極
103 ゲートライン
104 ゲート絶縁層
105 活性層
106 ストッパ層
107 データライン
1081 ドレイン電極
1082 ソース電極
109 画素電極
110 パッシベーション層
111 共通電極
112 保護層
Claims (15)
- 基板と、基板上に形成されている薄膜電界効果トランジスターおよびデータラインとを備え、前記薄膜トランジスターが、ゲート電極、活性層、ソース電極およびドレイン電極を備え、前記ゲート電極と前記活性層との間にゲート絶縁層が形成され、
アレイ基板が、前記ゲート絶縁層と前記データラインとの間に形成され、且つ、前記データラインと直接接触する保護層をさらに備え、前記保護層と前記活性層とが、同じ材料で同一層に設けられ、
前記データラインが前記保護層を越えて延在し、前記データラインの一部が前記ゲート絶縁層と直接接触することを特徴とするアレイ基板。 - 前記保護層の材料が、ZnO、InZnO、ZnSnO、GaInZnO、又はZrInZnOであることを特徴とする請求項1に記載のアレイ基板。
- 前記保護層の厚さが、200Å〜2000Åであることを特徴とする請求項1又は2に記載のアレイ基板。
- 前記薄膜電界効果トランジスターが、ボトムゲート型の薄膜電界効果トランジスターであることを特徴とする請求項1から3のいずれかの1項に記載のアレイ基板。
- 前記活性層上、および前記保護層以外のゲート絶縁層上に形成されているストッパ層をさらに備えることを特徴とする請求項1から4のいずれかの1項に記載のアレイ基板。
- 画素電極と、共通電極と、前記画素電極と前記共通電極との間に形成されるパッシベーション層と、をさらに備え、前記画素電極が前記ストッパ層上に形成され、前記ドレイン電極と電気的に接続されることを特徴とする請求項5に記載のアレイ基板。
- 前記活性層上に形成され、且つ、前記ソース電極と前記ドレイン電極との間の領域に位置するストッパ層をさらに備えることを特徴とする請求項1から4のいずれかの1項に記載のアレイ基板。
- 画素電極と、共通電極と、前記画素電極と前記共通電極との間に形成されるパッシベーション層と、をさらに備え、前記画素電極が前記ゲート絶縁層上に形成されることを特徴とする請求項7に記載のアレイ基板。
- 前記ゲート電極と同一層に設けられ、且つ、同期に形成されたゲートラインをさらに備え、前記保護層が少なくとも前記データラインと前記ゲートラインとが互いに交差する箇所に設けられることを特徴とする請求項1から8のいずれかの1項に記載のアレイ基板。
- 前記保護層の位置が前記データラインの位置に対応することを特徴とする請求項9に記載のアレイ基板。
- 請求項1から10のいずれかの1項に記載のアレイ基板を備えることを特徴とする表示装置。
- 基板を提供し、基板上に薄膜電界効果トランジスターのゲート電極を形成し、ゲート電極が位置している第1金属層上にゲート絶縁層を形成するステップと、
基板上に保護層の薄膜を形成し、パターニング工程によって前記保護層を含むパターンを形成するステップと、
前記保護層が形成された基板上に第2金属層の薄膜を形成し、パターニング工程によって前記保護層と直接接触するデータラインを含むパターンを形成するステップと、を含み、 前記薄膜電界効果トランジスターにおける活性層と前記保護層とが同じ材料で同一層に設けられ、前記薄膜電界効果トランジスターのソース電極、ドレイン電極、および前記データラインが同一層に設けられ、且つ、同期に完成され、
前記データラインが前記保護層を越えて延在し、前記データラインの一部が前記ゲート絶縁層と直接接触することを特徴とするアレイ基板の製作方法。 - 前記保護層が形成された基板上に、前記第2金属層の薄膜を形成する前にストッパ層の薄膜を形成し、パターニング工程によって前記ストッパ層を含むパターンを形成することを特徴とする請求項12に記載のアレイ基板の製作方法。
- 前記ストッパ層が形成された基板上に第1導電薄膜を形成し、パターニング工程によって前記ドレイン電極と電気的に接続される画素電極を含むパターンを形成し、
前記画素電極が形成された基板上にパッシベーション層を形成し、
前記パッシベーション層が形成された基板上に第2導電薄膜を形成し、パターニング工程によって共通電極を含むパターンを形成することを特徴とする請求項13に記載のアレイ基板の製作方法。 - アレイ基板におけるゲートラインと前記ゲート電極とが、同一層に設けられ、且つ同期に形成され、前記保護層が少なくとも前記データラインと前記ゲートラインとが互いに交差する箇所に設けられることを特徴とする請求項12から14のいずれかの1項に記載のアレイ基板の製作方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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CN201310282242.X | 2013-07-05 | ||
CN201310282242.XA CN103337479B (zh) | 2013-07-05 | 2013-07-05 | 一种阵列基板、显示装置及阵列基板的制作方法 |
PCT/CN2013/088420 WO2015000256A1 (zh) | 2013-07-05 | 2013-12-03 | 阵列基板、显示装置及阵列基板的制作方法 |
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JP2016525223A JP2016525223A (ja) | 2016-08-22 |
JP6359650B2 true JP6359650B2 (ja) | 2018-07-18 |
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EP (1) | EP3018704B1 (ja) |
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KR (1) | KR101668166B1 (ja) |
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CN103337479B (zh) * | 2013-07-05 | 2016-03-30 | 合肥京东方光电科技有限公司 | 一种阵列基板、显示装置及阵列基板的制作方法 |
TWI537656B (zh) | 2014-03-14 | 2016-06-11 | 群創光電股份有限公司 | 顯示裝置 |
US10324345B2 (en) | 2014-03-14 | 2019-06-18 | Innolux Corporation | Display device and display substrate |
CN105957812B (zh) * | 2016-06-06 | 2019-02-22 | 京东方科技集团股份有限公司 | 场效应晶体管及其制造方法、阵列基板及其制造方法以及显示面板 |
CN106057828A (zh) * | 2016-08-12 | 2016-10-26 | 京东方科技集团股份有限公司 | 一种基板及其制备方法、显示面板 |
CN106409844A (zh) * | 2016-11-29 | 2017-02-15 | 深圳市华星光电技术有限公司 | 底栅型多晶硅tft基板及其制作方法 |
CN109216373B (zh) * | 2017-07-07 | 2021-04-09 | 京东方科技集团股份有限公司 | 阵列基板及其制备方法 |
CN111430380A (zh) * | 2020-04-14 | 2020-07-17 | Tcl华星光电技术有限公司 | 显示面板及其制作方法 |
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---|---|---|---|---|
JPH0496022A (ja) * | 1990-08-13 | 1992-03-27 | Hitachi Ltd | アクティブマトリクス基板とその製造方法並びにこれを用いた液晶表示素子 |
KR100679518B1 (ko) * | 2000-07-13 | 2007-02-07 | 엘지.필립스 엘시디 주식회사 | 액정표장치용 어레이기판과 그 제조방법 |
JP2002108245A (ja) * | 2000-09-27 | 2002-04-10 | Toshiba Corp | マトリクスアレイ基板 |
KR100558716B1 (ko) * | 2003-10-14 | 2006-03-10 | 엘지.필립스 엘시디 주식회사 | 액정표시패널 및 그 제조 방법 |
US7220611B2 (en) * | 2003-10-14 | 2007-05-22 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display panel and fabricating method thereof |
US8098351B2 (en) * | 2007-11-20 | 2012-01-17 | Newport Fab, Llc | Self-planarized passivation dielectric for liquid crystal on silicon structure and related method |
KR101346921B1 (ko) * | 2008-02-19 | 2014-01-02 | 엘지디스플레이 주식회사 | 평판 표시 장치 및 그 제조방법 |
KR101479140B1 (ko) * | 2008-03-13 | 2015-01-08 | 삼성디스플레이 주식회사 | 표시 장치 및 이의 제조 방법 |
JP5375058B2 (ja) * | 2008-12-08 | 2013-12-25 | 凸版印刷株式会社 | 薄膜トランジスタアレイ及びその製造方法 |
CN101852953B (zh) * | 2009-03-30 | 2013-05-22 | 北京京东方光电科技有限公司 | Tft-lcd阵列基板及其制造方法和液晶显示面板 |
WO2010130099A1 (en) * | 2009-05-15 | 2010-11-18 | Abb Technology Ltd. | Lock device for restricting rotational movement |
US8957468B2 (en) * | 2010-11-05 | 2015-02-17 | Semiconductor Energy Laboratory Co., Ltd. | Variable capacitor and liquid crystal display device |
KR20120060664A (ko) * | 2010-12-02 | 2012-06-12 | 삼성전자주식회사 | 표시 장치 및 표시 장치 제조 방법 |
TWI544525B (zh) * | 2011-01-21 | 2016-08-01 | 半導體能源研究所股份有限公司 | 半導體裝置及其製造方法 |
JP2012204398A (ja) * | 2011-03-23 | 2012-10-22 | Toppan Printing Co Ltd | 薄膜トランジスタとその製造方法、および当該薄膜トランジスタを用いた画像表示装置 |
CN102969361B (zh) * | 2011-09-01 | 2015-09-23 | 中国科学院微电子研究所 | 光照稳定性非晶态金属氧化物tft器件以及显示器件 |
CN102709235B (zh) * | 2011-10-26 | 2015-04-29 | 京东方科技集团股份有限公司 | 阵列基板及其制造方法、显示装置 |
CN102636927B (zh) * | 2011-12-23 | 2015-07-29 | 京东方科技集团股份有限公司 | 阵列基板及其制造方法 |
CN203365871U (zh) * | 2013-07-05 | 2013-12-25 | 合肥京东方光电科技有限公司 | 一种阵列基板和显示装置 |
CN103337479B (zh) * | 2013-07-05 | 2016-03-30 | 合肥京东方光电科技有限公司 | 一种阵列基板、显示装置及阵列基板的制作方法 |
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WO2015000256A1 (zh) | 2015-01-08 |
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CN103337479A (zh) | 2013-10-02 |
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US20150021612A1 (en) | 2015-01-22 |
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