WO2016086531A1 - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

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Publication number
WO2016086531A1
WO2016086531A1 PCT/CN2015/072469 CN2015072469W WO2016086531A1 WO 2016086531 A1 WO2016086531 A1 WO 2016086531A1 CN 2015072469 W CN2015072469 W CN 2015072469W WO 2016086531 A1 WO2016086531 A1 WO 2016086531A1
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Prior art keywords
layer
array substrate
passivation protective
tft
color resist
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PCT/CN2015/072469
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English (en)
French (fr)
Inventor
宋利旺
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深圳市华星光电技术有限公司
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Priority to US14/424,007 priority Critical patent/US9804459B2/en
Publication of WO2016086531A1 publication Critical patent/WO2016086531A1/zh

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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133302—Rigid substrates, e.g. inorganic substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/103—Materials and properties semiconductor a-Si
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a method of fabricating the same.
  • Liquid crystal display has many advantages such as thin body, power saving, no radiation, etc., and is widely used, such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptops. Screen, etc.
  • Most of the liquid crystal display devices on the market are backlight type liquid crystal display devices, which include a backlight module and a liquid crystal panel coupled to the backlight module.
  • BM Black Matrix
  • BM On Array the black matrix is attached to the array substrate
  • the black matrix 200 and the color resist layer 300 are usually formed in the same layer in order to use the spraying technique, so that the color resist layer 300 undergoes TFT preparation.
  • the high temperature process of PVD (physical vapor deposition) and CVD (chemical vapor deposition) has a serious influence on the performance of the color resist layer 300.
  • the high temperature process causes the color resist layer 300 to volatilize to generate gas, which becomes a source of bubbles. Reduce product yield.
  • An object of the present invention is to provide an array substrate by disposing a black matrix and a color resist layer on an array substrate and disposing a color resist layer on the TFT layer, thereby avoiding a high temperature process to the color resist layer during TFT fabrication. The adverse effect is caused, so that the liquid crystal panel has a high display quality.
  • Another object of the present invention is to provide a method for fabricating an array substrate, firstly forming a black matrix on a substrate, secondly performing a TFT process on a black matrix, and then forming a color resist layer after the TFT is completed, thereby realizing a black matrix and
  • the color resist layers are all fabricated on the array substrate and
  • the color resist layer is formed after the TFT process, which avoids the bad phenomenon such as bubbles caused by the gas generated by the color resistance during the high-temperature process in the TFT preparation process, effectively improves the display quality of the liquid crystal panel, and improves the product yield.
  • the present invention provides an array substrate, comprising a substrate, a black matrix disposed on the substrate, a TFT layer disposed on the black matrix, a color resist layer disposed on the TFT layer, and a first a passivation protective layer and a pixel electrode layer;
  • the TFT layer includes a source/drain provided on the black matrix, a semiconductor layer disposed on the source/drain, a gate insulating layer disposed on the semiconductor layer, and the gate is disposed on the gate a gate on the insulating layer and a first passivation protective layer disposed on the gate.
  • the color resist layer is on the first passivation protective layer
  • the second passivation layer is on the color resist layer
  • the pixel electrode layer is on the second passivation layer
  • the array substrate further includes A via hole penetrating through the second passivation protective layer, the color resist layer, the first passivation protective layer, the gate insulating layer, and the semiconductor layer, and the pixel electrode layer is electrically connected to the source/drain via via holes.
  • the pixel electrode layer includes a first ITO electrode layer and a second ITO electrode layer, the first ITO electrode layer is located on the first passivation protective layer, and the array substrate further includes a first passivation protective layer and a gate. a via hole of the insulating layer and the semiconductor layer, the first ITO electrode layer is in contact with the source/drain via a via, the color resist layer is on the first ITO electrode layer, and the second passivation protection The layer is on the color resist layer, the second ITO electrode layer is on the second passivation protective layer, and the first ITO electrode layer and the second ITO electrode layer are connected to form a pixel electrode layer.
  • the material of the source/drain and the gate is copper or aluminum.
  • the semiconductor layer is a two-layer structure composed of an amorphous silicon layer and a heavily doped N-type silicon layer, and may also be a single-layer structure composed of an indium gallium zinc oxide layer.
  • the invention also provides a method for fabricating an array substrate, comprising the following steps:
  • Step 1 providing a substrate, forming a black matrix on the substrate;
  • Step 2 forming a TFT layer on the black matrix
  • Step 3 forming a color resist layer, a second passivation protective layer, and a pixel electrode layer on the TFT layer and the substrate;
  • the step 2 includes the following specific steps:
  • Step 21 depositing and patterning a first metal layer on the black matrix to form a source/drain;
  • Step 22 forming a semiconductor layer on the source/drain, forming a gate insulating layer on the semiconductor layer;
  • Step 23 depositing and patterning a second metal layer on the gate insulating layer to form a gate
  • Step 24 forming a passivation protective layer on the gate.
  • the step 3 includes the following specific steps:
  • Step 31 forming a color resist layer on the first passivation protective layer, and forming a second passivation protective layer on the color resist layer;
  • Step 32 forming via holes on the second passivation protective layer, the color resist layer, the first passivation protective layer, the gate insulating layer, and the semiconductor layer;
  • Step 33 Form a pixel electrode layer on the second passivation protective layer, and the pixel electrode layer is electrically connected to the source/drain via the via hole.
  • the step 3 includes the following specific steps:
  • Step 31 forming via holes on the first passivation protective layer, the gate insulating layer and the semiconductor layer;
  • Step 32 forming a first ITO electrode layer on the first passivation protective layer, the first ITO electrode layer contacting the source/drain via via holes;
  • Step 33 forming a color resist layer on the first ITO electrode layer, and forming a second passivation protective layer on the color resist layer;
  • Step 34 forming a second ITO electrode layer on the second passivation protective layer, and the first ITO electrode layer and the second ITO electrode layer are connected to form a pixel electrode layer.
  • the material of the source/drain and the gate is copper or aluminum.
  • the semiconductor layer is a two-layer structure composed of an amorphous silicon layer and a heavily doped N-type silicon layer, and may also be a single-layer structure composed of an indium gallium zinc oxide layer.
  • the present invention also provides an array substrate, comprising a substrate, a black matrix disposed on the substrate, a TFT layer disposed on the black matrix, a color resist layer disposed on the TFT layer, and a second passivation protection Layer and pixel electrode layer;
  • the TFT layer includes a source/drain provided on the black matrix, a semiconductor layer disposed on the source/drain, a gate insulating layer disposed on the semiconductor layer, and the gate is disposed on the gate a gate on the insulating layer, and a first passivation protective layer disposed on the gate;
  • the color resist layer is on the first passivation protective layer
  • the second passivation layer is on the color resist layer
  • the pixel electrode layer is on the second passivation layer
  • the array substrate a via hole penetrating through the second passivation protective layer, the color resist layer, the first passivation protective layer, the gate insulating layer and the semiconductor layer, the pixel electrode layer via the via and the source/drain electrical connection;
  • the material of the source/drain and the gate is copper or aluminum.
  • the invention provides an array substrate, wherein BOA and COA technologies are simultaneously applied to an array substrate, that is, a black matrix and a color resist layer are disposed on the array substrate, so as to prevent the color resist layer from being subjected to the TFT preparation process.
  • the effect of the high-temperature process is to eliminate the source of the bubbles in the liquid crystal display panel, and to set the color resist layer on the TFT layer and the black matrix, and to prevent leakage of the array substrate of the BOA structure, the TFT layer adopts a top gate type TFT structure. Effectively improve the display quality of the liquid crystal display panel.
  • the invention provides an array substrate manufacturing method, which will BOA and The COA technology is applied to the array substrate at the same time.
  • a black matrix is formed on the substrate, and then a TFT process is performed on the black matrix. Then, after the TFT is completed, a color resist layer is formed, thereby realizing the black matrix and the color resist layer.
  • the TFT layer adopts a top gate type TFT structure, which effectively improves the display quality of the liquid crystal panel and improves the yield of the product.
  • FIG. 1 is a schematic cross-sectional view showing a structure of a conventional TFT substrate
  • FIG. 2 is a cross-sectional view showing a first embodiment of a TFT substrate structure of the present invention
  • FIG. 3 is a cross-sectional view showing a second embodiment of a TFT substrate structure of the present invention.
  • FIG. 4 is a schematic flow chart of a method of fabricating a TFT substrate of the present invention.
  • the invention provides an array substrate, wherein BOA and COA technologies are simultaneously applied to an array substrate, that is, a black matrix and a color resist layer are disposed on the array substrate, so as to prevent the color resist layer from being affected by the high temperature process in the TFT preparation process,
  • the second embodiment of the array substrate of the present invention is provided.
  • the color resist layer is disposed on the TFT layer and the black matrix. Referring to FIG. 2, it is a cross-sectional view of the first embodiment of the array substrate of the present invention.
  • the array substrate includes a substrate 1, a black matrix 2 disposed on the substrate 1, a TFT layer 21 disposed on the black matrix 2, a color resist layer 8 disposed on the TFT layer 21, and a second blunt
  • the protective layer 9 and the pixel electrode layer 11 are provided.
  • the substrate 1 is a glass substrate.
  • the TFT layer 21 selects a top gate type TFT structure, and the TFT layer 21 includes a source/drain 3 disposed on the black matrix 2, and is disposed in the a semiconductor layer 4 on the source/drain 3, a gate insulating layer 5 provided on the semiconductor layer 4, a gate electrode 6 provided on the gate insulating layer 5, and a gate electrode 6 disposed on the gate electrode 6.
  • the semiconductor layer 4 may be a two-layer structure composed of an a-Si (amorphous silicon) layer and an n + Si (heavily doped N-type silicon) layer, or may be an IGZO (indium gallium zinc oxide) layer. A single layer structure.
  • the material of the source/drain 3 and the gate 6 is copper or aluminum.
  • the material of the gate insulating layer 5 is silicon nitride.
  • the color resist layer 8 is located on the first passivation protective layer 7, the second passivation protective layer 9 is located on the color resist layer 8, and the pixel electrode layer 11 is located on the second passivation protective layer 9.
  • the array substrate further includes a via 10 penetrating through the second passivation protective layer 9, the color resist layer 8, the first passivation protective layer 7, the gate insulating layer 5, and the semiconductor layer 4, the pixel electrode layer 11 is electrically connected to the source/drain 3 via a via 10 .
  • the materials of the first passivation protective layer 7 and the second passivation protective layer 9 are both silicon nitride.
  • the material of the pixel electrode layer 11 is indium tin oxide.
  • FIG. 4 is a schematic flow chart of a method for fabricating a TFT substrate according to the present invention.
  • the present invention further provides a method for fabricating the array substrate according to the first embodiment, which includes the following steps:
  • Step 1 Providing a substrate 1 on which a black matrix 2 is formed.
  • the substrate 1 is a glass substrate, and the black matrix 2 is fabricated on the substrate 1 by a coating process.
  • Step 2 forming a TFT layer 21 on the black matrix 2.
  • the TFT layer 21 selects a top gate type TFT structure.
  • step 2 includes the following specific steps:
  • Step 21 depositing and patterning a first metal layer on the black matrix 2 to form a source/drain 3;
  • the material of the source/drain 3 is copper or aluminum
  • Step 22 forming a semiconductor layer 4 on the source / drain 3, forming a gate insulating layer 5 on the semiconductor layer 4;
  • the semiconductor layer 4 may be a two-layer structure composed of an a-Si (amorphous silicon) layer and an n + Si (heavily doped N-type silicon) layer, or may be an IGZO (indium gallium zinc oxide) layer. a single layer structure
  • the material of the gate insulating layer 5 is silicon nitride
  • Step 23 depositing and patterning a second metal layer on the gate insulating layer 5 to form a gate electrode 6;
  • the material of the gate 6 is copper or aluminum
  • Step 24 forming a first passivation protective layer 7 on the gate 6;
  • the material of the first passivation protective layer 7 is silicon nitride.
  • Step 3 forming a color resist layer 8, a second passivation protective layer 9, and a pixel electrode layer 11 on the TFT layer 21 and the substrate 1.
  • step 3 includes the following specific steps:
  • Step 31 forming a color resist layer 8 on the first passivation protective layer 7, and forming a second passivation protective layer 9 on the color resist layer 8;
  • the color resist layer 8 is formed by a coating process
  • the materials of the first passivation protective layer 7 and the second passivation protective layer 9 are both silicon nitride;
  • Step 32 forming a via 10 on the second passivation protective layer 9, the color resist layer 8, the first passivation protective layer 7, the gate insulating layer 5 and the semiconductor layer 4;
  • the via hole 10 is formed by a dry etching process
  • Step 33 forming a pixel electrode layer 11 on the second passivation protective layer 9, the pixel electrode layer 11 contacting the source/drain 3 via the via hole 10;
  • the pixel electrode layer 11 is formed by a vacuum coating technique and a wet etching process
  • the material of the pixel electrode layer 11 is indium tin oxide.
  • the array substrate includes a substrate 1 and a black matrix 2 disposed on the substrate 1 is disposed at the The TFT layer 21 on the black matrix 2 is provided on the color resist layer 8, the second passivation protective layer 9, and the pixel electrode layer 11 on the TFT layer 21.
  • the substrate 1 is a glass substrate.
  • the TFT layer 21 is a top gate type TFT, and the TFT layer 21 includes a source/drain 3 disposed on the black matrix 2, and a semiconductor layer 4 disposed on the source/drain 3. a gate insulating layer 5 on the semiconductor layer 4, a gate electrode 6 provided on the gate insulating layer 5, and a first passivation protective layer 7 provided on the gate electrode 6.
  • the semiconductor layer 4 may be a two-layer structure composed of an a-Si (amorphous silicon) layer and an n + Si (heavily doped N-type silicon) layer, or may be an IGZO (indium gallium zinc oxide) layer. A single layer structure.
  • the material of the source/drain 3 and the gate 6 is copper or aluminum.
  • the material of the gate insulating layer 5 is silicon nitride.
  • the pixel electrode layer 11 includes a first ITO electrode layer 112 and a second ITO electrode layer 114.
  • the first ITO electrode layer 112 is located on the first passivation protective layer 7.
  • the array substrate further includes a through-passage a passivation protective layer 7, a gate insulating layer 5, and a via 10' of the semiconductor layer 4, the first ITO electrode layer 112 being in contact with the source/drain 3 via a via 10', the color resist
  • the layer 8 is on the first ITO electrode layer 112
  • the second passivation protective layer 9 is on the color resist layer 8
  • the second ITO electrode layer 114 is on the second passivation protective layer 9, and the First ITO
  • the electrode layer 112 and the second ITO electrode layer 114 are connected to each other to form the pixel electrode layer 11.
  • the materials of the first passivation protective layer 7 and the second passivation protective layer 9 are both silicon nitride.
  • the materials of the first ITO electrode layer 112 and the second ITO electrode layer 114 are indium tin oxide.
  • the array substrate of the second embodiment of the present invention has an advantage in that no via holes are formed in the color resist layer, so that planarization of the TFT substrate can be better maintained.
  • FIG. 4 is a schematic flow chart of a method for fabricating a TFT substrate according to the present invention.
  • the present invention further provides a method for fabricating the array substrate according to the second embodiment, which includes the following steps:
  • Step 1 Providing a substrate 1 on which a black matrix 2 is formed.
  • the substrate 1 in the step 1 is a glass substrate, and the black matrix 2 is fabricated on the substrate 1 by a coating process.
  • Step 2 forming a TFT layer 21 on the black matrix 2.
  • step 2 includes the following specific steps:
  • Step 21 depositing and patterning a first metal layer on the black matrix 2 to form a source/drain 3;
  • the material of the source/drain 3 is copper or aluminum
  • Step 22 forming a semiconductor layer 4 on the source / drain 3, forming a gate insulating layer 5 on the semiconductor layer 4;
  • the semiconductor layer 4 may be a two-layer structure composed of an a-Si (amorphous silicon) layer and an n + Si (heavily doped N-type silicon) layer, or may be an IGZO (indium gallium zinc oxide) layer. a single layer structure
  • the material of the gate insulating layer 5 is silicon nitride
  • Step 23 depositing and patterning a second metal layer on the gate insulating layer 5 to form a gate electrode 6;
  • the material of the gate 6 is copper or aluminum
  • Step 24 forming a first passivation protective layer 7 on the gate 6;
  • the material of the first passivation protective layer 7 is silicon nitride.
  • Step 3 forming a color resist layer 8, a second passivation protective layer 9, and a pixel electrode layer 11 on the TFT layer 21 and the substrate 1.
  • step 3 includes the following specific steps:
  • Step 31 forming a via 10 on the first passivation protective layer 7, the gate insulating layer 5, and the semiconductor layer 4;
  • the via hole 10' is formed by a dry etching process
  • Step 32 forming a first ITO electrode layer 112 on the first passivation protective layer 7, the first ITO electrode layer 112 contacting the source/drain 3 via a via 10';
  • the first ITO electrode layer 112 is formed by a vacuum coating technology and a wet etching process
  • Step 33 forming a color resist layer 8 on the first ITO electrode layer 112, and forming a second passivation protective layer 9 on the color resist layer 8;
  • the color resist layer 8 is formed by a coating process
  • the material of the second passivation protective layer 9 is silicon nitride
  • Step 34 forming a second ITO electrode layer 114 on the second passivation protective layer 9, and the first ITO electrode layer 112 and the second ITO electrode layer 114 are connected to form a pixel electrode layer 11;
  • the second ITO electrode layer 114 is formed by a vacuum coating technology and a wet etching process
  • the materials of the first ITO electrode layer 112 and the second ITO electrode layer 114 are indium tin oxide.
  • the manufacturing method of the second embodiment of the array substrate of the present invention has the advantages that no via holes are formed on the color resist layer, so that the flatness of the TFT substrate can be better maintained. Chemical.
  • the present invention provides an array substrate in which BOA and COA technologies are simultaneously applied to an array substrate, that is, a black matrix and a color resist layer are disposed on the array substrate, in order to prevent the color resist layer from being subjected to TFT preparation.
  • the effect of the high-temperature process is to eliminate the source of the bubbles in the liquid crystal display panel, and to set the color resist layer on the TFT layer and the black matrix, and to prevent leakage of the array substrate of the BOA type structure, the TFT layer adopts a top gate type TFT structure, which is effective Improve the display quality of the LCD panel.
  • the invention provides a method for fabricating an array substrate, wherein BOA and COA technologies are simultaneously applied to an array substrate, first forming a black matrix on the substrate, secondly performing a TFT process on the black matrix, and then forming a color after the TFT is completed.
  • the TFT layer adopts a top gate type TFT structure, which effectively improves the display quality of the liquid crystal panel and improves the product yield.

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Abstract

一种阵列基板及其制作方法，所述阵列基板通过将黑色矩阵(2)和色阻层(8)均设置于阵列基板上，并且将色阻层(8)设置于TFT层(21)上，避免了TFT制备过程中的高温制程对色阻层(8)产生不良影响，同时为防止阵列基板漏电，TFT层(21)采用顶栅型TFT结构，从而使得液晶面板具有较高的显示品质。所述阵列基板的制作方法，首先在基板(1)上形成黑色矩阵(2)，其次在黑色矩阵(2)上进行TFT制程，然后在TFT制作完成后再形成色阻层(8)，从而实现将黑色矩阵(2)和色阻层(8)均制作于阵列基板上，并且由于在TFT制程之后形成色阻层(8)，避免了TFT制备过程中的高温制程中色阻挥发产生气体而导致产生气泡等不良现象，有效提升了液晶面板的显示品质，并且提高了产品良率。

Description

阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制作方法。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等。现有市场上的液晶显示装置大部分为背光型液晶显示装置，其包括背光模组(Backlight module)及结合于背光模组上的液晶面板。
在TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器)中，通常会在基板上制作一层BM(Black Matrix，黑色矩阵)，用于分割相邻色阻，遮挡色彩的空隙，防止漏光或者混色，将黑色矩阵制备在TFT阵列基板的技术叫做BOA(BM On Array，黑色矩阵贴附于阵列基板)，BOA可以解决上下基板错位导致遮光区域不匹配的问题。
同时，为了提升TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器)的显示品质，还提出了一种COA(Color Filter On Array，色阻层贴附于阵列基板)技术。
如图1所示，当BOA和COA技术都应用在阵列基板100上，通常为了使用喷涂技术而把黑色矩阵200和色阻层300做在同一层，这样色阻层300会经历TFT制备过程中的PVD(物理气相沉积)和CVD(化学气相沉积)的高温制程，对色阻层300的性能会有严重的影响，此外，高温制程会使得色阻层300挥发产生气体，成为气泡的来源，降低产品良率。
发明内容
本发明的目的在于提供一种阵列基板，通过将黑色矩阵和色阻层均设置于阵列基板上，并且将色阻层设置于TFT层上，避免了TFT制备过程中的高温制程对色阻层产生不良影响，从而使得液晶面板具有较高的显示品质。
本发明的目的还在于提供一种阵列基板的制作方法，首先在基板上形成黑色矩阵，其次在黑色矩阵上进行TFT制程，然后在TFT制作完成后再形成色阻层，从而实现将黑色矩阵和色阻层均制作于阵列基板上，并且由 于在TFT制程之后形成色阻层，避免了TFT制备过程中的高温制程中色阻挥发产生气体而导致的气泡等不良现象，有效提升了液晶面板的显示品质，并且提高了产品良率。
为实现上述目的，本发明提供一种阵列基板，包括基板，设于所述基板上的黑色矩阵，设于所述黑色矩阵上的TFT层，设于所述TFT层上的色阻层、第二钝化保护层、及像素电极层；
所述TFT层包括设于所述黑色矩阵上的源/漏极、设于所述源/漏极上的半导体层、设于所述半导体层上的栅极绝缘层、设于所述栅极绝缘层上的栅极、以及设于所述栅极上的第一钝化保护层。
所述色阻层位于第一钝化保护层上，所述第二钝化保护层位于色阻层上，所述像素电极层位于所述第二钝化保护层上，所述阵列基板还包括一贯穿第二钝化保护层、色阻层、第一钝化保护层、栅极绝缘层和半导体层的过孔，所述像素电极层经由过孔与所述源/漏极电性连接。
所述像素电极层包括第一ITO电极层和第二ITO电极层，所述第一ITO电极层位于第一钝化保护层上，所述阵列基板还包括一贯穿第一钝化保护层、栅极绝缘层和半导体层的过孔，所述第一ITO电极层经由过孔与所述源/漏极相接触，所述色阻层位于第一ITO电极层上，所述第二钝化保护层位于色阻层上，所述第二ITO电极层位于所述第二钝化保护层上，并且所述第一ITO电极层和第二ITO电极层相连，共同形成像素电极层。
所述源/漏极和栅极的材料为铜或铝。
所述半导体层是由非晶硅层和重掺杂的N型硅层组成的双层结构，也可以是由铟镓锌氧化物层构成的单层结构。
本发明还提供一种阵列基板的制作方法，包括以下步骤：
步骤1、提供基板，在所述基板上形成黑色矩阵；
步骤2、在所述黑色矩阵上制作TFT层；
步骤3、在所述TFT层和基板上形成色阻层、第二钝化保护层、及像素电极层；
所述步骤2包括以下具体步骤：
步骤21、在所述黑色矩阵上沉积并图案化第一金属层，形成源/漏极；
步骤22、在所述源/漏极上形成半导体层，在所述半导体层上形成栅极绝缘层；
步骤23、在所述栅极绝缘层上沉积并图案化第二金属层，形成栅极；
步骤24、在所述栅极上形成钝化保护层。
所述步骤3包括如下具体步骤：
步骤31、在所述第一钝化保护层上形成色阻层，并在所述色阻层上形成第二钝化保护层；
步骤32、在所述第二钝化保护层、色阻层、第一钝化保护层、栅极绝缘层、及半导体层上形成过孔；
步骤33、在所述第二钝化保护层上形成像素电极层，所述像素电极层经由所述过孔与所述源/漏极电性连接。
所述步骤3包括如下具体步骤：
步骤31、在所述第一钝化保护层、栅极绝缘层和半导体层上形成过孔；
步骤32、在所述第一钝化保护层上形成第一ITO电极层，所述第一ITO电极层经由过孔与所述源/漏极相接触；
步骤33、在所述第一ITO电极层上形成色阻层，并在所述色阻层上形成第二钝化保护层；
步骤34、在所述第二钝化保护层上形成第二ITO电极层，并且所述第一ITO电极层和第二ITO电极层相连，共同形成像素电极层。
所述源/漏极和栅极的材料为铜或铝。
所述半导体层是由非晶硅层和重掺杂的N型硅层组成的双层结构，也可以是由铟镓锌氧化物层构成的单层结构。
本发明还提供一种阵列基板，包括基板，设于所述基板上的黑色矩阵，设于所述黑色矩阵上的TFT层，设于所述TFT层上的色阻层、第二钝化保护层、及像素电极层；
所述TFT层包括设于所述黑色矩阵上的源/漏极、设于所述源/漏极上的半导体层、设于所述半导体层上的栅极绝缘层、设于所述栅极绝缘层上的栅极、以及设于所述栅极上的第一钝化保护层；
其中，所述色阻层位于第一钝化保护层上，所述第二钝化保护层位于色阻层上，所述像素电极层位于所述第二钝化保护层上，所述阵列基板还包括一贯穿第二钝化保护层、色阻层、第一钝化保护层、栅极绝缘层和半导体层的过孔，所述像素电极层经由过孔与所述源/漏极电性连接；
其中，所述源/漏极和栅极的材料为铜或铝。
本发明的有益效果：本发明提供的一种阵列基板，将BOA和COA技术同时应用于阵列基板上，即将黑色矩阵和色阻层均设置于阵列基板上，为避免色阻层受到TFT制备过程中的高温制程的影响，消除液晶显示面板中气泡的来源，将色阻层设置于TFT层和黑色矩阵之上，同时为防止BOA型结构的阵列基板漏电，TFT层采用顶栅型TFT结构，有效提升了液晶显示面板的显示品质。本发明提供的一种阵列基板的制作方法，将BOA和 COA技术同时应用于阵列基板上，首先在基板上形成黑色矩阵，其次在黑色矩阵上进行TFT制程，然后在TFT制作完成后再形成色阻层，从而实现将黑色矩阵和色阻层均制作于阵列基板上，并且由于在TFT制程之后形成色阻层，避免了TFT制备过程中的高温制程中色阻挥发产生气体而导致液晶显示面板产生气泡等不良现象，同时为防止BOA型结构的阵列基板漏电，TFT层采用顶栅型TFT结构，有效提升了液晶面板的显示品质，并且提高了产品良率。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为一种现有TFT基板结构的剖面示意图；
图2为本发明TFT基板结构的第一实施例的剖面示意图；
图3为本发明TFT基板结构的第二实施例的剖面示意图；
图4为本发明TFT基板制作方法的示意流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段极其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明提供一种阵列基板，将BOA和COA技术同时应用于阵列基板上，即将黑色矩阵和色阻层均设置于阵列基板上，为避免色阻层受到TFT制备过程中的高温制程的影响，消除液晶显示面板中气泡的来源，将色阻层设置于TFT层和黑色矩阵之上，请参阅图2，为本发明阵列基板的第一实施例的剖面示意图，在该第一实施例中，所述阵列基板包括基板1，设于所述基板1上的黑色矩阵2，设于所述黑色矩阵2上的TFT层21，设于所述TFT层21上的色阻层8、第二钝化保护层9、及像素电极层11。
优选的，所述基板1为玻璃基板。
优选的，为防止BOA型结构的阵列基板漏电，所述TFT层21选择顶栅型TFT结构，所述TFT层21包括设于所述黑色矩阵2上的源/漏极3、设于所述源/漏极3上的半导体层4、设于所述半导体层4上的栅极绝缘层5、设于所述栅极绝缘层5上的栅极6、以及设于所述栅极6上的第一钝化保护层7。
所述半导体层4可以是由a-Si(非晶硅)层和n+Si(重掺杂的N型硅) 层组成的双层结构，也可以是由IGZO(铟镓锌氧化物)层构成的单层结构。
优选的，所述源/漏极3和栅极6的材料为铜或铝。
优选的，所述栅极绝缘层5的材料为氮化硅。
其中，所述色阻层8位于第一钝化保护层7上，所述第二钝化保护层9位于色阻层8上，所述像素电极层11位于所述第二钝化保护层9上，所述阵列基板还包括一贯穿第二钝化保护层9、色阻层8、第一钝化保护层7、栅极绝缘层5和半导体层4的过孔10，所述像素电极层11经由过孔10与所述源/漏极3电性连接。
优选的，所述第一钝化保护层7与第二钝化保护层9的材料均为氮化硅。
优选的，所述像素电极层11的材料为氧化铟锡。
请参阅图4，为本发明TFT基板制作方法的示意流程图，为获得本发明第一实施例的阵列基板，本发明还提供上述第一实施例的阵列基板的制作方法，其包括以下步骤：
步骤1、提供基板1，在所述基板1上形成黑色矩阵2。
具体的，所述基板1为玻璃基板，在基板1上通过涂布工艺制作所述黑色矩阵2。
步骤2、在所述黑色矩阵2上制作TFT层21。
优选的，为防止BOA型结构的阵列基板漏电，所述TFT层21选择顶栅型TFT结构。
具体的，所述步骤2包括以下具体步骤：
步骤21、在所述黑色矩阵2上沉积并图案化第一金属层，形成源/漏极3；
优选的，所述源/漏极3的材料为铜或铝；
步骤22、在所述源/漏极3上形成半导体层4，在所述半导体层4上形成栅极绝缘层5；
所述半导体层4可以是由a-Si(非晶硅)层和n+Si(重掺杂的N型硅)层组成的双层结构，也可以是由IGZO(铟镓锌氧化物)层构成的单层结构；
优选的，所述栅极绝缘层5的材料为氮化硅；
步骤23、在所述栅极绝缘层5上沉积并图案化第二金属层，形成栅极6；
优选的，所述栅极6的材料为铜或铝；
步骤24、在所述栅极6上形成第一钝化保护层7；
优选的，所述第一钝化保护层7的材料为氮化硅。
步骤3、在所述TFT层21和基板1上形成色阻层8、第二钝化保护层9和像素电极层11。
具体的，所述步骤3包括如下具体步骤：
步骤31、在所述第一钝化保护层7上形成色阻层8，并在所述色阻层8上形成第二钝化保护层9；
具体的，采用涂布工艺形成所述色阻层8；
优选的，所述第一钝化保护层7与第二钝化保护层9的材料均为氮化硅；
步骤32、在所述第二钝化保护层9、色阻层8、第一钝化保护层7、栅极绝缘层5和半导体层4上形成过孔10；
具体的，通过干蚀刻工艺形成所述过孔10；
步骤33、在所述第二钝化保护层9上形成像素电极层11，所述像素电极层11经由所述过孔10与所述源/漏极3相接触；
具体的，通过真空镀膜技术及湿蚀刻工艺形成像素电极层11；
优选的，所述像素电极层11的材料为氧化铟锡。
请参阅图3，为本发明阵列基板的第二实施例的剖面示意图，在该第二实施例中，所述阵列基板包括基板1，设于所述基板1上的黑色矩阵2，设于所述黑色矩阵2上的TFT层21，设于所述TFT层21上的色阻层8、第二钝化保护层9、及像素电极层11。
优选的，所述基板1为玻璃基板。
其中，所述TFT层21为顶栅型TFT，所述TFT层21包括设于所述黑色矩阵2上的源/漏极3、设于所述源/漏极3上的半导体层4、设于所述半导体层4上的栅极绝缘层5、设于所述栅极绝缘层5上的栅极6、以及设于所述栅极6上的第一钝化保护层7。
所述半导体层4可以是由a-Si(非晶硅)层和n+Si(重掺杂的N型硅)层组成的双层结构，也可以是由IGZO(铟镓锌氧化物)层构成的单层结构。
优选的，所述源/漏极3和栅极6的材料为铜或铝。
优选的，所述栅极绝缘层5的材料为氮化硅。
其中，所述像素电极层11包括第一ITO电极层112和第二ITO电极层114，所述第一ITO电极层112位于第一钝化保护层7上，所述阵列基板还包括一贯穿第一钝化保护层7、栅极绝缘层5和半导体层4的过孔10’，所述第一ITO电极层112经由过孔10’与所述源/漏极3相接触，所述色阻层8位于第一ITO电极层112上，所述第二钝化保护层9位于色阻层8上，所述第二ITO电极层114位于所述第二钝化保护层9上，并且所述第一ITO 电极层112和第二ITO电极层114相连，共同形成像素电极层11。
优选的，所述第一钝化保护层7与第二钝化保护层9的材料均为氮化硅。
优选的，所述第一ITO电极层112和第二ITO电极层114的材料均为氧化铟锡。
与本发明第一实施例的阵列基板相比，本发明第二实施例的阵列基板的优点在于，没有在色阻层上形成过孔，从而可以更好地保持TFT基板的平坦化。
请参阅图4，为本发明TFT基板制作方法的示意流程图，为获得本发明第二实施例的阵列基板，本发明还提供上述第二实施例的阵列基板的制作方法，其包括以下步骤：
步骤1、提供基板1，在所述基板1上形成黑色矩阵2。
具体的，所述步骤1中的基板1为玻璃基板，在基板1上通过涂布工艺制作所述黑色矩阵2。
步骤2、在所述黑色矩阵2上制作TFT层21。
具体的，所述步骤2包括以下具体步骤：
步骤21、在所述黑色矩阵2上沉积并图案化第一金属层，形成源/漏极3；
优选的，所述源/漏极3的材料为铜或铝；
步骤22、在所述源/漏极3上形成半导体层4，在所述半导体层4上形成栅极绝缘层5；
所述半导体层4可以是由a-Si(非晶硅)层和n+Si(重掺杂的N型硅)层组成的双层结构，也可以是由IGZO(铟镓锌氧化物)层构成的单层结构；
优选的，所述栅极绝缘层5的材料为氮化硅；
步骤23、在所述栅极绝缘层5上沉积并图案化第二金属层，形成栅极6；
优选的，所述栅极6的材料为铜或铝；
步骤24、在所述栅极6上形成第一钝化保护层7；
优选的，所述第一钝化保护层7的材料均为氮化硅。
步骤3、在所述TFT层21和基板1上形成色阻层8、第二钝化保护层9、及像素电极层11。
具体的，所述步骤3包括如下具体步骤：
步骤31、在所述第一钝化保护层7、栅极绝缘层5、及半导体层4上形成过孔10；
具体地，通过干蚀刻工艺形成所述过孔10’；
步骤32、在所述第一钝化保护层7上形成第一ITO电极层112，所述第一ITO电极层112经由过孔10’与所述源/漏极3相接触；
具体的，通过真空镀膜技术及湿蚀刻工艺形成第一ITO电极层112；
步骤33、在所述第一ITO电极层112上形成色阻层8，并在所述色阻层8上形成第二钝化保护层9；
具体的，采用涂布工艺形成所述色阻层8；
优选的，所述第二钝化保护层9的材料为氮化硅；
步骤34、在所述第二钝化保护层9上形成第二ITO电极层114，并且所述第一ITO电极层112和第二ITO电极层114相连，共同形成像素电极层11；
具体的，通过真空镀膜技术及湿蚀刻工艺形成第二ITO电极层114；
优选的，所述第一ITO电极层112和第二ITO电极层114的材料均为氧化铟锡。
与本发明阵列基板第一实施例的制作方法相比，本发明阵列基板第二实施例的制作方法的优点在于，没有在色阻层上形成过孔，从而可以更好地保持TFT基板的平坦化。
综上所述，本发明提供的一种阵列基板，将BOA和COA技术同时应用于阵列基板上，即将黑色矩阵和色阻层均设置于阵列基板上，为避免色阻层受到TFT制备过程中的高温制程的影响，消除液晶显示面板中气泡的来源，将色阻层设置于TFT层和黑色矩阵之上，同时为防止BOA型结构的阵列基板漏电，TFT层采用顶栅型TFT结构，有效提升了液晶显示面板的显示品质。本发明提供的一种阵列基板的制作方法，将BOA和COA技术同时应用于阵列基板上，首先在基板上形成黑色矩阵，其次在黑色矩阵上进行TFT制程，然后在TFT制作完成后再形成色阻层，从而实现将黑色矩阵和色阻层均制作于阵列基板上，并且由于在TFT制程之后形成色阻层，避免了TFT制备过程中的高温制程中色阻挥发产生气体而导致液晶显示面板产生气泡等不良现象，同时为防止BOA型结构的阵列基板漏电，TFT层采用顶栅型TFT结构，有效提升了液晶面板的显示品质，并且提高了产品良率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (12)

  1. 一种阵列基板，包括基板，设于所述基板上的黑色矩阵，设于所述黑色矩阵上的TFT层，设于所述TFT层上的色阻层、第二钝化保护层、及像素电极层；
    所述TFT层包括设于所述黑色矩阵上的源/漏极、设于所述源/漏极上的半导体层、设于所述半导体层上的栅极绝缘层、设于所述栅极绝缘层上的栅极、以及设于所述栅极上的第一钝化保护层。
  2. 如权利要求1所述的阵列基板，其中，所述色阻层位于第一钝化保护层上，所述第二钝化保护层位于色阻层上，所述像素电极层位于所述第二钝化保护层上，所述阵列基板还包括一贯穿第二钝化保护层、色阻层、第一钝化保护层、栅极绝缘层和半导体层的过孔，所述像素电极层经由过孔与所述源/漏极电性连接。
  3. 如权利要求1所述的阵列基板，其中，所述像素电极层包括第一ITO电极层和第二ITO电极层，所述第一ITO电极层位于第一钝化保护层上，所述阵列基板还包括一贯穿第一钝化保护层、栅极绝缘层和半导体层的过孔，所述第一ITO电极层经由过孔与所述源/漏极相接触，所述色阻层位于第一ITO电极层上，所述第二钝化保护层位于色阻层上，所述第二ITO电极层位于所述第二钝化保护层上，并且所述第一ITO电极层和第二ITO电极层相连，共同形成像素电极层。
  4. 如权利要求1所述的阵列基板，其中，所述源/漏极和栅极的材料为铜或铝。
  5. 如权利要求1所述的阵列基板，其中，所述半导体层是由非晶硅层和重掺杂的N型硅层组成的双层结构，或者是由铟镓锌氧化物层构成的单层结构。
  6. 一种阵列基板的制作方法，包括以下步骤：
    步骤1、提供基板，在所述基板上形成黑色矩阵；
    步骤2、在所述黑色矩阵上制作TFT层；
    步骤3、在所述TFT层和基板上形成色阻层、第二钝化保护层、及像素电极层；
    所述步骤2包括以下具体步骤：
    步骤21、在所述黑色矩阵上沉积并图案化第一金属层，形成源/漏极；
    步骤22、在所述源/漏极上形成半导体层，在所述半导体层上形成栅极 绝缘层；
    步骤23、在所述栅极绝缘层上沉积并图案化第二金属层，形成栅极；
    步骤24、在所述栅极上形成第一钝化保护层。
  7. 如权利要求6所述的阵列基板的制作方法，其中，所述步骤3包括如下具体步骤：
    步骤31、在所述第一钝化保护层上形成色阻层，并在所述色阻层上形成第二钝化保护层；
    步骤32、在所述第二钝化保护层、色阻层、第一钝化保护层、栅极绝缘层和半导体层上形成过孔；
    步骤33、在所述第二钝化保护层上形成像素电极层，所述像素电极层经由所述过孔与所述源/漏极电性连接。
  8. 如权利要求6所述的阵列基板的制作方法，其中，所述步骤3包括如下具体步骤：
    步骤31、在所述第一钝化保护层、栅极绝缘层、及半导体层上形成过孔；
    步骤32、在所述第一钝化保护层上形成第一ITO电极层，所述第一ITO电极层经由过孔与所述源/漏极相接触；
    步骤33、在所述第一ITO电极层上形成色阻层，并在所述色阻层上形成第二钝化保护层；
    步骤34、在所述第二钝化保护层上形成第二ITO电极层，并且所述第一ITO电极层和第二ITO电极层相连，共同形成像素电极层。
  9. 如权利要求6所述的阵列基板的制作方法，其中，所述源/漏极和栅极的材料为铜或铝。
  10. 如权利要求6所述的阵列基板的制作方法，其中，所述半导体层是由非晶硅层和重掺杂的N型硅层组成的双层结构，或者是由铟镓锌氧化物层构成的单层结构。
  11. 一种阵列基板，包括基板，设于所述基板上的黑色矩阵，设于所述黑色矩阵上的TFT层，设于所述TFT层上的色阻层、第二钝化保护层、及像素电极层；
    所述TFT层包括设于所述黑色矩阵上的源/漏极、设于所述源/漏极上的半导体层、设于所述半导体层上的栅极绝缘层、设于所述栅极绝缘层上的栅极、以及设于所述栅极上的第一钝化保护层；
    其中，所述色阻层位于第一钝化保护层上，所述第二钝化保护层位于色阻层上，所述像素电极层位于所述第二钝化保护层上，所述阵列基板还 包括一贯穿第二钝化保护层、色阻层、第一钝化保护层、栅极绝缘层和半导体层的过孔，所述像素电极层经由过孔与所述源/漏极电性连接；
    其中，所述源/漏极和栅极的材料为铜或铝。
  12. 如权利要求11所述的阵列基板，其中，所述半导体层是由非晶硅层和重掺杂的N型硅层组成的双层结构，或者是由铟镓锌氧化物层构成的单层结构。
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