WO2016045238A1 - 阵列基板及其制作方法、液晶显示装置 - Google Patents
阵列基板及其制作方法、液晶显示装置 Download PDFInfo
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- WO2016045238A1 WO2016045238A1 PCT/CN2015/070024 CN2015070024W WO2016045238A1 WO 2016045238 A1 WO2016045238 A1 WO 2016045238A1 CN 2015070024 W CN2015070024 W CN 2015070024W WO 2016045238 A1 WO2016045238 A1 WO 2016045238A1
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Definitions
- the present disclosure relates to the field of display, and in particular to an array substrate, a method of fabricating the same, and a liquid crystal display device.
- LCD Liquid Crystal Display
- OLED Organic Light-Emitting Diode
- LCD flat panel display due to its small size, light weight, thin thickness, low power consumption, no radiation, etc., has been rapidly developed in recent years, occupying a dominant position in the current flat panel display market, in various large Small and medium-sized products have been widely used, covering almost all major electronic products in today's information society, such as LCD TVs, computers, mobile phones, PDAs, GPS, car displays, projection displays, camcorders, digital cameras, electronic watches, calculators. , electronic instruments, meters, public display and unreal display.
- each liquid crystal pixel in the LCD display is driven by a Thin Film Transistor (TFT) integrated in the TFT array substrate, and then combined with a peripheral driving circuit to realize image display; active matrix driving In an OLED (Active Matrix Organic Light Emission Display, AMOLED) display, a corresponding OLED pixel in an OLED panel is driven by a TFT in a TFT substrate, and then a peripheral driving circuit is used to realize image display.
- the TFT is a switch for controlling light emission, which is the key to realize the large size of the liquid crystal display and the OLED display, and is directly related to the development direction of the high performance flat panel display.
- TFTs which have been industrialized mainly include amorphous silicon TFTs, polycrystalline silicon TFTs, single crystal silicon TFTs, etc., and amorphous silicon TFTs are most used for preparing array substrates in flat panel displays.
- metal oxide TFTs have emerged, which have the advantages of high carrier mobility, so that the TFT can be made small, so that the resolution of the flat panel display is further improved. High, the display effect is better; at the same time, the use of metal oxide TFT also has the advantages of less characteristic unevenness, low material and process cost, low process temperature, available coating process, high transparency and large band gap. Therefore, the application of metal oxide TFTs to flat panel displays has attracted industry attention.
- a metal oxide TFT is generally used in a six-time photolithography process, mainly because the metal oxide semiconductor layer is etched away when the source and the drain metal electrode are etched. Therefore, an etch barrier layer is generally added to the metal oxide semiconductor layer. In order to protect the metal oxide semiconductor layer from being etched by the source and drain metal etching solution during etching of the source and drain metal electrodes. In general, the smaller the number of masks used in fabricating a metal oxide TFT, the higher the production efficiency and the lower the cost.
- an embodiment of the present disclosure provides an array substrate, a manufacturing method thereof, and a liquid crystal display device.
- An embodiment of the present disclosure is: a method of fabricating an array substrate, comprising the steps of:
- Step 1 sequentially forming a metal oxide semiconductor layer and an etch barrier layer on the gate insulating layer;
- Step 2 performing a patterning process on the etching barrier layer to form a source electrode contact region via hole, a drain electrode contact region via hole, and an isolation region;
- Step 3 forming a source/drain electrode layer on the etch barrier layer completing step 2;
- Step 4 in the process of forming a source/drain electrode pattern by performing a patterning process on the source/drain electrode layer, removing a portion of the metal oxide semiconductor layer corresponding to the isolation region, so that the metal oxide semiconductor layer is The corresponding position of the isolation area is disconnected.
- isolation region surrounds the source and drain electrode patterns.
- the present disclosure also provides an array substrate, including:
- a metal oxide semiconductor layer and an etch barrier layer sequentially formed on the gate insulating layer
- the etch barrier layer is formed with an isolation region surrounding the source/drain electrode pattern, the metal oxide semiconductor layer being disconnected at a position corresponding to the isolation region.
- the present disclosure also provides a display device including the above array substrate.
- the beneficial effects of the present disclosure are: according to the method of fabricating an array substrate according to an embodiment of the present disclosure, after the metal oxide semiconductor layer is formed on the gate insulating layer, the etching stopper layer is directly formed on the metal oxide semiconductor layer, that is, The metal oxide semiconductor layer is not etched before the formation of the etch barrier layer, thereby facilitating a good interface between the metal oxide semiconductor layer and the etch barrier layer.
- a patterning process is performed on the etching stopper layer to form a source electrode contact region via hole, a drain electrode contact region via hole, and an isolation region surrounding the source/drain electrode pattern to be formed;
- the metal oxide semiconductor corresponding to the isolation region is removed by a patterning process to isolate the metal oxide semiconductor layer from the metal oxide semiconductor layer.
- the corresponding position of the zone is broken.
- the method of fabricating the array substrate according to the embodiments of the present disclosure can not only reduce one lithography process, but also avoid a large-area etching process on the etch barrier layer, thereby improving production efficiency.
- FIG. 1 is a schematic structural view of an array substrate according to an embodiment of the present disclosure
- FIG. 2 is a cross-sectional view of the array substrate formed along the A-B direction of FIG. 1 according to an embodiment of the present disclosure
- FIG. 3 is a cross-sectional view of the array substrate formed along the A-B direction of FIG. 1 according to an embodiment of the present disclosure
- FIG. 4 is a cross-sectional view of the array substrate formed along the A-B direction of FIG. 1 according to an embodiment of the present disclosure
- FIG. 5 is a cross-sectional view of the array substrate formed along the A-B direction of FIG. 1 according to an embodiment of the present disclosure
- FIG. 6 is a cross-sectional view of the array substrate formed along the AB direction of FIG. 1 in accordance with an embodiment of the present disclosure.
- the present disclosure provides a method of fabricating an array substrate, the method comprising the steps of:
- Step 101 sequentially forming a metal oxide semiconductor layer and an etch barrier layer on the gate insulating layer;
- Step 102 performing a patterning process on the etch barrier layer to form a source electrode contact region via hole, a drain electrode contact region via hole, and an isolation region surrounding the source/drain electrode pattern to be formed;
- Step 103 forming a source/drain electrode layer on the etch barrier layer of step 102;
- Step 104 in the process of forming a source/drain electrode pattern by performing a patterning process on the source/drain electrode layer, removing a portion of the metal oxide semiconductor layer corresponding to the isolation region, so that the metal oxide semiconductor layer is The corresponding position of the isolation area is broken.
- the etching stopper layer is directly formed on the metal oxide semiconductor layer, that is, before the etching stopper layer is formed.
- the metal oxide semiconductor layer is etched, thereby facilitating a good interface between the metal oxide semiconductor layer and the etch barrier layer.
- a patterning process is performed on the etching stopper layer to form a source electrode contact region via hole, a drain electrode contact region via hole, and an isolation region surrounding the source/drain electrode pattern to be formed;
- the metal oxide semiconductor corresponding to the isolation region is removed by a patterning process, so that the metal oxide semiconductor layer is in the isolation region. The corresponding position is broken.
- the etching barrier layer corresponding to the region outside the source/drain electrode pattern the method of fabricating the array substrate according to the embodiment of the present disclosure, only needs to remove the portion of the metal oxide semiconductor layer corresponding to the isolation region, thereby avoiding large The area is etched by the etch barrier to waste resources.
- the step 101 further includes a step of forming a gate electrode and a gate insulating layer on the substrate.
- a gate metal film is formed on the substrate 1, and a gate electrode pattern is formed on the gate metal film by one patterning process.
- a gate insulating layer 3 is formed on the gate electrode.
- a metal oxide semiconductor layer 4 and an etching stopper layer 5 on the metal oxide semiconductor layer 4 are formed on the gate insulating layer.
- the metal oxide semiconductor layer 4 needs to be etched in advance before the etching stopper layer 5 is formed.
- the metal oxide semiconductor layer 4 is not etched before the etching barrier layer 5 is formed, but the etching stopper layer 5 is directly formed on the metal oxide semiconductor layer 4. This facilitates the formation of a good interface between the metal oxide semiconductor layer and the etch stop layer.
- the etching stopper layer is subjected to a patterning process to form a source electrode contact region via hole, a drain electrode contact region via hole, and an isolation region surrounding the source/drain electrode pattern to be formed.
- the isolation region of the source-drain electrode pattern refers to a region surrounding the source-drain electrode pattern and isolated from the source-drain electrode pattern.
- the patterning process of the etching stopper layer may be performed by etching or the like, and the source electrode contact region via hole, the drain electrode contact region via hole, and the isolation region are formed by a patterning process.
- a source/drain electrode layer is formed on the etch barrier layer completed in step 102, and utilized.
- the patterning process forms a source-drain electrode pattern.
- the patterning process for forming the source-drain electrode pattern can employ an existing etching process.
- step 104 in the process of forming the source/drain electrode pattern by the patterning process of the source/drain electrode layer, the metal oxide semiconductor corresponding to the isolation region is connected to the metal oxide semiconductor of other regions. This step simultaneously removes a portion of the metal oxide semiconductor layer corresponding to the isolation region by one patterning process to break the metal oxide semiconductor layer at a position corresponding to the isolation region.
- the step of removing the metal oxide semiconductor layer corresponding to the isolation region by the source-drain electrode etching medium is performed to make the metal oxide
- the semiconductor layer is disconnected at a position corresponding to the isolation region. Since the position of the metal oxide semiconductor layer corresponding to the isolation region is exposed, the metal oxide semiconductor of the isolation region can be removed by the source/drain electrode etching medium, thereby forming a source isolated from the metal oxide semiconductor layer. Drain electrode pattern.
- the method of fabricating the array substrate according to the embodiment of the present disclosure only needs to remove the portion of the metal oxide semiconductor layer corresponding to the isolation region, thereby avoiding large-area etching, corresponding to the etch barrier layer of the region other than the source/drain electrode pattern. Waste of resources caused by etching the barrier layer.
- step 104 the method further includes:
- Step 105 Form a contact via pattern. That is, after the metal oxide semiconductor layer is disconnected at a position corresponding to the isolation region, the method further includes:
- a protective layer is formed on the source/drain electrode layer of step 104, and a patterning process is performed on the protective layer to form a contact via pattern for connecting the pixel electrode and the drain electrode.
- step 105 the method further includes:
- Step 106 Form a pixel electrode pattern. That is, after the step of forming the protective layer on the source/drain electrode layer of the step 104, the step of forming the contact via pattern for connecting the pixel electrode and the drain electrode by one patterning process further includes:
- a conductive layer is formed on the protective layer completing step 105, and the conductive layer is subjected to a patterning process to form a pixel electrode pattern.
- Figure 2-6 shows a flow chart for forming an array substrate.
- the specific process flow includes:
- Step 1 sequentially depositing a thickness on the substrate by sputtering or thermal evaporation.
- Grid metal film The gate metal film may be selected from a metal or an alloy such as Cr, W, Cu, Ti, Ta, Mo, etc., and a gate metal layer composed of a plurality of layers of metal may also satisfy the needs.
- the gate electrode 2 is formed as shown in FIG.
- Step 2 Continuously depositing a thickness by a PECVD (plasma enhanced chemical vapor deposition) method on the substrate on which step 1 is completed
- the gate insulating layer 3, the gate insulating layer 3 may be an oxide, a nitride or an oxynitride compound, wherein the reaction gas corresponding to the silicon oxide may be N 2 O and SiH 4 ; the reaction gas corresponding to the silicon oxynitride may be N 2 O , SiH 4 , NH 3 and N 2 ; the reaction gas corresponding to silicon nitride may be SiH 4 , NH 3 and N 2 or SiH 2 Cl 2 , NH 3 and N 2 .
- the metal oxide semiconductor layer may be amorphous IGZO, HIZO, IZO, a-InZnO, a-InZnO, ZnO: F, In 2 O 3 :Sn, In 2 O 3 :Mo, Made of Cd 2 SnO 4 , ZnO:Al, TiO 2 :Nb, Cd-Sn-O or other metal oxide, and then deposited by PECVD to a thickness of
- the etch stop layer 5 the etch stop layer may be an oxide, a nitride or an oxynitride compound, wherein the reaction gas corresponding to the silicon oxide may be N 2 O and SiH 4 ; the reaction gas corresponding to the silicon oxynitride may be N 2 O, SiH 4 , NH 3 and N 2 ; the reaction gas corresponding to silicon nitride may be SiH 4
- the etching barrier layer may also use Al 2 O 3 or a double-layer barrier structure.
- the source electrode contact region via 13, the drain electrode contact region via 11, and the isolation region 10 surrounding the source and drain electrode patterns are then formed by a conventional photolithography process, as shown in FIG.
- Step 3 On the substrate on which the step 2 is completed, the thickness is sequentially deposited by sputtering or thermal evaporation.
- the source leaks the metal film.
- the source/drain metal film may be a metal or an alloy such as Cr, W, Cu, Ti, Ta, Mo, etc., and a gate metal layer composed of a plurality of layers of metal may also satisfy the needs.
- the source electrode 6, the drain electrode 7 and the data line are formed by a common photolithography process, and the dielectric of the drain metal electrode is etched away by etching the source of the metal electrode with the source and drain electrodes in the isolation region 10 corresponding to the source/drain electrode pattern.
- the location of the metal oxide semiconductor is shown in Figure 4.
- the metal oxide protective layer 8 may be a single layer of silicon oxide or a composite structure of silicon nitride and silicon oxide, or a three-layer structure of silicon nitride/silicon oxynitride/silicon oxide, wherein oxidation
- the reaction gas corresponding to silicon may be N 2 O and SiH 4 ;
- the reaction gas corresponding to silicon oxynitride may be N 2 O, SiH 4 , NH 3 and N 2 ;
- the reaction gas corresponding to silicon nitride may be SiH 4 , NH 3 And N 2 or SiH 2 Cl 2 , NH 3 and N 2 .
- a protective layer is formed on the source/drain electrode layer, and the contact via 12 for connecting the pixel electrode and the drain electrode is formed by the patterning process for the protective layer, as shown in FIG.
- Step 5 depositing the upper thickness by sputtering or thermal evaporation on the substrate on which step 4 is completed a transparent conductive layer
- the transparent conductive layer may be ITO or IZO, or other transparent metal oxide
- the transparent conductive layer is formed into a pixel electrode 9 by a photolithography process, and the cross-sectional view thereof is as shown in FIG.
- the technical scheme for fabricating a metal oxide TFT of the present disclosure adopts five photolithography processes, skillfully designing the structure of the TFT, and reducing the photolithography process by using a common mask, mainly using the pattern of the source and drain layers as a transparent metal oxide.
- a mask of the semiconductor layer forms a semiconductor layer pattern.
- This design not only reduces the lithography process, but also avoids the large-area etching process of the etch barrier layer, which is beneficial to improve production efficiency.
- the etch etch barrier layer is directly deposited after the deposition of the metal oxide semiconductor layer is completed, which is advantageous for forming a good interface and is advantageous for improving the metal oxide semiconductor measurement performance.
- the present disclosure also provides an array substrate, including:
- a metal oxide semiconductor layer and an etch barrier layer sequentially formed on the gate insulating layer
- the etch barrier layer is formed with an isolation region surrounding the source/drain electrode pattern, the metal oxide semiconductor layer being disconnected at a position corresponding to the isolation region.
- a protective layer is formed on the source/drain electrode layer, and the protective layer is formed with a contact via pattern for connecting the pixel electrode and the drain electrode.
- a data line is further formed on the etch barrier layer, and the data line is connected to a source in the source/drain electrode pattern.
- the present disclosure also provides a display device including the above array substrate.
- the display device uses any of the array substrates as described in the above embodiments.
- the display device may be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
- the array substrate fabricated according to the above technical solution is a metal oxide semiconductor in which an isolation region is removed by a source/drain electrode etching medium, thereby reducing one photolithography process.
- the method of fabricating the array substrate according to the embodiment of the present disclosure requires only the portion of the removed metal oxide semiconductor layer corresponding to the isolation region, corresponding to the etch barrier layer of the region other than the source/drain electrode pattern, thereby avoiding large The area is etched by the etch barrier to waste resources.
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Abstract
Description
Claims (10)
- 一种制作阵列基板的方法,包括以下步骤:步骤101:在栅绝缘层上依次形成金属氧化物半导体层和蚀刻阻挡层;步骤102:对蚀刻阻挡层进行一次构图工艺,形成源电极接触区过孔、漏电极接触区过孔以及隔离区;步骤103:在完成步骤102的蚀刻阻挡层上形成源漏电极层;以及步骤104:在对所述源漏电极层进行一次构图工艺形成源漏电极图案的过程中,去除金属氧化物半导体层与所述隔离区对应的部分,以使所述金属氧化物半导体层在与所述隔离区对应的位置断开,其中所述隔离区围绕在所述源漏电极图案周围。
- 根据权利要求1所述的方法,其中在对所述源漏电极层进行一次构图工艺形成源漏电极图案的过程中,通过源漏电极刻蚀介质去除金属氧化物半导体层与所述隔离区对应的部分。
- 根据权利要求1或2所述的方法,其中在栅绝缘层上依次形成金属氧化物半导体层和蚀刻阻挡层的步骤之前,还包括:在基板上形成栅金属膜,通过一次构图工艺形成栅电极图案;在所述栅电极上形成所述栅绝缘层;在所述栅绝缘层上形成所述金属氧化物半导体层,以及在所述金属氧化物半导体层上形成所述蚀刻阻挡层。
- 根据权利要求1-3任一项所述的方法,其中所述形成源漏电极层的步骤进一步包括:在完成步骤102的蚀刻阻挡层上形成金属膜,对所述金属膜进行一次构图工艺形成源电极图案、漏电极图案和数据线图案。
- 根据权利要求1-4任一项所述的方法,其中在完成步骤104之后,还包括:步骤105:在完成步骤104的源漏电极层上形成保护层,通过一次构图工艺形成用于连接像素电极和所述漏电极的接触过孔图案。
- 根据权利要求5所述的方法,其中在完成步骤105之后还包括:步骤106:在完成步骤105的保护层上形成导电层,对所述导电层进行一次构图工艺形成像素电极图案。
- 一种阵列基板,包括:依次形成在基板上的栅电极、栅绝缘层;依次形成在栅绝缘层上的金属氧化物半导体层和蚀刻阻挡层;形成在所述蚀刻阻挡层上的源漏电极层,其中所述蚀刻阻挡层形成有围绕源漏电极图案的隔离区,所述金属氧化物半导体层在与所述隔离区对应的位置断开。
- 根据权利要求7所述的阵列基板,其中在所述源漏电极层上形成有保护层,所述保护层形成有用于连接像素电极和所述漏电极的接触过孔图案。
- 根据权利要求7或8所述的阵列基板,其中所述蚀刻阻挡层上还形成有数据线,所述数据线与所述源漏电极图案中的源极连接。
- 一种显示装置,包括根据权利要求7-9任何一项所述的阵列基板。
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CN111725134A (zh) * | 2020-05-21 | 2020-09-29 | 南京中电熊猫液晶显示科技有限公司 | 一种阵列基板及其制造方法 |
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US9684217B2 (en) | 2017-06-20 |
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