WO2015043220A1 - 薄膜晶体管及其制备方法、阵列基板和显示装置 - Google Patents

薄膜晶体管及其制备方法、阵列基板和显示装置 Download PDF

Info

Publication number
WO2015043220A1
WO2015043220A1 PCT/CN2014/078859 CN2014078859W WO2015043220A1 WO 2015043220 A1 WO2015043220 A1 WO 2015043220A1 CN 2014078859 W CN2014078859 W CN 2014078859W WO 2015043220 A1 WO2015043220 A1 WO 2015043220A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulating layer
thin film
silicon oxide
film transistor
oxide film
Prior art date
Application number
PCT/CN2014/078859
Other languages
English (en)
French (fr)
Inventor
刘翔
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/408,493 priority Critical patent/US20160268440A1/en
Publication of WO2015043220A1 publication Critical patent/WO2015043220A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Definitions

  • Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, an array substrate, and a display device. Background technique
  • Flat panel displays have replaced bulky Cathode Ray Tube (CRT) displays that are increasingly in people's daily lives.
  • CTR Cathode Ray Tube
  • Currently, commonly used flat panel displays include Liquid Crystal Display (LCD) and Organic Light-Emitting Diode (OLED) displays.
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • the above two flat panel displays have the characteristics of small size, low power consumption, no radiation, etc., and occupy a dominant position in the current flat panel display market.
  • amorphous silicon thin film transistor generally about 0.5cm 2 / VS, a flat panel display sizes over 80 inches, the driving frequency needs more than lcm 2 / VS mobility rate of 120Hz, the mobility of an amorphous silicon thin film transistor apparently difficult Satisfy.
  • the uniformity of the polysilicon thin film transistor is poor, and the preparation process is complicated.
  • Metal oxide thin film transistors have high mobility, uniformity, transparency, simple preparation process, and can meet the high mobility requirements of large size, high refresh rate LCD and OLED displays.
  • silicon oxide (SiO X) of the gate insulating layer of metal oxide thin film transistor prepared material SiO ⁇ slow deposition rate, low etch rate, the thickness of the presence within the same interval SiO film defects such as uneven density mass.
  • SiO X silicon oxide
  • SiO ⁇ slow deposition rate
  • low etch rate the thickness of the presence within the same interval SiO film defects
  • the adverse effect of the defect becomes conspicuous, and the interface formed between the SiO x film and the metal oxide is in a defective state, thereby affecting the characteristics of the thin film transistor.
  • other insulating layers that are in contact with the metal oxide such as etch barriers, passivation layers, and the like, also present such problems. Summary of the invention
  • a thin film transistor includes an active layer And an insulating layer adjacent to the active layer.
  • the insulating layer includes a first insulating layer composed of a first silicon oxide film and a second silicon oxide film, and the second silicon oxide film is in direct contact with the active layer.
  • the denseness of the second silicon oxide film is greater than the denseness of the first silicon oxide film.
  • the first insulating layer has a thickness of 300 A - 1500 A.
  • the thickness of the second silicon oxide film is from 300 A to 800 A.
  • the insulating layer further includes a second insulating layer on a side opposite to a side of the first insulating layer on which the active layer is formed, and the second insulating layer is formed of a silicon nitride film , a silicon oxynitride film or a combination thereof.
  • the active layer is composed of a metal oxide semiconductor film.
  • the thin film transistor further includes a gate electrode, the insulating layer being located between the gate electrode and the active layer to serve as a gate insulating layer.
  • the insulating layer is over the active layer to serve as an etch stop.
  • an array substrate is provided.
  • the array substrate includes a thin film transistor as described above.
  • a display device includes the array substrate as described above.
  • a method of fabricating a thin film transistor includes an active layer and an insulating layer, and the insulating layer includes a first insulating layer composed of a first silicon oxide film and a second silicon oxide film.
  • the method includes a step of forming an active layer and a step of forming an insulating layer.
  • the step of forming the insulating layer includes: depositing the first silicon oxide film at a first rate and depositing the second silicon oxide film at a second rate, the second silicon oxide film is in direct contact with the active layer, and The second rate is less than the first rate.
  • the second rate is 1/5 to 4/5 of the first rate.
  • the device power is
  • the pressure is 1000-4000mT
  • the ratio of the reaction gas N 2 0/SiH 4 is 20:1 ⁇ 50:1
  • the deposition temperature is 200-300 °C.
  • the thin film transistor further includes a gate electrode, and the insulating layer is located between the gate electrode and the active layer to serve as a gate insulating layer.
  • the insulating layer is over the active layer to serve as an etch stop.
  • the insulating layer further includes a second insulating layer on a side opposite to a side of the first insulating layer on which the active layer is formed, and the second insulating layer is formed of a silicon nitride film , a silicon oxynitride film or a combination thereof.
  • FIG. 1 is a schematic structural diagram of a bottom gate thin film transistor according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a top gate thin film transistor according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural view of an array substrate of a bottom-gate thin film transistor for a germanium according to an embodiment of the present invention
  • FIG. 4 is a schematic cross-sectional view of the array substrate shown in FIG. 3 at A-B. detailed description
  • the embodiment of the invention provides a thin film transistor to solve the problem that the interface formed between the insulating layer of the thin film transistor and the metal oxide constituting the active layer has a defect state, thereby affecting the characteristics of the thin film transistor.
  • the thin film transistor provided by the embodiment of the invention may be a bottom gate type structure or a top gate type structure.
  • the thin film transistor includes a gate 2, a semiconductor layer 4, a gate insulating layer 3 between the gate 2 and the semiconductor layer 4, and a semiconductor.
  • the gate insulating layer 3 includes a first insulating layer, the first insulating layer is composed of a first silicon oxide film 31 and a second silicon oxide film 32, and a second silicon oxide film 32 is formed over the first silicon oxide film, the second silicon oxide film 32 is in direct contact with the semiconductor layer 4; wherein the denseness of the second silicon oxide film 32 is greater than the density of the first silicon oxide film 31.
  • the thin film transistor includes a gate electrode 2, a semiconductor layer 4, and a gate insulating layer 3 (not labeled in FIG. 2, refer to FIG. 1), and a source electrode 6 And drain 7.
  • the gate insulating layer 3 includes a first insulating layer, the first insulating layer is composed of a first silicon oxide film 31 and a second silicon oxide film 32, and the second silicon oxide film 32 is formed under the first silicon oxide film.
  • the second silicon oxide film 32 is in direct contact with the semiconductor layer 4; wherein the denseness of the second silicon oxide film 32 is greater than the density of the first silicon oxide film 31.
  • the thickness of the second silicon oxide film 32 is 300 A - 800 A, and the sum of the thicknesses of the first silicon oxide film 31 and the second silicon oxide film 32 is 300 A - 1500 A.
  • the gate insulating layer 3 may further include a second insulating layer (not shown).
  • the second insulating layer is located on a side opposite to the side of the first insulating layer on which the active layer is formed. For example, in Figs. 1 and 2, the second insulating layer is located between the first insulating layer 3 and the gate 2.
  • the second insulating layer may be formed of silicon nitride, silicon oxynitride, or an inorganic insulating material having the same or similar properties as silicon nitride or silicon oxynitride.
  • the second insulating layer is composed of a silicon nitride film and a silicon oxynitride film; for example, the second insulating layer is composed of a silicon nitride film; and, for example, the second insulating layer is composed of a silicon oxynitride film.
  • the second insulating layer has a strong ability to prevent diffusion of water molecules and metal ions, and can effectively prevent water molecules or metal ions from diffusing into the active layer, thereby improving the characteristics of the thin film transistor.
  • the etching rate of silicon nitride or silicon oxynitride forming the second insulating layer is fast with respect to the silicon oxide forming the first insulating material, and thus the gate insulating layer is passed through the gate insulating layer 3 to form via holes.
  • the inclusion of the second insulating layer in 3 can improve the etching efficiency and avoid the influence of long-time etching on the performance of the active layer.
  • the first insulating layer and any of the second insulating layers exemplified above constitute the gate insulating layer 3.
  • the gate insulating layer 3 may have an overall thickness of 2000 A to 5000 A. It is to be noted that the above is merely illustrative, and the present invention is not limited thereto.
  • the above description is only for the case where the insulating layer is a gate insulating layer, and the insulating layer may also be an etch barrier layer, a passivation layer, or the like, which will not be described herein.
  • the insulating layer of the thin film transistor includes at least a first insulating layer, and the first insulating layer includes a first silicon oxide film and a second silicon oxide film having different densities;
  • the large second silicon oxide film is in direct contact with the semiconductor layer, and forms a good interface with the metal oxide constituting the semiconductor layer, thereby improving the characteristics of the thin film transistor.
  • Embodiments of the present invention provide an array substrate including the thin film transistor as provided in the above embodiments.
  • the array substrate includes: a substrate 1, followed by a gate electrode 2 and a gate line 11 on the substrate 1, a gate insulating layer 3, a semiconductor layer 4, an etch barrier layer 5, a source electrode 6, a drain electrode 7 and a data line 12, a passivation layer 8 and a via hole 10, And the pixel electrode 9.
  • the semiconductor layer 4 is a metal oxide.
  • the gate insulating layer 3 includes a first insulating layer composed of a first silicon oxide film 31 and a second silicon oxide film 32, and the second silicon oxide film 32 is in direct contact with the semiconductor layer 4, wherein the denseness of the second silicon oxide film 32 is greater than The density of the first silicon oxide film 31.
  • the first insulating layer has a thickness of 300 A - 1500 A.
  • the thickness of the second silicon oxide film is from 300 A to 800 A.
  • the gate insulating layer 3 further includes a second gate insulating layer composed of a silicon nitride film and/or a silicon oxynitride film.
  • the gate line 11 and the gate 2 are disposed on the same layer.
  • the gate line 11 and the gate 2 are made of metal Cr,
  • At least one of W, Cu, Ti, Ta, and Mo is formed and has a thickness of between 4000 A and 15000 A.
  • the semiconductor layer 4 is a metal oxide, and may be indium gallium oxide (IGZO), yttrium indium oxide (HIZO), indium oxide (IZO), amorphous indium oxide (InZnO), ZnO:F, At 2 0 3 : at least one of semiconductor oxides having semiconductor properties such as Sn, In 2 0 3 :Mo, Cd 2 Sn0 4 , ZnO:Al, Ti0 2 :Nb, and Cd-Sn-0, - enumeration.
  • IGZO indium gallium oxide
  • HZO yttrium indium oxide
  • IZO indium oxide
  • InZnO amorphous indium oxide
  • ZnO:F ZnO:F
  • At 2 0 3 at least one of semiconductor oxides having semiconductor properties such as Sn, In 2 0 3 :Mo, Cd 2 Sn0 4 , ZnO:Al, Ti0 2 :Nb, and Cd-Sn
  • the etch barrier layer 5 and the passivation layer 8 are one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, or a composite structure of the at least two films, an etch barrier layer 5 and a passivation layer 8
  • the thickness is 1000 A ⁇ 3000A. It is of course also possible to use a structure such as the gate insulating layer 3, that is, a structure of a two-layer silicon oxide film.
  • a person skilled in the art can change the etch barrier layer 5 and the passivation layer 8 according to the structure description of the gate insulating layer 3, which is still within the protection scope of the present invention, and the examples are not repeated here.
  • the source 6, drain 7, and data line 11 are disposed on the same layer.
  • they may be formed of at least one of metals such as Cr, W, Cu, Ti, Ta, and Mo.
  • the pixel electrode 9 may be indium tin oxide (ITO), indium oxide (IZO) or other transparent conductive metal oxide, having a thickness of, for example, 300 A to 1000 A, and the pixel electrode 9 passes through the via 10 and the source.
  • ITO indium tin oxide
  • IZO indium oxide
  • the beneficial effects of the embodiments of the present invention are as follows:
  • the thin film transistor included in the array substrate has an insulating layer including at least a first insulating layer, and the first insulating layer includes a first silicon oxide film and a second silicon oxide film of different densities;
  • the large second silicon oxide film is in direct contact with the semiconductor layer, and forms a good interface with the metal oxide constituting the semiconductor layer, thereby improving the characteristics of the thin film transistor.
  • the embodiment of the invention provides a display device, which comprises the array substrate provided by the above embodiments.
  • Embodiments of the present invention provide a method of fabricating a thin film transistor for fabricating a thin film transistor as described above, the thin film transistor including an active layer and an insulating layer, the insulating layer including a first silicon oxide film and a second oxide A first insulating layer composed of a silicon film.
  • the method includes: a step of forming a semiconductor layer and a step of forming an insulating layer.
  • the step of forming an insulating layer includes: depositing the first silicon oxide film at a first rate and depositing the second silicon oxide film in direct contact with the semiconductor layer at a second rate, wherein the second The rate is less than the first rate.
  • the first silicon oxide film and the second silicon oxide film are layered, and the dense silicon dioxide film is in direct contact with the semiconductor layer to form a good interface with the metal oxide constituting the semiconductor layer;
  • the faster deposition rate of the first silicon oxide film ensures the speed and productivity of the TFT fabrication process.
  • the device power is 8000-15000 W
  • the gas pressure is 1000-4000 mT
  • the ratio of the reaction gas N 2 0/SiH 4 is 20:1 to 50:1, deposition.
  • the temperature is 200-300 °C.
  • the device power is 4000-8000 W
  • the gas pressure is 500-1000 mT
  • the ratio of the reaction gas N 2 /Si is 50:1 to 90:1
  • the deposition temperature is 250. -400 °C.
  • the second rate is 1/5 to 4/5 of the first rate.
  • the insulating layer may be a gate insulating layer or an etch barrier layer in contact with the active layer.
  • the active layer is formed of a metal oxide.
  • a method of fabricating a thin film transistor according to an embodiment of the present invention further includes: a step of forming a gate, and a step of forming a source and a drain.
  • the beneficial effects of the embodiments of the present invention are as follows:
  • the insulating layer deposited by the thin film transistor with different deposition rates includes a first silicon oxide film and a second silicon oxide film, and the second silicon oxide film deposited at a lower rate and constitutes an active layer.
  • Layer metal oxide direct contact, low deposition rate deposition of second oxidation
  • the silicon thin film has higher compactness and less internal defects than the first silicon oxide film deposited at a high deposition rate; therefore, the second silicon oxide film can form a good interface with the metal oxide, thereby improving the characteristics of the thin film transistor.
  • a method for preparing a thin film transistor including a bottom gate structure, an insulating layer as a gate insulating layer, and only a first insulating layer will be described as an example.
  • the preparation steps are as follows:
  • the first metal thin film may be at least one of the metals Cr, W, Cu, Ti, Ta, and Mo, and the deposited thickness is between 4,000 ⁇ and 15,000 ⁇ .
  • a first silicon oxide film is deposited by a first rate deposition, and a second silicon oxide film is deposited by a second rate to form a first insulating layer of the gate insulating layer.
  • the second rate is less than the first rate.
  • the second rate is 1/5 ⁇ 4/5 of the first rate, and the specific value is selected according to the actual situation.
  • the device power is 8000-15000 W
  • the gas pressure is 1000-4000 mT
  • the ratio of N 2 0/SiH 4 is 20:1 to 50:1
  • the deposition temperature is 200 ⁇ . 300 °C.
  • the device power is 4000-8000 W
  • the gas pressure is 500-1000 mT
  • the ratio of N 2 O/SiH 4 is 50:1 to 90:1
  • the deposition temperature is 250 ⁇ . 400 °C.
  • deposition conditions are for illustrative purposes only, and are not limiting of the embodiments of the present invention, and the deposition conditions may be set according to actual application conditions.
  • the thickness of the second silicon oxide film is 300 A to 800 A, and the total thickness of the first silicon oxide film and the second silicon oxide film is 300 A to 1500 A.
  • the active layer is a metal oxide material
  • the metal oxide material is IGZO, HIZO, IZO, a-InZnO, ZnO:F, In 2 0 3 :Sn, In 2 0 3 :Mo, Cd 2 Sn0 4 , ZnO: Al, Ti0 2 : Nb or Cd-Sn-0.
  • the etch stop layer formed in step 104 it may be one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, or a composite structure of at least two of the above films.
  • the etch barrier layer has a thickness of 1000 A to 3000 A. It is of course also possible to use a structure such as a gate insulating layer, that is, a structure of two silicon oxide films. A person skilled in the art can change the etch barrier layer according to the structure description of the above-mentioned gate insulating layer, which is still within the protection scope of the present invention, and the examples are not repeated here.
  • the preparation of the thin film transistor of the top gate type structure those skilled in the art can refer to the structure of the thin film transistor of the top gate structure shown in FIG. 2 and the method for preparing the thin film transistor of the bottom gate type structure, which will not be repeated here. For example.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管及其制备方法、阵列基板和显示装置。该薄膜晶体管包括有源层(4)和与所述有源层(4)相邻的绝缘层(3)。所述绝缘层(3) 包括第一绝缘层，所述第一绝缘层由第一氧化硅薄膜(31)和第二氧化硅薄膜(32)组成，所述第二氧化硅薄膜(32)与所述有源层(4)直接接触。所述第二氧化硅薄膜(32)的致密性大于所述第一氧化硅薄膜(31)的致密性。第二氧化硅薄膜(32)与有源层(4)之间可以形成良好的界面，从而减少了缺陷态，提高了薄膜晶体管特性。

Description

薄膜晶体管及其制备方法、 阵列基板和显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管及其制备方法、 阵列基板和显示装 置。 背景技术
平板显示器已取代笨重的阴极射线管（ Cathode Ray Tube, CRT )显示器 日益深入人们的日常生活中。 目前， 常用的平板显示器包括液晶显示器 (Liquid Crystal Display , LCD)和有机发光二极管 (Organic Light-Emitting Diode, OLED)显示器。 上述两种平板显示器具有体积小、 功耗低、 无辐射等 特点， 在当前的平板显示器市场中占据了主导地位。
随着平板显示器的飞速发展， 其尺寸和分辨率不断地提高， 同时也造成 了驱动电路的频率不断地提高。 非晶硅薄膜晶体管的迁移率一般在 0.5cm2/V.S左右， 平板显示器尺寸超过 80英寸、 驱动频率为 120Hz时需要 lcm2/V.S以上的迁移率， 显然非晶硅薄膜晶体管的迁移率很难满足。 尽管对 多晶硅薄膜晶体管研究比较早， 但是多晶硅薄膜晶体管的均匀性差， 制备工 艺复杂。 金属氧化物薄膜晶体管迁移率高， 均匀性好， 透明， 制备工艺简单， 并且可以艮好地满足大尺寸， 高刷新频率 LCD及 OLED显示器对高迁移率 的需求。
通常， 使用氧化硅 ( SiOx )材料制备金属氧化物薄膜晶体管的栅绝缘层， 但是 SiO^ 积速度慢， 刻蚀速率低， 同一厚度区间的 SiO 膜内部存在质 密度不均匀等缺陷。 随着 SiOx薄膜厚度的增加， 缺陷带来的不利影响变得明 显， 使得 SiOx薄膜与金属氧化物所形成的界面存在缺陷态， 从而影响到薄膜 晶体管的特性。 同样的， 与金属氧化物相接触的其他绝缘层， 例如刻蚀阻挡 层、 钝化层等也存在这样的问题。 发明内容
根据本发明的实施例， 提供一种薄膜晶体管。 该薄膜晶体管包括有源层 和与所述有源层相邻的绝缘层。 所述绝缘层包括第一绝缘层， 所述第一绝缘 层由第一氧化硅薄膜和第二氧化硅薄膜组成， 所述第二氧化硅薄膜与所述有 源层直接接触。 所述第二氧化硅薄膜的致密性大于所述第一氧化硅薄膜的致 密性。
例如， 所述第一绝缘层的厚度为 300 A -1500 A。
例如， 所述第二氧化硅薄膜的厚度为 300 A -800 A。
例如， 所述绝缘层还包括第二绝缘层， 所述第二绝缘层位于与第一绝缘 层的形成有有源层的一侧相反的一侧， 所述第二绝缘层由氮化硅薄膜、 氮氧 化硅薄膜或它们的组合组成。
例如， 所述有源层由金属氧化物半导体薄膜组成。
例如， 所述薄膜晶体管还包括栅极， 所述绝缘层位于所述栅极和所述有 源层之间以用作栅绝缘层。
例如， 所述绝缘层位于所述有源层的上方以用作蚀刻阻挡层。
根据本发明的实施例， 提供一种阵列基板。 该阵列基板包括如上所述的 薄膜晶体管。
根据本发明的实施例， 提供一种显示装置。 该显示装置包括如上所述所 述的阵列基板。
根据本发明的实施例， 提供一种薄膜晶体管的制备方法。 所述薄膜晶体 管包括有源层和绝缘层， 所述绝缘层包括由第一氧化硅薄膜和第二氧化硅薄 膜组成的第一绝缘层。所述方法包括形成有源层的步骤和形成绝缘层的步骤。 所述形成绝缘层的步骤包括： 釆用第一速率沉积所述第一氧化硅薄膜以及釆 用第二速率沉积所述第二氧化硅薄膜， 第二氧化硅薄膜与有源层直接接触， 并且所述第二速率小于所述第一速率。
例如， 所述第二速率为所述第一速率的 1/5 ~ 4/5。
例如， 釆用第一速率沉积所述第一氧化硅薄膜时， 设备功率为
8000-15000W，气压为 1000-4000mT，反应气体 N20/SiH4的比例为 20:1 ~ 50:1, 沉积温度为 200-300 °C。
例如， 釆用第二速率沉积第二氧化硅薄膜时， 设备功率为 4000-8000W, 气压为 500-1000mT， 反应气体 N20/Si 的比例为 50: 1 ~ 90: 1， 沉积温度为 250-400 °C。 例如， 所述薄膜晶体管还包括栅极， 所述绝缘层位于所述栅极和所述有 源层之间以用作栅绝缘层。
例如， 所述绝缘层位于所述有源层的上方以用作蚀刻阻挡层。
例如， 所述绝缘层还包括第二绝缘层， 所述第二绝缘层位于与第一绝缘 层的形成有有源层的一侧相反的一侧， 所述第二绝缘层由氮化硅薄膜、 氮氧 化硅薄膜或它们的组合组成。
附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例提供的底栅型薄膜晶体管的结构示意图；
图 2为本发明实施例提供的顶栅型薄膜晶体管的结构示意图；
图 3为本发明实施例提供的釆用底栅型薄膜晶体管的阵列基板的结构示 意图； 以及
图 4为图 3所示阵列基板在 A-B处的剖面示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图， 对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例提供一种薄膜晶体管， 以解决薄膜晶体管的绝缘层与构成 有源层的金属氧化物之间形成的界面存在缺陷态， 从而影响到薄膜晶体管的 特性的问题。 本发明实施例提供的薄膜晶体管可以为底栅型结构， 也可以为 顶栅型结构。
参见图 1， 示出了本发明实施例提供的底栅型结构的薄膜晶体管， 薄膜 晶体管包括栅极 2、半导体层 4、位于栅极 2和半导体层 4之间的栅绝缘层 3、 位于半导体层 4上方的刻蚀阻挡层 5、源极 6和漏极 7。所述栅绝缘层 3包括 第一绝缘层， 所述第一绝缘层由第一氧化硅薄膜 31和第二氧化硅薄膜 32组 成，第二氧化硅薄膜 32形成于第一氧化硅薄膜的上方，所述第二氧化硅薄膜 32与所述半导体层 4直接接触； 其中， 所述第二氧化硅薄膜 32的致密性大 于所述第一氧化硅薄膜 31的致密性。
参见图 2， 示出了本发明实施例提供的顶栅型结构的薄膜晶体管， 薄膜 晶体管包括栅极 2、 半导体层 4、 栅绝缘层 3 (图 2未标注， 参考图 1 ) 、 源 极 6和漏极 7。 所述栅绝缘层 3包括第一绝缘层， 所述第一绝缘层由第一氧 化硅薄膜 31和第二氧化硅薄膜 32组成，第二氧化硅薄膜 32形成于第一氧化 硅薄膜的下方， 所述第二氧化硅薄膜 32与所述半导体层 4直接接触； 其中， 所述第二氧化硅薄膜 32的致密性大于所述第一氧化硅薄膜 31的致密性。
例如， 第二氧化硅薄膜 32的厚度为 300 A -800 A， 所述第一氧化硅薄膜 31和所述第二氧化硅薄膜 32的厚度之和为 300 A -1500 A。
所述栅绝缘层 3还可以包括第二绝缘层（图中未示出） 。 第二绝缘层位 于与第一绝缘层的形成有有源层的一侧相反的一侧。例如，在图 1和图 2中， 第二绝缘层位于第一绝缘层 3和栅极 2之间。 第二绝缘层可以釆用氮化硅、 氮氧化硅、 或者和氮化硅或氮氧化硅特性相同或相近的无机绝缘材料形成。 例如， 所述第二绝缘层由氮化硅薄膜和氮氧化硅薄膜组成； 又例如所述第二 绝缘层由氮化硅薄膜组成； 又例如， 所述第二绝缘层由氮氧化硅薄膜组成。 第二绝缘层防止水分子和金属离子扩散的能力强， 能有效地避免水分子或金 属离子扩散到有源层， 提高薄膜晶体管的特性。 另外， 相对于形成第一绝缘 材料的氧化硅， 形成第二绝缘层的氮化硅或氮氧化硅的蚀刻速率快， 因此在 蚀刻栅绝缘层 3以形成过孔的情形下， 通过栅绝缘层 3中包括第二绝缘层可 以提高蚀刻效率， 并避免长时间蚀刻对有源层性能的影响。
第一绝缘层和上述例举的任一种第二绝缘层构成栅绝缘层 3。栅绝缘层 3 包括第二绝缘层时， 栅绝缘层 3的总体厚度可以为 2000 A ~ 5000A。 需要说 明的是， 上述只是举例说明， 本发明并不限于此。
此外， 对于本发明实施例中的薄膜晶体管， 以上仅对绝缘层为栅绝缘层 的情况进行详述， 绝缘层还可以为刻蚀阻挡层、 钝化层等， 在此不再赘述。
本发明实施例有益效果如下：薄膜晶体管的绝缘层至少包括第一绝缘层， 第一绝缘层包括致密性不同的第一氧化硅薄膜和第二氧化硅薄膜； 致密性较 大的第二氧化硅薄膜与半导体层直接接触， 与构成半导体层的金属氧化物之 间形成良好的界面， 提高薄膜晶体管特性。
本发明实施例提供一种阵列基板，包括如上述实施例提供的薄膜晶体管。 以底栅型结构的薄膜晶体管为例， 参见图 3示出的该阵列基板的俯视图、 图 4示出的在图 3所示阵列基板 A-B处的剖面图， 该阵列基板包括： 基板 1、 依次位于基板 1 上的栅极 2及栅极线 11、 栅绝缘层 3、 半导体层 4、 刻蚀阻 挡层 5 、 源极 6、 漏极 7及数据线 12、钝化层 8及过孔 10、 以及像素电极 9。 半导体层 4为金属氧化物。栅绝缘层 3包括由第一氧化硅薄膜 31和第二氧化 硅薄膜 32组成的第一绝缘层， 第二氧化硅薄膜 32和半导体层 4直接接触， 其中第二氧化硅薄膜 32的致密性大于第一氧化硅薄膜 31的致密性。
例如， 第一绝缘层的厚度为 300 A -1500 A。
例如， 第二氧化硅薄膜的厚度为 300 A -800 A。
例如，栅绝缘层 3还包括由氮化硅薄膜和 /或氮氧化硅薄膜组成的第二栅 绝缘层。
栅极线 11和栅极 2设置于同一层。例如，栅极线 11和栅极 2由金属 Cr、
W、 Cu、 Ti、 Ta和 Mo中的至少一种形成， 厚度在 4000 A ~ 15000A之间。
半导体层 4为金属氧化物， 可以为铟镓辞氧化物（IGZO )、 铪铟辞氧化 物（HIZO ) 、 铟辞氧化物（IZO ) 、 非晶铟辞氧化物 -InZnO ) 、 ZnO:F、 In203:Sn、 In203:Mo、 Cd2Sn04、 ZnO:Al、 Ti02:Nb和 Cd-Sn-0等具有半导体 性质的金属氧化物中的至少一种， 在此不——列举。
刻蚀阻挡层 5和钝化层 8为氧化硅薄膜、 氮化硅薄膜和氮氧化硅薄膜中 的一种， 或是上述至少两种薄膜的复合结构， 刻蚀阻挡层 5和钝化层 8的厚 度均为 1000 A ~ 3000A。 当然也可以釆用如栅绝缘层 3的结构， 即两层氧化 硅薄膜的结构。 本领域技术人员可以根据上述栅绝缘层 3的结构描述对刻蚀 阻挡层 5和钝化层 8进行变动， 这仍在本发明保护范围内， 在此不再重复举 例。
源极 6、 漏极 7和数据线 11设置于同一层。 例如， 它们可以由 Cr、 W、 Cu、 Ti、 Ta和 Mo等金属中的至少一种形成。
像素电极 9可以为铟锡氧化物（ITO )、 铟辞氧化物（IZO )或其他透明 导电金属氧化物， 厚度例如为 300 A ~ 1000A, 像素电极 9通过过孔 10与源 本发明实施例有益效果如下： 阵列基板所包括的薄膜晶体管， 其绝缘层 至少包括第一绝缘层， 第一绝缘层包括不同致密性的第一氧化硅薄膜和第二 氧化硅薄膜； 致密性较大的第二氧化硅薄膜与半导体层直接接触， 与构成半 导体层的金属氧化物之间形成良好的界面， 提高薄膜晶体管特性。
本发明实施例提供一种显示装置， 包括如上述实施例提供的阵列基板。 本发明实施例提供一种薄膜晶体管的制备方法， 用于制备如上所述的薄 膜晶体管， 所述薄膜晶体管包括有源层和绝缘层， 所述绝缘层包括由第一氧 化硅薄膜和第二氧化硅薄膜组成的第一绝缘层。 所述方法包括： 形成半导体 层的步骤和形成绝缘层的步骤。 所述形成绝缘层的步骤包括： 釆用第一速率 沉积所述第一氧化硅薄膜以及釆用第二速率沉积与所述半导体层直接接触的 所述第二氧化硅薄膜， 其中所述第二速率小于所述第一速率。
釆用第一氧化硅薄膜和第二氧化硅薄膜的分层制作， 致密性较大的第二 氧化硅薄膜与半导体层直接接触， 与构成半导体层的金属氧化物之间形成良 好的界面； 而第一氧化硅薄膜釆用较快的沉积速率可以保证 TFT制备工艺的 速度和产能。
例如， 釆用第一速率沉积所述第一氧化硅薄膜时， 设备功率为 8000-15000W，气压为 1000-4000mT，反应气体 N20/SiH4的比例为 20:1 ~ 50:1, 沉积温度为 200-300 °C。
例如， 釆用第二速率沉积第二氧化硅薄膜时， 设备功率为 4000-8000W, 气压为 500-1000mT， 反应气体 N20/Si 的比例为 50: 1 ~ 90: 1， 沉积温度为 250-400 °C。
例如， 所述第二速率为所述第一速率的 1/5 ~ 4/5。
例如， 所述绝缘层可以为与有源层接触的栅绝缘层或蚀刻阻挡层。
例如， 所述有源层由金属氧化物形成。
例如， 根据本发明实施例的薄膜晶体管的制备方法还包括： 形成栅极的 步骤、 形成源极和漏极的步骤。
本发明实施例有益效果如下： 薄膜晶体管的釆用不同的沉积速率沉积的 绝缘层包括第一氧化硅薄膜和第二氧化硅薄膜， 釆用较低速率沉积的第二氧 化硅薄膜与构成有源层的金属氧化物直接接触， 低沉积速率沉积的第二氧化 硅薄膜比高沉积速率沉积的第一氧化硅薄膜致密性较大， 内部缺陷较少； 因 此第二氧化硅薄膜可以与金属氧化物之间形成良好的界面， 从而提高薄膜晶 体管特性。
为了更清楚的说明本发明实施例提供的薄膜晶体管的制备方法， 下面将 以底栅型结构、 绝缘层为栅绝缘层、 且仅包括第一绝缘层的薄膜晶体管的制 备方法为例进行描述， 制备步骤如下：
101、 在基板上沉积第一金属薄膜， 通过一次构图工艺形成栅极。
例如， 第一金属薄膜可以为金属 Cr、 W、 Cu、 Ti、 Ta和 Mo中的至少一 种， 沉积的厚度在 4000 A ~ 15000A之间。
102、釆用第一速率沉积形成第一氧化硅薄膜，釆用第二速率沉积形成第 二氧化硅薄膜， 从而形成栅绝缘层的第一绝缘层。 所述第二速率小于所述第 一速率。
例如， 第二速率为第一速率的 1/5 ~ 4/5， 具体取值根据实际情况进行选 择。
例如，釆用第一速率沉积第一氧化硅薄膜时，设备功率为 8000-15000W, 气压为 1000-4000mT， N20/SiH4的比例为 20:1 ~ 50:1, 沉积温度为 200 ~ 300 °C。
例如， 釆用第二速率沉积第二氧化硅薄膜时， 设备功率为 4000-8000W, 气压为 500-1000mT，N2O/SiH4的比例为 50:1 ~ 90:1，沉积温度为 250 ~ 400 °C。
当然以上沉积条件只是为了进行说明， 并非对本发明实施例的限制， 沉 积条件可根据实际应用情况进行设定。
例如， 所述第二氧化硅薄膜的厚度为 300 A ~ 800A， 第一氧化硅薄膜和 第二氧化硅薄膜的总厚度为 300 A ~ 1500A。
103、沉积有源层薄膜，通过构图工艺形成有源层。 第二氧化硅薄膜与所 述有源层薄膜直接接触。
例如， 所述有源层为金属氧化物材料， 所述金属氧化物材料为 IGZO、 HIZO、 IZO、 a-InZnO、 ZnO:F、 In203:Sn、 In203:Mo、 Cd2Sn04、 ZnO:Al、 Ti02:Nb 或 Cd-Sn-0。
104、 沉积刻蚀阻挡层薄膜， 通过一次构图工艺形成刻蚀阻挡层。
105、 沉积第二金属薄膜， 通过一次构图工艺形成源电极和漏电极。 对于步骤 104形成的刻蚀阻挡层， 其可以为氧化硅薄膜、 氮化硅薄膜和 氮氧化硅薄膜中的一种， 或是上述至少两种薄膜的复合结构。 例如， 刻蚀阻 挡层的厚度为 1000 A ~ 3000A。 当然也可以釆用如栅绝缘层的结构， 即两层 氧化硅薄膜的结构。 本领域技术人员可以根据上述栅绝缘层的结构描述对刻 蚀阻挡层进行变动， 这仍在本发明保护范围内， 在此不再重复举例。
对于顶栅型结构的薄膜晶体管的制备， 本领域技术人员可以参考图 2所 示的顶栅型结构的薄膜晶体管的结构、 以及上述底栅型结构的薄膜晶体管的 制备方法， 在此不再重复举例。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。
相关申请的交叉引用
本申请要求于 2013年 9月 26日递交的第 201310446633.0号中国专利申 请的优先权，在此全文引用上述中国专利申请的内容以作为本申请的一部分。

Claims

权利要求书
1、 一种薄膜晶体管， 包括有源层和与所述有源层相邻的绝缘层， 其中 所述绝缘层包括第一绝缘层， 所述第一绝缘层由第一氧化硅薄膜和第二 氧化硅薄膜组成， 所述第二氧化硅薄膜与所述有源层直接接触； 并且
所述第二氧化硅薄膜的致密性大于所述第一氧化硅薄膜的致密性。
2、 如权利要求 1所述的薄膜晶体管， 其中所述第一绝缘层的厚度为 300 A -1500 A。
3、如权利要求 2所述的薄膜晶体管，其中所述第二氧化硅薄膜的厚度为 300 A -800 A。
4、如权利要求 1-3任一项所述的薄膜晶体管， 其中所述绝缘层还包括第 二绝缘层， 所述第二绝缘层位于与第一绝缘层的形成有有源层的一侧相反的 一侧， 所述第二绝缘层由氮化硅薄膜、 氮氧化硅薄膜或它们的组合组成。
5、如权利要求 1-3任一项所述的薄膜晶体管， 其中所述有源层由金属氧 化物半导体薄膜组成。
6、如权利要求 1-3任一项所述的薄膜晶体管， 其中所述薄膜晶体管还包 括栅极， 所述绝缘层位于所述栅极和所述有源层之间以用作栅绝缘层。
7、如权利要求 1-3任一项所述的薄膜晶体管， 其中所述绝缘层位于所述 有源层的上方以用作蚀刻阻挡层。
8、 一种阵列基板， 包括如权利要求 1-7任一项所述的薄膜晶体管。
9、 一种显示装置， 包括如权利要求 8所述的阵列基板。
10、一种薄膜晶体管的制备方法，所述薄膜晶体管包括有源层和绝缘层， 所述绝缘层包括由第一氧化硅薄膜和第二氧化硅薄膜组成的第一绝缘层， 所 述方法包括形成有源层的步骤和形成绝缘层的步骤， 其中
所述形成绝缘层的步骤包括： 釆用第一速率沉积所述第一氧化硅薄膜以 及釆用第二速率沉积所述第二氧化硅薄膜， 第二氧化硅薄膜与有源层直接接 触， 并且所述第二速率小于所述第一速率。
11、 如权利要求 10 所述的方法， 其中所述第二速率为所述第一速率的 1/5 ~ 4/5。
12、 如权利要求 10或 11所述的方法，其中釆用第一速率沉积所述第一 氧化硅薄膜时， 设备功率为 8000-15000W， 气压为 1000-4000mT， 反应气体 N20/SiH4的比例为 20:1 ~ 50:1, 沉积温度为 200-300 °C。
13、 如权利要求 10或 11所述的方法，其中釆用第二速率沉积第二氧化 硅薄膜时，设备功率为 4000-8000W，气压为 500-1000mT，反应气体 N20/SiH4 的比例为 50:1 ~ 90:1 , 沉积温度为 250-400 °C。
14、 如权利要求 10-13任一项所述的方法， 其中所述薄膜晶体管还包括 栅极， 所述绝缘层位于所述栅极和所述有源层之间以用作栅绝缘层。
15、 如权利要求 10-14任一项所述的方法， 其中所述绝缘层位于所述有 源层的上方以用作蚀刻阻挡层。
16、 如权利要求 10-15任一项所述的方法， 其中所述绝缘层还包括第二 绝缘层， 所述第二绝缘层位于与第一绝缘层的形成有有源层的一侧相反的一 侧， 所述第二绝缘层由氮化硅薄膜、 氮氧化硅薄膜或它们的组合组成。
PCT/CN2014/078859 2013-09-26 2014-05-29 薄膜晶体管及其制备方法、阵列基板和显示装置 WO2015043220A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/408,493 US20160268440A1 (en) 2013-09-26 2014-05-29 Thin film transistor and fabrication method thereof, array substrate and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310446633.0A CN103489920B (zh) 2013-09-26 2013-09-26 一种薄膜晶体管及其制备方法、阵列基板和显示装置
CN201310446633.0 2013-09-26

Publications (1)

Publication Number Publication Date
WO2015043220A1 true WO2015043220A1 (zh) 2015-04-02

Family

ID=49830015

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/078859 WO2015043220A1 (zh) 2013-09-26 2014-05-29 薄膜晶体管及其制备方法、阵列基板和显示装置

Country Status (3)

Country Link
US (1) US20160268440A1 (zh)
CN (1) CN103489920B (zh)
WO (1) WO2015043220A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103489920B (zh) * 2013-09-26 2016-08-17 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示装置
CN105826250B (zh) * 2016-05-17 2018-11-30 京东方科技集团股份有限公司 薄膜晶体管、阵列基板、显示装置及薄膜晶体管制作方法
CN106128940B (zh) * 2016-08-15 2019-01-22 武汉华星光电技术有限公司 一种低温多晶硅薄膜的制备方法
CN107591411A (zh) * 2017-07-06 2018-01-16 惠科股份有限公司 一种显示面板和显示装置
CN107644880B (zh) * 2017-10-19 2020-04-14 京东方科技集团股份有限公司 氧化物薄膜晶体管显示基板及其制作方法、显示装置
CN110914749B (zh) * 2017-10-26 2022-03-29 深圳市柔宇科技有限公司 感光电路、感光电路制备方法及显示装置
CN109545690A (zh) * 2018-12-03 2019-03-29 惠科股份有限公司 薄膜晶体管结构及其制作方法、显示装置
CN109786440A (zh) * 2018-12-25 2019-05-21 惠科股份有限公司 阵列基板的制造方法、装置及阵列基板
CN109817724A (zh) * 2019-02-01 2019-05-28 武汉华星光电半导体显示技术有限公司 阵列基板和阵列基板的制造方法
CN110212071B (zh) * 2019-05-22 2020-07-07 华灿光电（浙江）有限公司 发光二极管芯片及其制作方法
CN110416228A (zh) * 2019-07-31 2019-11-05 云谷（固安）科技有限公司 显示面板及显示装置
CN113161292B (zh) * 2021-04-12 2023-04-25 北海惠科光电技术有限公司 阵列基板的制作方法、阵列基板及显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1188243A (zh) * 1996-12-09 1998-07-22 株式会社半导体能源研究所 有源矩阵显示器件及其制作方法
JP2000012863A (ja) * 1998-06-19 2000-01-14 Sanyo Electric Co Ltd 薄膜トランジスタ及びそれを用いた表示装置
US20060145158A1 (en) * 2005-01-04 2006-07-06 Samsung Electronics Co., Ltd. Poly-crystalline silicon thin film transistor
CN102646595A (zh) * 2011-11-11 2012-08-22 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、显示器件
CN103199111A (zh) * 2012-01-10 2013-07-10 三星显示有限公司 半导体器件及其制造方法
CN103489920A (zh) * 2013-09-26 2014-01-01 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW523931B (en) * 2001-02-20 2003-03-11 Hitachi Ltd Thin film transistor and method of manufacturing the same
JP2008012863A (ja) * 2006-07-07 2008-01-24 Ricoh Co Ltd 画像形成装置
JP2011222767A (ja) * 2010-04-09 2011-11-04 Sony Corp 薄膜トランジスタならびに表示装置および電子機器
US9362313B2 (en) * 2012-05-09 2016-06-07 Kobe Steel, Ltd. Thin film transistor and display device
CN103000628B (zh) * 2012-12-14 2015-04-22 京东方科技集团股份有限公司 显示装置、阵列基板及其制作方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1188243A (zh) * 1996-12-09 1998-07-22 株式会社半导体能源研究所 有源矩阵显示器件及其制作方法
JP2000012863A (ja) * 1998-06-19 2000-01-14 Sanyo Electric Co Ltd 薄膜トランジスタ及びそれを用いた表示装置
US20060145158A1 (en) * 2005-01-04 2006-07-06 Samsung Electronics Co., Ltd. Poly-crystalline silicon thin film transistor
CN102646595A (zh) * 2011-11-11 2012-08-22 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、显示器件
CN103199111A (zh) * 2012-01-10 2013-07-10 三星显示有限公司 半导体器件及其制造方法
CN103489920A (zh) * 2013-09-26 2014-01-01 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示装置

Also Published As

Publication number Publication date
CN103489920A (zh) 2014-01-01
CN103489920B (zh) 2016-08-17
US20160268440A1 (en) 2016-09-15

Similar Documents

Publication Publication Date Title
WO2015043220A1 (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
JP5766467B2 (ja) 薄膜トランジスタ及びその製造方法、表示装置
TWI575087B (zh) 製造氧化物薄膜電晶體陣列之方法以及含有氧化物薄膜電晶體陣列之裝置
WO2016041304A1 (zh) 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置
JP5015472B2 (ja) 薄膜トランジスタ及びその製法
WO2019010960A1 (zh) 阵列基板及其制备方法、显示面板、显示装置
WO2018010214A1 (zh) 金属氧化物薄膜晶体管阵列基板的制作方法
JP2013232619A (ja) 表示装置、アレイ基板、薄膜トランジスタ及びその製造方法
TWI405335B (zh) 半導體結構及其製造方法
WO2012144165A1 (ja) 薄膜トランジスタ、表示パネル及び薄膜トランジスタの製造方法
TWI478355B (zh) 薄膜電晶體
WO2016086531A1 (zh) 阵列基板及其制作方法
CN104218094B (zh) 一种薄膜晶体管、显示基板及显示装置
WO2014166160A1 (zh) 薄膜晶体管及其制造方法、阵列基板和显示装置
US8119465B1 (en) Thin film transistor and method for fabricating the same
JP2011091110A (ja) 酸化物半導体素子を用いた回路及びその製造方法、並びに表示装置
WO2013170605A1 (zh) 薄膜晶体管阵列基板及其制造方法、显示面板、显示装置
WO2013097554A1 (zh) Tft阵列基板的制造方法
WO2018152875A1 (zh) 薄膜晶体管的制作方法、薄膜晶体管及显示器
WO2013063971A1 (zh) 薄膜晶体管阵列基板
JP2017508275A (ja) 低温ポリシリコン薄膜トランジスタ及びその製造方法
WO2013086909A1 (zh) 阵列基板及其制造方法、显示装置
WO2014131258A1 (zh) 氧化物薄膜晶体管及其制备方法、阵列基板和显示装置
US20150311345A1 (en) Thin film transistor and method of fabricating the same, display substrate and display device
WO2015096307A1 (zh) 氧化物薄膜晶体管、显示器件、及阵列基板的制造方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14408493

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14849515

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 05.09.2016)

122 Ep: pct application non-entry in european phase

Ref document number: 14849515

Country of ref document: EP

Kind code of ref document: A1