WO2018010214A1 - 金属氧化物薄膜晶体管阵列基板的制作方法 - Google Patents

金属氧化物薄膜晶体管阵列基板的制作方法 Download PDF

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WO2018010214A1
WO2018010214A1 PCT/CN2016/091824 CN2016091824W WO2018010214A1 WO 2018010214 A1 WO2018010214 A1 WO 2018010214A1 CN 2016091824 W CN2016091824 W CN 2016091824W WO 2018010214 A1 WO2018010214 A1 WO 2018010214A1
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layer
metal oxide
drain
thin film
film transistor
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PCT/CN2016/091824
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French (fr)
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向舟翊
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深圳市华星光电技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/2605—Bombardment with radiation using natural radiation, e.g. alpha, beta or gamma radiation
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a metal oxide thin film transistor array substrate.
  • flat panel display devices are widely used in mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, desktop computers, etc. due to their high image quality, power saving, thin body and wide application range.
  • Various consumer electronic products have become the mainstream in display devices.
  • TFT Thin Film Transistor
  • LCD liquid crystal display
  • AMOLED Active Matrix Organic Light-Emitting Diode
  • the thin film transistor has various structures, and the material of the active layer of the thin film transistor for preparing the corresponding structure is also various, wherein the metal oxide TFT has high field effect mobility ( ⁇ 10 cm 2 /V ⁇ s).
  • the preparation process is simple, the uniformity of large-area deposition is good, the response speed is fast, and the transmittance in the visible light range is high. It is considered to be the most promising backplane technology for the development of the display in the direction of large size and flexibility, but In order to improve the electrical and stability of the metal oxide thin film transistor, a high temperature annealing process is required, which limits its application in the flexible direction.
  • the carrier forms a conductive channel at the interface between the insulating layer and the active layer.
  • the channel resistance is negligible compared to the contact resistance, and the total resistance mainly depends on the contact of the device.
  • the resistance that is, the magnitude of the contact resistance at this time affects the source-drain current in the saturation region, which in turn affects the field-effect mobility of the saturation region of the device. How to reduce the contact resistance is an important direction to improve the electrical properties of the device.
  • the metal oxide thin film transistor of the conventional bottom gate structure since the overlapping area between the gate and the source and drain electrodes is large, a large parasitic capacitance is generated, which causes a delay of the signal, and the transistor which is fabricated has a large size. Limit its application.
  • the top gate self-aligned structure has lower parasitic capacitance and better ductility due to no overlap between the source and drain electrodes and the gate.
  • An object of the present invention is to provide a metal oxide thin film transistor array substrate
  • the method is to treat the active layer by illumination to improve the defects of the low temperature deposited film, thereby improving the conductivity of the source and drain contact regions, increasing the carrier concentration of the channel region, and improving the electrical properties of the device.
  • the present invention provides a method for fabricating a metal oxide thin film transistor array substrate, comprising the following steps:
  • Step 1 Providing a substrate, sequentially depositing a buffer layer and a metal oxide semiconductor layer on the substrate, patterning the metal oxide semiconductor layer to obtain an active layer, and then performing the active layer in an air environment Performing a first illumination treatment to increase the carrier concentration of the active layer;
  • Step 2 sequentially depositing an insulating layer and a gate metal layer on the buffer layer and the active layer, and patterning the insulating layer and the gate metal layer to obtain a gate and a gate insulating layer;
  • the gate layer and the gate insulating layer are used as a barrier layer, and the active layer is subjected to a second illumination treatment in an air environment such that the gate layer and the gate insulating layer are not on the active layer.
  • the conductive region of the covered region is enhanced to form a source contact region, a drain contact region, and a channel region between the source contact region and the drain contact region;
  • Step 3 depositing an interlayer dielectric layer on the gate electrode, the active layer, and the buffer layer, patterning the interlayer dielectric layer, and forming corresponding layers on the interlayer dielectric layer respectively a first via hole and a second via hole of the source contact region and the drain contact region;
  • Step 4 depositing a source/drain metal layer on the interlayer dielectric layer, patterning the source and drain metal layers to obtain a source and a drain, and the source and drain respectively pass through the first pass
  • the hole and the second via are in contact with the source contact region and the drain contact region of the active layer
  • Step 5 depositing a passivation layer on the interlayer dielectric layer, the source, and the drain, patterning the passivation layer, and forming a corresponding layer on the passivation layer corresponding to the drain A three-via hole is formed on the passivation layer, and the pixel electrode is in contact with the drain through the third via hole, thereby fabricating a metal oxide thin film transistor array substrate.
  • the active layer is subjected to illumination treatment using ultraviolet light, microwave, or infrared light.
  • the active layer is subjected to illumination treatment using ultraviolet light having a wavelength of 185 nm to 254 nm.
  • the active layer is subjected to illumination treatment using an excimer laser.
  • the material of the metal oxide semiconductor layer is indium gallium zinc oxide, indium tin zinc oxide, or zinc oxide.
  • the metal oxide semiconductor layer is deposited by a physical vapor deposition method or a gel solution method at room temperature.
  • the insulating layer, the interlayer dielectric layer, and the passivation layer are made of silicon oxide, aluminum oxide, and nitride. Aluminum, or yttrium oxide.
  • the insulating layer, the interlayer dielectric layer, and the passivation layer are deposited by chemical vapor deposition, atomic layer deposition, or physical vapor deposition.
  • the material of the gate, source, and drain is a stacked combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the material of the pixel electrode is indium tin oxide.
  • the invention also provides a method for fabricating a metal oxide thin film transistor array substrate, comprising the following steps:
  • Step 1 Providing a substrate, sequentially depositing a buffer layer and a metal oxide semiconductor layer on the substrate, patterning the metal oxide semiconductor layer to obtain an active layer, and then performing the active layer for the first time Illumination treatment, such that the carrier concentration of the active layer is increased;
  • Step 2 sequentially depositing an insulating layer and a gate metal layer on the buffer layer and the active layer, and patterning the insulating layer and the gate metal layer to obtain a gate and a gate insulating layer;
  • the gate layer and the gate insulating layer are used as a barrier layer, and the active layer is subjected to a second illumination treatment in an air environment such that the gate layer and the gate insulating layer are not on the active layer.
  • the conductive region of the covered region is enhanced to form a source contact region, a drain contact region, and a channel region between the source contact region and the drain contact region;
  • Step 3 depositing an interlayer dielectric layer on the gate electrode, the active layer, and the buffer layer, patterning the interlayer dielectric layer, and forming corresponding layers on the interlayer dielectric layer respectively a first via hole and a second via hole of the source contact region and the drain contact region;
  • Step 4 depositing a source/drain metal layer on the interlayer dielectric layer, patterning the source and drain metal layers to obtain a source and a drain, and the source and drain respectively pass through the first pass
  • the hole and the second via are in contact with the source contact region and the drain contact region of the active layer
  • Step 5 depositing a passivation layer on the interlayer dielectric layer, the source, and the drain, patterning the passivation layer, and forming a corresponding layer on the passivation layer corresponding to the drain a three-via hole, a pixel electrode is formed on the passivation layer, and the pixel electrode is in contact with the drain through the third via hole, thereby preparing a metal oxide thin film transistor array substrate;
  • the material of the insulating layer, the interlayer dielectric layer, and the passivation layer is silicon oxide, aluminum oxide, aluminum nitride, or tantalum oxide;
  • the insulating layer, the interlayer dielectric layer, and the passivation layer are deposited by chemical vapor deposition, atomic layer deposition, or physical vapor deposition;
  • the material of the gate, the source, and the drain is a stacked combination of one or more of molybdenum, titanium, aluminum, and copper;
  • the material of the pixel electrode is indium tin oxide.
  • the present invention provides a method for fabricating a metal oxide thin film transistor array substrate.
  • the thin film transistor adopts a top gate coplanar structure, which can effectively reduce parasitic capacitance, and separately processes the active layer by using two illumination methods.
  • the insulating layer and the gate metal layer are patterned to expose the exposed region of the active layer to improve the defects of the low temperature deposited film, so that the carrier concentration of the channel region is increased, and the conductivity of the source and drain contact regions is enhanced, thereby The contact resistance of the source, the drain and the active layer is lowered, the mobility and the current switching ratio are improved, and the electrical properties of the thin film transistor are improved.
  • FIG. 1 is a schematic flow chart of a method for fabricating a metal oxide thin film transistor array substrate of the present invention
  • 2-3 is a schematic diagram of the first step of the method for fabricating the metal oxide thin film transistor array substrate of the present invention.
  • FIGS. 4-5 are schematic diagrams showing the second step of the method for fabricating the metal oxide thin film transistor array substrate of the present invention.
  • step 3 is a schematic diagram of step 3 of a method for fabricating a metal oxide thin film transistor array substrate of the present invention
  • step 4 is a schematic diagram of step 4 of a method for fabricating a metal oxide thin film transistor array substrate of the present invention.
  • FIG. 8 is a schematic view showing the fifth step of the method for fabricating the metal oxide thin film transistor array substrate of the present invention.
  • the present invention provides a method for fabricating a metal oxide thin film transistor array substrate, comprising the following steps:
  • Step 1 as shown in FIG. 2-3, a substrate 10 is provided, and a buffer layer 20 and a metal oxide semiconductor layer 30 are sequentially deposited on the substrate 10, and the metal oxide semiconductor layer 30 is patterned.
  • the source layer 35 is then subjected to a first illumination treatment of the active layer 35 such that the carrier concentration of the active layer 35 is increased.
  • the material of the metal oxide semiconductor layer 30 is indium gallium zinc oxide (IGZO), Indium tin zinc oxide (ITZO), zinc oxide (ZnO), or other transparent metal oxide materials.
  • IGZO indium gallium zinc oxide
  • ITZO Indium tin zinc oxide
  • ZnO zinc oxide
  • the metal oxide semiconductor layer 30 is deposited by a method of depositing a film at a low temperature, preferably a physical vapor deposition (PVD) method, or a gel solution method.
  • PVD physical vapor deposition
  • Step 2 As shown in FIG. 4-5, an insulating layer 40 and a gate metal layer 50 are sequentially deposited on the buffer layer 20 and the active layer 35, and the insulating layer 40 and the gate metal layer 50 are patterned. Processing to obtain the gate 55 and the gate insulating layer 45;
  • the gate layer 55 and the gate insulating layer 45 are used as a barrier layer, and the active layer 35 is subjected to a second illumination treatment in an air environment such that the gate layer 55 is not on the active layer 35.
  • the conductivity of the region covered with the gate insulating layer 45 is enhanced to form a source contact region 351, a drain contact region 352, and a channel region 353 between the source contact region 351 and the drain contact region 352.
  • the carrier concentration of the active layer 35 is increased, that is, the channel region 353 of the active layer 35 is loaded.
  • the concentration of the carrier is increased to increase the switching ratio of the thin film transistor; in the step 2, the active layer 35 is subjected to a second illumination treatment to make the source contact region 351 and the drain contact region on the active layer 35.
  • the conductivity of 352 is enhanced, and the contact resistance between source 71 and drain 72 and source contact region 351 and drain contact region 352 is reduced; therefore, the electrical properties of the thin film transistor are improved.
  • the active layer 35 is subjected to illumination treatment by using ultraviolet light, microwave, or infrared light, and the specific illumination treatment time and the illumination energy intensity are adjusted according to the optimal electrical properties of the device;
  • the ultraviolet light used includes ultraviolet light of 185 nm to 254 nm, and excimer laser light.
  • the active layer 35 is subjected to illumination treatment using ultraviolet light having a wavelength of 185 nm to 254 nm.
  • the basic principle of enhancing the conductivity of the source contact region 351 and the drain contact region 352 by illumination is: by illuminating the exposed region on the active layer 35 in an air environment, the light wave is made in the air.
  • the water (H 2 O) is decomposed into hydroxide ions (OH - ) and hydrogen ions (H + ), thereby increasing the source contact region 351 of the active layer 35 and the hydroxide in the drain contact region 352.
  • the ion concentration in turn, enhances its conductivity.
  • Step 3 as shown in FIG. 6, an interlayer dielectric layer 60 is deposited on the gate electrode 55, the active layer 35, and the buffer layer 20, and the interlayer dielectric layer 60 is patterned.
  • a first via hole 61 and a second via hole 62 respectively corresponding to the source contact region 351 and the drain contact region 352 are formed on the interlayer dielectric layer 60.
  • Step 4 depositing a source/drain metal layer on the interlayer dielectric layer 60, and patterning the source and drain metal layers to obtain a source 71 and a drain 72, the source The pole 71 and the drain 72 are in contact with the source contact region 351 and the drain contact region 352 of the active layer 35 through the first via 61 and the second via 62, respectively.
  • Step 5 as shown in FIG. 8, a passivation layer 80 is deposited on the interlayer dielectric layer 60, the source 71, and the drain 72, and the passivation layer 80 is patterned to be in the passivation layer.
  • a third via 81 corresponding to the drain 72 is formed on the 80, a pixel electrode 90 is formed on the passivation layer 80, and the pixel electrode 90 is in contact with the drain 72 through the third via 81.
  • a metal oxide thin film transistor array substrate was produced.
  • the insulating layer 40, the material of the interlayer dielectric layer 60 and passivation layer 80 is silicon oxide (SiO x), aluminum oxide (AlO x), aluminum nitride (AlN x), or hafnium oxide ( HfO 2 ).
  • the insulating layer 40, the interlayer dielectric layer 60, and the passivation layer 80 are subjected to a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, an Atomic layer deposition (ALD) method, or a physics. Deposited by vapor deposition.
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • ALD Atomic layer deposition
  • physics Deposited by vapor deposition.
  • the material of the gate 55, the source 71, and the drain 72 is a stack combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu). .
  • the material of the pixel electrode 90 is indium tin oxide (ITO).
  • the present invention provides a method for fabricating a metal oxide thin film transistor array substrate.
  • the thin film transistor adopts a top gate coplanar structure, which can effectively reduce parasitic capacitance, and separately processes the active layer and the insulation by using two illumination methods.
  • a region in which the active layer is exposed after the layer and the gate metal layer are patterned to improve defects of the low temperature deposited film, increase carrier concentration in the channel region, and increase conductivity of the source and drain contact regions, thereby reducing
  • the contact resistance of the source, the drain and the active layer improves the mobility and current switching ratio, thereby improving the electrical properties of the thin film transistor.

Abstract

本发明提供一种金属氧化物薄膜晶体管阵列基板的制作方法，薄膜晶体管采用顶栅共面结构，能够有效降低寄生电容，并利用两次光照的方法分别处理有源层、绝缘层与栅极金属层图案化后有源层暴露的区域，来改善低温沉积膜的缺陷，增加沟道区的载流子浓度，增强源、漏极接触区导电性，从而降低了源、漏极与有源层的接触电阻，提高了迁移率和电流开关比，进而提高了薄膜晶体管的电性。

Description

金属氧化物薄膜晶体管阵列基板的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种金属氧化物薄膜晶体管阵列基板的制作方法。
背景技术
在显示技术领域，平板显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
薄膜晶体管(Thin Film Transistor，TFT)是目前液晶显示装置(Liquid Crystal Display，LCD)和有源矩阵驱动式有机电致发光显示装置(Active Matrix Organic Light-Emitting Diode，简称AMOLED)中的主要驱动元件，直接关系到高性能平板显示装置的发展方向。
薄膜晶体管具有多种结构，制备相应结构的薄膜晶体管有源层的材料也具有多种，其中，金属氧化物薄膜晶体管(metal oxide TFT)具有场效应迁移率高(≥10cm2/V·s)、制备工艺简单、大面积沉积均匀性好、响应速度快、及可见光范围内透过率高等特点，被认为是显示器朝着大尺寸、及柔性化方向发展的最有潜力的背板技术，但是为了提高金属氧化物薄膜晶体管的电性和稳定性，需要进行高温退火制程，限制了其在柔性方向的应用。
金属氧化物薄膜晶体管器件工作在饱和区时，载流子在绝缘层与有源层界面处形成导电沟道，此时沟道电阻相比于接触电阻可以忽略，总电阻主要取决于器件的接触电阻，即此时接触电阻的大小影响饱和区的源漏电流，进而影响器件的饱和区场效应迁移率，如何降低接触电阻是改善器件电性的一个重要方向。
传统底栅结构的金属氧化物薄膜晶体管，由于栅极与源漏电极之间重叠面积较大，产生了较大的寄生电容，会导致信号的延迟，且其制作出来的晶体管尺寸较大，因而限制了其应用。顶栅自对准结构由于源漏电极之间与栅极之间没有重叠，因此具有更低的寄生电容和更好的延展性。
发明内容
本发明的目的在于提供一种金属氧化物薄膜晶体管阵列基板的制作方 法，通过光照的方式处理有源层，来改善低温沉积膜的缺陷，从而提高源、漏极接触区的导电性，增加沟道区的载流子浓度，提高器件电性。
为实现上述目的，本发明提供一种金属氧化物薄膜晶体管阵列基板的制作方法，包括如下步骤：
步骤1、提供一基板，在所述基板上依次沉积缓冲层、及金属氧化物半导体层，对该金属氧化物半导体层进行图案化处理得到有源层，然后在空气环境中对该有源层进行第一次光照处理，使得所述有源层的载流子浓度增加；
步骤2、在所述缓冲层、及有源层上依次沉积绝缘层、及栅极金属层，对该绝缘层、及栅极金属层进行图案化处理得到栅极与栅极绝缘层；
以所述栅极、及栅极绝缘层为阻挡层，在空气环境中对所述有源层进行第二次光照处理，使得所述有源层上未被所述栅极与栅极绝缘层覆盖的区域的导电性增强，形成源极接触区、漏极接触区、以及位于所述源极接触区与漏极接触区之间的沟道区；
步骤3、在所述栅极、有源层、及缓冲层上沉积层间介电层，对该层间介电层进行图案化处理，在所述层间介电层上形成分别对应于所述源极接触区与漏极接触区的第一通孔与第二通孔；
步骤4、在所述层间介电层上沉积源漏极金属层，对该源漏极金属层进行图案化处理，得到源极与漏极，所述源极和漏极分别通过第一通孔和第二通孔与所述有源层的源极接触区和漏极接触区相接触；
步骤5、在所述层间介电层、源极、及漏极上沉积钝化层，对该钝化层进行图案化处理，在所述钝化层上形成对应于所述漏极的第三通孔，在所述钝化层上形成像素电极，所述像素电极通过第三通孔与所述漏极相接触，从而制得一金属氧化物薄膜晶体管阵列基板。
所述步骤1和步骤2中采用紫外光、微波、或者红外光对所述有源层进行光照处理。
所述步骤1和步骤2中采用波长为185nm-254nm的紫外光对所述有源层进行光照处理。
所述步骤1和步骤2中采用准分子激光对所述有源层进行光照处理。
所述金属氧化物半导体层的材料为铟镓锌氧化物、铟锡锌氧化物、或氧化锌。
所述金属氧化物半导体层通过物理气相沉积法、或凝胶溶液法在室温下沉积得到。
所述绝缘层、层间介电层、及钝化层的材料为氧化硅、氧化铝、氮化 铝、或氧化铪。
所述绝缘层、层间介电层、及钝化层通过化学气相沉积法、原子层沉积、或物理气相沉积法沉积得到。
所述栅极、源极、及漏极的材料为钼、钛、铝、及铜中的一种或多种的堆栈组合。
所述像素电极的材料为氧化铟锡。
本发明还提供一种金属氧化物薄膜晶体管阵列基板的制作方法，包括如下步骤：
步骤1、提供一基板，在所述基板上依次沉积缓冲层、及金属氧化物半导体层，对该金属氧化物半导体层进行图案化处理得到有源层，然后对该有源层进行第一次光照处理，使得所述有源层的载流子浓度增加；
步骤2、在所述缓冲层、及有源层上依次沉积绝缘层、及栅极金属层，对该绝缘层、及栅极金属层进行图案化处理得到栅极与栅极绝缘层；
以所述栅极、及栅极绝缘层为阻挡层，在空气环境中对所述有源层进行第二次光照处理，使得所述有源层上未被所述栅极与栅极绝缘层覆盖的区域的导电性增强，形成源极接触区、漏极接触区、以及位于所述源极接触区与漏极接触区之间的沟道区；
步骤3、在所述栅极、有源层、及缓冲层上沉积层间介电层，对该层间介电层进行图案化处理，在所述层间介电层上形成分别对应于所述源极接触区与漏极接触区的第一通孔与第二通孔；
步骤4、在所述层间介电层上沉积源漏极金属层，对该源漏极金属层进行图案化处理，得到源极与漏极，所述源极和漏极分别通过第一通孔和第二通孔与所述有源层的源极接触区和漏极接触区相接触；
步骤5、在所述层间介电层、源极、及漏极上沉积钝化层，对该钝化层进行图案化处理，在所述钝化层上形成对应于所述漏极的第三通孔，在所述钝化层上形成像素电极，所述像素电极通过第三通孔与所述漏极相接触，从而制得一金属氧化物薄膜晶体管阵列基板；
其中，所述绝缘层、层间介电层、及钝化层的材料为氧化硅、氧化铝、氮化铝、或氧化铪；
其中，所述绝缘层、层间介电层、及钝化层通过化学气相沉积法、原子层沉积、或物理气相沉积法沉积得到；
其中，所述栅极、源极、及漏极的材料为钼、钛、铝、及铜中的一种或多种的堆栈组合；
其中，所述像素电极的材料为氧化铟锡。
本发明的有益效果：本发明提供一种金属氧化物薄膜晶体管阵列基板的制作方法，薄膜晶体管采用顶栅共面结构，能够有效降低寄生电容，并利用两次光照的方法分别处理有源层、绝缘层与栅极金属层图案化后有源层暴露的区域，来改善低温沉积膜的缺陷，使得沟道区的载流子浓度增加，并使得源、漏极接触区的导电性增强，从而降低了源、漏极与有源层的接触电阻，提高了迁移率和电流开关比，进而提高了薄膜晶体管的电性。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为本发明的金属氧化物薄膜晶体管阵列基板的制作方法的流程示意图；
图2-3为本发明的金属氧化物薄膜晶体管阵列基板的制作方法的步骤1的示意图；
图4-5为本发明的金属氧化物薄膜晶体管阵列基板的制作方法的步骤2的示意图；
图6为本发明的金属氧化物薄膜晶体管阵列基板的制作方法的步骤3的示意图；
图7为本发明的金属氧化物薄膜晶体管阵列基板的制作方法的步骤4的示意图；
图8为本发明的金属氧化物薄膜晶体管阵列基板的制作方法的步骤5的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种金属氧化物薄膜晶体管阵列基板的制作方法，包括如下步骤：
步骤1、如图2-3所示，提供一基板10，在所述基板10上依次沉积缓冲层20、及金属氧化物半导体层30，对该金属氧化物半导体层30进行图案化处理得到有源层35，然后对该有源层35进行第一次光照处理，使得所述有源层35的载流子浓度增加。
具体地，所述金属氧化物半导体层30的材料为铟镓锌氧化物(IGZO)、 铟锡锌氧化物(ITZO)、氧化锌(ZnO)、或其他透明的金属氧化物材料。
具体地，所述金属氧化物半导体层30通过低温沉积膜的方法沉积得到，优选物理气相沉积(Physical Vapor Deposition，PVD)法、或凝胶溶液法。
步骤2、如图4-5所示，在所述缓冲层20、有源层35上依次沉积绝缘层40、及栅极金属层50，对该绝缘层40、及栅极金属层50进行图案化处理得到栅极55与栅极绝缘层45；
以所述栅极55、及栅极绝缘层45为阻挡层，在空气环境中对所述有源层35进行第二次光照处理，使得所述有源层35上未被所述栅极55与栅极绝缘层45覆盖的区域的导电性增强，形成源极接触区351、漏极接触区352、以及位于所述源极接触区351与漏极接触区352之间的沟道区353。
具体地，所述步骤1中对有源层35进行第一次光照处理后，使得所述有源层35的载流子浓度增加，即使得所述有源层35的沟道区353的载流子浓度增加，提高了薄膜晶体管的开关比；所述步骤2中对有源层35进行第二次光照处理，使得所述有源层35上的源极接触区351、及漏极接触区352的导电性增强，降低了源极71、及漏极72分别与源极接触区351、及漏极接触区352的接触电阻；因此，提高了薄膜晶体管的电性。
具体地，所述步骤1和步骤2中采用紫外光、微波、或者红外光对所述有源层35进行光照处理，具体光照处理时间和光照能量强度随器件取得最佳电性而做调整；所采用的紫外光包括185nm-254nm的紫外光、和准分子激光。优选地，所述步骤1和步骤2中采用波长为185nm-254nm的紫外光对所述有源层35进行光照处理。
需要说明的是，通过光照使得源极接触区351、及漏极接触区352的导电性增强的基本原理为：通过在空气环境中对有源层35上露出的区域进行光照，光波使空气中的水(H2O)分解成氢氧根离子(OH-)和氢离子(H+)，从而提高了有源层35的源极接触区351、及漏极接触区352中的氢氧根离子浓度，进而使其导电性得以增强。
步骤3、如图6所示，在所述栅极55、有源层35、及缓冲层20上沉积层间介电层60，对该层间介电层60进行图案化处理，在所述层间介电层60上形成分别对应于所述源极接触区351与漏极接触区352的第一通孔61与第二通孔62。
步骤4、如图7所示，在所述层间介电层60上沉积源漏极金属层，对该源漏极金属层进行图案化处理，得到源极71与漏极72，所述源极71和漏极72分别通过第一通孔61和第二通孔62与所述有源层35的源极接触区351和漏极接触区352相接触。
步骤5、如图8所示，在所述层间介电层60、源极71及漏极72上沉积钝化层80，对该钝化层80进行图案化处理，在所述钝化层80上形成对应于所述漏极72的第三通孔81，在所述钝化层80上形成像素电极90，所述像素电极90通过第三通孔81与所述漏极72相接触，从而制得一金属氧化物薄膜晶体管阵列基板。
具体地，所述绝缘层40、层间介电层60、及钝化层80的材料为氧化硅(SiOx)、氧化铝(AlOx)、氮化铝(AlNx)、或氧化铪(HfO2)。
具体地，所述绝缘层40、层间介电层60、及钝化层80通过化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)法、原子层沉积(Atomic layer deposition，ALD)法、或物理气相沉积法沉积得到。
具体地，所述栅极55、源极71、及漏极72的材料为钼(Mo)、钛(Ti)、铝(Al)、及铜(Cu)中的一种或多种的堆栈组合。
具体地，所述像素电极90的材料为氧化铟锡(ITO)。
综上所述，本发明提供一种金属氧化物薄膜晶体管阵列基板的制作方法，薄膜晶体管采用顶栅共面结构，能够有效降低寄生电容，并利用两次光照的方法分别处理有源层、绝缘层与栅极金属层图案化后有源层暴露的区域，来改善低温沉积膜的缺陷，使得沟道区的载流子浓度增加，并使得源、漏极接触区的导电性增强，从而降低了源、漏极与有源层的接触电阻，提高了迁移率和电流开关比，进而了提高薄膜晶体管的电性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (16)

  1. 一种金属氧化物薄膜晶体管阵列基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在所述基板上依次沉积缓冲层、及金属氧化物半导体层，对该金属氧化物半导体层进行图案化处理得到有源层，然后对该有源层进行第一次光照处理，使得所述有源层的载流子浓度增加；
    步骤2、在所述缓冲层、及有源层上依次沉积绝缘层、及栅极金属层，对该绝缘层、及栅极金属层进行图案化处理得到栅极与栅极绝缘层；
    以所述栅极、及栅极绝缘层为阻挡层，在空气环境中对所述有源层进行第二次光照处理，使得所述有源层上未被所述栅极与栅极绝缘层覆盖的区域的导电性增强，形成源极接触区、漏极接触区、以及位于所述源极接触区与漏极接触区之间的沟道区；
    步骤3、在所述栅极、有源层、及缓冲层上沉积层间介电层，对该层间介电层进行图案化处理，在所述层间介电层上形成分别对应于所述源极接触区与漏极接触区的第一通孔与第二通孔；
    步骤4、在所述层间介电层上沉积源漏极金属层，对该源漏极金属层进行图案化处理，得到源极与漏极，所述源极和漏极分别通过第一通孔和第二通孔与所述有源层的源极接触区和漏极接触区相接触；
    步骤5、在所述层间介电层、源极、及漏极上沉积钝化层，对该钝化层进行图案化处理，在所述钝化层上形成对应于所述漏极的第三通孔，在所述钝化层上形成像素电极，所述像素电极通过第三通孔与所述漏极相接触，从而制得一金属氧化物薄膜晶体管阵列基板。
  2. 如权利要求1所述的金属氧化物薄膜晶体管阵列基板的制作方法，其中，所述步骤1和步骤2中采用紫外光、微波、或者红外光对所述有源层进行光照处理。
  3. 如权利要求2所述的金属氧化物薄膜晶体管阵列基板的制作方法，其中，所述步骤1和步骤2中采用波长为185nm-254nm的紫外光对所述有源层进行光照处理。
  4. 如权利要求2所述的金属氧化物薄膜晶体管阵列基板的制作方法，其中，所述步骤1和步骤2中采用准分子激光对所述有源层进行光照处理。
  5. 如权利要求1所述的金属氧化物薄膜晶体管阵列基板的制作方法，其中，所述金属氧化物半导体层的材料为铟镓锌氧化物、铟锡锌氧化物、或氧化锌。
  6. 如权利要求1所述的金属氧化物薄膜晶体管阵列基板的制作方法，其中，所述金属氧化物半导体层通过物理气相沉积法、或凝胶溶液法在室温下沉积得到。
  7. 如权利要求1所述的金属氧化物薄膜晶体管阵列基板的制作方法，其中，所述绝缘层、层间介电层、及钝化层的材料为氧化硅、氧化铝、氮化铝、或氧化铪。
  8. 如权利要求1所述的金属氧化物薄膜晶体管阵列基板的制作方法，其中，所述绝缘层、层间介电层、及钝化层通过化学气相沉积法、原子层沉积、或物理气相沉积法沉积得到。
  9. 如权利要求1所述的金属氧化物薄膜晶体管阵列基板的制作方法，其中，所述栅极、源极、及漏极的材料为钼、钛、铝、及铜中的一种或多种的堆栈组合。
  10. 如权利要求1所述的金属氧化物薄膜晶体管阵列基板的制作方法，其中，所述像素电极的材料为氧化铟锡。
  11. 一种金属氧化物薄膜晶体管阵列基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在所述基板上依次沉积缓冲层、及金属氧化物半导体层，对该金属氧化物半导体层进行图案化处理得到有源层，然后对该有源层进行第一次光照处理，使得所述有源层的载流子浓度增加；
    步骤2、在所述缓冲层、及有源层上依次沉积绝缘层、及栅极金属层，对该绝缘层、及栅极金属层进行图案化处理得到栅极与栅极绝缘层；
    以所述栅极、及栅极绝缘层为阻挡层，在空气环境中对所述有源层进行第二次光照处理，使得所述有源层上未被所述栅极与栅极绝缘层覆盖的区域的导电性增强，形成源极接触区、漏极接触区、以及位于所述源极接触区与漏极接触区之间的沟道区；
    步骤3、在所述栅极、有源层、及缓冲层上沉积层间介电层，对该层间介电层进行图案化处理，在所述层间介电层上形成分别对应于所述源极接触区与漏极接触区的第一通孔与第二通孔；
    步骤4、在所述层间介电层上沉积源漏极金属层，对该源漏极金属层进行图案化处理，得到源极与漏极，所述源极和漏极分别通过第一通孔和第二通孔与所述有源层的源极接触区和漏极接触区相接触；
    步骤5、在所述层间介电层、源极、及漏极上沉积钝化层，对该钝化层进行图案化处理，在所述钝化层上形成对应于所述漏极的第三通孔，在所述钝化层上形成像素电极，所述像素电极通过第三通孔与所述漏极相接触，从而制得一金属氧化物薄膜晶体管阵列基板；
    其中，所述绝缘层、层间介电层、及钝化层的材料为氧化硅、氧化铝、氮化铝、或氧化铪；
    其中，所述绝缘层、层间介电层、及钝化层通过化学气相沉积法、原子层沉积、或物理气相沉积法沉积得到；
    其中，所述栅极、源极、及漏极的材料为钼、钛、铝、及铜中的一种或多种的堆栈组合；
    其中，所述像素电极的材料为氧化铟锡。
  12. 如权利要求11所述的金属氧化物薄膜晶体管阵列基板的制作方法，其中，所述步骤1和步骤2中采用紫外光、微波、或者红外光对所述有源层进行光照处理。
  13. 如权利要求12所述的金属氧化物薄膜晶体管阵列基板的制作方法，其中，所述步骤1和步骤2中采用波长为185nm-254nm的紫外光对所述有源层进行光照处理。
  14. 如权利要求12所述的金属氧化物薄膜晶体管阵列基板的制作方法，其中，所述步骤1和步骤2中采用准分子激光对所述有源层进行光照处理。
  15. 如权利要求11所述的金属氧化物薄膜晶体管阵列基板的制作方法，其中，所述金属氧化物半导体层的材料为铟镓锌氧化物、铟锡锌氧化物、或氧化锌。
  16. 如权利要求11所述的金属氧化物薄膜晶体管阵列基板的制作方法，其中，所述金属氧化物半导体层通过物理气相沉积法、或凝胶溶液法在室温下沉积得到。
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