CN109817724A - 阵列基板和阵列基板的制造方法 - Google Patents

阵列基板和阵列基板的制造方法 Download PDF

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CN109817724A
CN109817724A CN201910104730.9A CN201910104730A CN109817724A CN 109817724 A CN109817724 A CN 109817724A CN 201910104730 A CN201910104730 A CN 201910104730A CN 109817724 A CN109817724 A CN 109817724A
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谭威
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/481,072 priority patent/US20210335843A1/en
Priority to PCT/CN2019/084170 priority patent/WO2020155435A1/zh
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Abstract

本申请实施例公开一种阵列基板和阵列基板的制造方法，该阵列基板包括：基板、缓冲层、半导体层、绝缘层和栅极层；所述缓冲层设置在所述基板之上；所述半导体层设置在所述缓冲层之上；所述绝缘层覆盖所述缓冲层和所述半导体层；所述栅极层设置在所述绝缘层之上；其中，所述半导体层包括载流子通道，所述载流子通道位于所述半导体层朝向所述绝缘层的一侧，所述绝缘层包括第一薄膜层和第二薄膜层，所述第一薄膜层覆盖所述半导体层和所述缓冲层，所述第二薄膜层覆盖所述第一薄膜层，所述栅极层位于所述第二薄膜层上，所述第一薄膜层的致密度大于所述第二薄膜层的致密度，所述载流子通道与所述第一薄膜层相接。本方案可以提高阵列基板的电性稳定性。

Description

阵列基板和阵列基板的制造方法
技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板和阵列基板的制造方法。
背景技术
在现有的低温多晶硅技术(LTPS，Low Temperature Poly-silicon)产品中，半导体层与栅极层之间的绝缘层常通过TEOS/O2或者SiH4/N2O两种方式沉积而成。
其中，由于N2O中的N元素会使得半导体层与绝缘层界面的缺陷较多，造成平带电压漂移较大，导致产品的电性不稳定。因此，业界较多采用TEOS/O2的方式形成绝缘层，然而该方式的成本较高。
发明内容
本申请实施例提供了一种阵列基板和阵列基板的制造方法，可以提高阵列基板的电性稳定性。
本申请实施例提供了一种阵列基板，包括：基板、缓冲层、半导体层、绝缘层和栅极层；
所述缓冲层设置在所述基板之上；
所述半导体层设置在所述缓冲层之上；
所述绝缘层覆盖所述缓冲层和所述半导体层；
所述栅极层设置在所述绝缘层之上；
其中，所述半导体层包括载流子通道，所述载流子通道位于所述半导体层朝向所述绝缘层的一侧，所述绝缘层包括第一薄膜层和第二薄膜层，所述第一薄膜层覆盖所述半导体层和所述缓冲层，所述第二薄膜层覆盖所述第一薄膜层，所述栅极层位于所述第二薄膜层上，所述第一薄膜层的致密度大于所述第二薄膜层的致密度，所述载流子通道与所述第一薄膜层相接。
在本申请实施例提供的阵列基板中，所述第一薄膜层的厚度在之间。
在本申请实施例提供的阵列基板中，所述第一薄膜层的沉积速率小于
在本申请实施例提供的阵列基板中，所述第一薄膜层包括第一氧化硅薄膜。
在本申请实施例提供的阵列基板中，所述第二薄膜层的厚度在之间。
在本申请实施例提供的阵列基板中，所述第二薄膜层的沉积速率大于等于
在本申请实施例提供的阵列基板中，所述第二薄膜层包括第二氧化硅薄膜。
在本申请实施例提供的阵列基板中，所述载流子通道的厚度在之间。
在本申请实施例提供的阵列基板中，所述缓冲层的材料包括氧化硅，厚度在之间。
本申请实施例还提供了一种阵列基板的制造方法，包括：
提供一基板，在所述基板上依次沉积缓冲层和半导体层；
在所述半导体层中设置载流子通道；
在所述半导体层上沉积绝缘层，包括：
在所述半导体层上沉积第一薄膜层，所述第一薄膜层覆盖所述半导体层和所述缓冲层；以及
在所述第一薄膜层上设置第二薄膜层，其中，所述第一薄膜层的致密度大于所述第二薄膜层的致密度；以及
在所述绝缘层上沉积栅极层。
本申请实施例提供的阵列基板，包括基板、缓冲层、半导体层、绝缘层和栅极层，其中，绝缘层可以包括第一薄膜层和第二薄膜层，第一薄膜层的致密度大于第二薄膜层的致密度，通过将致密度高的第一薄膜层与载流子通道相接，可以保证载流子通道的稳定，进而提高阵列基板的电性稳定性。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的阵列基板的结构示意图。
图2是本申请实施例提供的阵列基板的制造方法的流程示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例提供一种阵列基板和阵列基板的制造方法，以下分别进行详细说明。
请参阅图1，图1是本申请实施例提供的阵列基板的结构示意图。本申请实施例提供的阵列基板可以包括：基板10、缓冲层20、半导体层30、绝缘层40和栅极层50。需要说明的是，本申请实施例提供的阵列基板并不限于此，比如阵列基板还可以包括源极、漏极等。
其中，基板10的材料玻璃、石英或蓝宝石等，需要说明的是，基板10的材料包括但不限于以上材料，其还可以包括其他材料，在此不再一一列举。
其中，缓冲层20设置在基板10之上，在一些实施例中，可以采用化学气相沉积技术在基板10上形成缓冲层10。其中，缓冲层20其中可以为氧化硅(SiOx)薄膜、氮化硅(SiNx)薄膜、或者氧化硅薄膜与氮化硅薄膜交替层叠设置形成的复合薄膜。在一些实施例中，该缓冲层20的厚度可以在之间。
其中，半导体层30设置在缓冲层20之上，在一些实施例中，可以采用物理气相沉积技术在缓冲层20上形成半导体层30。在一些实施例中，半导体层30可以由多晶硅(POLY-Si)构成。
在一些实施例中，半导体30中可以包括载流子通道31。其中，该载流子通道31同样也可以由多晶硅构成。需要说明的是，该载流子通道31所使用的多晶硅与半导体层30其余部位所使用的多晶硅所掺杂的元素的浓度不同。载流子通道31中所掺杂元素的浓度较高，半导体层30其余部位所掺杂的元素浓度较低。在一些实施例中，掺杂的元素可以为硼、铟或镓等元素。其中，载流子通道31主要用于提高填充因子、短路电流和开路电压。在一些实施例中，载流子通道31的厚度可以在之间。
其中，绝缘层40设置在半导体30之上，且覆盖缓冲层20和半导体层30。
其中，载流子通道31位于半导体层30朝向绝缘层40的一侧。
其中，绝缘层40可以包括第一薄膜层41和第二薄膜层42，第一薄膜层41覆盖半导体30和缓冲层20，第二薄膜层41覆盖第一薄膜层42。第一薄膜层41的致密度大于第二薄膜层42的致密度。其中，第一薄膜层41与载流子通道31相接，其致密的薄膜可以保证载流子通道31的稳定。
需要说明的是，在本申请的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。
需要说明的是，在实际操作过程中，第一薄膜层41和第二薄膜层42的致密度一般难以直接测得，由此，可以通过其他手段从侧面反映出第一薄膜层41和第二薄膜层42的致密度。
在一些实施例中，可以在第一薄膜层41和第二薄膜层42的沉积过程中通过测量其沉积速率从侧面反映出其大概致密度，致密度越高则沉积速率越小。在一些实施例中，第一薄膜层的沉积速率小于第二薄膜层的沉积速率大于等于
在一些实施例中，还可以采用同一蚀刻液对第一薄膜层41和第二薄膜层42进行蚀刻，通过其蚀刻速率来反映第一薄膜层41和第二薄膜层42的大概致密度，致密度越高则蚀刻速率越小。在一些实施例中，第一薄膜层的蚀刻速率可以在150nm/min-190nm/min之间，第二薄膜层的蚀刻速率大于190nm/min。
在实际应用中，制备致密的薄膜所需的成本较高。对此，第一薄膜层41的厚度可以小于第二薄膜层42的厚度，以节省成本。在一些实施例中，第一薄膜层的厚度可以在之间，第二薄膜层的厚度可以在之间。
在一些实施例中，第一薄膜层41可以包括第一氧化硅薄膜，第二薄膜层42可以包括第二氧化硅薄膜。
在一些实施例中，氧化硅薄膜可以采用硅烷和氧化氮作为反应气体，通过化学沉积技术而形成。在实际应用中，可以通过改变沉积的因素，比如硅烷和氧化氮的比例、压力等，来调整氧化硅薄膜的致密度。
其中，栅极层50设置在绝缘层40之上，即栅极层50位于第二薄膜层42上。在一些实施例中，可以通过物理气相沉积技术，比如金属溅射在绝缘层40上沉积一金属层，然后再对该金属层进行光刻处理形成栅极层50。其中，栅极层50的材料可以包括铝、钼、铜或银等金属。
本申请实施例提供的阵列基板，通过将绝缘层40分为致密度较高第一薄膜层41和致密度较低的第二薄膜层42，其中，第一薄膜层41的厚度可以小于第二薄膜层42的厚度，在一定程度上，可以节省制作该阵列基板的成本。并且，本申请实施例提供的阵列基板通过将致密度高的第一薄膜层41与载流子通道31相接，可以保证载流子通道31的稳定，进而提高阵列基板的电性稳定性。
请参阅图2，本申请实施例还提供了一种阵列基板的制造方法，该阵列基板的制造方法的具体流程可以如下：
101、提供一基板10，在所述基板10上依次沉积缓冲层20和半导体层30。
102、在所述半导体层30中设置载流子通道31。
103、在所述半导体层30上沉积绝缘层40。
具体的，可以在半导体层30上沉积第一薄膜层41，该第一薄膜层41覆盖半导体层30和缓冲层20；以及在该第一薄膜层41上设置第二薄膜层42，其中，第一薄膜层41的致密度大于第二薄膜层42的致密度。
104、在所述绝缘层40上沉积栅极层50。
需要说明的是，本实施例所提供的阵列基板的制造方法所形成阵列基板与上述的阵列基板的结构一致，具体可以参照上述实施例，在此不做赘述。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种阵列基板和阵列基板的制造方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (10)

1.一种阵列基板，其特征在于，包括：基板、缓冲层、半导体层、绝缘层和栅极层；
所述缓冲层设置在所述基板之上；
所述半导体层设置在所述缓冲层之上；
所述绝缘层覆盖所述缓冲层和所述半导体层；
所述栅极层设置在所述绝缘层之上；
其中，所述半导体层包括载流子通道，所述载流子通道位于所述半导体层朝向所述绝缘层的一侧，所述绝缘层包括第一薄膜层和第二薄膜层，所述第一薄膜层覆盖所述半导体层和所述缓冲层，所述第二薄膜层覆盖所述第一薄膜层，所述栅极层位于所述第二薄膜层上，所述第一薄膜层的致密度大于所述第二薄膜层的致密度，所述载流子通道与所述第一薄膜层相接。
2.如权利要求1所述的阵列基板，其特征在于，所述第一薄膜层的厚度在之间。
3.如权利要求1所述的阵列基板，其特征在于，所述第一薄膜层的沉积速率小于
4.如权利要求1-3任一项所述的阵列基板，其特征在于，所述第一薄膜层包括第一氧化硅薄膜。
5.如权利要求1所述的阵列基板，其特征在于，所述第二薄膜层的厚度在之间。
6.如权利要求1所述的阵列基板，其特征在于，所述第二薄膜层的沉积速率大于等于
7.如权利要求1或5-6任一项所述的阵列基板，其特征在于，所述第二薄膜层包括第二氧化硅薄膜。
8.如权利要求1所述的阵列基板，其特征在于，所述载流子通道的厚度在之间。
9.如权利要求1所述的阵列基板，其特征在于，所述缓冲层的材料包括氧化硅，厚度在之间。
10.一种阵列基板的制作方法，其特征在于，包括：
提供一基板，在所述基板上依次沉积缓冲层和半导体层；
在所述半导体层中设置载流子通道；
在所述半导体层上沉积绝缘层，包括：
在所述半导体层上沉积第一薄膜层，所述第一薄膜层覆盖所述半导体层和所述缓冲层；以及
在所述第一薄膜层上设置第二薄膜层，其中，所述第一薄膜层的致密度大于所述第二薄膜层的致密度；以及
在所述绝缘层上沉积栅极层。
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