WO2013097554A1 - Tft阵列基板的制造方法 - Google Patents

Tft阵列基板的制造方法 Download PDF

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Publication number
WO2013097554A1
WO2013097554A1 PCT/CN2012/084598 CN2012084598W WO2013097554A1 WO 2013097554 A1 WO2013097554 A1 WO 2013097554A1 CN 2012084598 W CN2012084598 W CN 2012084598W WO 2013097554 A1 WO2013097554 A1 WO 2013097554A1
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Prior art keywords
layer
metal oxide
oxide semiconductor
forming
semiconductor layer
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PCT/CN2012/084598
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English (en)
French (fr)
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刘翔
薛建设
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京东方科技集团股份有限公司
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Priority to US13/704,156 priority Critical patent/US9647013B2/en
Publication of WO2013097554A1 publication Critical patent/WO2013097554A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • Embodiments of the present invention relate to a method of fabricating a TFT array substrate. Background technique
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • each pixel is driven by a corresponding Thin Film Transistor (TFT) in the TFT array substrate, and then combined with a peripheral driving circuit to realize image display.
  • TFT Thin Film Transistor
  • AMOLED Active Matrix Organic Light Emission Display
  • the TFT in the TFT array substrate drives the corresponding OLED pixel in the OLED panel, and then cooperates with the peripheral driving circuit to realize image display.
  • the TFT is used as a switching element, which is the key to the display of the above display, and is directly related to the development of a high performance flat panel display.
  • the TFTs which have been industrialized mainly include amorphous silicon TFTs, polycrystalline silicon TFTs, single crystal silicon TFTs, and the like, and amorphous silicon TFTs are most used for preparing array substrates in flat panel displays.
  • the metal oxide TFT has the advantage of high carrier mobility, so that the TFT can be made small, and the resolution of the flat panel display is improved, and the display effect is improved.
  • the metal oxide TFT has the advantages of less characteristic unevenness, lower material and process cost, low process temperature, available coating process, high transparency, and large band gap.
  • Array substrates including metal oxide TFTs are typically fabricated using six photolithography processes. If the number of lithography processes can be reduced, that is, if the number of times of using the reticle can be reduced, the production efficiency can be improved and the production cost can be reduced. Summary of the invention
  • a method of fabricating a TFT array substrate is provided.
  • the TFT array substrate is formed to include a plurality of scan lines and a plurality of data lines and the scan lines and the data lines are intersected by each other A plurality of pixel units defined by the fork, each of the pixel units including a TFT and a pixel electrode.
  • the TFT is formed to include: a gate electrode, a gate insulating layer, a metal oxide semiconductor layer serving as an active layer, an etch barrier layer formed on a portion of a surface of the metal oxide semiconductor layer, a source electrode, and a drain electrode.
  • the metal oxide semiconductor layer, the source electrode, and the drain electrode are formed by one patterning process.
  • the pattern of the metal oxide semiconductor layer is formed using the source/drain electrode and the etch barrier layer as a mask, and the TFT array substrate provided with the metal oxide TFT in the conventional art.
  • the lithography process is reduced, the fabrication process is simplified, the production efficiency is improved, the yield is improved, and the production cost is reduced.
  • FIG. 1 is a plan view showing a TFT array substrate fabricated by using the manufacturing method of the embodiment of the present invention
  • FIG. 2 is a cross-sectional view showing a TFT array substrate after a first patterning process in a manufacturing method according to an embodiment of the present invention
  • FIG. 3 is a schematic cross-sectional view of a TFT array substrate after a second patterning process in a manufacturing method according to an embodiment of the present invention
  • FIG. 4 is a cross-sectional view showing a TFT array substrate after a third patterning process in a manufacturing method according to an embodiment of the present invention
  • FIG. 5 is a cross-sectional view showing a TFT array substrate after a fourth patterning process in a manufacturing method according to an embodiment of the present invention
  • FIG. 6 is a cross-sectional view showing a TFT array substrate after a fifth patterning process in the manufacturing method of the embodiment of the present invention. detailed description
  • the patterning process includes a photolithography process and other processes for forming a predetermined pattern such as printing, ink jet, and the like.
  • the photolithography process includes processes such as exposure, development, etching, and the like.
  • Figure 1 is a plan view schematically showing a TFT array substrate produced by the manufacturing method of the embodiment of the present invention.
  • the TFT array substrate includes a plurality of scanning lines 12 and a plurality of data lines 11, which intersect with each other thereby defining pixel units arranged in a matrix.
  • Each of the pixel units includes a TFT as a switching element and a pixel electrode for controlling the arrangement of the liquid crystal.
  • the TFT of each pixel unit includes: a gate; a gate insulating layer formed on the gate; a metal oxide semiconductor layer serving as an active layer and formed on the gate insulating layer; an etch barrier layer formed on the metal a portion of the surface of the oxide semiconductor layer; a source electrode having one end on the etch stop layer and the other end on the metal oxide semiconductor layer; and a drain electrode having an opposite end from the source electrode on the etch stop layer and the other end on On the metal oxide semiconductor layer.
  • the gate of the thin film transistor is electrically connected to the corresponding scan line, the source is electrically connected to the corresponding data line, and the drain is electrically connected to the pixel electrode.
  • FIG. 2-6 are cross-sectional views taken along line A-B of Fig. 1. The following is a comparison with FIG. 2-6 in this embodiment.
  • the TFT array substrate manufacturing method includes the following steps:
  • Step S1 A pattern including the gate electrode 2 and the scanning line 12 is formed on the substrate 1 by one patterning process, as shown in Fig. 2.
  • the thickness of the substrate 1 is deposited by sputtering or thermal evaporation.
  • the gate metal film may be made of a single layer film formed of any one of Cr, W, Cu, Ti, Ta, Mo, or may be made of an alloy of any of the above metals, or may be made of the above metal.
  • the multilayer film formed by the combination is made.
  • the gate electrode 2 and the scanning line 12 (not shown in Fig. 2) are formed by a photolithography process using a conventional mask.
  • Step S2 forming a gate insulating layer 3 on the substrate 1 on which step S1 is completed, and then A metal oxide semiconductor film 4 is deposited on the edge layer 3, and then an etch barrier film is deposited, and an etch barrier layer 5 is formed on the metal oxide semiconductor film 4' by one patterning process, as shown in FIG.
  • the gate insulating layer 3 having a thickness of 2000 to 8000 A is continuously deposited by the PECVD (Plasma Enhanced Chemical Vapor Deposition) method on the substrate 1 on which the step S1 is completed.
  • the material of the gate insulating layer 3 may be silicon oxide SiO x , silicon nitride SiN x , silicon oxynitride SiN x O y , or a metal oxide of an insulator such as A1 2 0 3 or the like.
  • the gate insulating layer may be a single layer or a combination of the above multiple layers.
  • the reaction gas for forming silicon nitride may be SiH4, NH3, N2 or SiH2C12, NH3, N2, and the reaction gas for forming silicon oxide may be SiH4, N20, NH3 for forming nitrogen oxide.
  • the reaction gas for silicon may be SiH4, N20, NH3, N2.
  • a metal oxide semiconductor film 4' having a thickness of 100 to 4000 A is deposited on the gate insulating layer 3 by sputtering or thermal evaporation, and the metal oxide semiconductor film is made of amorphous IGZO, HIZO, IZO, a-InZnO, a-InZnO, ZnO:F, In 2 0 3 :Sn, In 2 0 3 :Mo, Cd 2 Sn0 4 , ZnO:Al, Ti0 2 :Nb, Cd-Sn-0 or other metal oxidation Made of semiconductors.
  • an etch barrier film having a thickness of 500 to 4000 ⁇ is deposited by a PECVD method.
  • the material for etching the barrier film may be silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiNxOy, or a metal oxide of an insulator such as A1203.
  • the etch stop layer may be a single layer or a combination of the above multiple layers.
  • the reaction gas for forming silicon nitride may be SiH4, NH3, N2 or SiH2C12, NH3, N2, and the reaction gas for forming silicon oxide may be SiH4, N20, NH3 for forming nitrogen oxide.
  • the reaction gases of silicon may be SiH4, N20, Li 3, N2 0
  • the etch barrier layer 5 is formed by a photolithography process using a conventional mask, as shown in FIG.
  • Step S3 A source/drain metal film is deposited on the substrate 1 on which the step S2 is completed, and a pattern including the source electrode 6, the drain electrode 7, the data line 11, and the metal oxide semiconductor layer 4 is formed by one patterning process, as shown in FIG.
  • the source electrode 6, the drain electrode 7, and the etch barrier layer 5 are used as a mask for forming the metal oxide semiconductor layer 4, and a metal is formed while forming the source electrode 6, the drain electrode 7, and the data line 11. Oxide semiconductor layer 4.
  • the side of the substrate 1 on which step S2 is completed is sputtered or thermally evaporated.
  • the method is to deposit a source-drain metal film with a thickness of 2000 ⁇ 10000A.
  • the source/drain metal film may be made of a single layer film formed of any one of Cr, W, Cu, Ti, Ta, Mo, or may be made of an alloy of any of the above metals, or may be made of the above metal.
  • the source electrode 6, the drain electrode 7, and the data line 11 (not shown in FIG. 4) are formed by a photolithography process using a conventional mask, and the patterns of the source electrode 6, the drain electrode 7, and the etch barrier 5 are used as a pattern.
  • the mask plate simultaneously forms a pattern of the metal oxide semiconductor layer 4 in a photolithography process in which the source electrode 6, the drain electrode 7, and the data line 11 are formed.
  • the pattern of the source electrode 6, the drain electrode 7, the data line 11, and the metal oxide semiconductor layer 4 can be simultaneously formed by one photolithography process.
  • the metal oxide semiconductor layer 4 is formed by blocking the metal oxide semiconductor film 4' formed in the step S2 in the illumination direction (that is, as a mask) by using the source/drain metal electrode and the etch barrier layer 5.
  • the pattern thus directly omits the lithography process used in the conventional technology for the metal oxide semiconductor layer alone. Comparing Fig. 3 with Fig. 4, the effect of the source/drain metal electrode and the etch stop layer as a mask can be clearly understood.
  • Step S4 forming a protective layer on the substrate of step S3, forming a contact via 9 by a patterning process, as shown in FIG.
  • the protective layer 8 having a thickness of 2000 to 8000 A is continuously deposited by a PECVD method on the substrate on which the step S3 is completed.
  • the material of the protective layer 8 may be silicon oxide SiO x , silicon nitride SiN x , silicon oxynitride SiN x O y , or a metal oxide of an insulator such as A1 2 0 3 or the like.
  • the protective layer 8 may be a single layer or a combination of the above multiple layers.
  • the reaction gas for forming silicon nitride may be SiH4, NH3, N2 or SiH2C12, NH3, N2, and the reaction gas for forming silicon oxide may be SiH4, N20, NH3 for forming nitrogen oxide.
  • the reaction gas for silicon may be SiH4, N20, NH3, N2.
  • the contact via 9 is formed by a photolithography process using a conventional mask, as shown in FIG.
  • Step S5 depositing a transparent conductive film on the substrate on which step S4 is completed, and forming a transparent pixel electrode 10 by one patterning process, as shown in FIG.
  • a transparent conductive film having a thickness of 300 to 1500 ⁇ is deposited by sputtering or thermal evaporation on the substrate on which step S4 is completed.
  • Transparent conductive films are generally made of ITO or other metals and metal oxides.
  • the transparent pixel electrode 10 is formed by a photolithography process using a conventional mask.
  • Example 2 In the above-described Embodiment 1, in the step S2, the gate insulating layer 3 and the etch barrier layer 5 each have a single layer structure. However, in the present embodiment, both the gate insulating layer 3 and the etch barrier layer 5 have a two-layer structure.
  • one layer in contact with the metal oxide semiconductor layer 4 is a protective layer
  • one layer not in contact with the metal oxide semiconductor layer 4 is an insulating layer.
  • the protective layer is made of SiO x and is formed by low-speed deposition.
  • the insulating layer is made of SiN x and is formed by high-speed deposition. In the deposition process of the gate insulating layer 3, the insulating layer is deposited by high-speed deposition, and then the protective layer is deposited by low-speed deposition.
  • a layer in contact with the metal oxide semiconductor layer 4 is a protective layer
  • a layer not in contact with the metal oxide semiconductor layer 4 is a barrier layer.
  • the protective layer is made of SiO x and is formed by low-speed deposition.
  • the insulating layer is made of SiN x and is formed by high-speed deposition.
  • the protective layer is deposited by low-speed deposition
  • the barrier layer is deposited by high-speed deposition.
  • the protective layer and the etch barrier protective layer in the gate insulating layer in contact with the metal oxide semiconductor layer 4 are respectively formed by low-speed deposition, the deposited layer is formed to be dense, and thus can be oxidized with metal.
  • the semiconductor layer 4 forms a good interface, which is advantageous for improving the stability performance of the TFT.
  • the insulating layer in the gate insulating layer away from the MOS layer 4 and the barrier layer in the etch barrier layer are respectively formed by high-speed deposition, and the deposition speed is fast, so that the production efficiency can be effectively improved. .
  • a method for fabricating a TFT array substrate provided with a metal oxide TFT according to an embodiment of the present invention using a source/drain electrode and an etch barrier layer as a mask to form a pattern of a metal oxide semiconductor layer, which is set in a conventional technique
  • the photolithography process is reduced, the fabrication process is simplified, the production efficiency is improved, the yield is improved, and the production cost is reduced.
  • Embodiments of the present invention are particularly well suited for fabricating large size, high resolution TFT-LCD flat panel displays and active matrix driven OLED flat panel displays.

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Abstract

一种TFT阵列基板的制造方法。该TFT阵列基板形成为包括多条扫描线（12）和多条数据线（11）及由这些扫描线（12）和数据线（11）彼此交叉限定的多个像素单元，每个像素单元包括TFT和像素电极（10）。该TFT形成为包括：栅极（2）、栅极绝缘层（3）、用作有源层的金属氧化物半导体层（4）、形成在金属氧化物半导体层（4）的部分表面上的刻蚀阻档层（5）、源电极（6）以及漏电极（7）。金属氧化物半导体层（4）、源电极（6）、漏电极（7）通过一次构图工艺形成。

Description

TFT阵列基板的制造方法 技术领域
本发明的实施例涉及一种 TFT阵列基板的制造方法。 背景技术
目前，平板显示器已逐渐取代了笨重的 CRT显示器。常用的平板显示器 包括 LCD ( Liquid Crystal Display： 液晶显示器） 和 OLED ( Organic Light-Emitting Diode: 有机发光二极管）显示器。
在 LCD平板显示器中， 每一像素点由 TFT阵列基板中的对应的薄膜晶 体管（ Thin Film Transistor: 简称 TFT )来驱动 , 再配合外围驱动电路， 实现 图像显示。 在有源矩阵驱动式 OLED ( Active Matrix Organic Light Emission Display, 简称 AMOLED )显示器中， TFT阵列基板中的 TFT驱动 OLED 面板中对应的 OLED像素， 再配合外围驱动电路， 实现图像显示。 在上述显 示器中， TFT用作开关元件， 是上述显示器实现显示的关键， 直接关系到高 性能平板显示器的发展。
已实现产业化的 TFT主要有非晶硅 TFT、 多晶硅 TFT、 单晶硅 TFT等， 而用于制备平板显示器中的阵列基板使用最多的是非晶硅 TFT。
目前， 出现了金属氧化物 TFT, 金属氧化物 TFT具有载流子迁移率高的 优点， 使得 TFT可以做的很小， 而使平板显示器的分辨率提高， 显示效果改 善。 此外， 金属氧化物 TFT还具有特性不均现象少、 材料和工艺成本降低、 工艺温度低、 可利用涂布工艺、 透明率高、 带隙大等优点。
包括金属氧化物 TFT的阵列基板一般釆用六次光刻工艺制成。如果能够 减少光刻工艺的数量， 即如果能够减少掩模板的使用次数， 则可以提高生产 效率， 降低生产成本。 发明内容
根据本发明的实施例， 提供一种 TFT阵列基板的制造方法。 该 TFT阵 列基板形成为包括多条扫描线和多条数据线及由这些扫描线和数据线彼此交 叉限定的多个像素单元， 每个像素单元包括 TFT和像素电极。 该 TFT形成 为包括： 栅极、 栅极绝缘层、 用作有源层的金属氧化物半导体层、 形成在金 属氧化物半导体层的部分表面上的刻蚀阻挡层、 源电极以及漏电极。 金属氧 化物半导体层、 源电极、 漏电极通过一次构图工艺形成。
在根据本发明实施例的上述制造方法中， 巧妙地利用源漏电极和刻蚀阻 挡层作为掩模板来形成金属氧化物半导体层的图形， 与传统技术中设置有金 属氧化物 TFT的 TFT阵列基板的釆用六次光刻工艺的制造方法相比， 减少 了一次光刻工艺， 简化了制作工艺， 提高了生产效率， 提高了良品率， 降低 了生产成本。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1 为釆用本发明实施例制造方法所制成的 TFT阵列基板的平面示意 图；
图 2 为本发明实施例制造方法中第一次构图工艺后 TFT阵列基板的截 面示意图；
图 3为本发明实施例制造方法中第二次构图工艺后 TFT阵列基板的截面 示意图；
图 4 为本发明实施例制造方法中第三次构图工艺后 TFT阵列基板的截 面示意图；
图 5 为本发明实施例制造方法中第四次构图工艺后 TFT阵列基板的截 面示意图；
图 6 为本发明实施例制造方法中第五次构图工艺后 TFT阵列基板的截 面示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
在下面的描述中， 构图工艺包括光刻工艺以及诸如打印、 喷墨等的其他 用于形成预定图形的工艺。 光刻工艺包括曝光、 显影、 刻蚀等工艺。
下面的描述主要针对单个像素单元进行， 但是其他像素单元可以相同地 形成。
实施例 1
图 1 为釆用本发明实施例制造方法所制成的 TFT阵列基板的平面示意 图。
该 TFT阵列基板包括多条扫描线 12和多条数据线 11 , 这些扫描线 12 和数据线 11彼此交叉由此限定了排列为矩阵的像素单元。每个像素单元包括 作为开关元件的 TFT和用于控制液晶的排列的像素电极。
每个像素单元的 TFT包括： 栅极； 栅极绝缘层， 形成在栅极上； 金属氧 化物半导体层， 用作有源层且形成在栅极绝缘层上； 刻蚀阻挡层， 形成在金 属氧化物半导体层的部分表面上； 源电极， 其一端位于蚀刻阻挡层上， 另一 端位于金属氧化物半导体层上； 以及漏电极， 其与源电极相对的一端位于蚀 刻阻挡层上， 另一端位于金属氧化物半导体层上。 薄膜晶体管的栅极与相应 的扫描线电连接， 源极与相应的数据线电连接， 漏极与像素电极电连接。
图 2-6为沿图 1的线 A-B剖取的截面图。 下面结合图 2-6对本实施例中
TFT阵列基板的制造方法进行详细介绍。
本实施例中， TFT阵列基板制造方法包括以下步骤：
步骤 S1: 通过一次构图工艺在基板 1上形成包括栅电极 2和扫描线 12 的图形， 如图 2所示。
例如， 在该步骤中， 在基板 1 上釆用溅射或热蒸发的方法沉积厚度为
2000 ~ 10000A的栅极金属膜。 栅极金属膜可以釆用 Cr、 W、 Cu、 Ti、 Ta、 Mo 中的任一种所形成的单层膜制成， 或者釆用以上任一金属的合金制成， 或者釆用以上金属的组合所形成的多层膜制成。 利用普通掩模板通过一次光 刻工艺形成栅电极 2和扫描线 12 (未示于图 2中） 。
步骤 S2: 在完成步骤 S1的基板 1上形成栅极绝缘层 3, 接着在栅极绝 缘层 3上沉积金属氧化物半导体膜 4，， 然后沉积刻蚀阻挡膜， 通过一次构图 工艺在金属氧化物半导体膜 4'上形成刻蚀阻挡层 5, 如图 3所示。
例如， 在该步骤中， 在完成步骤 S1 的基板 1 上通过 PECVD ( Plasma Enhanced Chemical Vapor Deposition, 等离子体增强化学气象沉积）方法连续 沉积厚度为 2000 ~ 8000 A的栅极绝缘层 3。栅极绝缘层 3的材料可以是氧化 硅 SiOx、 氮化硅 SiNx、 氮氧化硅 SiNxOy, 也可以是绝缘体的金属氧化物如 A1203等。 栅极绝缘层可以是单层， 也可以是上述多层的组合。 釆用 PECVD 方法时， 用于形成氮化硅的反应气体可以为 SiH4、 NH3、 N2或 SiH2C12、 NH3、 N2, 用于形成氧化硅的反应气体可以是 SiH4、 N20、 NH3, 用于形成 氮氧化硅的反应气体可以是 SiH4、 N20、 NH3、 N2。
然后， 例如， 在栅极绝缘层 3 上通过溅射或热蒸发的方法沉积厚度为 100 ~ 4000 A 的金属氧化物半导体膜 4' , 金属氧化物半导体膜釆用非晶 IGZO、 HIZO、 IZO、 a-InZnO, a-InZnO, ZnO:F、 In203:Sn、 In203:Mo、 Cd2Sn04、 ZnO:Al、 Ti02:Nb、 Cd-Sn-0或其他的金属氧化物半导体制成。
接着， 例如， 再通过 PECVD方法沉积厚度为 5 00 ~ 4000 A的刻蚀阻挡 膜。刻蚀阻挡膜的材料可以是氧化硅 SiOx、 氮化硅 SiNx、氮氧化硅 SiNxOy, 也可以是绝缘体的金属氧化物如 A1203等。 刻蚀阻挡层可以是单层， 也可以 是上述多层的组合。 釆用 PECVD方法时， 用于形成氮化硅的反应气体可以 为 SiH4、 NH3、 N2或 SiH2C12、 NH3、 N2, 用于形成氧化硅的反应气体可 以是 SiH4、 N20、 NH3 , 用于形成氮氧化硅的反应气体可以是 SiH4、 N20、 丽 3、 N20
然后， 釆用普通掩模板通过一次光刻工艺形成刻蚀阻挡层 5, 如图 3所 示。
步骤 S3: 在完成步骤 S2的基板 1上沉积源漏金属膜， 通过一次构图工 艺形成包括源电极 6、 漏电极 7、 数据线 11以及金属氧化物半导体层 4的图 形， 如图 4所示。
在此次构图工艺中， 利用源电极 6、 漏电极 7和刻蚀阻挡层 5作为形成 金属氧化物半导体层 4的掩模板， 在形成源电极 6、 漏电极 7和数据线 11的 同时形成金属氧化物半导体层 4。
例如， 在该步骤中， 在完成步骤 S2的基板 1上釆用溅射或热蒸发的方 法沉积厚度为 2000 ~ 10000A的源漏金属膜。 源漏金属膜可以釆用 Cr、 W、 Cu、 Ti、 Ta、 Mo 中的任一种所形成的单层膜制成， 或者釆用以上任一金属 的合金制成， 或者釆用以上金属的任一组合所形成的多层膜制成。 釆用普通 的掩模板通过一次光刻工艺形成源电极 6、 漏电极 7及数据线 11 (图 4中未 示出） ， 并利用源电极 6、 漏电极 7和刻蚀阻挡层 5的图形作为掩模板， 在 形成源电极 6、漏电极 7和数据线 11的光刻工艺中同时形成金属氧化物半导 体层 4的图形。
在该步骤中， 利用一次光刻工艺即可同时形成源电极 6、 漏电极 7、数据 线 11以及金属氧化物半导体层 4的图形。在该过程中，利用源漏金属电极和 刻蚀阻挡层 5对步骤 S2中形成的金属氧化物半导体膜 4'在光照方向上的遮 挡作用 （即作为掩模板）来形成金属氧化物半导体层 4的图形， 从而直接省 去了传统技术中对金属氧化物半导体层单独釆用的一次光刻工艺。 对比图 3 与图 4, 可以很清楚地理解源漏金属电极和刻蚀阻挡层作为掩模板的作用。
步骤 S4: 在完成步骤 S3的基板上形成保护层 8, 通过一次构图工艺形 成接触过孔 9, 如图 5所示。
例如，在该步骤中， 在完成步骤 S3的基板上通过 PECVD方法连续沉积 厚度为 2000 ~ 8000 A的保护层 8。保护层 8的材料可以是氧化硅 SiOx、 氮化 硅 SiNx、 氮氧化硅 SiNxOy, 也可以是绝缘体的金属氧化物如 A1203等。 保护 层 8可以是单层， 也可以是上述多层的组合。 釆用 PECVD方法时， 用于形 成氮化硅的反应气体可以为 SiH4、 NH3、 N2或 SiH2C12、 NH3、 N2, 用于 形成氧化硅的反应气体可以是 SiH4、 N20、 NH3 , 用于形成氮氧化硅的反应 气体可以是 SiH4、 N20、 NH3、 N2。 釆用普通掩模板通过一次光刻工艺形成 接触过孔 9, 如图 5所示。
步骤 S5: 在完成步骤 S4的基板上沉积透明导电膜， 通过一次构图工艺 形成透明像素电极 10, 如图 6所示。
例如， 在该步骤中， 在完成步骤 S4 的基板上通过溅射或热蒸发的方法 沉积厚度为 300 ~ 1500 A的透明导电膜。 透明导电膜一般釆用 ITO或其他的 金属及金属氧化物制成。 釆用普通掩模板通过一次光刻工艺形成透明像素电 极 10。
实施例 2 在上述实施例 1中， 在步骤 S2中， 栅极绝缘层 3和刻蚀阻挡层 5均釆 用单层结构。 然而， 在本实施例中， 栅极绝缘层 3和刻蚀阻挡层 5均釆用双 层结构。
在栅极绝缘层 3中， 与金属氧化物半导体层 4接触的一层为保护层， 未 与金属氧化物半导体层 4接触的一层为绝缘层。例如，保护层釆用 SiOx制成， 且釆用低速沉积方式形成。 例如， 绝缘层釆用 SiNx制成， 且釆用高速沉积方 式形成。 在栅极绝缘层 3的沉积过程中， 先釆用高速沉积方式沉积绝缘层， 再釆用低速沉积方式沉积保护层。
在刻蚀阻挡层 5中， 与金属氧化物半导体层 4接触的一层为保护层， 未 与金属氧化物半导体层 4接触的一层为阻挡层。例如，保护层釆用 SiOx制成， 且釆用低速沉积方式形成。 例如， 绝缘层釆用 SiNx制成， 且釆用高速沉积方 式形成。 在刻蚀阻挡层 5的沉积过程中， 先釆用低速沉积方式沉积保护层， 再釆用高速沉积方式沉积阻挡层。
一方面， 由于与金属氧化物半导体层 4接触的栅极绝缘层中的保护层和 刻蚀阻挡层保护层均分别釆用低速沉积方式形成， 所形成的沉积层较致密， 因此能与金属氧化物半导体层 4形成很好的交界面，有利于提高 TFT的稳定 性性能。 另一方面， 远离金属氧化物半导体层 4的栅极绝缘层中的绝缘层和 刻蚀阻挡层中的阻挡层均分别釆用高速沉积方式形成， 沉积速度较快， 因此 能有效提高其生产效率。
本发明实施例中提供的设置有金属氧化物 TFT的 TFT阵列基板的制造 方法， 巧妙地利用源漏电极和刻蚀阻挡层作为掩模板来形成金属氧化物半导 体层的图形， 与传统技术中设置有金属氧化物 TFT的 TFT阵列基板的釆用 六次光刻工艺的制造方法相比， 减少了一次光刻工艺， 简化了制作工艺， 提 高了生产效率， 提高了良品率， 降低了生产成本。
本发明实施例尤其适合于制造大尺寸、 高分辨率的 TFT-LCD平板显示 器以及有源矩阵驱动式 OLED平板显示器。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1. 一种 TFT阵列基板的制造方法，
该 TFT 阵列基板形成为包括多条扫描线和多条数据线及由这些扫描线 和数据线彼此交叉限定的多个像素单元， 每个像素单元包括 TFT 和像素电 极，
该 TFT形成为包括： 栅极、 栅极绝缘层、 用作有源层的金属氧化物半导 体层、 形成在金属氧化物半导体层的部分表面上的刻蚀阻挡层、 源电极以及 漏电极，
其中所述金属氧化物半导体层、源电极、漏电极通过一次构图工艺形成。
2. 根据权利要求 1所述的制造方法，其中在形成源电极和漏电极的构图 工艺中， 将源电极、 漏电极和刻蚀阻挡层的图形作为形成金属氧化物半导体 层的掩模板， 从而在形成源电极、 漏电极的同时形成金属氧化物半导体层。
3. 根据权利要求 2所述的制造方法， 其中所述方法包括如下步骤： 步骤 S1 : 在基板上形成栅极金属膜， 通过一次构图工艺形成栅电极和扫 描线；
步骤 S2: 在完成步骤 S1的基板上形成栅极绝缘层， 接着在栅极绝缘层 上沉积金属氧化物半导体膜， 然后沉积蚀刻阻挡膜， 通过一次构图工艺在金 属氧化物半导体膜上形成刻蚀阻挡层；
步骤 S3: 在完成步骤 S2的基板上沉积源漏金属膜， 通过一次构图工艺 形成源电极、 漏电极、 数据线以及金属氧化物半导体层；
步骤 S4: 在完成步骤 S3的基板上形成保护层， 通过一次构图工艺形成 接触过孔；
步骤 S5: 在完成步骤 S4的基板上沉积透明导电膜， 通过一次构图工艺 形成透明像素电极， 该透明像素电极通过接触过孔连接漏电极。
4. 根据权利要求 3所述的方法， 其中步骤 S1至 S5中的构图工艺均釆 用普通掩模板。
5.根据权利要求 1所述的方法，其中源电极形成为其一端位于蚀刻阻挡 层上， 另一端位于金属氧化物半导体层上； 并且
其中漏电极形成为其与源电极相对的一端位于蚀刻阻挡层上， 另一端位 于金属氧化物半导体层上。
6.根据权利要求 1所述的方法， 其中所述金属氧化物半导体膜釆用非晶 IGZO、 HIZO、 IZO、 a-InZnO, a-InZnO, ZnO:F、 In203:Sn、 In203:Mo、 Cd2Sn04、 ZnO:Al、 Ti02:Nb、 Cd-Sn-0制成。
7、根据权利要求 1所述的方法， 其中所述栅极绝缘层具有双层结构， 并 且
其中该双层结构中与金属氧化物半导体层接触的一层为保护层， 而未与 金属氧化物半导体层接触的一层为绝缘层。
8、 根据权利要求 7所述的方法。 其中保护层釆用 81( 制成且釆用低速 沉积方式形成。
9、 根据权利要求 7所述的方法， 其中绝缘层釆用 SiN>^ij成且釆用高速 沉积、方式形成。
10、 根据权利要求 1所述的方法， 其中所述刻蚀阻挡层具有双层结构， 并且
其中该双层结构中与金属氧化物半导体层接触的一层为保护层， 而未与 金属氧化物半导体层接触的一层为阻挡层。
11、 根据权利要求 10所述的方法， 其中保护层釆用 SiOx制成且釆用低 速沉积方式形成。
12、 根据权利要求 10所述的方法， 其中阻挡层釆用 SiNx制成且釆用高 速沉积方式形成。
13、 根据权利要求 1所述的方法， 其中所述栅极绝缘层具有单层结构且 由氧化硅或氮化硅或氮氧化硅制成。
14、 根据权利要求 1所述的方法， 其中所述刻蚀阻挡层具有单层结构且 由氧化硅或氮化硅或氮氧化硅制成。
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