WO2013097554A1 - Tft阵列基板的制造方法 - Google Patents
Tft阵列基板的制造方法 Download PDFInfo
- Publication number
- WO2013097554A1 WO2013097554A1 PCT/CN2012/084598 CN2012084598W WO2013097554A1 WO 2013097554 A1 WO2013097554 A1 WO 2013097554A1 CN 2012084598 W CN2012084598 W CN 2012084598W WO 2013097554 A1 WO2013097554 A1 WO 2013097554A1
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- WO
- WIPO (PCT)
- Prior art keywords
- layer
- metal oxide
- oxide semiconductor
- forming
- semiconductor layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 69
- 239000000758 substrate Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 53
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 53
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 104
- 230000004888 barrier function Effects 0.000 claims description 28
- 238000000059 patterning Methods 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 239000011241 protective layer Substances 0.000 claims description 17
- 230000008021 deposition Effects 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 239000002356 single layer Substances 0.000 claims description 8
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 4
- 229910052758 niobium Inorganic materials 0.000 claims description 2
- 229910052718 tin Inorganic materials 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 20
- 238000000206 photolithography Methods 0.000 description 11
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 9
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 9
- 239000012495 reaction gas Substances 0.000 description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 7
- 238000001459 lithography Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- -1 N2 or SiH2C12 Chemical compound 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000002207 thermal evaporation Methods 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910004286 SiNxOy Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Definitions
- Embodiments of the present invention relate to a method of fabricating a TFT array substrate. Background technique
- LCD Liquid Crystal Display
- OLED Organic Light-Emitting Diode
- each pixel is driven by a corresponding Thin Film Transistor (TFT) in the TFT array substrate, and then combined with a peripheral driving circuit to realize image display.
- TFT Thin Film Transistor
- AMOLED Active Matrix Organic Light Emission Display
- the TFT in the TFT array substrate drives the corresponding OLED pixel in the OLED panel, and then cooperates with the peripheral driving circuit to realize image display.
- the TFT is used as a switching element, which is the key to the display of the above display, and is directly related to the development of a high performance flat panel display.
- the TFTs which have been industrialized mainly include amorphous silicon TFTs, polycrystalline silicon TFTs, single crystal silicon TFTs, and the like, and amorphous silicon TFTs are most used for preparing array substrates in flat panel displays.
- the metal oxide TFT has the advantage of high carrier mobility, so that the TFT can be made small, and the resolution of the flat panel display is improved, and the display effect is improved.
- the metal oxide TFT has the advantages of less characteristic unevenness, lower material and process cost, low process temperature, available coating process, high transparency, and large band gap.
- Array substrates including metal oxide TFTs are typically fabricated using six photolithography processes. If the number of lithography processes can be reduced, that is, if the number of times of using the reticle can be reduced, the production efficiency can be improved and the production cost can be reduced. Summary of the invention
- a method of fabricating a TFT array substrate is provided.
- the TFT array substrate is formed to include a plurality of scan lines and a plurality of data lines and the scan lines and the data lines are intersected by each other A plurality of pixel units defined by the fork, each of the pixel units including a TFT and a pixel electrode.
- the TFT is formed to include: a gate electrode, a gate insulating layer, a metal oxide semiconductor layer serving as an active layer, an etch barrier layer formed on a portion of a surface of the metal oxide semiconductor layer, a source electrode, and a drain electrode.
- the metal oxide semiconductor layer, the source electrode, and the drain electrode are formed by one patterning process.
- the pattern of the metal oxide semiconductor layer is formed using the source/drain electrode and the etch barrier layer as a mask, and the TFT array substrate provided with the metal oxide TFT in the conventional art.
- the lithography process is reduced, the fabrication process is simplified, the production efficiency is improved, the yield is improved, and the production cost is reduced.
- FIG. 1 is a plan view showing a TFT array substrate fabricated by using the manufacturing method of the embodiment of the present invention
- FIG. 2 is a cross-sectional view showing a TFT array substrate after a first patterning process in a manufacturing method according to an embodiment of the present invention
- FIG. 3 is a schematic cross-sectional view of a TFT array substrate after a second patterning process in a manufacturing method according to an embodiment of the present invention
- FIG. 4 is a cross-sectional view showing a TFT array substrate after a third patterning process in a manufacturing method according to an embodiment of the present invention
- FIG. 5 is a cross-sectional view showing a TFT array substrate after a fourth patterning process in a manufacturing method according to an embodiment of the present invention
- FIG. 6 is a cross-sectional view showing a TFT array substrate after a fifth patterning process in the manufacturing method of the embodiment of the present invention. detailed description
- the patterning process includes a photolithography process and other processes for forming a predetermined pattern such as printing, ink jet, and the like.
- the photolithography process includes processes such as exposure, development, etching, and the like.
- Figure 1 is a plan view schematically showing a TFT array substrate produced by the manufacturing method of the embodiment of the present invention.
- the TFT array substrate includes a plurality of scanning lines 12 and a plurality of data lines 11, which intersect with each other thereby defining pixel units arranged in a matrix.
- Each of the pixel units includes a TFT as a switching element and a pixel electrode for controlling the arrangement of the liquid crystal.
- the TFT of each pixel unit includes: a gate; a gate insulating layer formed on the gate; a metal oxide semiconductor layer serving as an active layer and formed on the gate insulating layer; an etch barrier layer formed on the metal a portion of the surface of the oxide semiconductor layer; a source electrode having one end on the etch stop layer and the other end on the metal oxide semiconductor layer; and a drain electrode having an opposite end from the source electrode on the etch stop layer and the other end on On the metal oxide semiconductor layer.
- the gate of the thin film transistor is electrically connected to the corresponding scan line, the source is electrically connected to the corresponding data line, and the drain is electrically connected to the pixel electrode.
- FIG. 2-6 are cross-sectional views taken along line A-B of Fig. 1. The following is a comparison with FIG. 2-6 in this embodiment.
- the TFT array substrate manufacturing method includes the following steps:
- Step S1 A pattern including the gate electrode 2 and the scanning line 12 is formed on the substrate 1 by one patterning process, as shown in Fig. 2.
- the thickness of the substrate 1 is deposited by sputtering or thermal evaporation.
- the gate metal film may be made of a single layer film formed of any one of Cr, W, Cu, Ti, Ta, Mo, or may be made of an alloy of any of the above metals, or may be made of the above metal.
- the multilayer film formed by the combination is made.
- the gate electrode 2 and the scanning line 12 (not shown in Fig. 2) are formed by a photolithography process using a conventional mask.
- Step S2 forming a gate insulating layer 3 on the substrate 1 on which step S1 is completed, and then A metal oxide semiconductor film 4 is deposited on the edge layer 3, and then an etch barrier film is deposited, and an etch barrier layer 5 is formed on the metal oxide semiconductor film 4' by one patterning process, as shown in FIG.
- the gate insulating layer 3 having a thickness of 2000 to 8000 A is continuously deposited by the PECVD (Plasma Enhanced Chemical Vapor Deposition) method on the substrate 1 on which the step S1 is completed.
- the material of the gate insulating layer 3 may be silicon oxide SiO x , silicon nitride SiN x , silicon oxynitride SiN x O y , or a metal oxide of an insulator such as A1 2 0 3 or the like.
- the gate insulating layer may be a single layer or a combination of the above multiple layers.
- the reaction gas for forming silicon nitride may be SiH4, NH3, N2 or SiH2C12, NH3, N2, and the reaction gas for forming silicon oxide may be SiH4, N20, NH3 for forming nitrogen oxide.
- the reaction gas for silicon may be SiH4, N20, NH3, N2.
- a metal oxide semiconductor film 4' having a thickness of 100 to 4000 A is deposited on the gate insulating layer 3 by sputtering or thermal evaporation, and the metal oxide semiconductor film is made of amorphous IGZO, HIZO, IZO, a-InZnO, a-InZnO, ZnO:F, In 2 0 3 :Sn, In 2 0 3 :Mo, Cd 2 Sn0 4 , ZnO:Al, Ti0 2 :Nb, Cd-Sn-0 or other metal oxidation Made of semiconductors.
- an etch barrier film having a thickness of 500 to 4000 ⁇ is deposited by a PECVD method.
- the material for etching the barrier film may be silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiNxOy, or a metal oxide of an insulator such as A1203.
- the etch stop layer may be a single layer or a combination of the above multiple layers.
- the reaction gas for forming silicon nitride may be SiH4, NH3, N2 or SiH2C12, NH3, N2, and the reaction gas for forming silicon oxide may be SiH4, N20, NH3 for forming nitrogen oxide.
- the reaction gases of silicon may be SiH4, N20, Li 3, N2 0
- the etch barrier layer 5 is formed by a photolithography process using a conventional mask, as shown in FIG.
- Step S3 A source/drain metal film is deposited on the substrate 1 on which the step S2 is completed, and a pattern including the source electrode 6, the drain electrode 7, the data line 11, and the metal oxide semiconductor layer 4 is formed by one patterning process, as shown in FIG.
- the source electrode 6, the drain electrode 7, and the etch barrier layer 5 are used as a mask for forming the metal oxide semiconductor layer 4, and a metal is formed while forming the source electrode 6, the drain electrode 7, and the data line 11. Oxide semiconductor layer 4.
- the side of the substrate 1 on which step S2 is completed is sputtered or thermally evaporated.
- the method is to deposit a source-drain metal film with a thickness of 2000 ⁇ 10000A.
- the source/drain metal film may be made of a single layer film formed of any one of Cr, W, Cu, Ti, Ta, Mo, or may be made of an alloy of any of the above metals, or may be made of the above metal.
- the source electrode 6, the drain electrode 7, and the data line 11 (not shown in FIG. 4) are formed by a photolithography process using a conventional mask, and the patterns of the source electrode 6, the drain electrode 7, and the etch barrier 5 are used as a pattern.
- the mask plate simultaneously forms a pattern of the metal oxide semiconductor layer 4 in a photolithography process in which the source electrode 6, the drain electrode 7, and the data line 11 are formed.
- the pattern of the source electrode 6, the drain electrode 7, the data line 11, and the metal oxide semiconductor layer 4 can be simultaneously formed by one photolithography process.
- the metal oxide semiconductor layer 4 is formed by blocking the metal oxide semiconductor film 4' formed in the step S2 in the illumination direction (that is, as a mask) by using the source/drain metal electrode and the etch barrier layer 5.
- the pattern thus directly omits the lithography process used in the conventional technology for the metal oxide semiconductor layer alone. Comparing Fig. 3 with Fig. 4, the effect of the source/drain metal electrode and the etch stop layer as a mask can be clearly understood.
- Step S4 forming a protective layer on the substrate of step S3, forming a contact via 9 by a patterning process, as shown in FIG.
- the protective layer 8 having a thickness of 2000 to 8000 A is continuously deposited by a PECVD method on the substrate on which the step S3 is completed.
- the material of the protective layer 8 may be silicon oxide SiO x , silicon nitride SiN x , silicon oxynitride SiN x O y , or a metal oxide of an insulator such as A1 2 0 3 or the like.
- the protective layer 8 may be a single layer or a combination of the above multiple layers.
- the reaction gas for forming silicon nitride may be SiH4, NH3, N2 or SiH2C12, NH3, N2, and the reaction gas for forming silicon oxide may be SiH4, N20, NH3 for forming nitrogen oxide.
- the reaction gas for silicon may be SiH4, N20, NH3, N2.
- the contact via 9 is formed by a photolithography process using a conventional mask, as shown in FIG.
- Step S5 depositing a transparent conductive film on the substrate on which step S4 is completed, and forming a transparent pixel electrode 10 by one patterning process, as shown in FIG.
- a transparent conductive film having a thickness of 300 to 1500 ⁇ is deposited by sputtering or thermal evaporation on the substrate on which step S4 is completed.
- Transparent conductive films are generally made of ITO or other metals and metal oxides.
- the transparent pixel electrode 10 is formed by a photolithography process using a conventional mask.
- Example 2 In the above-described Embodiment 1, in the step S2, the gate insulating layer 3 and the etch barrier layer 5 each have a single layer structure. However, in the present embodiment, both the gate insulating layer 3 and the etch barrier layer 5 have a two-layer structure.
- one layer in contact with the metal oxide semiconductor layer 4 is a protective layer
- one layer not in contact with the metal oxide semiconductor layer 4 is an insulating layer.
- the protective layer is made of SiO x and is formed by low-speed deposition.
- the insulating layer is made of SiN x and is formed by high-speed deposition. In the deposition process of the gate insulating layer 3, the insulating layer is deposited by high-speed deposition, and then the protective layer is deposited by low-speed deposition.
- a layer in contact with the metal oxide semiconductor layer 4 is a protective layer
- a layer not in contact with the metal oxide semiconductor layer 4 is a barrier layer.
- the protective layer is made of SiO x and is formed by low-speed deposition.
- the insulating layer is made of SiN x and is formed by high-speed deposition.
- the protective layer is deposited by low-speed deposition
- the barrier layer is deposited by high-speed deposition.
- the protective layer and the etch barrier protective layer in the gate insulating layer in contact with the metal oxide semiconductor layer 4 are respectively formed by low-speed deposition, the deposited layer is formed to be dense, and thus can be oxidized with metal.
- the semiconductor layer 4 forms a good interface, which is advantageous for improving the stability performance of the TFT.
- the insulating layer in the gate insulating layer away from the MOS layer 4 and the barrier layer in the etch barrier layer are respectively formed by high-speed deposition, and the deposition speed is fast, so that the production efficiency can be effectively improved. .
- a method for fabricating a TFT array substrate provided with a metal oxide TFT according to an embodiment of the present invention using a source/drain electrode and an etch barrier layer as a mask to form a pattern of a metal oxide semiconductor layer, which is set in a conventional technique
- the photolithography process is reduced, the fabrication process is simplified, the production efficiency is improved, the yield is improved, and the production cost is reduced.
- Embodiments of the present invention are particularly well suited for fabricating large size, high resolution TFT-LCD flat panel displays and active matrix driven OLED flat panel displays.
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Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US13/704,156 US9647013B2 (en) | 2011-12-31 | 2012-11-14 | Manufacturing method of TFT array substrate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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CN201110460545.7A CN102651340B (zh) | 2011-12-31 | 2011-12-31 | 一种tft阵列基板的制造方法 |
CN201110460545.7 | 2011-12-31 |
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WO2013097554A1 true WO2013097554A1 (zh) | 2013-07-04 |
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PCT/CN2012/084598 WO2013097554A1 (zh) | 2011-12-31 | 2012-11-14 | Tft阵列基板的制造方法 |
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US (1) | US9647013B2 (zh) |
CN (1) | CN102651340B (zh) |
WO (1) | WO2013097554A1 (zh) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102651340B (zh) * | 2011-12-31 | 2014-11-19 | 京东方科技集团股份有限公司 | 一种tft阵列基板的制造方法 |
WO2014085971A1 (zh) * | 2012-12-04 | 2014-06-12 | 深圳市柔宇科技有限公司 | 一种金属氧化物tft器件及制造方法 |
CN103050412B (zh) * | 2012-12-20 | 2015-10-21 | 深圳丹邦投资集团有限公司 | 氧化物薄膜晶体管的制造方法 |
WO2014121469A1 (zh) * | 2013-02-06 | 2014-08-14 | 深圳市柔宇科技有限公司 | 一种薄膜晶体管及其像素单元的制造方法 |
CN103219284B (zh) * | 2013-03-19 | 2015-04-08 | 北京京东方光电科技有限公司 | Tft阵列基板、tft阵列基板的制作方法及显示装置 |
CN103681696A (zh) | 2013-12-24 | 2014-03-26 | 京东方科技集团股份有限公司 | 一种电极引出结构、阵列基板以及显示装置 |
CN104269413B (zh) * | 2014-09-22 | 2017-08-11 | 京东方科技集团股份有限公司 | 阵列基板及其制作方法、液晶显示装置 |
CN105390507B (zh) * | 2015-12-03 | 2018-04-10 | 深圳市华星光电技术有限公司 | Tft阵列基板的制备方法、阵列基板及显示装置 |
CN105632896B (zh) * | 2016-01-28 | 2018-06-15 | 深圳市华星光电技术有限公司 | 制造薄膜晶体管的方法 |
CN105679707A (zh) * | 2016-04-20 | 2016-06-15 | 京东方科技集团股份有限公司 | 阵列基板及其制造方法、显示装置 |
CN106024908A (zh) * | 2016-07-26 | 2016-10-12 | 京东方科技集团股份有限公司 | 一种薄膜晶体管制作方法和阵列基板制作方法 |
CN106129071B (zh) * | 2016-09-13 | 2018-12-25 | 京东方科技集团股份有限公司 | 一种阵列基板的制作方法及相应装置 |
CN106876387B (zh) * | 2017-02-17 | 2020-01-10 | 京东方科技集团股份有限公司 | 一种阵列基板及其制造方法 |
CN107632731B (zh) | 2017-09-15 | 2021-01-26 | 京东方科技集团股份有限公司 | 触控面板的制造方法及触控面板 |
US10804406B2 (en) * | 2018-10-30 | 2020-10-13 | Sharp Kabushiki Kaisha | Thin-film transistor substrate, liquid crystal display device including the same, and method for producing thin-film transistor substrate |
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US20140154823A1 (en) | 2014-06-05 |
US9647013B2 (en) | 2017-05-09 |
CN102651340B (zh) | 2014-11-19 |
CN102651340A (zh) | 2012-08-29 |
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