WO2013097529A1 - 薄膜晶体管、阵列基板以及显示器件 - Google Patents

薄膜晶体管、阵列基板以及显示器件 Download PDF

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Publication number
WO2013097529A1
WO2013097529A1 PCT/CN2012/083500 CN2012083500W WO2013097529A1 WO 2013097529 A1 WO2013097529 A1 WO 2013097529A1 CN 2012083500 W CN2012083500 W CN 2012083500W WO 2013097529 A1 WO2013097529 A1 WO 2013097529A1
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layer
insulating layer
thin film
film transistor
sub
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PCT/CN2012/083500
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English (en)
French (fr)
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曹占锋
童晓阳
姚琪
刘圣烈
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京东方科技集团股份有限公司
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Priority to US13/703,551 priority Critical patent/US8946701B2/en
Publication of WO2013097529A1 publication Critical patent/WO2013097529A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device

Definitions

  • the present invention relates to a thin film transistor, an array substrate including the same, and a display device. Background technique
  • the display generally includes a cathode ray tube (CRT) display and a liquid crystal display (LCD).
  • CTR cathode ray tube
  • LCD liquid crystal display
  • OLED Organic Light-Emitting Diode
  • each liquid crystal pixel in the liquid crystal display is driven by a Thin Film Transistor (TFT) integrated in the thin film transistor substrate, and then combined with a peripheral driving circuit to realize image display.
  • TFT Thin Film Transistor
  • AMOLED Active Matrix Organic Light Emission Display
  • a corresponding OLED pixel in an OLED panel is driven by a TFT in a TFT substrate, and a peripheral driving circuit is used to realize image display.
  • the TFT is a switch for controlling the illumination, and is the key to realizing the large size of the liquid crystal display and the OLED display, and is directly related to the development direction of the high performance flat panel display.
  • the TFT is generally made of a semiconductor material, and the semiconductor material according to which the active layer is prepared can be divided into: an inorganic TFT, an organic TFT, and an inorganic/organic composite TFT.
  • inorganic TFTs which use materials such as silicon, compounds, and metal oxides.
  • the TFT which has been industrialized is mainly made of a silicon-based material such as amorphous silicon, polycrystalline silicon, or single crystal silicon.
  • Amorphous silicon TFTs are currently the most used for fabricating array substrates in flat panel displays.
  • the mobility of TFTs is required to be sufficiently high.
  • the existing amorphous silicon TFT has a long charging time due to its limited carrier mobility.
  • the existing amorphous silicon TFT can meet the requirements on a small-sized flat panel display, it is difficult to meet the high display quality and driving of the large-sized flat panel display. Demand. Therefore, researchers have turned their attention to metal oxide materials that can bring higher carrier mobility to TFTs.
  • the metal oxide semiconductor has a high carrier density, so that the metal is oxidized.
  • the TFT made of the material has the advantage of high carrier mobility, so that the TFT can be made small, and the resolution of the flat panel display is higher, and the display effect is better; and the TFT made of metal oxide has characteristics. Less unevenness, lower material and process costs, lower process temperature, available coating process, high transparency, and large band gap.
  • the structure of the metal oxide TFT mainly has three types: an etch stop type, a back channel etch type, and a coplanar type.
  • the three types of metal oxide TFTs generally include a gate layer, a gate insulating layer, an active layer, a source/drain layer, a passivation layer, and a transparent electrode layer.
  • the most commonly used is an etch barrier metal oxide TFT.
  • the most used metal oxide in the active layer of the etch barrier metal oxide TFT is IGZO (In-Ga-Zn-0)hack
  • the etch-blocking metal oxide TFT also forms an etch barrier layer over the active layer, so that the metal oxide IGZO forming the active layer can be protected from damage during formation of the source and drain, thereby improving metal oxidation.
  • the performance and stability of the TFT due to the poor stability of the metal oxide in air, it is sensitive to oxygen and water vapor. In actual use, oxygen and water vapor can still oxidize the metal through the etch barrier.
  • the performance of the material deteriorates, so that the performance of the metal oxide TFT formed by using the metal oxide to prepare the active layer is lowered, resulting in deterioration of the performance of the metal oxide TFT array substrate and affecting the display quality of the flat panel display.
  • the etch-blocking metal oxide TFT is generally prepared by a 6-mask lithography process, that is, an etch barrier layer is used to prevent damage to the active layer made of metal oxide when the source and the drain are etched.
  • the gate insulating layer under the active layer is a single layer and is made of SiN x material
  • the etch barrier layer above the active layer is also a single layer and SiO is used.
  • x material preparation Since the etching rate of the SiN x material and the SiO x material under the same conditions is relatively large, for example, assuming that the etching rate of SiO x is 1, the etching rate of SiN x may reach 10 or more under the same condition.
  • the gate insulating layer not covered by the active layer pattern is exposed after the etching process of the SiO x layer in the etch barrier layer is completed.
  • the uniformity of the layers is considered in the general preparation process, and the etching barrier layer is etched for a period of time, that is, the etching time, for example, the etching process of the 500 A thick etching barrier layer is completed for 50 s, It takes 30% (15s) or more Engraved. During the etching process, more etching is inevitably generated on the gate insulating layer, so that the impact of the over-etching on the gate insulating layer is large, and the occurrence rate of the metal oxide TFT is increased.
  • An embodiment of the present invention provides a thin film transistor including: a gate layer, a first insulating layer, an active layer, an etch barrier layer, and a source and drain layer, wherein the active layer is made of a metal oxide material,
  • the first insulating layer, the active layer, the etch stop layer and the source and drain layers are sequentially stacked from bottom to top, and the source and drain layers include a source and a drain separated Interval, the etch stop layer is below the interval, and the width of the etch stop layer is greater than the width of the interval
  • the first insulating layer comprises a stacked first sub-insulation layer and a second sub-insulation a layer, the second sub-insulating layer is in contact with the active layer, and is made of an oxygen-rich insulating material.
  • an array substrate including: a substrate; a thin film transistor formed on the substrate, wherein the thin film transistor uses a thin film transistor according to any of the embodiments of the present invention, wherein the first The insulating layer has an extended portion extending beyond the region of the thin film transistor, and the array substrate further includes a pixel electrode formed over the extended portion of the first insulating layer.
  • Yet another embodiment of the present invention provides a display device comprising an array substrate according to any of the embodiments of the present invention.
  • FIG. 1 is a schematic structural diagram of a TFT in Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural diagram of a TFT in Embodiment 2 of the present invention.
  • Embodiment 3 is a schematic structural view of an array substrate in Embodiment 2 of the present invention.
  • FIG. 4 is a schematic structural view of an array substrate according to Embodiment 2 of the present invention
  • FIG. 5 is a schematic structural view of an array substrate of a top gate type structure for TFT ⁇ . detailed description
  • Embodiments of the present invention provide a thin film transistor (TFT) comprising: a gate layer, a first insulating layer, an active layer, an etch stop layer, and a source and drain layer.
  • the active layer is prepared from a metal oxide material.
  • the first insulating layer, the active layer, the etch barrier layer, and the source and drain layers are stacked in order from bottom to top.
  • the source drain layer includes a space separating the source and the drain, the etch stop layer is below the interval, and the width of the etch stop layer is greater than the width of the interval.
  • the first insulating layer includes a laminated first sub-insulating layer and a second sub-insulating layer, the second sub-insulating layer is in contact with the active layer, and is made of an oxygen-rich insulating material.
  • the TFT includes a gate layer 2, a gate insulating layer (ie, a gate protective layer) (3 and 4), an active layer 5, and an etch barrier layer (6 and sequentially stacked on the substrate 1. 7) and source drain layer 8.
  • a gate layer 2 As shown in FIG. 1, the TFT includes a gate layer 2, a gate insulating layer (ie, a gate protective layer) (3 and 4), an active layer 5, and an etch barrier layer (6 and sequentially stacked on the substrate 1. 7) and source drain layer 8.
  • the active layer 5 is made of a metal oxide semiconductor material.
  • the gate insulating layer and the etch barrier layer directly adjacent to the active layer are laminated.
  • the gate insulating layer includes two layers, a first gate insulating layer 3 and a second gate insulating layer 4, respectively, and the second gate insulating layer 4 is in contact with the active layer 5.
  • the etch barrier layer comprises two layers, a first etch barrier layer 6 and a second etch barrier layer 7, respectively, and the first etch barrier layer 6 is in contact with the active layer 5.
  • the second gate insulating layer 4 is made of an oxygen-rich insulating material, and the first gate insulating layer 3 is made of an easily etchable insulating material.
  • the first etch barrier layer 6 is made of an oxygen-rich material, and the second etch barrier layer 7 is made of an easily etchable material. That is, the first gate insulating layer 3 and the second gate insulating layer 4 are formed of materials having different etching rates, and the etching rate of the second gate insulating layer 4 is small.
  • the first etch barrier layer 6 and the second etch barrier layer 7 are formed of materials having different etch rates, and the etch rate of the first etch barrier layer 6 is small.
  • the second gate insulating layer 4 and the first etch barrier layer 6 are in direct contact with the active layer 5 from below and above the active layer 5, respectively.
  • the second gate insulating layer 4 and the first etch barrier layer 6 may be selected from SiO x , Made of one of A1 2 0 3 , SiN x Oy and Zr0 2
  • the first gate insulating layer 3 and the second etch barrier layer 7 may be made of one selected from the group consisting of SiN x , resin and SiC .
  • the active layer 5 is made of a metal oxide IGZ0 material; the first gate insulating layer 3 is made of SiN x , and the second gate insulating layer 4 is made of SiO x , the first The etch stop layer 6 is made of SiO x and the second etch stop layer 7 is made of SiN x .
  • the active layer 5 is made of IGZ0 material, and the second gate insulating layer 4 and the first etch barrier layer 6 adjacent to the active layer 5 are made of SiO x . Therefore, the material in contact with the active layer 5 is an SiO x material as an oxygen-rich material.
  • the gate insulating layer and the etch barrier layer respectively contacting the active layer are made of SiN x , and the SiN x is caused by a large flow of Si 3 ⁇ 4 gas during deposition, resulting in hydrogen content in the SiN x . Higher, its hydrogen content is about 4-6 times higher than SiO x . Therefore, using SiO x instead of SiN x in the prior art can prevent hydrogen atoms in the SiN x material from diffusing into the metal oxide IGZO material of the active layer, and can also effectively prevent oxygen atoms in the IGZO in the active layer 5. The diffusion ensures the stability of the IGZO material in the active layer, avoids the change of the TFT characteristics caused by the diffusion of oxygen atoms in the active layer 5, and ensures the stability of the metal oxide TFT.
  • the thickness of the first gate insulating layer 3 can be made larger than the thickness of the second gate insulating layer 4,
  • the thickness of the etch barrier layer 7 is greater than the thickness of the first etch stop layer 6 to improve production efficiency.
  • the first gate insulating layer 3 has a thickness of 2000-5000A
  • the second gate insulating layer 4 has a thickness of 200-500A
  • the first etch barrier layer 6 has a thickness of 200-400A.
  • the etching barrier layer 7 has a thickness of 200 to 500 ⁇ .
  • the gate insulating layer and the etch barrier layer adjacent to the active layer 5 are each laminated, and the second gate insulating layer 4 (made of SiO x ) and the first engraving
  • the etch stop layer 6 (made of SiO x ) is directly adjacent to the active layer 5, respectively.
  • etching is performed during the etching of the etch barrier layer. Since under the same conditions, the etching rate of the SiO x SiN x etching rate much smaller than the material, therefore, the second etch stop layer of SiN x. 7 can be cut too quickly, and the first etch stop layer
  • the SiO x in 6 can provide a good buffering effect.
  • the etching rate is more obvious in the etching process than the etching time. Since the etching rates of the first etching barrier layer 6 and the second gate insulating layer 4 are the same, the second gate can be insulated.
  • the thickness of the layer 4 is designed to be thicker than the first etch barrier layer 6, so that it can be guaranteed When an etch stop layer 6 is completed, the second gate insulating layer 4 does not completely etch. In this case, the first gate insulating layer 3 is not etched or only a very small portion is etched.
  • a passivation layer and a pixel electrode are formed thereon to form a TFT array substrate.
  • the common electrode may be disposed in the same layer as the gate layer (for example, see the common electrode 11 in Figs. 3 and 4). Between the pixel electrode and the common electrode in the fabricated array substrate, there is only the first gate insulating layer 3 and the passivation layer 9, or only the first gate insulating layer 3 (ie, outside the TFT, the passivation layer 9 is also The pixel electrode or the passivation layer may be in direct contact with the first gate insulating layer 3 without being provided.
  • the gate insulating layer can be effectively etched as little as possible, that is, the influence of the over-etching on the gate insulating layer is very small, and the yield of the metal oxide TFT is improved.
  • the process quality of the metal oxide TFT is ensured. Since the common electrode is usually disposed in the same layer as the gate, the distance between the pixel electrode and the common electrode is reduced, so that the storage capacitance can be increased and the flicker of the display screen can be reduced.
  • the width of the etch stop layer can be designed according to the width of the interval between the source and drain layers.
  • the etch stop layer needs to have a width greater than the above spacing to protect the active layer when etching the source drain electrode pattern.
  • the width of the etch barrier layer needs to be designed to be as small as possible, so that the contact area of the active layer 5 with the source and drain electrodes can be increased.
  • the width of the active layer is designed in accordance with the width of the etch stop layer and the above-described spacing. In the present embodiment, the width of the active layer 5 ranges from 14 to 18 ⁇ m, and the width of the etch barrier layer ranges from 8 to 10 ⁇ m.
  • the above widths are smaller than the existing widths, so the source and drain electrodes are The area of overlap between them will decrease.
  • the parasitic capacitance consumes some voltage after the TFT is charged, which causes the TFT driving voltage to be insufficient, which eventually causes the flat panel display to display poorly.
  • the capacitance calculation formula the smaller the area, the smaller the capacitance. Therefore, the width is designed to be smaller, and the parasitic capacitance between the source drain and the gate can be reduced.
  • the TFT array substrate is prepared by first preparing the gate layer 2 according to the prior art process and completing the gate layer pattern; then depositing a first gate insulating layer 3 in the deposition apparatus, and then depositing the same a second gate insulating layer 4 is formed by low temperature deposition in the device, and an etching gas corresponding to the second gate insulating layer is formed to include SF 6 , CF 4 , 0 2 or Cl 2 , and the gate insulating layer pattern is completed;
  • the metal oxide IGZO performs deposition of the active layer 5 and forms an active layer pattern; then on the active layer 5 Forming a first etch barrier layer 6 by deposition of a deposition device, and continuously depositing a second etch barrier layer 7 in the same deposition apparatus, and then forming an etch barrier layer by one exposure and then etching process on the exposure apparatus.
  • Graphic Next, the source and drain layers 8 are formed in accordance with the prior art process, and finally the passivation layer 9 is formed, and the preparation of the transparent
  • the two-layer structure in the gate insulating layer and the etch barrier layer can be continuously deposited on the same deposition device without increasing the number of process steps.
  • the first gate insulating layer and the second gate insulating layer may be deposited at a high temperature with a deposition temperature of 350-400.
  • C the first etch barrier layer and the second etch barrier layer are deposited at a low temperature, and the deposition temperature is 150-200.
  • C The gate insulating layer deposition is performed before the deposition of the metal oxide semiconductor, so that high temperature deposition can be employed.
  • the etch stop layer is performed after the deposition of the metal oxide semiconductor, and if it is still deposited at a high temperature, the semiconductor layer is destroyed and the TFT performance is affected.
  • the etch stop layer is deposited at a low temperature to prevent damage to the metal oxide semiconductor during the deposition process.
  • first etch barrier layer and the second etch barrier layer continuous etching may be performed on the same dry etching device, and the etching gas may be SF 6 , CF 4 , 0 2 or Cl 2 , during use.
  • a suitable gas content can be selected according to the process conditions to obtain a suitable etching rate.
  • the TFT in this embodiment is different from the first embodiment in that the etching resist layer in the TFT is only used in one layer, that is, the first etching barrier layer 6.
  • the first gate insulating layer 3 is made of SiN x
  • the second gate insulating layer 4 is made of 8 (the second gate insulating layer 4 is in contact with the active layer 5; the first etching preclude the barrier layer 6 is made of SiO x, SiO x thickness of the layer is 400-1000A, a first etch stop layer 6 in contact with the active layer 5.
  • FIG. 3 shows an example in which the second gate insulating layer 4 and the passivation layer 9 are provided between the pixel electrode 10 and the common electrode 11.
  • FIG. 4 shows an example in which only the second gate insulating layer 4 exists between the pixel electrode 10 and the common electrode 11.
  • the TFT array substrate shown in FIG. 3 and FIG. 4 can also be used in the TFT structure provided by other embodiments of the present invention.
  • the TFT structure in FIGS. 3 and 4 can be replaced by the TFT structure shown in FIG. 1, 2 or 5.
  • the positions of the pixel electrodes 10 and 11 of the TFT array substrate according to the embodiment of the present invention are not limited to those shown in FIGS. 3 and 4. Condition. Also, in some cases (for example, in a vertical electric field mode liquid crystal display), the common electrode may not be included on the array substrate.
  • the difference between the TFT and the first embodiment in the present embodiment is that the gate insulating layer of the TFT has a laminated structure of a plurality of sub-layers.
  • the gate insulating layer includes a first gate insulating layer 3 and a second gate insulating layer 4, and the first gate insulating layer 3 and the second gate insulating layer 4 respectively comprise two layers which are sequentially stacked, that is, the first A gate insulating layer includes two sub-layers, a lower sub-layer and an upper sub-layer, wherein the lower sub-layer is formed by high-speed deposition, and the upper sub-layer is formed by low-speed deposition; the second gate insulating layer includes two sub-layers, that is, the lower sub-layer And an upper sub-layer, wherein the lower sub-layer is formed by high-speed deposition, and the upper sub-layer is formed by low-speed deposition.
  • the deposition speed of the lower sub-layer deposited at a high speed is faster, the reduction time is compared, and the deposition quality of the upper sub-layer deposited at a low speed is better, and it is easier to meet the process requirements and improve the TFT characteristics.
  • the TFT ⁇ top gate type structure that is, the gate layer 2 is disposed at the uppermost side of each layer, as shown in FIG.
  • the scheme according to the embodiment of the present invention can be applied not only to the bottom gate type structure as shown in Figs. 1-3 but also to the top gate structure as shown in Fig. 5.
  • the gate layer 2 is located above the layer 9, and at this time, the layer 9 and the etch barrier layer 6 serve as a gate insulating layer.
  • the insulating layers 3 and 4 are not used as the gate insulating layer.
  • the insulating layers 3 and 4 under the active layer 5 can still have the same configuration as the gate insulating layer shown in the above embodiments 1-3.
  • a layer adjacent to the active layer is made of an oxygen-rich material.
  • SiO ⁇ for SiN x which is currently used for the gate insulating layer, it is possible to prevent hydrogen atoms in SiN x from diffusing into the metal oxide in the active layer, and also to prevent metal oxides in the active layer.
  • the oxygen atoms diffuse.
  • the stability of the active layer IGZO is ensured, so that the metal oxide TFT has high stability and at the same time, the gold is improved. It belongs to the product yield during the preparation of oxide TFT.
  • the performance of the array substrate prepared by using the metal oxide TFT is also improved, and the display quality of the display device using the array substrate is improved.
  • An embodiment of the present invention further provides an array substrate, comprising: a substrate and a thin film transistor formed on the substrate, wherein the thin film transistor uses a thin film transistor according to any of the embodiments of the present invention.
  • the first gate insulating layer 3 has an extension portion extending beyond the region of the thin film transistor.
  • the array substrate further includes a pixel electrode 10 formed over an extended portion of the first gate insulating layer 3.
  • the pixel electrode may be in direct contact with an extended portion of the first gate insulating layer 3.
  • the array substrate according to an embodiment of the present invention may further include a passivation layer 9 disposed over the thin film transistor and between the pixel electrode 10 and the first gate insulating layer 3, and the passivation layer 9 and the first insulating layer 3 The extension is in direct contact.
  • the TFT shown in FIG. 5 can also be applied to the above TFT array substrate, however, the insulating layer 3 and the insulating layer in FIG. 4 is not used for the gate insulating layer. Therefore, in the TFT array substrate according to the above embodiment, the first gate insulating layer 3 is only an example of the "first sub-insulating layer” of the present invention, and the second gate insulating layer 4 is only the “second sub-insulating layer” of the present invention. Example.
  • the embodiment of the invention further provides a display device comprising an array substrate, wherein the array substrate uses an array substrate according to any embodiment of the invention.
  • the display device may be a liquid crystal display device, such as a liquid crystal panel, a liquid crystal television, a mobile phone, a liquid crystal display, etc., including a color filter substrate, and the array substrate in the above embodiment; in addition to the liquid crystal display device, the display device may also be Other types of display devices, such as organic light emitting displays, etc., do not include a color film substrate, but include the array substrate in the above embodiments.

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Abstract

本发明的实施例提供一种薄膜晶体管、阵列基板和显示器件。该薄膜晶体管包括：栅极层、第一绝缘层、有源层、刻蚀阻挡层和源漏极层，其中所述有源层采用金属氧化物材料制备，所述第一绝缘层、所述有源层、所述刻蚀阻挡层和所述源漏极层从下至上依次堆叠，所述源漏极层中包括将源极和漏极分隔开的间隔，所述刻蚀阻挡层处于所述间隔下方，且所述刻蚀阻挡层的宽度大于所述间隔的宽度，以及所述第一绝缘层包括层叠的第一子绝缘层和第二子绝缘层，所述第二子绝缘层与所述有源层接触，并采用富氧的绝缘材料制成。

Description

薄膜晶体管、 阵列基板以及显示器件 技术领域
本发明涉及一种薄膜晶体管、 包含该薄膜晶体管的阵列基板以及显示器 件。 背景技术
在现有技术中， 显示器一般包括阴极射线管 （Cathode Ray Tube, CRT ) 显示器和液晶显示器（ Liquid Crystal Display, LCD )。 随着科学技术的发展， 有机发光二极管 （Organic Light-Emitting Diode, OLED )显示器也逐渐步入 人们的曰常生活中。
目前， CRT显示器逐渐被高性价比的液晶显示器、 OLED显示器所取代。 在成像过程中， 液晶显示器中每一液晶像素点都由集成在薄膜晶体管基板中 的薄膜晶体管（Thin Film Transistor: 简称 TFT )来驱动， 再配合外围驱动电 路， 实现图像显示。 有源矩阵驱动式 OLED ( Active Matrix Organic Light Emission Display,简称 AMOLED )显示器中由 TFT基板中的 TFT驱动 OLED 面板中对应的 OLED像素， 再配合外围驱动电路， 实现图像显示。 在上述显 示器中， TFT是控制发光的开关， 是实现液晶显示器和 OLED显示器大尺寸 的关键， 直接关系到高性能平板显示器的发展方向。
TFT一般釆用半导体材料制成， 按其制备有源层的半导体材料可将 TFT 分为： 无机 TFT、 有机 TFT和无机 /有机复合型 TFT。 目前使用最多的是无 机 TFT, 其釆用硅基、 化合物、 金属氧化物等材料。 在现有平板显示器生产 技术中， 已实现产业化的 TFT主要是釆用非晶硅、 多晶硅、 单晶硅等硅基材 料制成。 目前用于制备平板显示器中阵列基板使用最多的是非晶硅 TFT。 但 是，随着平板显示器尺寸的不断增大以及驱动电路的频率不断提高，要求 TFT 的迁移率要足够高。 这是因为迁移率越高， TFT就可以做得越小， 平板显示 器的分辨率就越大， 显示效果越好。 而现有的非晶硅 TFT由于其载流子迁移 率有限， 导致充电时间比较长。 现有的非晶硅 TFT虽然在小尺寸平板显示器 上可以满足要求， 但是很难满足大尺寸平板显示器较高的显示质量以及驱动 需求。 因此， 科研工作者将目光投向了能为 TFT带来更高载流子迁移率的金 属氧化物材料。
使用金属氧化物材料制作 TFT的有源层的情况下，由于金属氧化物半导 体内氧的缺乏增加了载流子的供给， 因此金属氧化物半导体具有很高的载流 子密度， 使得用金属氧化物制成的 TFT 具有载流子迁移率高的优点， 因而 TFT可以做的很小， 而使平板显示器的分辨率更高， 显示效果更好； 同时用 金属氧化物制成的 TFT还具有特性不均现象少、 材料和工艺成本降低、 工艺 温度低、 可利用涂布工艺、 透明率高、 带隙大等优点。
在现有技术中， 金属氧化物 TFT 的结构主要有刻蚀阻挡型 (etch stop type).背沟道刻独型 (back channel etch type)和共面型 (coplanar type)三种类型。 这三种类型的金属氧化物 TFT—般均包含栅极层、 栅极绝缘层、 有源层、 源 漏极层、 钝化层以及透明电极层。 目前， 最常釆用的是刻蚀阻挡型金属氧化 物 TFT,制备刻蚀阻挡型金属氧化物 TFT中有源层使用最多的金属氧化物是 IGZO(In-Ga-Zn-0)„ 由于刻蚀阻挡型金属氧化物 TFT在有源层的上方还形成 了一层刻蚀阻挡层， 因此， 可以在形成源漏极时保护形成有源层的金属氧化 物 IGZO不被破坏， 从而提高金属氧化物 TFT的性能和稳定性。 但是， 由于 金属氧化物在空气中稳定性较差，对氧气和水蒸气比较敏感，在实际使用中， 氧气和水蒸气仍可以透过刻蚀阻挡层使金属氧化物性能恶化， 从而使得釆用 金属氧化物制备有源层形成的金属氧化物 TFT 性能降低， 导致金属氧化物 TFT阵列基板性能降低， 影响平板显示器的显示质量。
目前， 刻蚀阻挡型金属氧化物 TFT—般釆用 6-mask光刻工艺制备， 即 釆用刻蚀阻挡层，以防止源漏极刻蚀时对金属氧化物制成的有源层造成损伤。 而在现有技术的金属氧化物 TFT中，有源层下方的栅极绝缘层为单层且釆用 SiNx材料制备， 而有源层上方的刻蚀阻挡层也为单层且釆用 SiOx材料制备。 由于 SiNx材料和 SiOx材料在同一条件下的刻蚀速率差别比较大， 例如， 假 设 SiOx的刻蚀速率为 1 , 则同一条件下 SiNx的刻蚀速率可能达到 10以上。 因此， 在实际生产过程中， 没有被有源层图形覆盖住的栅极绝缘层在刻蚀阻 挡层中的 SiOx层刻蚀过程完毕后就暴露出来。 另外， 在一般制备过程中会考 虑层间的均匀性， 而对刻蚀阻挡层再刻蚀一段时间， 即过刻时间， 比如 500A 厚的刻蚀阻挡层的刻蚀过程完成需要 50s, —般要花 30% ( 15s ) 以上的时间 进行过刻。 在过刻过程中， 不可避免地会对栅极绝缘层产生较多的刻蚀， 使 得过刻对栅极绝缘层的冲击量较大， 加大金属氧化物 TFT的不良发生率。
综上， 如何提高金属氧化物的稳定性， 以获得稳定性高的金属氧化物 TFT, 提高金属氧化物 TFT阵列基板的稳定性， 提高平板显示器的显示质量 是目前亟待解决的问题。 发明内容
本发明的实施例提供一种薄膜晶体管， 包括： 栅极层、 第一绝缘层、 有 源层、 刻蚀阻挡层和源漏极层， 其中所述有源层釆用金属氧化物材料制备， 所述第一绝缘层、 所述有源层、 所述刻蚀阻挡层和所述源漏极层从下至上依 次堆叠， 所述源漏极层中包括将源极和漏极分隔开的间隔， 所述刻蚀阻挡层 处于所述间隔下方， 且所述刻蚀阻挡层的宽度大于所述间隔的宽度， 以及所 述第一绝缘层包括层叠的第一子绝缘层和第二子绝缘层， 所述第二子绝缘层 与所述有源层接触， 并釆用富氧的绝缘材料制成。
本发明的另一实施例提供一种阵列基板， 包括： 基板； 形成在所述基板 上的薄膜晶体管， 其中所述薄膜晶体管釆用根据本发明任一实施例的薄膜晶 体管， 其中所述第一绝缘层具有延伸到所述薄膜晶体管的区域之外的延伸部 分， 以及所述阵列基板还包括形成在所述第一绝缘层的延伸部分上方的像素 电极。
本发明的再一个实施例提供一种显示器件， 包括根据本发明任一实施例 的阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例 1中 TFT的结构示意图；
图 2为本发明实施例 2中 TFT的结构示意图；
图 3 本发明实施例 2中阵列基板的结构示意图；
图 4为本发明实施例 2中阵列基板的结构示意图； 以及 图 5为 TFT釆用顶栅型结构的阵列基板的结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明的实施例提供一种薄膜晶体管 （TFT ) ， 包括： 栅极层、 第一绝 缘层、 有源层、 刻蚀阻挡层和源漏极层。 有源层釆用金属氧化物材料制备。 第一绝缘层、 有源层、 刻蚀阻挡层和源漏极层从下至上依次堆叠。 源漏极层 中包括将源极和漏极分隔开的间隔， 刻蚀阻挡层处于所述间隔下方， 且刻蚀 阻挡层的宽度大于间隔的宽度。 第一绝缘层包括层叠的第一子绝缘层和第二 子绝缘层， 第二子绝缘层与有源层接触， 并釆用富氧的绝缘材料制成。
实施例 1 :
如图 1所示， 该 TFT包括在基板 1上依次层叠的栅极层 2、 栅极绝缘层 (即栅极保护层） （ 3和 4 )、有源层 5、 刻蚀阻挡层（ 6和 7 )和源漏极层 8。
有源层 5釆用金属氧化物半导体材料制成。 本实施例中， 所述与有源层 直接相邻的栅极绝缘层和刻蚀阻挡层均釆用叠层结构。 所述栅极绝缘层包括 两层，分别为第一栅极绝缘层 3和第二栅极绝缘层 4 ,所述第二栅极绝缘层 4 与有源层 5接触。 所述刻蚀阻挡层包括两层， 分别为第一刻蚀阻挡层 6和第 二刻蚀阻挡层 7, 所述第一刻蚀阻挡层 6与有源层 5接触。
第二栅极绝缘层 4釆用富氧的绝缘材料制成， 所述第一栅极绝缘层 3釆 用易刻蚀的绝缘材料制成。 所述第一刻蚀阻挡层 6釆用富氧材料制成， 所述 第二刻蚀阻挡层 7釆用易刻蚀的材料制成。 也就是说， 第一栅极绝缘层 3和 第二栅极绝缘层 4釆用具有不同刻蚀速率的材料形成， 且第二栅极绝缘层 4 的蚀刻速率较小。 第一刻蚀阻挡层 6和第二刻蚀阻挡层 7釆用具有不同蚀刻 速率的材料形成， 且第一刻蚀阻挡层 6的刻蚀速率较小。
第二栅极绝缘层 4和第一刻蚀阻挡层 6分别从有源层 5的下方和上方与 有源层 5直接接触。第二栅极绝缘层 4和第一刻蚀阻挡层 6可釆用选自 SiOx、 A1203、 SiNxOy和 Zr02中的一种制成， 第一栅极绝缘层 3和第二刻蚀阻挡层 7可釆用选自 SiNx、 树脂和 SiC中的一种制成。
在一个实施例中， 有源层 5釆用金属氧化物 IGZ0材料制成； 第一栅极 绝缘层 3釆用 SiNx制成， 第二栅极绝缘层 4釆用 SiOx制成， 第一刻蚀阻挡 层 6釆用 SiOx制成， 第二刻蚀阻挡层 7釆用 SiNx制成。 在本实施例中， 有 源层 5釆用 IGZ0材料制成， 且与有源层 5相邻的第二栅极绝缘层 4和第一 刻蚀阻挡层 6均釆用 SiOx制成。 因此， 与有源层 5接触的材料为作为富氧材 料的 SiOx材料。而现有技术中与有源层分别接触的栅极绝缘层和刻蚀阻挡层 均釆用 SiNx制成， 而 SiNx由于沉积时釆用了大流量的 Si¾气体导致 SiNx中 含氢量较高， 其含氢量大约比 SiOx高 4-6倍。 因此， 釆用 SiOx代替现有技术 中的 SiNx, 可以防止 SiNx材料中的氢原子扩散到有源层的金属氧化物 IGZO 材料中， 也可以有效防止有源层 5中 IGZO中氧原子的扩散， 从而保证了有 源层中 IGZO材料的稳定性，避免有源层 5中因氧原子扩散而造成的 TFT特 性变化， 保证了金属氧化物 TFT的稳定性。
由于在制作过程中， 在同等条件下 SiN 々刻蚀速率要大大高于 SiO 々 刻蚀速率，因而可使第一栅极绝缘层 3的厚度大于第二栅极绝缘层 4的厚度， 第二刻蚀阻挡层 7的厚度大于第一刻蚀阻挡层 6的厚度， 以提高生产效率。
在一个实施例中， 第一栅极绝缘层 3的厚度为 2000-5000A, 第二栅极绝 缘层 4的厚度为 200-500A; 第一刻蚀阻挡层 6的厚度为 200-400A, 第二刻 蚀阻挡层 7的厚度为 200-500A。
在本实施例中， 与有源层 5相邻的栅极绝缘层和刻蚀阻挡层均釆用叠层 结构，且第二栅极绝缘层 4 (釆用 SiOx制成）和第一刻蚀阻挡层 6 (釆用 SiOx 制成 )分别与有源层 5直接相邻。 在该 TFT在制备过程中， 在刻蚀阻挡层刻 蚀过程中会进行过刻。 由于在同等条件下， SiOx的刻蚀速率远远小于 SiNx 材料的刻蚀速率， 因此， 第二刻蚀阻挡层 7中的 SiNx能很快被过刻， 而第一 刻蚀阻挡层 6中的 SiOx能起到很好的緩冲作用。在过刻第一刻蚀阻挡层 6中 的 SiOx时，不可避免地会使得没有被有源层 5覆盖的第二栅极绝缘层 4也同 时被过刻。 根据经验， 刻蚀过程中刻蚀速率相对刻蚀时间作用更为明显， 由 于在第一刻蚀阻挡层 6和第二栅极绝缘层 4的刻蚀速率相同， 因而可将第二 栅极绝缘层 4的厚度设计得比第一刻蚀阻挡层 6要厚一些， 这样可保证在第 一刻蚀阻挡层 6过刻完成时， 第二栅极绝缘层 4不会发生完全刻蚀。 在这种 情况下，第一栅极绝缘层 3不会被刻蚀，或者仅仅被刻蚀了非常小的一部分。 可见， 在过刻过程中， 能够保证刻蚀阻挡层中第一刻蚀阻挡层 6和第二刻蚀 阻挡层 7需要被刻蚀的部分都能被刻蚀掉。 制备 TFT以后， 在其上再形成钝 化层和像素电极， 便可以制成 TFT阵列基板。
在像素电极和公共电极均形成在 TFT阵列基板上的情况下， 例如， 公共 电极可以与栅极层设置在同一层（例如，参见图 3和图 4中的公共电极 11 )。 制成后的阵列基板中像素电极和公共电极之间只有第一栅极绝缘层 3和钝化 层 9, 或者只有第一栅极绝缘层 3 (即， 在 TFT之外， 钝化层 9也可以不设 置） ， 使得所述像素电极或钝化层与第一栅极绝缘层 3直接接触。 在制作根 据本实施例的 TFT阵列基板时， 能有效保证栅极绝缘层尽量少的被刻蚀掉， 即过刻对栅极绝缘层的影响非常小， 提高了金属氧化物 TFT的良率， 保证了 金属氧化物 TFT的工艺质量。 由于公共电极通常设置在与栅极同层， 此时， 像素电极和公共电极之间的距离减小， 所以又可以增大存储电容， 减少显示 屏的闪烁。
刻蚀阻挡层的宽度可以根据源漏极层间的间隔的宽度而设计。一般而言， 刻蚀阻挡层至少需要大于上述间隔的宽度， 以在刻蚀源漏电极图案时保护有 源层。 在上述设计规则下， 需要将刻蚀阻挡层的宽度设计得尽量小， 这样可 以增加有源层 5与源漏极的接触面积。 有源层的宽度依据刻蚀阻挡层和上述 间隔的宽度来进行设计。 在本实施例中有源层 5的宽度范围为 14-18μπι, 所 述刻蚀阻挡层的宽度范围为 8-10μπι, 上述宽度均比现有的宽度要小一些， 因 此源漏极和栅极之间的重叠面积会减小。寄生电容在 TFT充电完毕后会消耗 一些电压， 从而造成 TFT驱动电压的不足， 最终导致平板显示器出现显示不 良。 根据电容计算公式， 面积越小， 则电容越小。 因而将宽度设计得小一些， 可以减小源漏极和栅极之间的寄生电容。
本实施例中 TFT阵列基板的制备步骤为：先按现有技术工艺制备栅极层 2, 并完成栅极层图形； 接着在沉积设备中沉积形成第一栅极绝缘层 3 , 再在 同一沉积设备中低温沉积形成第二栅极绝缘层 4 , 形成第二栅极绝缘层所对 应的刻蚀气体包括 SF6、 CF4、 02或 Cl2, 并完成栅极绝缘层图形； 接着釆用 金属氧化物 IGZO进行有源层 5的沉积并形成有源层图形； 然后在有源层 5 上通过沉积设备沉积形成第一刻蚀阻挡层 6, 再在同一沉积设备中连续沉积 形成第二刻蚀阻挡层 7, 然后在曝光设备上经过一次曝光、 再经过刻蚀工艺 形成刻蚀阻挡层图形； 接着按现有技术工艺形成源漏极层 8, 最后形成钝化 层 9, 并完成透明电极层 10的制备。
本实施例中， 栅极绝缘层和刻蚀阻挡层中的双层结构可以在同一沉积设 备上连续进行沉积， 不会增加工艺步骤。 例如， 第一栅极绝缘层和第二栅极 绝缘层可以釆用高温沉积， 沉积温度为 350-400 。C, 第一刻蚀阻挡层和第二 刻蚀阻挡层釆用低温沉积， 沉积温度为 150-200 。C。 栅极绝缘层沉积在金属 氧化物半导体沉积前进行， 所以可以釆用高温沉积。 刻蚀阻挡层在金属氧化 物半导体沉积之后进行， 如果仍釆用高温沉积， 则会对半导体层形成破坏， 影响 TFT性能。 这里， 刻蚀阻挡层釆用低温沉积， 可以防止沉积过程对金属 氧化物半导体的破坏。
而且， 对第一刻蚀阻挡层和第二刻蚀阻挡层， 可以在同一干刻设备上进 行连续刻蚀， 刻蚀气体可以釆用 SF6、 CF4、 02或 Cl2, 使用过程中可根据工 艺条件选取合适的气体含量从而得到合适的刻蚀速率。
实施例 2:
如图 2所示， 本实施例中 TFT与实施例 1的区别在于， 所述 TFT中刻 蚀阻挡层只釆用一层， 即第一刻蚀阻挡层 6。
所述第一栅极绝缘层 3釆用 SiNx制成， 第二栅极绝缘层 4釆用 8 ( 制 成， 第二栅极绝缘层 4与有源层 5接触； 所述第一刻蚀阻挡层 6釆用 SiOx 制成，所述 SiOx层的厚度为 400-1000A,第一刻蚀阻挡层 6与有源层 5接触。
本实施例中 TFT的其他结构以及制备方法与实施例 1相同，这里不再赘 述。
包括本实施例中 TFT的阵列基板，其制备完成后的结构如图 3或图 4所 示。 图 3示出在像素电极 10和公共电极 11之间具有第二栅极绝缘层 4和钝 化层 9的示例。 图 4示出了在像素电极 10和公共电极 11之间仅存在第二栅 极绝缘层 4的示例。 需要说明的是， 图 3和图 4所示的 TFT阵列基板也可以 釆用才艮据本发明其他实施例提供的 TFT结构。 例如， 图 3和图 4中的 TFT 结构可以被图 1、 2或 5中所示的 TFT结构替换。 另外， 根据本发明实施例 的 TFT阵列基板的像素电极 10和 11的位置并不限定于图 3和图 4所示的情 况。 并且， 在某些情况下 （例如在垂直电场模式的液晶显示器中） ， 阵列基 板上也可以不包括公共电极。
实施例 3:
本实施例中 TFT与实施例 1的区别在于， 所述 TFT中栅极绝缘层釆用 多个子层的叠层结构。
栅极绝缘层包括第一栅极绝缘层 3和第二栅极绝缘层 4, 所述第一栅极 绝缘层 3和第二栅极绝缘层 4分别包含有顺序叠合的两层， 即第一栅极绝缘 层包括两个子层， 即下子层和上子层， 其中下子层通过高速沉积形成， 上子 层通过低速沉积形成； 第二栅极绝缘层中包括有两个子层， 即下子层和上子 层， 其中下子层通过高速沉积形成， 上子层通过低速沉积形成。
这样， 在 TFT的制备过程中， 高速沉积的下子层沉积速度较快， 比较节 约时间，而低速沉积的上子层沉积质量较好，更容易达到工艺要求，提升 TFT 特性。
本实施例中 TFT的其他结构以及制备方法与实施例 1相同，这里不再赘 述。
实施例 4:
本实施例中 TFT与实施例 2的区别在于， 所述 TFT釆用顶栅型结构， 即栅极层 2设置各层的最上方， 如图 5所示。 根据本发明实施例的方案不仅 能够应用于如图 1-3所示的底栅型结构， 而且还可以应用到如图 5所示的顶 栅极结构。 在图 5所示的实施例中， 栅极层 2位于层 9的上方， 此时， 层 9 和刻蚀阻挡层 6用作栅极绝缘层。 此时， 绝缘层 3和 4并不是用作栅极绝缘 层。 然而， 有源层 5下方的绝缘层 3和 4仍可釆用与上述实施例 1-3中所示 栅极绝缘层相同的构造。
本实施例中 TFT的其他结构以及制备方法均与实施例 1相同，这里不再 赘述。
实施例 1-实施例 4的 TFT中的绝缘保护层和刻蚀阻挡层中，与有源层相 邻的一层均釆用富氧材料制成。通过釆用 SiO^ 替目前用于制作栅极绝缘层 的 SiNx,从而可以防止 SiNx中的氢原子扩散到有源层中的金属氧化物内，也 可以防止有源层中金属氧化物内的氧原子扩散。 在这种情况下， 保证了有源 层 IGZO的稳定性， 使得金属氧化物 TFT具有较高的稳定性， 同时提高了金 属氧化物 TFT制备过程中的产品良率。 另外， 釆用这种金属氧化物 TFT制 备的阵列基板的性能也得到了提高， 釆用该阵列基板的显示器件的显示质量 得到了改善。
本发明实施例还提供一种阵列基板， 包括： 基板和形成在基板上的薄膜 晶体管， 其中薄膜晶体管釆用根据本发明任一实施例的薄膜晶体管。 第一栅 极绝缘层 3具有延伸到薄膜晶体管的区域之外的延伸部分。 阵列基板还包括 形成在第一栅极绝缘层 3的延伸部分上方的像素电极 10。
另外，所述像素电极可以与所述第一栅极绝缘层 3的延伸部分直接接触。 另外， 根据本发明实施例的阵列基板还可包括设置在薄膜晶体管上方以 及像素电极 10和第一栅极绝缘层 3之间的钝化层 9,且钝化层 9与第一绝缘 层 3的延伸部分直接接触。
虽然对上述阵列基板进行描述时使用了第一栅极绝缘层 3这一术语， 然 而， 图 5所示的 TFT也可以应用于上述 TFT阵列基板， 然而， 图 5中的绝 缘层 3和绝缘层 4不是用于栅极绝缘层。 因此， 根据上述实施例的 TFT阵列 基板中， 第一栅极绝缘层 3只是本发明 "第一子绝缘层" 的示例， 而第二栅 极绝缘层 4只是本发明 "第二子绝缘层" 的示例。
本发明实施例还提供一种显示器件， 包括阵列基板， 所述阵列基板釆用 根据本发明任一实施例中的阵列基板。 所述显示器件可以为液晶显示器件， 例如液晶面板、 液晶电视、 手机、 液晶显示器等， 其包括彩膜基板、 以及上 述实施例中的阵列基板； 除了液晶显示装置， 所述显示器件还可以是其他类 型的显示装置， 比如有机发光显示器等， 其不包括彩膜基板， 但是包括上述 实施例中的阵列基板。

Claims

权利要求书
1. 一种薄膜晶体管， 包括： 栅极层、 第一绝缘层、 有源层、 刻蚀阻挡层 和源漏极层， 其中，
所述有源层釆用金属氧化物材料制备，
所述第一绝缘层、 所述有源层、 所述刻蚀阻挡层和所述源漏极层从下至 上依次堆叠，
所述源漏极层中包括将源极和漏极分隔开的间隔， 所述刻蚀阻挡层处于 所述间隔下方， 且所述刻蚀阻挡层的宽度大于所述间隔的宽度， 以及
所述第一绝缘层包括层叠的第一子绝缘层和第二子绝缘层， 所述第二子 绝缘层与所述有源层接触， 并釆用富氧的绝缘材料制成。
2. 根据权利要求 1所述的薄膜晶体管， 其中， 所述栅极层位于所述第一 绝缘层的下方， 所述第一绝缘层用作栅极绝缘层。
3. 根据权利要求 1所述的薄膜晶体管， 其中， 所述第一子绝缘层和所述 第二子绝缘层釆用具有不同刻蚀速率的材料形成， 且所述第二子绝缘层的刻 蚀速率较小。
4. 根据权利要求 1所述的薄膜晶体管， 其中， 所述刻蚀阻挡层釆用富氧 材料制成。
5. 根据权利要求 1所述的薄膜晶体管， 其中， 所述刻蚀阻挡层包括层叠 的第一刻蚀阻挡层和第二刻蚀阻挡层， 所述第一刻蚀阻挡层与所述有源层接 触， 并釆用富氧材料制成。
6. 根据权利要求 5所述的薄膜晶体管， 其中， 所述第一刻蚀阻挡层和所 述第二刻蚀阻挡层釆用具有不同刻蚀速率的材料形成 , 且所述第一刻蚀阻挡 层的刻蚀速率较小。
7. 根据权利要求 1所述的薄膜晶体管， 其中， 所述第二子绝缘层与所述 第一子绝缘层的厚度比例在 1/10至 3/5的范围内。
8. 根据权利要求 5所述的薄膜晶体管， 其中， 所述第一刻蚀阻挡层与所 述第二刻蚀阻挡层的厚度比例在 1/2至 1/1的范围内。
9. 根据权利要求 1所述的薄膜晶体管， 其中， 所述第一子绝缘层的厚度 为 2000-5000A, 所述第二子绝缘层的厚度为 200-500A。
10. 根据权利要求 5所述的薄膜晶体管， 其中， 所述第一刻蚀阻挡层的 厚度为 200-400A, 所述第二刻蚀阻挡层的厚度为 200-500A。
11. 根据权利要求 5所述的薄膜晶体管， 其中， 所述第一子绝缘层和所 述第二刻蚀阻挡层由选自 SiNx、树脂和 SiC中的一种制成， 所述第二子绝缘 层和所述第一刻蚀阻挡层由选自 SiOx、 A1203、 SiNxOy和 Zr02中的一种制成。
12. 根据权利要求 1 所述的薄膜晶体管， 其中， 所述有源层釆用选自 IGZO、 ZnO、 Sn02、 In203和 IZO中的一种制成。
13. 根据权利要求 5所述的薄膜晶体管， 其中， 所述第二子绝缘层釆用 SiOx制成， 所述第一子绝缘层釆用 SiNx制成， 且所述第一子绝缘层和所述第 二子绝缘层通过高温沉积法形成； 所述第一刻蚀阻挡层釆用 SiOx制成， 所述 第二刻蚀阻挡层釆用 SiNx制成，且所述第一刻蚀阻挡层和所述第二刻蚀阻挡 层釆用低温沉积法形成。
14. 根据权利要求 1所述的薄膜晶体管， 其中， 所述有源层的宽度在 14 至 18μπι的范围内， 所述刻蚀阻挡层的宽度在 8至 ΙΟμπι的范围内。
15. 根据权利要求 1所述的薄膜晶体管， 其中， 所述有源层的两端部分 未被所述刻蚀阻挡层覆盖， 且所述有源层的未被所述刻蚀阻挡层覆盖的部分 与所述源漏极层接触。
16. 根据权利要求 1所述的薄膜晶体管， 还包括设置在所述源漏极层上 方的第二绝缘层， 其中所述栅极层设置在所述第二绝缘层上方。
17. 一种阵列基板， 包括：
基板；
形成在所述基板上的薄膜晶体管， 其中所述薄膜晶体管釆用根据权利要 求 1所述的薄膜晶体管， 其中，
所述第一绝缘层具有延伸到所述薄膜晶体管的区域之外的延伸部分， 以 及
所述阵列基板还包括形成在所述第一绝缘层的延伸部分上方的像素电 极。
18. 根据权利要求 17所述的阵列基板，其中所述像素电极与所述第一绝 缘层的延伸部分直接接触。
19. 根据权利要求 17所述的阵列基板，还包括设置在所述薄膜晶体管上 方以及所述像素电极和所述第一绝缘层之间的钝化层， 且所述钝化层与所述 第一绝缘层的延伸部分直接接触。
20. —种显示器件， 包括根据权利要求 17所述的阵列基板。
PCT/CN2012/083500 2011-12-31 2012-10-25 薄膜晶体管、阵列基板以及显示器件 WO2013097529A1 (zh)

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