WO2021103204A1 - 显示面板及其制备方法、显示装置 - Google Patents

显示面板及其制备方法、显示装置 Download PDF

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Publication number
WO2021103204A1
WO2021103204A1 PCT/CN2019/126133 CN2019126133W WO2021103204A1 WO 2021103204 A1 WO2021103204 A1 WO 2021103204A1 CN 2019126133 W CN2019126133 W CN 2019126133W WO 2021103204 A1 WO2021103204 A1 WO 2021103204A1
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Prior art keywords
layer
hole
insulating layer
metal layer
gate insulating
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PCT/CN2019/126133
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English (en)
French (fr)
Inventor
陈诚
Original Assignee
武汉华星光电半导体显示技术有限公司
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Priority to US16/638,767 priority Critical patent/US11495620B2/en
Publication of WO2021103204A1 publication Critical patent/WO2021103204A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

Definitions

  • the present invention relates to the field of display, in particular to a display panel, a preparation method thereof, and a display device.
  • OLED Organic Light-Emitting Diode
  • the purpose of the present invention is to solve the technical problem that the brightness uniformity of the existing display panel cannot meet the high requirements.
  • the present invention provides a display panel, which is divided into a display area, a line change area, and a bending area in the horizontal direction; the display panel includes a substrate, a barrier layer, a buffer layer, and an active layer from bottom to top.
  • a first gate insulating layer, a first metal layer, and a second gate insulating layer further comprising: a first through hole that sequentially penetrates the barrier layer, the buffer layer, and the The first gate insulating layer and the second gate insulating layer serve as source and drain lap openings; the second metal layer is partially disposed on the bottom and inner sidewalls of the first through hole and extends to all The surface of the second gate insulating layer; the first organic layer is provided on the surface of the second gate insulating layer away from the first gate insulating layer and in the first through hole; Two metal layers are partially provided on the surface of the first organic layer far away from the second gate insulating layer; an interlayer insulating layer is provided on the first organic layer far away from the second gate insulating layer The third metal layer is provided on the surface of the interlayer insulating layer away from the first organic layer; wherein, part of the third metal layer in the display area passes through the interlayer insulating layer , And electrically connected to the second metal layer shown.
  • the material of the first metal layer includes aluminum or aluminum alloy; and/or, the material of the second metal layer includes aluminum or aluminum alloy.
  • the display panel further includes a second through hole that penetrates the first organic layer in the display area, the second through hole is partially connected to the first through hole, and the other part is connected to the first through hole.
  • the bottom electrode pattern of a metal layer driving circuit capacitor is arranged oppositely to form a capacitor opening; wherein, the second metal layer is partially disposed in the second through hole, and is disposed far away from the second gate insulating layer. The surface on one side of the first gate insulating layer.
  • the display panel further includes a third through hole penetrating the interlayer insulating layer, the first organic layer, the second gate insulating layer, and the first gate insulating layer; and/or, The third through hole penetrates through the interlayer insulating layer and the first organic layer; and/or, the third through hole penetrates through the interlayer insulating layer.
  • the third metal layer is partially disposed in the third through hole.
  • the third metal layer is partially overlapped to the mesh traces of the second metal layer through the third through holes to form a parallel circuit.
  • the present invention also provides a display device, including the display device described above.
  • the present invention also provides a method for preparing a display panel, which in turn includes a substrate providing step, a barrier layer preparing step, a buffer layer preparing step, an active layer preparing step, a first gate insulating layer preparing step, and a first gate insulating layer preparing step.
  • the metal layer preparation step and the second gate insulating layer preparation step further include: a first through hole setting step, penetrating the barrier layer, the buffer layer, the first gate insulating layer, and the second gate A polar insulating layer, forming a first through hole; a first organic layer preparation step, a first organic layer is prepared on the upper surface of the second gate insulating layer and in the first through hole; a second metal layer preparation step , Exposing the first organic layer, forming a second metal layer on the bottom and inner sidewalls of the first through hole, and on the upper surface of the second gate insulating layer; forming a second metal layer on the upper surface of the first organic layer Two metal layers; an interlayer insulating layer preparation step, in which an interlayer insulating layer is prepared on the upper surface of the first organic layer and the second metal layer; and a third metal layer preparation step, in the interlayer insulating layer A third metal layer is prepared on the upper surface of the metal.
  • the method of preparing the display panel further includes a second through hole setting step, where a second through hole is provided at the first organic layer above the first metal layer; In the step of preparing the second metal layer, part of the second metal layer is disposed in the second through hole, and is disposed opposite to the first metal layer.
  • the method for preparing the display panel further includes: a fourth through hole setting step, disposing a fourth through hole on the interlayer insulating layer, so that the fourth The through hole penetrates the interlayer insulating layer and is disposed opposite to the first through hole; and the second organic layer preparation step is to prepare a second organic layer in the fourth through hole;
  • the third metal layer is partially provided on the upper surface of the second organic layer.
  • the technical effect of the present invention is that aluminum or aluminum alloy is used for the metal layer, which improves the electrical conductivity of the metal wiring and improves the bending characteristics of the metal wiring.
  • the data signal line in the bending area is directly arranged on the upper surface of the substrate, so that the data signal line is closer to the neutral surface, and the risk of breakage when the data signal line is bent is reduced.
  • the grid-shaped metal layer structure is used to form a double-layer power signal with a structure in which the source and drain layers are overlapped with the gate layer, which can reduce the resistance of the metal traces, thereby reducing the voltage drop of the display panel and improving the brightness uniformity of the display panel .
  • FIG. 1 is a cross-sectional view of a display panel according to an embodiment of the present invention
  • FIG. 2 is a top view of a display panel according to an embodiment of the invention.
  • FIG. 3 is a flowchart of a manufacturing method of a display panel according to an embodiment of the present invention.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present application, “multiple” means two or more than two, unless otherwise specifically defined.
  • connection should be understood in a broad sense, unless otherwise clearly specified and limited.
  • it can be a fixed connection or a detachable connection.
  • Connected or integrally connected it can be mechanically connected, or it can be electrically connected or can communicate with each other; it can be directly connected, or indirectly connected through an intermediary, it can be the internal communication of two components or the interaction of two components relationship.
  • connection should be understood according to specific circumstances.
  • the "on" or “under” of the first feature of the second feature may include direct contact between the first and second features, or may include the first and second features Not in direct contact but through other features between them.
  • the "above”, “above” and “above” of the first feature on the second feature include the first feature directly above and obliquely above the second feature, or it simply means that the first feature is higher in level than the second feature.
  • the “below”, “below” and “below” of the second feature of the first feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • this embodiment provides a display device including a display panel as shown in FIG. 1, the display panel is divided into a display area 100, a line change area 200, and a bending area 300 in the horizontal direction.
  • the display panel In the vertical direction, from bottom to top, it includes the substrate 101, the barrier layer 102, the buffer layer 103, the active layer 104, the first gate insulating layer 105, the first metal layer 106, the second gate insulating layer 107, and It includes a second metal layer 108, a first organic layer 109, an interlayer insulating layer 110, a third metal layer 111, a second organic layer 112, a flat layer 113, an anode layer 114, a pixel definition layer 115, and spacers 116.
  • the substrate 101 is a flexible substrate, which has the effect of blocking water and oxygen.
  • the substrate 101 can have better impact resistance and can effectively protect the display panel.
  • the material of the substrate 101 includes one or more of glass, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene terephthalate, polyimide, or polyurethane.
  • the barrier layer 102 is provided on the upper surface of the substrate 101 and plays a role of blocking water and oxygen.
  • the buffer layer 103 is provided on the upper surface of the barrier layer 102.
  • the buffer layer 103 serves as a buffer.
  • the material of the buffer layer 103 is silicon dioxide SiO2 or silicon nitride SiNx, which can be a single layer of SiO2 film or silicon dioxide SiO2.
  • the multilayer stack of silicon nitride SiNx, and the silicon dioxide SiO2 film layer is arranged on the top layer.
  • the active layer 104 is provided on the upper surface of the buffer layer 103.
  • the material of the active layer 104 is an oxide semiconductor, such as indium gallium zinc oxide IGZO, with a thickness of 300 A to 500 A (angstroms). In this embodiment, the thickness of the active layer 104 is preferably 400 A (angstroms).
  • the first gate insulating layer 105 is provided on the upper surfaces of the active layer 104 and the buffer layer 103, and the first gate insulating layer 105 plays an insulating role to prevent short circuit problems in the thin film transistor.
  • the first gate insulating layer 105 may be a single-layer SiO2 film layer or a multilayer stack of silicon dioxide SiO2, silicon nitride SiNx, and the silicon dioxide SiO2 film layer is provided on the bottom layer.
  • the first metal layer 106 is disposed on the upper surface of the first gate insulating layer 105 and is disposed opposite to the active layer 104.
  • the first metal layer 106 is a first gate layer, and the active layer directly under the first metal layer 106 retains semiconductor characteristics.
  • the material of the first metal layer 106 is metal. In this embodiment, it is preferably aluminum or aluminum alloy. Aluminum or aluminum alloy increases the electrical conductivity of the first metal layer 106, improves its bending characteristics, and reduces the first metal layer. 106 Fracture risk when being bent.
  • the second gate insulating layer 107 is provided on the upper surfaces of the first gate insulating layer 105 and the first metal layer 106, and the second gate insulating layer 107 plays an insulating role to prevent short circuit problems in the thin film transistor.
  • the second gate insulating layer 107 may be a single-layer SiO2 film layer or a multilayer stack of silicon dioxide SiO2, silicon nitride SiNx, and the silicon dioxide SiO2 film layer is provided on the bottom layer.
  • the first through hole sequentially penetrates the barrier layer 102, the buffer layer 103, the first gate insulating layer 105, and the second gate insulating layer 107 in the bending region 300, and serves as a source-drain lap hole.
  • the second metal layer 108 is disposed on the bottom of the first through hole and the inner sidewall thereof, and extends to the upper surface of the second gate insulating layer 107.
  • the material of the second metal layer 108 is metal. In this embodiment, it is preferably aluminum or aluminum alloy. Aluminum or aluminum alloy increases the conductivity of the second metal layer 108, improves its bending characteristics, and reduces the second metal layer. 108 Fracture risk when being bent.
  • the second metal layer 108 is used to transmit data signals.
  • the second metal layer 108 has a grid structure. Since FIG. 1 is a cross-sectional view of the display panel, the second metal layer 108 in FIG. 1 is a disconnected structure, but is actually a connected structure. The second metal layer 108 is provided at the bottom of the first through hole, which is closer to the neutral surface. Therefore, the second metal layer 108 is not easily broken when bent.
  • the first organic layer 109 is disposed on the upper surface of the second gate insulating layer 107 and in the first through hole.
  • the first organic layer 109 is an organic insulating layer, which has an insulating effect and prevents short circuit problems of various metal layers.
  • the second through hole penetrates through the first organic layer 109 of the display area 100, and the second through hole is partially connected to the first through hole and serves as a source-drain overlap hole; the other part is connected to the first metal layer 106
  • the lower electrode patterns of the capacitor of the driving circuit are arranged oppositely to form a capacitor opening.
  • the second metal layer 110 is disposed in the second through hole and the upper surface of the second gate insulating layer 107, and is disposed opposite to the first metal layer 106.
  • the second metal layer 110 is the second gate layer, and the material of the second metal layer 110 is metal.
  • it is preferably aluminum or aluminum alloy.
  • Aluminum or aluminum alloy improves the conductivity of the second metal layer 110 and improves Its bending characteristics reduce the risk of fracture of the second metal layer 110 when it is bent.
  • the interlayer insulating layer 110 is provided on the upper surfaces of the second metal layer 110 and the first organic layer 109.
  • the gate insulating layer 107 and the first gate insulating layer 105 provide channels for the subsequent third metal layer 111.
  • the third metal layer 111 is provided on the upper surface of the interlayer insulating layer 110, and is provided in the third through hole 117, partially electrically connected to the active layer 104, which is the source and drain layer, forming the third metal layer 111 and Electrical connection of the source layer 104.
  • the third metal layer 111 of the display area 100 is disposed in the third through hole 117 and is electrically connected to the second metal layer 110.
  • the second metal layer 110 has a mesh structure. See the top view of FIG. 2 for the metal layer resistance of the mesh structure. Smaller, can further reduce the voltage drop in the circuit.
  • the third metal layer 111 of the switching area 200 is disposed in the third through hole 117, is electrically connected to the second metal layer 108, and extends to the second metal layer 108 of the bending area 300 for carrying data signals.
  • the third metal layer 111 of the wire change area 200 is disposed in the third through hole, is electrically connected to the second metal layer 110, and directly changes wires to the second metal layer 108 in the bending area 300. Used to take data signals. Therefore, all the data signals in the bending area 300 are routed from the second metal layer 108.
  • the second metal layer 108 is provided at the bottom of the first through hole, which is closer to the neutral plane. Therefore, when bending, the second metal layer 108 The metal layer 108 is not easily broken.
  • the flat layer 113 is provided on the upper surfaces of the third metal layer 111 and the interlayer insulating layer 110, and the flat layer 113 functions to protect the underlying film layers.
  • the flat layer 113 is provided with a fourth through hole, the fourth through hole is arranged opposite to the first through hole, and the fourth through hole penetrates the flat layer 113 to provide a channel for subsequent film layers.
  • the second organic layer 112 is disposed in the fourth through hole, and the second organic layer 112 is an organic insulating layer, which plays a role of insulation and prevents short circuit problems in the metal layers of each layer.
  • the anode layer 114 is arranged on the upper surface of the flat layer 113 and is arranged opposite to the third metal layer 111.
  • the anode layer 114 passes through the flat layer 113 and is electrically connected to the third metal layer 111, which can obtain electrical signals from the thin film transistor, which is luminous.
  • the luminescence of the layer provides an electrical signal.
  • the fifth metal layer is a VI trace for carrying the initialization voltage signal.
  • the fifth metal layer can be provided on the third metal layer 111 or the anode layer 114 to provide an initial voltage signal for the display panel.
  • the fifth metal layer and the third metal layer 111 form a double-layer voltage trace, which can reduce resistance, further reduce voltage drop, and improve the brightness uniformity of the display panel.
  • the pixel definition layer 115 is provided on the upper surfaces of the flat layer 113 and the anode layer 114 to define the size of the light-emitting layer.
  • the pixel definition layer 115 is provided with a pixel definition layer through hole.
  • the pixel definition layer through hole penetrates the pixel definition layer 115 and is arranged opposite to the anode layer 114 to provide a channel for the subsequent light-emitting layer.
  • the spacer 116 is provided on the upper surface of the pixel definition layer 115 to support the subsequent film layer, prevent the problem of collapse and deformation, and ensure the yield of the display panel.
  • the technical effect of the display panel in this embodiment is that the metal layer is made of aluminum or aluminum alloy, which improves the electrical conductivity of the metal wiring and improves the bending characteristics of the metal wiring.
  • the data signal line in the bending area is directly arranged on the upper surface of the substrate, so that the data signal line is closer to the neutral surface, and the risk of breakage when the data signal line is bent is reduced.
  • the grid-shaped metal layer structure is used to form a double-layer power signal with a structure in which the source and drain layers are overlapped with the gate layer, which can reduce the resistance of the metal traces, thereby reducing the voltage drop of the display panel and improving the brightness uniformity of the display panel .
  • the present invention also provides a method for manufacturing a display panel, including steps S1 to S.
  • the step of providing the S1 substrate is to provide a substrate, the substrate is a flexible substrate, has a function of blocking water and oxygen, the substrate can have better impact resistance, and can effectively protect the display panel.
  • a barrier layer is prepared on the upper surface of the substrate, and the barrier layer plays a role of blocking water and oxygen.
  • a buffer layer is prepared on the upper surface of the barrier layer, the buffer layer plays a buffer role, and the material of the buffer layer is silicon dioxide SiO2 or silicon nitride SiNx, which may be a single layer
  • the SiO2 film layer or the multilayer stack of silicon dioxide SiO2 and silicon nitride SiNx, and the silicon dioxide SiO2 film layer is arranged on the top layer.
  • an active layer is prepared on the upper surface of the buffer layer.
  • the first gate insulating layer preparation step a first gate insulating layer is prepared on the upper surface of the active layer and the buffer layer, the insulating material can be deposited by vapor deposition method, and the first gate insulating layer is formed after curing Layer to prevent short circuit problems between various metal lines.
  • the second gate insulating layer preparation step a second gate insulating layer is prepared on the upper surface of the first gate insulating layer and the first metal layer, and the insulating material can be deposited by vapor deposition method, and formed after curing
  • the second gate insulating layer prevents short circuits between the metal lines.
  • the first through hole setting step is to set a first through hole through a mask, and the first through hole sequentially penetrates the barrier layer, the buffer layer, the first gate insulating layer, and the first through hole. Two gate insulating layer.
  • the first organic layer preparation step a first organic layer is prepared on the upper surface of the second gate insulating layer, the material of the first organic layer is an organic insulating material, which can prevent short circuits between the metal layers .
  • a second through hole setting step opening a second through hole on the first organic layer.
  • a second through hole is etched at the first organic layer above the first metal layer to provide a channel for the subsequent metal layer.
  • a second metal layer preparation step exposing the first organic layer, forming a second metal layer on the bottom and inner sidewalls of the first via hole, and on the upper surface of the second gate insulating layer; The upper surface of the organic layer forms a second metal layer.
  • an interlayer insulating layer is prepared on the upper surfaces of the first organic layer and the second metal layer.
  • the fourth through hole setting step is to provide a fourth through hole on the interlayer insulating layer, so that the fourth through hole penetrates the interlayer insulating layer and is disposed opposite to the first through hole.
  • the second organic layer preparation step is to prepare a second organic layer in the fourth through hole.
  • the third metal layer preparation step is to prepare a third metal layer on the upper surface of the interlayer insulating layer and the second organic layer.
  • a flat layer is prepared on the upper surface of the interlayer insulating layer and the third metal layer.
  • a mask is used to open a flat layer through hole on the flat layer to provide a channel for the subsequent anode layer.
  • an anode layer is prepared on the upper surface of the flat layer and in the through holes of the flat layer, so that the anode layer is electrically connected to the third metal layer, and can be disposed on the anode layer
  • the fifth metal layer is used to carry the initial voltage signal and provide the initial voltage signal to the entire display panel.
  • a pixel definition layer is prepared on the upper surface of the flat layer and the anode layer, and the pixel definition layer can be used to define the size of the light-emitting layer.
  • Step S20 spacer setting step: setting spacers above the pixel definition layer.
  • the deposited metal material is preferably aluminum or aluminum alloy, and aluminum or aluminum alloy is improved.
  • the conductivity of the metal layer is improved, its bending characteristics are improved, and the risk of fracture of the metal layer when it is bent is reduced.
  • the manufacturing method of the display panel may further include: a light-emitting layer preparation step, a pixel electrode layer preparation step, etc., as all of them are prior art and will not be repeated here.
  • the technical effect of the manufacturing method of the display panel according to the embodiment of the present invention is that the metal layer is made of aluminum or aluminum alloy, which improves the electrical conductivity of the metal wiring and improves the bending characteristics of the metal wiring.
  • the data signal line in the bending area is directly arranged on the upper surface of the substrate, so that the data signal line is closer to the neutral surface, and the risk of breakage when the data signal line is bent is reduced.
  • the grid-shaped metal layer structure is used to form a double-layer power signal with a structure in which the source and drain layers are overlapped with the gate layer, which can reduce the resistance of the metal traces, thereby reducing the voltage drop of the display panel and improving the brightness uniformity of the display panel .

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Abstract

一种显示面板及其制备方法、显示装置，显示面板在水平方向上被划分为显示区（100）、换线区（200）及弯折区（300）；显示面板从下至上依次包括基板（101）、阻隔层（102）、缓冲层（103）、有源层（104）、第一栅极绝缘层（105）、第一金属层（106）及第二栅极绝缘层（107），还包括：第一通孔、第二金属层（108）、第一有机层（109）、层间绝缘层（110）、第三金属层（111）；其中，位于显示区（100）的部分第三金属层（111）穿过层间绝缘层（110），电连接至第二金属层（108）。

Description

显示面板及其制备方法、显示装置 
本申请要求于2019年11月26日提交中国专利局、申请号为201911169679.6、发明名称为“显示面板及其制备方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示领域，特别涉及一种显示面板及其制备方法、显示装置。
 背景技术
OLED（Organic Light-Emitting Diode）由于其重量轻，自发光，广视角、驱动电压低、发光效率高功耗低、响应速度快等优点，应用范围越来越广泛，尤其是柔性OLED显示装置具有可弯折易携带的特点，成为显示技术领域研究和开发的主要领域。
目前高端手机对亮度均一性要求较高，如何提升屏幕的亮度均一性是各大厂商开发的重点方向。
 技术问题
本发明的目的在于，解决现有的显示面板的亮度均一性无法满足高要求的技术问题。
 技术解决方案
为实现上述目的，本发明提供一种显示面板，在水平方向上被划分为显示区、换线区及弯折区；所述显示面板从下至上依次包括基板、阻隔层、缓冲层、有源层、第一栅极绝缘层、第一金属层及第二栅极绝缘层，还包括：第一通孔，依次贯穿位于所述弯折区的所述阻隔层、所述缓冲层、所述第一栅极绝缘层及所述第二栅极绝缘层，作为源漏极搭接开孔；第二金属层，部分地设于所述第一通孔的底部及内侧壁，且延伸至所述第二栅极绝缘层的表面；第一有机层，设于所述第二栅极绝缘层远离所述第一栅极绝缘层一侧的表面及所述第一通孔内；所述第二金属层部分地设于所述第一有机层远离所述第二栅极绝缘层一侧的表面；层间绝缘层，设于所述第一有机层远离所述第二栅极绝缘层一侧的表面；第三金属层，设于所述层间绝缘层远离所述第一有机层一侧的表面；其中，位于所述显示区的部分第三金属层穿过所述层间绝缘层，电连接至所示第二金属层。
进一步地，所述第一金属层材质包括铝或者铝合金；和/或，所述第二金属层材质包括铝或者铝合金。
进一步地，所述显示面板还包括第二通孔，贯穿所述显示区内的第一有机层，所述第二通孔部分地连通至所述第一通孔，另一部分与与所述第一金属层驱动电路电容下电极图形相对设置，为形成电容开孔；其中，所述第二金属层部分地设于所述第二通孔内，且设于所述第二栅极绝缘层远离所述第一栅极绝缘层一侧的表面。
进一步地，所述显示面板还包括第三通孔，贯穿于所述层间绝缘层、所述第一有机层、所述第二栅极绝缘层及第一栅极绝缘层；和/或，第三通孔，贯穿于所述层间绝缘层及所述第一有机层；和/或，第三通孔，贯穿于所述层间绝缘层。
进一步地，所述第三金属层部分地设于所述第三通孔内。
进一步地，所述第三金属层通过所述第三通孔部分地搭接至所述第二金属层的网状走线，形成并联电路。
为实现上述目的，本发明还提供一种显示装置，包括前文所述的显示装置。
为实现上述目的，本发明还提供一种显示面板的制备方法，依次包括基板提供步骤、阻隔层制备步骤、缓冲层制备步骤、有源层制备步骤、第一栅极绝缘层制备步骤、第一金属层制备步骤及第二栅极绝缘层制备步骤，还包括：第一通孔设置步骤，穿透所述阻隔层、所述缓冲层、所述第一栅极绝缘层及所述第二栅极绝缘层，形成第一通孔；第一有机层制备步骤，在所述第二栅极绝缘层的上表面及所述第一通孔内制备出第一有机层；第二金属层制备步骤，曝光所述第一有机层，在所述第一通孔的底部及内侧壁、所述第二栅极绝缘层上表面形成第二金属层；在所述第一有机层的上表面形成第二金属层；层间绝缘层制备步骤，在所述第一有机层及所述第二金属层的上表面制备出层间绝缘层；以及第三金属层制备步骤，在所述层间绝缘层的上表面制备出第三金属层。
进一步地，在所述第一有机层制备步骤之后，所述显示面板的制备方法还包括第二通孔设置步骤，在所述第一金属层上方的第一有机层处设置第二通孔；在所述第二金属层制备步骤中，部分第二金属层设于所述第二通孔内，与所述第一金属层相对设置。
进一步地，在所述层间绝缘层制备步骤之后，所述显示面板的制备方法还包括：第四通孔设置步骤，在所述层间绝缘层上设置第四通孔，使得所述第四通孔贯穿于所述层间绝缘层，且与所述第一通孔相对设置；以及第二有机层制备步骤，在所述第四通孔内制备出第二有机层；在所述第三金属层制备步骤中，所述第三金属层部分地设于所述第二有机层的上表面。
 有益效果
本发明的技术效果在于，金属层采用铝或铝合金，提高金属走线是电导率，改善金属走线的弯折特性。弯折区的数据信号线直接设于基板上表面，使得数据信号线更接近于中性面，降低数据信号线弯折时的断裂风险。采用网格形的金属层结构，源漏极与栅极层搭接的结构，形成双层电源信号，可降低金属走线的电阻，进而降低显示面板的压降，改善显示面板的亮度均一性。
 附图说明
图1为本发明实施例所述显示面板的截面图；
图2为本发明实施例所述显示面板的俯视图；
图3为本发明实施例所述显示面板的制备方法的流程图。
部分组件标识如下：
100、显示区；200、换线区；300、弯折区；
101、基板；102、阻隔层；103、缓冲层；104、有源层；105、第一栅极绝缘层；106、第一金属层；107、第二栅极绝缘层；108、第二金属层；109、第一有机层；110、层间绝缘层；111、第三金属层；112、第二有机层；113、平坦层；114、阳极层；115、像素定义层；116、隔垫物；117、第三通孔。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
具体的，本实施例提供一种显示装置，包括如图1所示的显示面板，所述显示面板在水平方向上被划分为显示区100、换线区200及弯折区300。在竖直方向上，从下至上依次包括基板101、阻隔层102、缓冲层103、有源层104、第一栅极绝缘层105、第一金属层106、第二栅极绝缘层107，还包括第二金属层108、第一有机层109、层间绝缘层110、第三金属层111、第二有机层112、平坦层113、阳极层114、像素定义层115及隔垫物116。
基板101为柔性基板，具有阻隔水氧作用，基板101可具有较好的抗冲击能力，可以有效保护显示面板。基板101的材质包括玻璃、二氧化硅、聚乙烯、聚丙烯、聚苯乙烯、聚乳酸、聚对苯二甲酸乙二醇酯、聚酰亚胺或聚氨酯中的一种或多种。
阻隔层102设于基板101的上表面，起到阻隔水氧的作用。
缓冲层103设于阻隔层102的上表面，缓冲层103起到缓冲作用，缓冲层103的材质为二氧化硅SiO2或者硅的氮化物SiNx，可为单层SiO2膜层或者二氧化硅SiO2、硅的氮化物SiNx的多层堆叠，且二氧化硅SiO2膜层设于顶层。
有源层104设于缓冲层103的上表面。有源层104的材质为氧化物半导体，例如铟镓锌氧化物IGZO，厚度为300A~500A（埃），在本实施例中，有源层104的厚度优选为400A（埃）。
第一栅极绝缘层105设于有源层104及缓冲层103的上表面，第一栅极绝缘层105起到绝缘作用，防止薄膜晶体管内部发生短路问题。第一栅极绝缘层105可为单层SiO2膜层或者二氧化硅SiO2、硅的氮化物SiNx的多层堆叠，且二氧化硅SiO2膜层设于底层。
第一金属层106设于第一栅极绝缘层105的上表面，且与有源层104相对设置。第一金属层106为第一栅极层，设于第一金属层106正下方的有源层保留半导体特性。第一金属层106的材质为金属，在本实施例中，优选为铝或铝合金，铝或铝合金提升了第一金属层106的电导率，改善其弯折特性，降低了第一金属层106在被弯折时的断裂风险。
第二栅极绝缘层107设于第一栅极绝缘层105及第一金属层106的上表面，第二栅极绝缘层107起到绝缘作用，防止薄膜晶体管内部发生短路问题。第二栅极绝缘层107可为单层SiO2膜层或者二氧化硅SiO2、硅的氮化物SiNx的多层堆叠，且二氧化硅SiO2膜层设于底层。
第一通孔依次贯穿于弯折区300内的阻隔层102、缓冲层103、第一栅极绝缘层105及第二栅极绝缘层107，作为源漏极搭接开孔。
第二金属层108设于所述第一通孔的底部及其内侧壁，且延伸至第二栅极绝缘层107的上表面。第二金属层108的材质为金属，在本实施例中，优选为铝或铝合金，铝或铝合金提升了第二金属层108的电导率，改善其弯折特性，降低了第二金属层108在被弯折时的断裂风险。第二金属层108用以传输数据信号。
第二金属层108为网格状结构，由于图1为显示面板的截面图，所以在图1中的第二金属层108为断开的结构，但实际为相连的结构。第二金属层108设于所述第一通孔的底部，更接近于中性面，所以，在弯折时，第二金属层108不易断裂。
第一有机层109设于第二栅极绝缘层107的上表面及所述第一通孔内，第一有机层109为有机绝缘层，起到绝缘作用，防止各层金属层出现短路问题。
第二通孔贯穿于显示区100的第一有机层109，所述第二通孔部分地连通至所述第一通孔，作为源漏极搭接开孔；另一部分与第一金属层106的驱动电路电容下电极图形相对设置，为形成电容开孔。
第二金属层110设于所述第二通孔内及第二栅极绝缘层107的上表面，且与第一金属层106相对设置。第二金属层110为第二栅极层，第二金属层110材质为金属，在本实施例中，优选为铝或铝合金，铝或铝合金提升了第二金属层110的电导率，改善其弯折特性，降低了第二金属层110在被弯折时的断裂风险。
层间绝缘层110设于第二金属层110及第一有机层109的上表面，层间绝缘层110上设有两个以上第三通孔117，第三通孔117穿过层间绝缘层110，和/或，第三通孔117穿过层间绝缘层110及第一有机层109，和/或，第三通孔117贯穿于层间绝缘层110、第一有机层109、第二栅极绝缘层107及第一栅极绝缘层105，为后续第三金属层111提供通道。
第三金属层111设于层间绝缘层110的上表面，且设于第三通孔117内，部分地电连接至有源层104，为源漏极层，形成第三金属层111与有源层104的电性连接。
显示区100的第三金属层111设于第三通孔117内，电连接至第二金属层110，第二金属层110为网状结构，参见图2的俯视图，网状结构的金属层电阻较小，可进一步降低电路中的压降。
换线区200的第三金属层111设于第三通孔117内，电连接至第二金属层108，延伸到弯折区300的第二金属层108，用以走数据信号。换线区200的第三金属层111设于所述第三通孔内，电连接至第二金属层110，在弯折区300直接换线到第二金属层108。用以走数据信号。所以，弯折区300所有的数据信号都从第二金属层108走，二金属层108设于所述第一通孔的底部，更接近于中性面，所以，在弯折时，第二金属层108不易断裂。
平坦层113设于第三金属层111及层间绝缘层110的上表面，平坦层113起到保护下面各膜层的作用。平坦层113上设有第四通孔，所述第四通孔与所述第一通孔相对设置，所述第四通孔贯穿平坦层113，为后续膜层提供通道。
第二有机层112设于所述第四通孔内，第二有机层112为有机绝缘层，起到绝缘作用，防止各层金属层出现短路问题。
阳极层114设于平坦层113的上表面，且与第三金属层111相对设置，阳极层114穿过平坦层113，电连接至第三金属层111，可从薄膜晶体管获得电信号，为发光层的发光提供电信号。
第五金属层为VI走线，用以走初始化电压信号，所述第五金属层可设于第三金属层111或阳极层114上，为显示面板提供初始的电压信号。所述第五金属层与第三金属层111形成双层电压走线，可降低电阻，进一步降低压降，改善显示面板的亮度均一性。
像素定义层115设于平坦层113及阳极层114的上表面，用以定义发光层的大小。像素定义层115上设有像素定义层通孔，所述像素定义层通孔贯穿像素定义层115，与阳极层114相对设置，为后续的发光层提供通道。
隔垫物116设于像素定义层115的上表面，用以支撑后续膜层，防止出现坍塌变形的问题，保障显示面板的良率。
本实施例所述显示面板的技术效果在于，金属层采用铝或铝合金，提高金属走线是电导率，改善金属走线的弯折特性。弯折区的数据信号线直接设于基板上表面，使得数据信号线更接近于中性面，降低数据信号线弯折时的断裂风险。采用网格形的金属层结构，源漏极与栅极层搭接的结构，形成双层电源信号，可降低金属走线的电阻，进而降低显示面板的压降，改善显示面板的亮度均一性。
如图3所示，本发明还提供一种显示面板的制备方法，包括步骤S1~S。
S1基板提供步骤，提供一基板，所述基板为柔性基板，具有阻隔水氧作用，所述基板可具有较好的抗冲击能力，可以有效保护显示面板。
S2 阻隔层制备步骤，在所述基板的上表面制备出阻隔层，所述阻隔层起到阻隔水氧的作用。
S3缓冲层制备步骤，在所述阻隔层的上表面制备出缓冲层，所述缓冲层起到缓冲作用，所述缓冲层的材质为二氧化硅SiO2或者硅的氮化物SiNx，可为单层SiO2膜层或者二氧化硅SiO2、硅的氮化物SiNx的多层堆叠，且二氧化硅SiO2膜层设于顶层。
S4有源层制备步骤，在所述缓冲层的上表面制备出有源层。
S5第一栅极绝缘层制备步骤，在所述有源层及所述缓冲层的上表面制备出第一栅极绝缘层，可采用气相沉积法沉积绝缘材料，固化后形成第一栅极绝缘层，防止各金属线路之间造成短路问题。
S6 第一金属层制备步骤，在所述第一栅极绝缘层的上表面制备出第一金属层。
S7第二栅极绝缘层制备步骤，在所述第一栅极绝缘层及所述第一金属层的上表面制备出第二栅极绝缘层，可采用气相沉积法沉积绝缘材料，固化后形成第二栅极绝缘层，防止各金属线路之间造成短路问题。
S8 第一通孔设置步骤，通过掩膜板在设置第一通孔，所述第一通孔依次贯穿于所述阻隔层、所述缓冲层、所述第一栅极绝缘层及所述第二栅极绝缘层。
S9第一有机层制备步骤，在所述第二栅极绝缘层的上表面制备出第一有机层，所述第一有机层的材质为有机绝缘材料，可防止各金属层之间造成短路问题。
S10 第二通孔设置步骤，在所述第一有机层上开设第二通孔。在所述第一金属层的上方的第一有机层处刻蚀出第二通孔，为后续金属层提供通道。
S11 第二金属层制备步骤，曝光所述第一有机层，在所述第一通孔的底部及内侧壁、所述第二栅极绝缘层上表面形成第二金属层；在所述第一有机层的上表面形成第二金属层。
S12层间绝缘层制备步骤，在所述第一有机层及所述第二金属层的上表面制备出层间绝缘层。
S13 第四通孔设置步骤，在所述层间绝缘层上设置第四通孔，使得所述第四通孔贯穿于所述层间绝缘层，且与所述第一通孔相对设置。
S14第二有机层制备步骤，在所述第四通孔内制备出第二有机层。
S15 第三金属层制备步骤，在所述层间绝缘层及所述第二有机层的上表面制备出第三金属层。
S16 平坦层制备步骤，在所述层间绝缘层及所述第三金属层的上表面制备出平坦层。
S17平坦层开孔步骤，采用掩膜板在所述平坦层上开设一平坦层通孔，用以为后续的阳极层提供通道。
S18 阳极层制备步骤，在所述平坦层的上表面及所述平坦层通孔内制备出阳极层，使得所述阳极层电连接至所述第三金属层，可在所述阳极层上设置第五金属层，所述第五金属层用以走初始电压信号，给整个显示面板提供初始电压信号。
S19像素定义层制备步骤，在所述平坦层及所述阳极层的上表面制备出像素定义层，所述像素定义层可用以定义发光层的大小。
S20 隔垫物设置步骤，在所述像素定义层的上方设置隔垫物。
在金属层制备步骤（所述第一金属层制备、所述第二金属层制备步骤及所述第三金属层制备步骤）中，沉积的金属材质优选为铝或铝合金，铝或铝合金提升了金属层电导率，改善其弯折特性，降低了金属层在被弯折时的断裂风险。
在所述像素定义层之后，所述显示面板的制备方法还可包括：发光层制备步骤，像素电极层制备步骤等，因其都为现有技术，在此不作赘述。
本发明实施例所述显示面板的制备方法的技术效果在于，金属层采用铝或铝合金，提高金属走线是电导率，改善金属走线的弯折特性。弯折区的数据信号线直接设于基板上表面，使得数据信号线更接近于中性面，降低数据信号线弯折时的断裂风险。采用网格形的金属层结构，源漏极与栅极层搭接的结构，形成双层电源信号，可降低金属走线的电阻，进而降低显示面板的压降，改善显示面板的亮度均一性。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种显示面板及其制备方法、显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (10)

  1. 一种显示面板，其中，在水平方向上被划分为显示区、换线区及弯折区；
    所述显示面板从下至上依次包括基板、阻隔层、缓冲层、有源层、第一栅极绝缘层、第一金属层及第二栅极绝缘层，还包括：
    第一通孔，依次贯穿位于所述弯折区的所述阻隔层、所述缓冲层、所述第一栅极绝缘层及所述第二栅极绝缘层，作为源漏极搭接开孔；
    第二金属层，部分地设于所述第一通孔的底部及内侧壁，且延伸至所述第二栅极绝缘层的表面；
    第一有机层，设于所述第二栅极绝缘层远离所述第一栅极绝缘层一侧的表面及所述第一通孔内；所述第二金属层部分地设于所述第一有机层远离所述第二栅极绝缘层一侧的表面；
    层间绝缘层，设于所述第一有机层远离所述第二栅极绝缘层一侧的表面；以及
    第三金属层，设于所述层间绝缘层远离所述第一有机层一侧的表面；
    其中，位于所述显示区的部分第三金属层穿过所述层间绝缘层，电连接至所示第二金属层。
  2. 如权利要求1所述的显示面板，其中，
    所述第一金属层材质包括铝或者铝合金；和/或，
    所述第二金属层材质包括铝或者铝合金。
  3. 如权利要求1所述的显示面板，其还包括
    第二通孔，贯穿所述显示区内的第一有机层，所述第二通孔部分地连通至所述第一通孔，作为源漏极搭接开孔；另一部分与所述第一金属层驱动电路电容下电极图形相对设置，为形成电容开孔；
    其中，所述第二金属层部分地设于所述第二通孔内，且设于所述第二栅极绝缘层远离所述第一栅极绝缘层一侧的表面。
  4. 如权利要求1所述的显示面板，其还包括
    第三通孔，贯穿于所述层间绝缘层、所述第一有机层、所述第二栅极绝缘层及第一栅极绝缘层；和/或，
    第三通孔，贯穿于所述层间绝缘层及所述第一有机层；和/或，
    第三通孔，贯穿于所述层间绝缘层。
  5. 如权利要求4所述的显示面板，其中，
    所述第三金属层部分地设于所述第三通孔内。
  6. 如权利要求4所述的显示面板，其中，
    所述第三金属层通过所述第三通孔部分地搭接至所述第二金属层的网状走线，形成并联电路。
  7. 一种显示装置，包括如权利要求1所述的显示面板。
  8. 一种显示面板的制备方法，其依次包括基板提供步骤、阻隔层制备步骤、缓冲层制备步骤、有源层制备步骤、第一栅极绝缘层制备步骤、第一金属层制备步骤及第二栅极绝缘层制备步骤，还包括：
    第一通孔设置步骤，穿透所述阻隔层、所述缓冲层、所述第一栅极绝缘层及所述第二栅极绝缘层，形成第一通孔；
    第一有机层制备步骤，在所述第二栅极绝缘层的上表面及所述第一通孔内制备出第一有机层；
    第二金属层制备步骤，曝光所述第一有机层，在所述第一通孔的底部及内侧壁、所述第二栅极绝缘层上表面形成第二金属层；在所述第一有机层的上表面形成第二金属层；
    层间绝缘层制备步骤，在所述第一有机层及所述第二金属层的上表面制备出层间绝缘层；以及
    第三金属层制备步骤，在所述层间绝缘层的上表面制备出第三金属层。
  9. 如权利要求8所述的显示面板的制备方法，其中，
    在所述第一有机层制备步骤之后，还包括
    第二通孔设置步骤，在所述第一金属层上方的第一有机层处设置第二通孔；
    在所述第二金属层制备步骤中，
    部分第二金属层设于所述第二通孔内，与所述第一金属层相对设置。
  10. 如权利要求8所述的显示面板的制备方法，其中，
    在所述层间绝缘层制备步骤之后，还包括：
    第四通孔设置步骤，在所述层间绝缘层上设置第四通孔，使得所述第四通孔贯穿于所述层间绝缘层，且与所述第一通孔相对设置；以及
    第二有机层制备步骤，在所述第四通孔内制备出第二有机层；
    在所述第三金属层制备步骤中，
    所述第三金属层部分地设于所述第二有机层的上表面。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113900542A (zh) * 2021-10-08 2022-01-07 昆山国显光电有限公司 触控面板及其制备方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111540757B (zh) * 2020-05-07 2024-03-05 武汉华星光电技术有限公司 显示面板及其制备方法、显示装置
CN111584570A (zh) * 2020-05-13 2020-08-25 武汉华星光电半导体显示技术有限公司 显示面板以及显示装置
CN111769142B (zh) * 2020-06-23 2022-07-12 武汉华星光电半导体显示技术有限公司 一种显示面板及其制备方法、显示装置
CN112086576B (zh) * 2020-09-07 2022-09-09 武汉华星光电半导体显示技术有限公司 一种显示面板及制程方法
CN113053969B (zh) * 2021-03-10 2023-06-30 深圳市华星光电半导体显示技术有限公司 显示面板及显示装置
CN114093277A (zh) * 2021-12-09 2022-02-25 武汉华星光电半导体显示技术有限公司 拼接屏

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8173494B2 (en) * 2006-11-21 2012-05-08 Samsung Electronics Co., Ltd. Thin film transistor array and method of manufacturing the same
CN108288631A (zh) * 2017-01-09 2018-07-17 昆山工研院新型平板显示技术中心有限公司 柔性oled显示面板及其形成方法
CN109300848A (zh) * 2018-08-24 2019-02-01 武汉华星光电半导体显示技术有限公司 制作柔性阵列基板的方法以及柔性阵列基板
CN109585511A (zh) * 2018-12-03 2019-04-05 武汉华星光电半导体显示技术有限公司 显示面板及其制造方法
CN109659339A (zh) * 2018-12-10 2019-04-19 武汉华星光电半导体显示技术有限公司 可折叠显示面板及其制作方法和可折叠显示装置
CN109742121A (zh) * 2019-01-10 2019-05-10 京东方科技集团股份有限公司 一种柔性基板及其制备方法、显示装置
CN110265409A (zh) * 2019-06-20 2019-09-20 武汉华星光电半导体显示技术有限公司 一种tft阵列基板、其制备方法及其显示面板
CN110429116A (zh) * 2019-07-24 2019-11-08 武汉华星光电半导体显示技术有限公司 一种阵列基板、显示面板及阵列基板的制造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108389869B (zh) * 2018-03-01 2020-09-22 上海天马微电子有限公司 柔性显示面板
CN109065575A (zh) * 2018-07-24 2018-12-21 武汉华星光电半导体显示技术有限公司 显示面板及其制备方法、显示装置
CN109166880A (zh) * 2018-07-25 2019-01-08 武汉华星光电半导体显示技术有限公司 柔性oled显示面板及其制备方法
CN109686758A (zh) * 2018-12-04 2019-04-26 武汉华星光电半导体显示技术有限公司 一种柔性显示面板及其制备方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8173494B2 (en) * 2006-11-21 2012-05-08 Samsung Electronics Co., Ltd. Thin film transistor array and method of manufacturing the same
CN108288631A (zh) * 2017-01-09 2018-07-17 昆山工研院新型平板显示技术中心有限公司 柔性oled显示面板及其形成方法
CN109300848A (zh) * 2018-08-24 2019-02-01 武汉华星光电半导体显示技术有限公司 制作柔性阵列基板的方法以及柔性阵列基板
CN109585511A (zh) * 2018-12-03 2019-04-05 武汉华星光电半导体显示技术有限公司 显示面板及其制造方法
CN109659339A (zh) * 2018-12-10 2019-04-19 武汉华星光电半导体显示技术有限公司 可折叠显示面板及其制作方法和可折叠显示装置
CN109742121A (zh) * 2019-01-10 2019-05-10 京东方科技集团股份有限公司 一种柔性基板及其制备方法、显示装置
CN110265409A (zh) * 2019-06-20 2019-09-20 武汉华星光电半导体显示技术有限公司 一种tft阵列基板、其制备方法及其显示面板
CN110429116A (zh) * 2019-07-24 2019-11-08 武汉华星光电半导体显示技术有限公司 一种阵列基板、显示面板及阵列基板的制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113900542A (zh) * 2021-10-08 2022-01-07 昆山国显光电有限公司 触控面板及其制备方法
CN113900542B (zh) * 2021-10-08 2023-09-22 昆山国显光电有限公司 触控面板及其制备方法

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