WO2020093478A1 - 一种tft的制备方法、tft、oled背板和显示装置 - Google Patents

一种tft的制备方法、tft、oled背板和显示装置 Download PDF

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WO2020093478A1
WO2020093478A1 PCT/CN2018/117794 CN2018117794W WO2020093478A1 WO 2020093478 A1 WO2020093478 A1 WO 2020093478A1 CN 2018117794 W CN2018117794 W CN 2018117794W WO 2020093478 A1 WO2020093478 A1 WO 2020093478A1
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layer
light
gate insulating
shielding
insulating layer
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PCT/CN2018/117794
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English (en)
French (fr)
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周星宇
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020093478A1 publication Critical patent/WO2020093478A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks

Definitions

  • the invention relates to the technical field of semiconductor materials, in particular to a method for preparing a TFT, a TFT, an OLED backplane, and a display device.
  • Organic light-emitting diode (Organic Light-Emitting Diode) has the characteristics of self-luminescence, high brightness, wide viewing angle, high contrast, flexibility, low energy consumption, etc., so it has received extensive attention and has become a new generation of display methods. It began to gradually replace traditional LCD monitors and was widely used in mobile phone screens, computer monitors, and full-color TVs.
  • the flatter surface of the light-emitting area needs to be as flat as possible, so that the OLED layer can have a uniform film thickness, but usually thin-film transistor (TFT) substrates have various traces and vias. Cause ups and downs.
  • TFT thin-film transistor
  • Planarization layer for inkjet printing (InkjetPrinter, IJP), which requires high flatness, PLN needs to be very thick. On the one hand, it is a waste of material, on the other hand, too thick material. Impurity content increases, affecting TFT performance.
  • Embodiments of the present invention provide a method for preparing a TFT, a TFT, an OLED backplane, and a display device, so that the thickness of the planarization layer can be reduced, the accuracy of the exposure process is improved, and the flatness of the OLED light emitting region corresponding to the TFT is increased.
  • the present application provides a method for preparing a TFT according to the present invention.
  • the method includes:
  • the light shielding layer includes a first light shielding area, the width of the second semiconductor layer is smaller than the width of the first light shielding area, the light shielding layer includes a second light shielding area, and the second light shielding area is located Below the pixel opening area of the pixel definition layer;
  • the step of forming the light-shielding layer on the glass substrate using the black photoresist material includes:
  • a layer of black resist material of acrylic or polyimide is coated, and the pattern is defined by yellow light to form a light-shielding layer.
  • the light-shielding layer has a thickness of 0.5-4 ⁇ m.
  • the step of sequentially depositing a buffer layer, a first semiconductor layer, a first gate insulating layer and a gate metal layer on the light-shielding layer includes:
  • step of etching away the first gate insulating layer except the gate metal layer to obtain a second gate insulating layer includes:
  • the pattern of the gate metal layer is etched
  • the gate insulating layer is etched, and the first gate insulating layer outside the gate metal layer is etched away to obtain a second gate insulating layer.
  • the present application provides a method for preparing a TFT according to the present invention.
  • the method includes:
  • the light shielding layer includes a first light shielding area, and the width of the second semiconductor layer is smaller than the width of the first light shielding area.
  • the light-shielding layer further includes a second light-shielding area, and the second light-shielding area is located below the pixel opening area of the pixel definition layer.
  • the step of forming the light-shielding layer on the glass substrate using the black photoresist material includes:
  • a layer of black resist material of acrylic or polyimide is coated, and the pattern is defined by yellow light to form a light-shielding layer.
  • the thickness of the light-shielding layer is 0.5-4 ⁇ m.
  • the step of sequentially depositing a buffer layer, a first semiconductor layer, a first gate insulating layer and a gate metal layer on the light shielding layer includes:
  • the step of etching away the first gate insulating layer outside the gate metal layer to obtain a second gate insulating layer includes:
  • the pattern of the gate metal layer is etched
  • the gate insulating layer is etched, and the first gate insulating layer outside the gate metal layer is etched away to obtain a second gate insulating layer.
  • the plasma processing is performed on the first semiconductor layer, so that the unshielded first semiconductor layer of the second gate insulating layer forms a conductor layer, and the remaining steps of forming the second semiconductor layer include:
  • the N2 plasma treatment process is performed on the first semiconductor layer, so that the first semiconductor layer unshielded by the second gate insulating layer forms an N ion conductor layer, and the remaining forms a second semiconductor layer.
  • the step of sequentially depositing an interlayer insulating layer, a source-drain metal layer, a passivation layer, a planarization layer, a pixel electrode layer, and a pixel definition layer includes:
  • a pixel electrode and a pixel definition layer are formed on the planarization layer.
  • the thickness of the planarization layer is 0.5-2 ⁇ m.
  • the present application provides a TFT, the TFT includes:
  • Shading layer prepared on the surface of the glass substrate, the shading layer is made of black photoresist material, the shading layer includes a first shading area;
  • a buffer layer prepared on the surface of the shading layer
  • a semiconductor layer, prepared on the surface of the buffer layer, the width of the semiconductor layer is smaller than the width of the first light-shielding region
  • An interlayer dielectric layer covering the gate metal layer and the buffer layer, and correspondingly providing two openings above the conductor area;
  • the source-drain metal layer including the source metal region and the drain metal region, are respectively disposed in the two openings between the interlayer dielectric layers;
  • a passivation layer prepared on the surface of the interlayer dielectric layer, covering the source-drain metal layer;
  • a planarization layer prepared on the passivation layer, wherein the passivation layer and the planarization layer above the drain metal region form an opening;
  • the pixel electrode layer is prepared on the planarization layer and in the openings of the passivation layer and the planarization layer;
  • a pixel definition layer is prepared on the pixel electrode layer and fills the opening formed by the passivation layer and the planarization layer.
  • the light-shielding layer further includes a second light-shielding area, and the second light-shielding area is located below the pixel opening area of the pixel definition layer.
  • the thickness of the light-shielding layer is 0.5-4 ⁇ m.
  • the thickness of the planarization layer is 0.5-2 ⁇ m.
  • the semiconductor layer is an N ion conductor layer.
  • the present application provides an OLED backplane, including the TFT according to any one of the third aspect.
  • the present application provides a display device including the OLED backplane as described in the fourth aspect.
  • the method of the embodiment of the present invention uses a black photoresist material to form a light shielding layer on a glass substrate; depositing a buffer layer, a first semiconductor layer, a first gate insulating layer and a gate metal layer in sequence on the light shielding layer; The first gate insulating layer except the lower part is etched away to obtain a second gate insulating layer; the first semiconductor layer is subjected to plasma treatment so that the unshielded first semiconductor layer of the second gate insulating layer forms a conductor layer, and the remaining Forming a second semiconductor layer; sequentially depositing an interlayer insulating layer, a source-drain metal layer, a passivation layer, a planarization layer, a pixel electrode layer, and a pixel definition layer.
  • a black photoresist material is used to prepare the light-shielding layer on the glass substrate.
  • the light-shielding layer is not a metal material, there is no need to connect signals, and no special opening process is required for the buffer layer.
  • the width is smaller than the width of the first light-shielding region in the light-shielding layer, which protects the semiconductor layer of the channel from being irradiated by light, which can reduce the thickness of the planarization layer, improve the accuracy of the exposure process, and increase the flatness of the OLED light-emitting region corresponding to the TFT degree.
  • FIG. 1 is a schematic flowchart of an embodiment of a method for preparing a TFT provided by an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of an embodiment of a TFT provided by an embodiment of the present invention.
  • first and second are used for description purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.
  • features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more, unless otherwise specifically limited.
  • FIG. 1 it is a schematic diagram of an embodiment of a method for preparing a TFT in an embodiment of the present invention.
  • the method includes:
  • the step of forming a light-shielding layer on the glass substrate by using a black photoresist material may further include: coating a layer of black photoresist material of acrylic or polyimide, and defining a pattern using yellow light to form a light-shielding layer.
  • S102 Deposit a buffer layer, a first semiconductor layer, a first gate insulating layer, and a gate metal layer in sequence on the light shielding layer.
  • the step of sequentially depositing a buffer layer, a first semiconductor layer, a first gate insulating layer and a gate metal layer on the light-shielding layer may further include: depositing a layer on the light-shielding layer Multi-layer structure film as a buffer layer; deposit a layer of metal oxide semiconductor material as the first semiconductor layer and etch the pattern; deposit a multi-layer structure film as the first gate insulating layer; deposit a layer of metal as the gate metal Floor.
  • a multilayer structure film is deposited on the light shielding layer as a buffer layer, and the thickness of the buffer layer may be 1000-5000 angstroms.
  • the multilayer structure film corresponding to the buffer layer may be a multilayer structure film of SiOx or SiNx, or a multilayer structure film composed of SiOx and SiNx, which is not limited herein.
  • the metal oxide semiconductor material when depositing a layer of metal oxide semiconductor material as the first semiconductor layer, may be indium gallium zinc oxide (IGZO), indium zinc tin oxide ⁇ (Indium Zinc Tin Oxide, IZTO) or indium gallium zinc tin oxide ((Indium Gallium Zinc Tin Oxide (IGZTO), etc., thickness 100-1000 Angstroms, and etched patterns.
  • IGZO indium gallium zinc oxide
  • IZTO Indium Zinc Tin Oxide
  • IGZTO Indium Gallium Zinc Tin Oxide
  • the first gate insulating layer refers to a GI layer
  • the GI layer is formed by a process in an LTPS called GI Deposition, which is a GI layer deposition.
  • GI is the insulating layer between the gate metal and the semiconductor layer in TFT, usually SiNx / SiOx, called Gate Insulator.
  • the multilayer structure film corresponding to the first gate insulating layer may be a SiOx or SiNx multilayer structure film, and may also be SiOx
  • the multi-layer structure film composed of SiNx has a thickness of 1000-3000 angstroms.
  • the step of etching away the first gate insulating layer outside the gate metal layer to obtain a second gate insulating layer may further include: etching the gate metal layer using a yellow light The pattern of the gate metal layer is self-aligned, the gate insulating layer is etched, and the first gate insulating layer outside the gate metal layer is etched away to obtain a second gate insulating layer .
  • the gate insulating layer exists only under the film layer with the gate metal pattern, and the gate insulating layer is etched away from the rest.
  • Plasma processing is performed on the first semiconductor layer, so that the first semiconductor layer that is not blocked by the second gate insulating layer forms a conductor layer, and the remaining second semiconductor layer is formed.
  • the light-shielding layer includes a first light-shielding region, and the width of the second semiconductor layer is smaller than the width of the first light-shielding region, so that the first light-shielding region can block the second semiconductor layer region and protect the semiconductor layer of the channel from light irradiation .
  • the plasma processing is performed on the first semiconductor layer, so that the unshielded first semiconductor layer of the second gate insulating layer forms a conductor layer
  • the remaining steps of forming the second semiconductor layer may further include : Performing N2 plasma treatment on the first semiconductor layer, so that the first semiconductor layer that is not blocked by the second gate insulating layer forms an N ion conductor layer, and the rest forms the second semiconductor layer.
  • the final result is that for the first semiconductor layer that is not protected by the second gate insulating layer and the gate metal layer above, the resistance is significantly reduced after processing, forming an N + conductor layer, and the second semiconductor layer below the second gate insulating layer does not It is processed to maintain the semiconductor characteristics as a TFT channel.
  • an interlayer insulating layer a source-drain metal layer, a passivation layer, a planarization layer, a pixel electrode layer, and a pixel definition layer are sequentially deposited.
  • the step of sequentially depositing an interlayer insulating layer, a source-drain metal layer, a passivation layer, a planarization layer, a pixel electrode layer, and a pixel definition layer may further include: Perform yellow light and etch the opening; deposit a layer of metal as the source and drain metal layer in the opening of the interlayer insulating layer; deposit a passivation layer on the source and drain metal layer; use the passivation layer to make a planarization Layer, and use yellow light contact holes; pixel electrode and pixel definition layer are formed on the planarization layer.
  • the deposited interlayer insulating layer ILD can be a multi-layer structure film of SiOx or SiNx, and can also be a multi-layer structure film composed of SiOx and SiNx, with a thickness of 2000A-10000A, and then yellow light and Etch.
  • the material of the source and drain metal layers may be metals such as Mo, Al, Cu, Ti, or alloys of at least two such as Mo, Al, Cu, Ti, etc.
  • the thickness of the source and drain metal layers is 2000-8000A.
  • the pattern is defined after the polar metal layer.
  • a planarization layer is formed on the passivation layer, and a yellow light contact hole is used; a pixel electrode and a pixel definition layer are formed on the planarization layer.
  • the passivation layer may be a multi-layer structure film of SiOx or SiNx, and may also be a multi-layer structure film composed of SiOx and SiNx, with a thickness of 1000-5000 angstroms.
  • the thickness of the planarization layer may be 0.5-2 ⁇ m. This is greatly reduced compared to the planarization layer in the prior art, that is, the planarization layer (Planarization) Layer, PLN) does not need to be too thick photoresist material, so that the flatness of the OLED light emitting area is improved, and the degree of unevenness is reduced.
  • the planarization layer (Planarization) Layer, PLN) does not need to be too thick photoresist material, so that the flatness of the OLED light emitting area is improved, and the degree of unevenness is reduced.
  • the method of the embodiment of the present invention uses a black photoresist material to form a light shielding layer on a glass substrate; depositing a buffer layer, a first semiconductor layer, a first gate insulating layer and a gate metal layer in sequence on the light shielding layer; The first gate insulating layer except the lower part is etched away to obtain a second gate insulating layer; the first semiconductor layer is subjected to plasma treatment so that the unshielded first semiconductor layer of the second gate insulating layer forms a conductor layer, and the remaining Forming a second semiconductor layer; sequentially depositing an interlayer insulating layer, a source-drain metal layer, a passivation layer, a planarization layer, a pixel electrode layer, and a pixel definition layer.
  • a black photoresist material is used to prepare the light-shielding layer on the glass substrate.
  • the light-shielding layer is not a metal material, there is no need to connect signals, and no special opening process is required for the buffer layer.
  • the width is smaller than the width of the first light-shielding region in the light-shielding layer, which protects the semiconductor layer of the channel from being irradiated by light, which can reduce the thickness of the planarization layer, improve the accuracy of the exposure process, and increase the flatness of the OLED light-emitting region corresponding to the TFT degree.
  • the light-shielding layer may further include a second light-shielding area, and the second light-shielding area is located below the pixel opening area of the pixel definition layer.
  • the pixel opening area of the pixel definition layer corresponds to the recessed area of the light-emitting area of the OLED backplane.
  • the recessed area of the light-emitting area of the OLED backplane also has a light-shielding layer pattern (second light-shielding area), which further avoids light irradiation and improves the exposure process. Accuracy.
  • the thickness of the shading layer may be set to 0.5-4 ⁇ m.
  • the thickness of the light-shielding layer may be set to 0.8-3 ⁇ m.
  • the first light-shielding area and the second light-shielding area may be unified with the thickness of the light-shielding layer.
  • An embodiment of the present invention also provides a TFT. As shown in FIG. 2, it is a schematic structural diagram of an embodiment of the TFT in the embodiment of the present invention.
  • the TFT includes:
  • a light shielding layer 202 prepared on the surface of the glass substrate 201, the light shielding layer 202 is made of a black photoresist material, and the light shielding layer 202 includes a first light shielding area 2021;
  • the buffer layer 203 is prepared on the surface of the shading layer 202;
  • a semiconductor layer 204 is prepared on the surface of the buffer layer, and the width of the semiconductor layer is smaller than the width of the first light-shielding region;
  • Conductor regions 205 are prepared on both sides of the semiconductor layer 204;
  • the gate insulating layer 206 is prepared on the semiconductor layer 204;
  • the gate metal layer 207 is prepared on the gate insulating layer 206;
  • An interlayer dielectric layer 208 covers the gate metal layer 207 and the buffer layer 203, and two openings are correspondingly provided above the conductor region 205;
  • the source-drain metal layer 209 including the source metal region and the drain metal region 2091, are respectively disposed in the two openings between the interlayer dielectric layers 208;
  • the passivation layer 210 is prepared on the surface of the interlayer dielectric layer 208 and covers the source-drain metal layer 209;
  • a planarization layer 211 is prepared on the passivation layer 210, wherein the passivation layer 210 and the planarization layer 211 above the drain metal region 2091 form an opening;
  • the pixel electrode layer 212 is prepared on the planarization layer and in the openings of the passivation layer 210 and the planarization layer 211;
  • a pixel definition layer 213 is prepared on the pixel electrode layer 212 and fills the opening formed by the passivation layer 210 and the planarization layer 211.
  • a black photoresist material is used to prepare the light-shielding layer 202 on the glass substrate.
  • the light-shielding layer 202 is not a metal material, there is no need to connect signals, and no special opening process is required for the buffer layer 203.
  • the width of 204 is smaller than the width of the first light-shielding region 2021 in the light-shielding layer 202, which protects the semiconductor layer 204 of the channel from light irradiation, so that the thickness of the planarization layer 211 can be reduced, the accuracy of the exposure process is improved, and the TFT correspondence The flatness of the OLED light-emitting area.
  • the light-shielding layer 202 further includes a second light-shielding region 2022, and the second light-shielding region 2022 is located under the pixel opening area of the pixel definition layer 213.
  • the pixel opening area of the pixel definition layer 213 corresponds to where the light-emitting area of the OLED backplane is recessed, and the light-emitting area of the OLED backplane also has a light-shielding layer pattern (second light-shielding area 2022), which further avoids light irradiation and improves exposure The accuracy of the process.
  • the thickness of the light shielding layer 202 is 0.5-4 ⁇ m.
  • the thickness of the light-shielding layer may be set to 0.8-3 ⁇ m.
  • the first light-shielding area and the second light-shielding area may be unified with the thickness of the light-shielding layer.
  • the thickness of the planarization layer 211 is 0.5-2 ⁇ m. This is greatly reduced compared to the planarization layer in the prior art, that is, the planarization layer (Planarization) Layer, PLN) does not need to be too thick photoresist material, so that the flatness of the OLED light emitting area is improved, and the degree of unevenness is reduced.
  • the planarization layer (Planarization) Layer, PLN) does not need to be too thick photoresist material, so that the flatness of the OLED light emitting area is improved, and the degree of unevenness is reduced.
  • the semiconductor layer 204 is an N ion conductor layer.
  • An embodiment of the present invention also provides an OLED backplane, including the TFT described in any of the embodiments described in the embodiments of the present invention.
  • An embodiment of the present invention also provides a display device, including the OLED backplane as described in any of the embodiments of the present invention.
  • the above units or modules can be implemented as independent entities, or they can be combined in any combination and implemented as the same or several entities.
  • the above units or modules please refer to the previous method embodiments, for example The thickness of each layer and the selection of materials for each layer are not repeated here.

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Abstract

一种TFT的制备方法、TFT、OLED背板和显示装置，在玻璃基板（201）上采用黑色光阻材料制备遮光层（202），不需要对缓冲层（203）进行专门的开洞工艺，同时由于第二半导体层（204）的宽度小于第一遮光区（2021）的宽度，保护了半导体层（204）不被光照射，使得可以降低平坦化层（211）的厚度，提升了曝光工艺的准确度，增加TFT对应的OLED发光区的平坦度。

Description

一种TFT的制备方法、TFT、OLED背板和显示装置 技术领域
本发明涉及半导体材料技术领域，具体涉及一种TFT的制备方法、TFT、OLED背板和显示装置。
 背景技术
OLED即有机发光二极管(Organic Light-Emitting Diode)，具备自发光、高亮度、宽视角、高对比度、可挠曲、低能耗等特性，因此受到广泛的关注，并作为新一代的显示方式，已开始逐渐取代传统液晶显示器，被广泛应用在手机屏幕、电脑显示器、全彩电视等。
喷墨打印工艺的OLED器件，需要发光区的表面越平坦越好，这样OLED层就可以膜厚均一，但是通常薄膜晶体管（Thin-film transistor，TFT）基板会有各种走线和过孔，造成起伏。
 技术问题
通常的TFT基板都会制作平坦化层（Planarization layer，PLN），对于平整度要求较高的喷墨打印（InkjetPrinter，IJP）来讲，PLN需要做的很厚，一方面浪费材料，另一方面材料太厚曝光工艺也比较难控制，材料的杂质含量增加，影响TFT性能。
 技术解决方案
本发明实施例提供一种TFT的制备方法、TFT、OLED背板和显示装置，使得可以降低平坦化层的厚度，提升了曝光工艺的准确度，增加TFT对应的OLED发光区的平坦度。
为解决上述问题，第一方面，本申请本发明一种TFT的制备方法，所述方法包括：
利用黑色光阻材料在玻璃基板上形成遮光层；
在所述遮光层之上依次沉积缓冲层、第一半导体层、第一栅极绝缘层和栅极金属层；
将所述栅极金属层下方之外的第一栅极绝缘层蚀刻掉，得到第二栅极绝缘层；
对所述第一半导体层进行等离子处理处理，使得所述第二栅极绝缘层未遮挡的第一半导体层形成导体层，剩余的形成第二半导体层；
依次沉积层间绝缘层、源漏极金属层、钝化层、平坦化层、像素电极层以及像素定义层；
其中，所述遮光层包括第一遮光区，所述第二半导体层的宽度小于所述第一遮光区的宽度，所述遮光层包括还包括第二遮光区，所述第二遮光区位于所述像素定义层的像素开口区域下方；
所述利用黑色光阻材料在玻璃基板上形成遮光层的步骤包括：
涂覆一层亚克力类或者聚酰亚胺的黑色光阻材料，并利用黄光定义图形，形成遮光层。
进一步的，其中，所述遮光层厚度为0.5~4μm。
进一步的，其中，所述在所述遮光层之上依次沉积缓冲层、第一半导体层、第一栅极绝缘层和栅极金属层的步骤，包括：
在所述遮光层之上沉积一层多层结构薄膜，作为缓冲层；
沉积一层金属氧化物半导体材料作为第一半导体层，并蚀刻图形；
沉积一多层结构薄膜，作为第一栅极绝缘层；
沉积一层金属作为栅极金属层。
进一步的，其中，所述将所述栅极金属层下方之外的第一栅极绝缘层蚀刻掉，得到第二栅极绝缘层的步骤，包括：
利用一道黄光，蚀刻出栅极金属层的图形；
利用栅极金属层的图形为自对准，蚀刻所述栅极绝缘层，将所述栅极金属层下方之外的第一栅极绝缘层蚀刻掉，得到第二栅极绝缘层。
第二方面，本申请本发明一种TFT的制备方法，所述方法包括：
利用黑色光阻材料在玻璃基板上形成遮光层；
在所述遮光层之上依次沉积缓冲层、第一半导体层、第一栅极绝缘层和栅极金属层；
将所述栅极金属层下方之外的第一栅极绝缘层蚀刻掉，得到第二栅极绝缘层；
对所述第一半导体层进行等离子处理处理，使得所述第二栅极绝缘层未遮挡的第一半导体层形成导体层，剩余的形成第二半导体层；
依次沉积层间绝缘层、源漏极金属层、钝化层、平坦化层、像素电极层以及像素定义层；
其中，所述遮光层包括第一遮光区，所述第二半导体层的宽度小于所述第一遮光区的宽度。
进一步的，所述遮光层包括还包括第二遮光区，所述第二遮光区位于所述像素定义层的像素开口区域下方。
进一步的，所述利用黑色光阻材料在玻璃基板上形成遮光层的步骤包括：
涂覆一层亚克力类或者聚酰亚胺的黑色光阻材料，并利用黄光定义图形，形成遮光层。
进一步的，所述遮光层厚度为0.5~4μm。
进一步的，所述在所述遮光层之上依次沉积缓冲层、第一半导体层、第一栅极绝缘层和栅极金属层的步骤，包括：
在所述遮光层之上沉积一层多层结构薄膜，作为缓冲层；
沉积一层金属氧化物半导体材料作为第一半导体层，并蚀刻图形；
沉积一多层结构薄膜，作为第一栅极绝缘层；
沉积一层金属作为栅极金属层。
进一步的，所述将所述栅极金属层下方之外的第一栅极绝缘层蚀刻掉，得到第二栅极绝缘层的步骤，包括：
利用一道黄光，蚀刻出栅极金属层的图形；
利用栅极金属层的图形为自对准，蚀刻所述栅极绝缘层，将所述栅极金属层下方之外的第一栅极绝缘层蚀刻掉，得到第二栅极绝缘层。
进一步的，所述对所述第一半导体层进行等离子处理处理，使得所述第二栅极绝缘层未遮挡的第一半导体层形成导体层，剩余的形成第二半导体层的步骤，包括：
对所述第一半导体层进行N2等离子处理处理，使得所述第二栅极绝缘层未遮挡的第一半导体层形成N离子导体层，剩余的形成第二半导体层。
进一步的，所述依次沉积层间绝缘层、源漏极金属层、钝化层、平坦化层、像素电极层以及像素定义层的步骤，包括：
沉积层间绝缘层，并进行黄光和蚀刻出开口；
在所述层间绝缘层的开口内沉积一层金属作为源漏极金属层；
在所述源漏极金属层之上沉积钝化层；
利用在所述钝化层之上制作平坦化层，并利用黄光接触孔；
在所述平坦化层之上制作像素电极以及像素定义层。
进一步的，所述平坦化层的厚度为0.5~2μm。
第三方面，本申请提供一种TFT，所述TFT包括：
玻璃基板；
遮光层；制备于所述玻璃基板表面，所述遮光层为黑色光阻材料制备，所述遮光层包括第一遮光区；
缓冲层，制备于所述遮光层表面；
半导体层，制备于所述缓冲层表面，所述半导体层的宽度小于所述第一遮光区的宽度；
导体区，制备于所述半导体层两侧；
栅极绝缘层，制备于所述半导体层之上；
栅极金属层，制备于所述栅极绝缘层之上；
层间介质层，覆盖所述栅极金属层和所述缓冲层，并在所述导体区上方对应设置两个开口；
源漏金属层，包括源极金属区和漏极金属区，分别设置于所述层间介质层之间的两个开口内；
钝化层，制备于层间介质层表面，覆盖所述源漏金属层；
平坦化层，制备于所述钝化层之上，其中，所述漏极金属区之上的所述钝化层和所述平坦化层除形成开口；
像素电极层，制备于所述平坦化层之上，以及所述钝化层和所述平坦化层的开口内；
像素定义层，制备于所述像素电极层之上，并填充满所述钝化层和所述平坦化层除形成的开口。
进一步的，所述遮光层包括还包括第二遮光区，所述第二遮光区位于所述像素定义层的像素开口区域下方。
进一步的，所述遮光层厚度为0.5~4μm。
进一步的，所述平坦化层的厚度为0.5~2μm。
进一步的，所述半导体层为N离子导体层。
第四方面，本申请提供一种OLED背板，包括如第三方面中任一项所述的TFT。
第五方面，本申请提供一种显示装置包括如第四方面中所述的OLED背板。
 有益效果
本发明实施例方法利用黑色光阻材料在玻璃基板上形成遮光层；在遮光层之上依次沉积缓冲层、第一半导体层、第一栅极绝缘层和栅极金属层；将栅极金属层下方之外的第一栅极绝缘层蚀刻掉，得到第二栅极绝缘层；对第一半导体层进行等离子处理处理，使得第二栅极绝缘层未遮挡的第一半导体层形成导体层，剩余的形成第二半导体层；依次沉积层间绝缘层、源漏极金属层、钝化层、平坦化层、像素电极层以及像素定义层。本发明实施例中在玻璃基板上采用黑色光阻材料制备遮光层，一方面由于遮光层不是金属材料，不用连接讯号，不需要对缓冲层进行专门的开洞工艺，同时由于第二半导体层的宽度小于遮光层中第一遮光区的宽度，保护了沟道的半导体层不被光照射，使得可以降低平坦化层的厚度，提升了曝光工艺的准确度，增加TFT对应的OLED发光区的平坦度。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种TFT的制备方法的一个实施例流程示意图；
图2是本发明实施例提供的一种TFT的一个实施例结构示意图。
 本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
如图1所示，为本发明实施例中TFT的制备方法的一个实施例示意图，该方法包括：
S101、利用黑色光阻材料在玻璃基板上形成遮光层。
其中，所述利用黑色光阻材料在玻璃基板上形成遮光层的步骤可以进一步包括：涂覆一层亚克力类或者聚酰亚胺的黑色光阻材料，并利用黄光定义图形，形成遮光层。
S102、在遮光层之上依次沉积缓冲层、第一半导体层、第一栅极绝缘层和栅极金属层。
本实施例中，在所述遮光层之上依次沉积缓冲层、第一半导体层、第一栅极绝缘层和栅极金属层的步骤，可以进一步包括：在所述遮光层之上沉积一层多层结构薄膜，作为缓冲层；沉积一层金属氧化物半导体材料作为第一半导体层，并蚀刻图形；沉积一多层结构薄膜，作为第一栅极绝缘层；沉积一层金属作为栅极金属层。
其中，在遮光层之上沉积一层多层结构薄膜，作为缓冲层，缓冲层的厚度可以为厚度1000-5000埃。该缓冲层对应的多层结构薄膜可以是SiOx或SiNx的多层结构薄膜，也可以是SiOx和SiNx组成的多层结构薄膜，此处不作限定。
本发明实施例中，沉积一层金属氧化物半导体材料作为第一半导体层时，该金属氧化物半导体材料（Oxide）可以是铟镓锌氧化物(Indium Gallium Zinc Oxide， IGZO)、铟锌锡氧化物（Indium Zinc Tin Oxide，IZTO）或铟镓锌锡氧化物（(Indium Gallium Zinc Tin Oxide，IGZTO）等等，厚度100-1000埃，并蚀刻出图形。
另外，该第一栅极绝缘层指的是GI层，GI层通过一个LTPS中的工艺，叫GI Deposition也就是GI层沉积形成。GI是TFT中，栅极金属和半导体层之间的绝缘层，通常为SiNx/SiOx，称之为Gate Insulator。具体的，沉积一多层结构薄膜，作为第一栅极绝缘层的步骤中，该第一栅极绝缘层对应的多层结构薄膜可以是SiOx或SiNx的多层结构薄膜，同样也可以是SiOx和SiNx组成的多层结构薄膜，厚度为1000-3000埃。
S103、将栅极金属层下方之外的第一栅极绝缘层蚀刻掉，得到第二栅极绝缘层。
具体的，所述将所述栅极金属层下方之外的第一栅极绝缘层蚀刻掉，得到第二栅极绝缘层的步骤，可以进一步包括：利用一道黄光，蚀刻出栅极金属层的图形；利用栅极金属层的图形为自对准，蚀刻所述栅极绝缘层，将所述栅极金属层下方之外的第一栅极绝缘层蚀刻掉，得到第二栅极绝缘层。此过程中，使得只在有栅极金属图形的膜层下方，才有栅极绝缘层存在，其余地方栅极绝缘层均被蚀刻掉。
S104、对第一半导体层进行等离子处理处理，使得第二栅极绝缘层未遮挡的第一半导体层形成导体层，剩余的形成第二半导体层。
其中，所述遮光层包括第一遮光区，第二半导体层的宽度小于第一遮光区的宽度，这样第一遮光区即可遮挡第二半导体层区域，保护沟道的半导体层不被光照射。
具体的，所述对所述第一半导体层进行等离子处理处理，使得所述第二栅极绝缘层未遮挡的第一半导体层形成导体层，剩余的形成第二半导体层的步骤，可以进一步包括：对第一半导体层进行N2等离子处理处理，使得第二栅极绝缘层未遮挡的第一半导体层形成N离子导体层，剩余的形成第二半导体层。最后的结果，对于上方没有第二栅极绝缘层和栅极金属层保护的第一半导体层，其处理以后电阻明显降低，形成N+导体层，第二栅极绝缘层下方的第二半导体层没有被处理到，保持半导体特性，作为TFT沟道。
S105、依次沉积层间绝缘层、源漏极金属层、钝化层、平坦化层、像素电极层以及像素定义层。
本发明实施例中，所述依次沉积层间绝缘层、源漏极金属层、钝化层、平坦化层、像素电极层以及像素定义层的步骤，可以进一步包括：沉积层间绝缘层，并进行黄光和蚀刻出开口；在层间绝缘层的开口内沉积一层金属作为源漏极金属层；在源漏极金属层之上沉积钝化层；利用在钝化层之上制作平坦化层，并利用黄光接触孔；在平坦化层之上制作像素电极以及像素定义层。
其中，沉积层间绝缘层ILD可以是SiOx或SiNx的多层结构薄膜，同样也可以是SiOx和SiNx组成的多层结构薄膜，厚度2000A-10000A，在沉积层间绝缘层ILD再进行黄光和蚀刻。
另外，源漏极金属层的材料可以是Mo，Al，Cu，Ti等金属，或者Mo，Al，Cu，Ti等至少两种的合金，源漏极金属层厚度为2000-8000A，在源漏极金属层之后定义出图形。然后，在钝化层之上制作平坦化层，并利用黄光接触孔；在平坦化层之上制作像素电极以及像素定义层。钝化层可以是SiOx或SiNx的多层结构薄膜，同样也可以是SiOx和SiNx组成的多层结构薄膜，厚度为1000-5000埃。
而本发明实施例中平坦化层的厚度可以为0.5~2μm。这相对于现有技术中平坦化层大大降低，即本发明中由于遮光层的设置使得平坦化层（Planarization layer，PLN）不用太厚的光阻材料即可，从而使得OLED发光区的平坦度提高，凹凸程度减轻。
本发明实施例方法利用黑色光阻材料在玻璃基板上形成遮光层；在遮光层之上依次沉积缓冲层、第一半导体层、第一栅极绝缘层和栅极金属层；将栅极金属层下方之外的第一栅极绝缘层蚀刻掉，得到第二栅极绝缘层；对第一半导体层进行等离子处理处理，使得第二栅极绝缘层未遮挡的第一半导体层形成导体层，剩余的形成第二半导体层；依次沉积层间绝缘层、源漏极金属层、钝化层、平坦化层、像素电极层以及像素定义层。本发明实施例中在玻璃基板上采用黑色光阻材料制备遮光层，一方面由于遮光层不是金属材料，不用连接讯号，不需要对缓冲层进行专门的开洞工艺，同时由于第二半导体层的宽度小于遮光层中第一遮光区的宽度，保护了沟道的半导体层不被光照射，使得可以降低平坦化层的厚度，提升了曝光工艺的准确度，增加TFT对应的OLED发光区的平坦度。
进一步的，在本发明一些实施例中，所述遮光层包括还可以包括第二遮光区，该第二遮光区位于所述像素定义层的像素开口区域下方。像素定义层的像素开口区域对应OLED背板的发光区凹下的地方，OLED背板的发光区凹下的地方也有遮光层图形（第二遮光区），进一步避免光照射，提升了曝光工艺的准确度。
为了达到良好的遮光效果，本发实施例中，所述遮光层厚度可以设置为0.5~4μm。优选的，所述遮光层厚度可以设置0.8~3μm。对应的，第一遮光区和第二遮光区可以与遮光层厚度统一。
本发明实施例中还提供一种TFT，如图2所示，为本发明实施例中TFT的一个实施例结构示意图，所述TFT包括：
玻璃基板201；
遮光层202；制备于所述玻璃基板201表面，所述遮光层202为黑色光阻材料制备，所述遮光层202包括第一遮光区2021；
缓冲层203，制备于所述遮光层202表面；
半导体层204，制备于所述缓冲层表面，所述半导体层的宽度小于所述第一遮光区的宽度；
导体区205，制备于所述半导体层204两侧；
栅极绝缘层206，制备于所述半导体层204之上；
栅极金属层207，制备于所述栅极绝缘层206之上；
层间介质层208，覆盖所述栅极金属层207和所述缓冲层203，并在所述导体区205上方对应设置两个开口；
源漏金属层209，包括源极金属区和漏极金属区2091，分别设置于所述层间介质层208之间的两个开口内；
钝化层210，制备于层间介质层208表面，覆盖所述源漏金属层209；
平坦化层211，制备于所述钝化层210之上，其中，所述漏极金属区2091之上的所述钝化层210和所述平坦化层211除形成开口；
像素电极层212，制备于所述平坦化层之上，以及所述钝化层210和所述平坦化层211的开口内；
像素定义层213，制备于所述像素电极层212之上，并填充满所述钝化层210和所述平坦化层211除形成的开口。
本发明实施例中在玻璃基板上采用黑色光阻材料制备遮光层202，一方面由于遮光层202不是金属材料，不用连接讯号，不需要对缓冲层203进行专门的开洞工艺，同时由于半导体层204的宽度小于遮光层202中第一遮光区2021的宽度，保护了沟道的半导体层204不被光照射，使得可以降低平坦化层211的厚度，提升了曝光工艺的准确度，增加TFT对应的OLED发光区的平坦度。
进一步的，所述遮光层202包括还包括第二遮光区2022，所述第二遮光区2022位于所述像素定义层213的像素开口区域下方。像素定义层213的像素开口区域对应OLED背板的发光区凹下的地方，OLED背板的发光区凹下的地方也有遮光层图形（第二遮光区2022），进一步避免光照射，提升了曝光工艺的准确度。
进一步的，所述遮光层202厚度为0.5~4μm。优选的，所述遮光层厚度可以设置0.8~3μm。对应的，第一遮光区和第二遮光区可以与遮光层厚度统一。
进一步的，所述平坦化层211的厚度为0.5~2μm。这相对于现有技术中平坦化层大大降低，即本发明中由于遮光层的设置使得平坦化层（Planarization layer，PLN）不用太厚的光阻材料即可，从而使得OLED发光区的平坦度提高，凹凸程度减轻。
进一步的，所述半导体层204为N离子导体层。
本发明实施例中还提供一种OLED背板，包括如本发明实施例中描述的任一实施例中所述的TFT。
本发明实施例中还提供一种显示装置，包括如本发明实施例中描述的任一实施例中所述的OLED背板。
具体实施时，以上各个单元或模块可以作为独立的实体来实现，也可以进行任意组合，作为同一或若干个实体来实现，以上各个单元或模块的具体实施方式可参见前面的方法实施例，例如各层的厚度和各层材料的选择等，在此不再赘述。
以上对本发明实施例所提供的一种TFT的制备方法、TFT、OLED背板和显示装置进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (20)

  1. 一种TFT的制备方法，其中，所述方法包括：
    利用黑色光阻材料在玻璃基板上形成遮光层；
    在所述遮光层之上依次沉积缓冲层、第一半导体层、第一栅极绝缘层和栅极金属层；
    将所述栅极金属层下方之外的第一栅极绝缘层蚀刻掉，得到第二栅极绝缘层；
    对所述第一半导体层进行等离子处理处理，使得所述第二栅极绝缘层未遮挡的第一半导体层形成导体层，剩余的形成第二半导体层；
    依次沉积层间绝缘层、源漏极金属层、钝化层、平坦化层、像素电极层以及像素定义层；
    其中，所述遮光层包括第一遮光区，所述第二半导体层的宽度小于所述第一遮光区的宽度，所述遮光层包括还包括第二遮光区，所述第二遮光区位于所述像素定义层的像素开口区域下方；
    所述利用黑色光阻材料在玻璃基板上形成遮光层的步骤包括：
    涂覆一层亚克力类或者聚酰亚胺的黑色光阻材料，并利用黄光定义图形，形成遮光层。
  2. 根据权利要求1所述的TFT的制备方法，其中，所述遮光层厚度为0.5~4μm。
  3. 根据权利要求1所述的TFT的制备方法，其中，所述在所述遮光层之上依次沉积缓冲层、第一半导体层、第一栅极绝缘层和栅极金属层的步骤，包括：
    在所述遮光层之上沉积一层多层结构薄膜，作为缓冲层；
    沉积一层金属氧化物半导体材料作为第一半导体层，并蚀刻图形；
    沉积一多层结构薄膜，作为第一栅极绝缘层；
    沉积一层金属作为栅极金属层。
  4. 根据权利要求1所述的TFT的制备方法，其中，所述将所述栅极金属层下方之外的第一栅极绝缘层蚀刻掉，得到第二栅极绝缘层的步骤，包括：
    利用一道黄光，蚀刻出栅极金属层的图形；
    利用栅极金属层的图形为自对准，蚀刻所述栅极绝缘层，将所述栅极金属层下方之外的第一栅极绝缘层蚀刻掉，得到第二栅极绝缘层。
  5. 一种TFT的制备方法，其中，所述方法包括：
    利用黑色光阻材料在玻璃基板上形成遮光层；
    在所述遮光层之上依次沉积缓冲层、第一半导体层、第一栅极绝缘层和栅极金属层；
    将所述栅极金属层下方之外的第一栅极绝缘层蚀刻掉，得到第二栅极绝缘层；
    对所述第一半导体层进行等离子处理处理，使得所述第二栅极绝缘层未遮挡的第一半导体层形成导体层，剩余的形成第二半导体层；
    依次沉积层间绝缘层、源漏极金属层、钝化层、平坦化层、像素电极层以及像素定义层；
    其中，所述遮光层包括第一遮光区，所述第二半导体层的宽度小于所述第一遮光区的宽度。
  6. 根据权利要求5所述的TFT的制备方法，其中，所述遮光层包括还包括第二遮光区，所述第二遮光区位于所述像素定义层的像素开口区域下方。
  7. 根据权利要求5所述的TFT的制备方法，其中，所述利用黑色光阻材料在玻璃基板上形成遮光层的步骤包括：
    涂覆一层亚克力类或者聚酰亚胺的黑色光阻材料，并利用黄光定义图形，形成遮光层。
  8. 根据权利要求7所述的TFT的制备方法，其中，所述遮光层厚度为0.5~4μm。
  9. 根据权利要求5所述的TFT的制备方法，其中，所述在所述遮光层之上依次沉积缓冲层、第一半导体层、第一栅极绝缘层和栅极金属层的步骤，包括：
    在所述遮光层之上沉积一层多层结构薄膜，作为缓冲层；
    沉积一层金属氧化物半导体材料作为第一半导体层，并蚀刻图形；
    沉积一多层结构薄膜，作为第一栅极绝缘层；
    沉积一层金属作为栅极金属层。
  10. 根据权利要求5所述的TFT的制备方法，其中，所述将所述栅极金属层下方之外的第一栅极绝缘层蚀刻掉，得到第二栅极绝缘层的步骤，包括：
    利用一道黄光，蚀刻出栅极金属层的图形；
    利用栅极金属层的图形为自对准，蚀刻所述栅极绝缘层，将所述栅极金属层下方之外的第一栅极绝缘层蚀刻掉，得到第二栅极绝缘层。
  11. 根据权利要求5所述的TFT的制备方法，其中，所述对所述第一半导体层进行等离子处理处理，使得所述第二栅极绝缘层未遮挡的第一半导体层形成导体层，剩余的形成第二半导体层的步骤，包括：
    对所述第一半导体层进行N2等离子处理处理，使得所述第二栅极绝缘层未遮挡的第一半导体层形成N离子导体层，剩余的形成第二半导体层。
  12. 根据权利要求5所述的TFT的制备方法，其中，所述依次沉积层间绝缘层、源漏极金属层、钝化层、平坦化层、像素电极层以及像素定义层的步骤，包括：
    沉积层间绝缘层，并进行黄光和蚀刻出开口；
    在所述层间绝缘层的开口内沉积一层金属作为源漏极金属层；
    在所述源漏极金属层之上沉积钝化层；
    在所述钝化层之上制作平坦化层，并利用黄光接触孔；
    在所述平坦化层之上制作像素电极以及像素定义层。
  13. 根据权利要求12所述的TFT的制备方法，其中，所述平坦化层的厚度为0.5~2μm。
  14. 一种TFT，其中，所述TFT包括：
    玻璃基板；
    遮光层；制备于所述玻璃基板表面，所述遮光层为黑色光阻材料制备，所述遮光层包括第一遮光区；
    缓冲层，制备于所述遮光层表面；
    半导体层，制备于所述缓冲层表面，所述半导体层的宽度小于所述第一遮光区的宽度；
    导体区，制备于所述半导体层两侧；
    栅极绝缘层，制备于所述半导体层之上；
    栅极金属层，制备于所述栅极绝缘层之上；
    层间介质层，覆盖所述栅极金属层和所述缓冲层，并在所述导体区上方对应设置两个开口；
    源漏金属层，包括源极金属区和漏极金属区，分别设置于所述层间介质层之间的两个开口内；
    钝化层，制备于层间介质层表面，覆盖所述源漏金属层；
    平坦化层，制备于所述钝化层之上，其中，所述漏极金属区之上的所述钝化层和所述平坦化层除形成开口；
    像素电极层，制备于所述平坦化层之上，以及所述钝化层和所述平坦化层的开口内；
    像素定义层，制备于所述像素电极层之上，并填充满所述钝化层和所述平坦化层除形成的开口。
  15. 根据权利要求14所述的TFT，其中，所述遮光层包括还包括第二遮光区，所述第二遮光区位于所述像素定义层的像素开口区域下方。
  16. 根据权利要求14所述的TFT，其中，所述遮光层厚度为0.5~4μm。
  17. 根据权利要求14所述的TFT，其中，所述平坦化层的厚度为0.5~2μm。
  18. 根据权利要求14所述的TFT，其中，所述半导体层为N离子导体层。
  19. 一种OLED背板，其中，包括如权利要求14所述的TFT。
  20. 一种显示装置，其中，包括如权利要求19中所述的OLED背板。
PCT/CN2018/117794 2018-11-09 2018-11-28 一种tft的制备方法、tft、oled背板和显示装置 WO2020093478A1 (zh)

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