WO2022227154A1 - 显示面板及其制备方法、显示装置 - Google Patents

显示面板及其制备方法、显示装置 Download PDF

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Publication number
WO2022227154A1
WO2022227154A1 PCT/CN2021/095641 CN2021095641W WO2022227154A1 WO 2022227154 A1 WO2022227154 A1 WO 2022227154A1 CN 2021095641 W CN2021095641 W CN 2021095641W WO 2022227154 A1 WO2022227154 A1 WO 2022227154A1
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WIPO (PCT)
Prior art keywords
layer
light
metal layer
transparent conductive
electrode
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Application number
PCT/CN2021/095641
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English (en)
French (fr)
Inventor
张乐陶
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US17/593,119 priority Critical patent/US20230189564A1/en
Publication of WO2022227154A1 publication Critical patent/WO2022227154A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel, a method for manufacturing the same, and a display device.
  • AMOLED Active Matrix Organic Light Emitting Display
  • LCD Liquid Crystal Display
  • AMOLED devices can be divided into top-emitting and bottom-emitting according to different light-emitting directions, while bottom-emitting AMOLED devices are limited by the opacity of the storage capacitor, resulting in a low aperture ratio.
  • the present application provides a display panel, a preparation method thereof, and a display device to alleviate the technical problem of the low aperture ratio of the existing bottom-emitting AMOLED devices.
  • An embodiment of the present application provides a display panel, which includes a plurality of sub-pixels, each of the sub-pixels includes a transistor region and a light-emitting region, the transistor region is provided with a thin film transistor, and the light-emitting region is provided with a storage capacitor and a light-emitting unit, The light-emitting unit is located above the storage capacitor, and the light-emitting surface of the light-emitting unit faces the storage capacitor;
  • the display panel includes a substrate, a first metal layer, an oxide semiconductor layer, a second metal layer, and a third a metal layer;
  • the first metal layer is disposed on the substrate, and includes a light-shielding layer with a two-layer structure formed in the transistor region, and a first transparent conductive electrode with a single-layer structure formed in the light-emitting region;
  • the The oxide semiconductor layer is disposed on the first metal layer, including the active region of the thin film transistor formed in the transistor region, and the second transparent conductive electrode
  • the source electrode, the drain electrode and the light shielding layer all include a stacked transparent conductive film and a first metal film, and the first metal film is located on the transparent conductive film. on the conductive film.
  • both the first transparent conductive electrode and the second transparent electrode include the transparent conductive film.
  • At least one of the first metal layer, the oxide semiconductor layer, and the third metal layer further includes a single-layer structure of transparent wires , the transparent wires are arranged corresponding to the light-emitting units.
  • the display panel provided in the embodiment of the present application further includes an external wiring area, the light emitting area is located between the transistor area and the external wiring area, the first metal layer and the third metal layer At least one of the layers further includes an external wiring of a two-layer structure formed in the external wiring area.
  • the transparent conductive film includes a film formed of an indium-based, zinc-based or titanium-based doped transparent oxide material.
  • the material of the first metal thin film includes one or a combination of several of Mo, Al, Ti, and Cu.
  • the display panel further includes a passivation layer, a planarization layer, a pixel electrode and a pixel definition layer stacked on the third metal layer, wherein the pixel definition layer is formed There is a first via hole, the pixel electrode is exposed by the first via hole, and the light emitting unit is arranged in the first via hole.
  • the display panel is further provided with a color filter layer between the passivation layer and the planarization layer, and the color filter layer is provided corresponding to the first via hole.
  • the orthographic projection of the color filter layer on the substrate covers the orthographic projection of the light-emitting unit on the substrate.
  • An embodiment of the present application further provides a method for fabricating a display panel, the display panel includes a plurality of sub-pixels, each of the sub-pixels includes a transistor region and a light-emitting region, the transistor region is provided with a thin film transistor, and the light-emitting region is provided with a storage capacitor and a light-emitting unit, wherein the light-emitting unit is located above the storage capacitor, and the light-emitting surface of the light-emitting unit faces the storage capacitor; the display panel manufacturing method includes:
  • a first composite metal layer is prepared on the substrate, and a first halftone mask is used to perform a yellow light process on the first composite metal layer to form a first metal layer, and the first metal layer is included in the transistor A light-shielding layer with a two-layer structure formed in the light-emitting region, and a first transparent conductive electrode with a single-layer structure formed in the light-emitting region;
  • a buffer layer is prepared on the first metal layer, and an oxide semiconductor thin film is prepared on the buffer layer, and a yellow light process is performed on the oxide semiconductor thin film to form an oxide semiconductor layer, and the oxide semiconductor layer is included in the an active region of the thin film transistor formed in the transistor region, an oxide semiconductor pattern formed in the light emitting region;
  • a gate insulating layer is prepared on the oxide semiconductor layer, and a second metal thin film is prepared on the gate insulating layer, and a yellow light process is performed on the second metal thin film to form a second metal layer.
  • a second metal thin film is prepared on the gate insulating layer, and a yellow light process is performed on the second metal thin film to form a second metal layer. including the gate electrode of the thin film transistor formed in the transistor region, and conducting the oxide semiconductor layer, so that the oxide semiconductor pattern forms a second transparent conductive electrode;
  • An interlayer insulating layer is prepared on the second metal layer, a second composite metal layer is prepared on the interlayer insulating layer, and a second halftone mask is used to perform a yellow light process on the second composite metal layer
  • a third metal layer is formed, the third metal layer includes a source electrode and a drain electrode of a two-layer structure formed in the transistor region, and a third transparent conductive electrode of a single-layer structure formed in the light-emitting region, wherein the The third transparent conductive electrode is electrically connected to the first transparent conductive electrode to form a first electrode plate of the storage capacitor, and the second transparent conductive electrode forms a second electrode plate of the storage capacitor.
  • the display panel manufacturing method further includes:
  • a passivation layer is prepared on the third metal layer, and a color filter layer is prepared on the passivation layer, and the color filter layer is disposed corresponding to the light-emitting region;
  • a planarization layer is prepared on the color filter layer and the passivation layer, and a pixel electrode is prepared on the planarization layer, and the pixel electrode is connected to the source electrode or the drain electrode;
  • a pixel definition layer is prepared on the pixel electrode and the planarization layer, the pixel definition layer is formed with a first via hole, the pixel electrode is exposed by the first via hole, and the light emitting unit is disposed on the in the first via hole, and the light emitting unit is arranged corresponding to the color filter layer;
  • a cathode is prepared on the light emitting unit and the pixel definition layer.
  • the first composite metal layer and the second composite metal layer both include a stacked transparent conductive film and a first metal film, and the first metal film is located in on the transparent conductive film.
  • An embodiment of the present application further provides a display device, which includes a display panel, a circuit board bound to the display panel, and a cover plate covering the display panel, wherein the display panel includes a plurality of sub-pixels, each The sub-pixel includes a transistor area and a light-emitting area, the transistor area is provided with a thin film transistor, the light-emitting area is provided with a storage capacitor and a light-emitting unit, the light-emitting unit is located above the storage capacitor, and the light-emitting unit emits light facing the storage capacitor; the display panel includes:
  • a first metal layer disposed on the substrate, comprising a light-shielding layer with a two-layer structure formed in the transistor region, and a first transparent conductive electrode with a single-layer structure formed in the light-emitting region;
  • an oxide semiconductor layer disposed on the first metal layer, including an active region of the thin film transistor formed in the transistor region, and a second transparent conductive electrode formed in the light-emitting region;
  • a second metal layer disposed on the oxide semiconductor layer, including the gate electrode of the thin film transistor formed in the transistor region;
  • a third metal layer, disposed on the second metal layer, includes a source electrode and a drain electrode with a two-layer structure formed in the transistor region, and a third transparent conductive electrode with a single-layer structure formed in the light-emitting region;
  • the first transparent conductive electrode and the third transparent conductive electrode are electrically connected to form the first electrode plate of the storage capacitor, and the second transparent conductive electrode forms the second electrode plate of the storage capacitor.
  • the source electrode, the drain electrode and the light shielding layer all include a stacked transparent conductive film and a first metal film, and the first metal film is located on the transparent conductive film. on the conductive film.
  • both the first transparent conductive electrode and the second transparent electrode include the transparent conductive film.
  • At least one of the first metal layer, the oxide semiconductor layer and the third metal layer further includes a single-layer transparent wire , the transparent wires are arranged corresponding to the light-emitting units.
  • an external wiring area is further included, the light emitting area is located between the transistor area and the external wiring area, the first metal layer and the third metal layer At least one of the layers further includes an external wiring of a two-layer structure formed in the external wiring area.
  • the transparent conductive thin film includes a thin film formed of an indium-based, zinc-based or titanium-based doped transparent oxide material.
  • the display panel and preparation method thereof provided by the present application, and the first metal layer and the third metal layer in the display device are all formed by patterning a composite metal layer, and the composite metal layer includes a first metal film and a transparent conductive film that are arranged in layers.
  • the halftone mask performs a yellow light process on the composite metal layer to remove the first metal film in the light-emitting area, and forms the first electrode plate of the storage capacitor in the light-emitting area.
  • the transparent oxide semiconductor layer is processed to form the active area and the light-emitting area
  • the second electrode plate of the storage capacitor so that the light emitted by the light-emitting unit can pass through the storage capacitor, the aperture ratio of the display panel is improved, and the storage capacity of the storage capacitor is increased, and a halftone mask is used to prepare the electrode of the storage capacitor.
  • the board can also save a mask.
  • transparent wires are also formed in the corresponding light-emitting regions, thereby further improving the aperture ratio of the display panel.
  • FIG. 1 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is another schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a pixel driving circuit provided by an embodiment of the present application.
  • FIG. 4 is another schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a method for fabricating a display panel according to an embodiment of the present application.
  • FIGS. 6 to 15 are schematic diagrams of the film layer structures of the display panel fabricated in each step of the display panel fabrication method provided by the embodiments of the present application.
  • FIG. 1 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application.
  • the display panel 100 includes an OLED display panel and the like, for example, an AMOLED display panel.
  • the display panel 100 includes a plurality of sub-pixels, each of the sub-pixels includes a transistor region TD and a light-emitting region LD, the transistor region TD is provided with a thin film transistor 1, and the light-emitting region LD is provided with a storage capacitor 2 and a light-emitting unit 3 , the light-emitting unit 3 is located above the storage capacitor 2 , and the light-emitting surface of the light-emitting unit 3 faces the storage capacitor 2 .
  • the display panel 100 includes a substrate 10 , a first metal layer 20 arranged on the substrate 10 , a buffer layer 11 arranged on the first metal layer 20 , and a buffer layer 11 arranged on the buffer layer 11 .
  • the upper interlayer insulating layer 13 and the third metal layer 50 are disposed on the interlayer insulating layer 13 .
  • the substrate 10 may be a rigid substrate or a flexible substrate.
  • the substrate 10 may include a rigid substrate such as a glass substrate; when the substrate 10 is a flexible substrate, it may include polyimide Amine (Polyimide, PI) film, ultra-thin glass film and other flexible substrates.
  • a rigid substrate such as a glass substrate
  • a flexible substrate it may include polyimide Amine (Polyimide, PI) film, ultra-thin glass film and other flexible substrates.
  • the first metal layer 20 includes a light shielding layer 21 with a two-layer structure formed in the transistor region TD, and a first transparent conductive electrode 22 with a single-layer structure formed in the light-emitting region LD.
  • the light shielding layer 21 includes a stacked first metal film 5 and a transparent conductive film 4, the first metal film 5 is located on the transparent conductive film 4, and the first transparent conductive electrode 22 includes the transparent conductive film 4.
  • the first metal layer before patterning is the first composite metal layer formed by the first metal film 5 and the transparent conductive film 4, and the first metal layer is formed by performing a yellow light process on the first composite metal layer.
  • the first metal layer 20 includes a light shielding layer 21 with a two-layer structure formed in the transistor region TD, and a first transparent conductive electrode 22 with a single-layer structure formed in the light-emitting region LD.
  • the material of the first metal thin film 5 includes one or a combination of metals such as Mo, Al, Ti, and Cu.
  • the transparent conductive film 4 includes a film formed by a transparent conductive oxide (Transparent Conductive Oxide, TCO), and the transparent conductive oxide includes doped transparent oxide materials such as indium-based, zinc-based, and titanium-based, such as In2O3: Sn (abbreviated as ITO, Indium tin oxide, indium tin oxide), ZnO:Al (abbreviated as AZO, Aluminium zinc oxide, aluminum zinc oxide), TiO2:Nb (abbreviated as NTO, Niobium titanium oxide, niobium titanium oxide) etc.
  • TCO transparent Conductive Oxide
  • a half-tone mask (Half-tone mask, HTM) may be used to perform a yellow light process on the first composite metal layer to form the first metal layer 20, and the first metal layer 20 is included in the The light shielding layer 21 formed by stacking the first metal film 5 and the transparent conductive film 4 formed in the transistor area TD, and the first transparent conductive electrode 22 formed in the light emitting area LD including only the patterned transparent conductive film 4 are formed in the light emitting area LD.
  • the buffer layer 11 is disposed on the first metal layer 20 , and the material of the buffer layer 11 may include inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, etc.
  • the buffer layer 11 can prevent unwanted impurities or contaminants (eg, moisture, oxygen, etc.) from the substrate 10 to diffuse into devices that may be damaged by these impurities or contaminants, while still providing a flat top surface.
  • the oxide semiconductor layer 30 is disposed on the buffer layer 11 , and the material of the oxide semiconductor layer 30 includes amorphous oxide semiconductor materials such as IGZO, IZO, and IZTO.
  • the oxide semiconductor layer 30 includes an active region 31 of the thin film transistor 1 formed in the transistor region TD, and a second transparent conductive electrode 32 formed in the light emitting region LD.
  • the active region 31 includes a channel region 311 and a source region 313 and a drain region 312 on both sides of the channel region 311, wherein the source region 313 and the drain region 312 and the second transparent conductive
  • Each of the electrodes 32 is formed by conducting the oxide semiconductor layer 30 .
  • the active region 31 is disposed corresponding to the light shielding layer 21 , and the light shielding layer 21 is used to shield the active region 31 to prevent light from irradiating the channel region 311 .
  • the gate insulating layer 12 is disposed on the oxide semiconductor layer 30 , the second metal layer 40 is disposed on the gate insulating layer 12 , and the second metal layer 40 is included in the transistor region TD
  • the gate 41 of the thin film transistor 1 is formed. Both the gate electrode 41 and the gate insulating layer 12 are disposed corresponding to the channel region 311 of the active region 31 .
  • the interlayer insulating layer 13 is disposed on the second metal layer 40 , the second transparent conductive electrode 32 and the buffer layer 11 , and the third metal layer 50 is disposed on the interlayer insulating layer 13 .
  • the third metal layer 50 includes a source electrode 51 and a drain electrode 52 with a two-layer structure formed in the transistor region TD, and a third transparent conductive electrode 53 with a single-layer structure formed in the light-emitting region LD.
  • the source electrode 51 and the drain electrode 52 both include a stacked first metal film 5' and a transparent conductive film 4', the first metal film 5' is located on the transparent conductive film 4', and the first metal film 5' is located on the transparent conductive film 4'.
  • the three transparent conductive electrodes 53 include the transparent conductive film 4'.
  • the materials of the first metal film 5' and the first metal film 5 may be the same, and the materials of the transparent conductive film 4' and the transparent conductive film 4 may also be the same.
  • the third metal layer before patterning is the second composite metal layer formed by the first metal film 5' and the transparent conductive film 4', and the second composite metal layer is subjected to a yellow light process to form the second composite metal layer.
  • Three metal layers 50, the third metal layer 50 includes the source electrode 51 and the drain electrode 52 of the two-layer structure formed in the transistor region TD, and the third transparent conductive layer of the single-layer structure formed in the light-emitting region LD electrode 53.
  • the drain 52 is connected to the drain region 312 through a second via hole 131 penetrating the interlayer insulating layer 13 .
  • the source electrode 51 is connected to the source region 313 through the third via hole 132 penetrating the interlayer insulating layer 13 , and the source electrode 51 also penetrates the interlayer insulating layer 13 and the buffer layer.
  • the fourth via hole 111 of 11 is connected to the light shielding layer 21 .
  • the third transparent conductive electrode 53 is connected to the first transparent conductive electrode 22 through a fifth via hole 112 penetrating the interlayer insulating layer 13 and the buffer layer 11 .
  • the third metal layer 50 is formed by performing a yellow light process on the second composite metal layer using a half-tone mask, and the third metal layer 50 includes the first metal layer formed in the transistor region TD.
  • the source electrode 51 and the drain electrode 52 are stacked with the metal film 5' and the transparent conductive film 4', and the third transparent conductive electrode 53 formed in the light emitting region LD only includes the patterned transparent conductive film 4'.
  • the first transparent conductive electrode 22 and the third transparent conductive electrode 53 are electrically connected to form the first electrode plate 28 of the storage capacitor 2 , and the second transparent conductive electrode 32 forms the storage capacitor 2 the second plate 29.
  • the first electrode plate 28 , the second electrode plate 29 , the buffer layer 11 and the interlayer insulating layer 13 constitute the storage capacitor 2 .
  • the display panel 100 further includes a passivation layer 14 , a planarization layer 15 , a pixel electrode 60 and a pixel definition layer 16 stacked on the third metal layer 50 .
  • the passivation layer 14 covers the third metal layer 50 and the interlayer insulating layer 13
  • the planarization layer 15 covers the passivation layer 14 .
  • the material of the planarization layer 15 includes organic materials, and the planarization layer 15 can provide a flat top surface.
  • the pixel electrode 60 is disposed on the planarization layer 15 , and the pixel electrode 60 is connected to the source electrode 51 through a sixth via hole 151 penetrating the planarization layer 15 and the passivation layer 14 .
  • the pixel electrode 60 is a transparent electrode, and the material of the pixel electrode 60 includes a transparent conductive material such as ITO (Indium tin oxide, indium tin oxide).
  • the pixel definition layer 16 is disposed on the pixel electrode 60 and the planarization layer 15 , and the material of the pixel definition layer 16 includes organic photoresist, and the organic photoresist may be PI system (polyimide) , acrylic and other organic photoresist.
  • the pixel definition layer 16 is provided with a first via hole 161 at a position corresponding to the pixel electrode 60 , the first via hole 161 exposes the pixel electrode 60 , and the light emitting unit 3 is disposed in the first via hole 161 . inside the hole 161.
  • the light-emitting surface of the light-emitting unit 3 faces the storage capacitor 2, that is, the display panel 100 adopts bottom light emission. Since the pixel electrode 60 and the storage capacitor 2 are both formed of transparent electrode materials, the light-emitting unit 3 The emitted light can penetrate the pixel electrode 60 and the storage capacitor 2 , and the storage capacitor 2 is arranged in the light emitting area, which reduces the area of the non-light emitting area of the display panel 100 and improves the performance of the display panel 100 . opening rate.
  • a cathode 70 needs to be provided, and the cathode 70 covers the light-emitting unit 3 and the pixel definition layer 16 .
  • the light-emitting unit 3 emits light under the joint action of the pixel electrode 60 and the cathode 70 .
  • the cathode 70 can be a reflective electrode, so as to improve the light utilization rate of the light-emitting unit 3 .
  • the display panel 100 may further include an encapsulation layer (not shown) disposed on the cathode 70 , the encapsulation layer may be encapsulated by a thin film, and the thin film encapsulation may be a first inorganic encapsulation layer, an organic encapsulation layer Layer and the second inorganic encapsulation layer three layers of thin films are stacked in sequence to form a laminated structure or a multi-layer laminated structure, which is used to protect the light-emitting unit 3 and prevent the light-emitting material of the light-emitting unit 3 from being ineffective due to water and oxygen intrusion.
  • an encapsulation layer (not shown) disposed on the cathode 70
  • the encapsulation layer may be encapsulated by a thin film
  • the thin film encapsulation may be a first inorganic encapsulation layer, an organic encapsulation layer Layer and the second inorganic encapsulation layer three layers of thin films are stacked in sequence to form a laminate
  • FIG. 2 is another schematic cross-sectional view of the display panel provided by the embodiment of the present application.
  • at least one of the first metal layer 20 , the oxide semiconductor layer 30 and the third metal layer 50 of the display panel 101 is further included in the light emitting region.
  • the formed transparent wires 6 are arranged corresponding to the light-emitting units 3 .
  • each of the first metal layer 20 , the oxide semiconductor layer 30 and the third metal layer 50 further includes a single-layer transparent wire 6 formed in the light-emitting region.
  • the transparent wires 23 of the first metal layer 20 and the first transparent conductive electrodes 22 are disposed in the same layer and formed at the same time by the same process
  • the transparent wires 33 of the oxide semiconductor layer 30 and the second transparent conductive electrodes 22 are formed at the same time.
  • the conductive electrodes 32 are disposed in the same layer and formed at the same time by the same process
  • the transparent wires 54 of the third metal layer 50 and the third transparent conductive electrodes 53 are disposed in the same layer and formed at the same time by the same process.
  • the transparent wires 6 include various internal connection wires for connecting the thin film transistors and/or storage capacitors in the pixel driving circuit.
  • the display panel 100 can be further reduced by arranging various internal connection lines connecting the thin film transistors and/or storage capacitors in the pixel driving circuit as transparent wires 6 , and arranging the transparent wires 6 corresponding to the light emitting units 3 .
  • the area of the non-light emitting area further increases the aperture ratio of the display panel 100 .
  • the display panel 100 further includes an external wiring area OA, the light emitting area LD is located between the transistor area TD and the external wiring area OA, and the external wiring area OA is provided with various external wirings A wiring 7, the external wiring 7 is used to provide a driving signal to the thin film transistor 1 in the pixel driving circuit.
  • the external wiring 7 includes data signal lines, gate scanning signal lines, sensing signal lines, etc., wherein the first metal layer 20 , the second metal layer 40 and the third metal layer At least one layer in 50 further includes the external wiring 7, and the external wiring 7 is an opaque wire. As shown in FIG.
  • the external traces 7 may include the external traces 24 of the first metal layer 20 , the external traces 42 of the second metal layer 40 , and the external traces of the third metal layer 50 .
  • Line 55 wherein the external wiring 24 of the first metal layer 20 and the external wiring 55 of the third metal layer 50 are both two-layer laminated metal structures, and the external wiring 24 of the first metal layer 20 and The light shielding layer 21 is disposed on the same layer and formed simultaneously by the same process; the external wiring 55 of the third metal layer 50 is disposed on the same layer as the source electrode 51 and the drain electrode 52 and formed simultaneously by the same process.
  • the pixel driving circuit may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst.
  • the first end of the first transistor T1 is connected to the data signal line Data, the control end is connected to the first gate scanning signal line Scan1; the control end of the second transistor T2 is connected to the second end of the first transistor T1, and the first end is connected to the power supply
  • the first end is connected to the sensing signal line Sense, and the second end is connected to the second end of the second transistor T2.
  • the sensing signal line Sense can be used to sense the output current of the driving transistor when the second transistor T2 is turned on, so as to detect the threshold voltage and mobility of the second transistor T2.
  • the sensing signal line Sense can also be used to input a constant voltage to the second terminal of the second transistor T2 during the light-emitting stage of the light-emitting unit 3, so as to control the output current of the second terminal of the second transistor T2 through the gate voltage of the second transistor T2.
  • the first gate scanning signal line Scan1 , the second gate scanning signal line Scan2 , the data signal line Data and the sensing signal line Sense are the external wiring 7 .
  • the connection lines between the first transistor T1 , the second transistor T2 , the third transistor T3 , the external wiring 7 and the storage capacitor Cst are the transparent wires 6 .
  • FIG. 4 is another schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application.
  • a color filter layer 80 is further disposed between the passivation layer 14 and the planarization layer 15 of the display panel 102 , and the color filter layer 80 is disposed corresponding to the light emitting unit 3 , and The orthographic projection of the color filter layer 80 on the substrate 10 covers the orthographic projection of the light-emitting unit 3 on the substrate 10, so that the light emitted by the light-emitting unit 3 can all be directed towards the color filter.
  • Membrane layer 80 is another schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application.
  • a color filter layer 80 is further disposed between the passivation layer 14 and the planarization layer 15 of the display panel 102 , and the color filter layer 80 is disposed corresponding to the light emitting unit 3 , and
  • the orthographic projection of the color filter layer 80 on the substrate 10 covers the orthographic projection of the light-emitting unit 3 on
  • the color filter layer 80 includes a red color filter, a green color filter, and a blue color filter, and each of the light-emitting units 3 corresponds to a color filter of one color.
  • the white light emitted by the light emitting unit 3 is converted into red light through a red color film, into green light through a green color film, and into blue light through a blue color film, thereby realizing the color display of the display panel 102 .
  • the present application further provides a method for manufacturing a display panel.
  • FIGS. 5 to 13 are A schematic diagram of the film layer structure of the display panel prepared by each step in the display panel manufacturing method provided in the application embodiment. This embodiment is described by taking the preparation of the display panel 102 shown in FIG. 4 as an example.
  • the display panel 102 includes a plurality of sub-pixels, and each of the sub-pixels includes a transistor area TD and a light-emitting area LD.
  • the transistor area TD A thin film transistor 1 is provided, and a storage capacitor 2 and a light-emitting unit 3 are provided in the light-emitting area LD.
  • the light-emitting unit 3 is located above the storage capacitor 2 , and the light-emitting surface of the light-emitting unit 3 faces the storage capacitor 2 .
  • the display panel preparation method includes the following steps:
  • the substrate 10 may be a rigid substrate or a flexible substrate.
  • the substrate 10 may include a rigid substrate such as a glass substrate.
  • the substrate 10 is a In the case of flexible substrates, flexible substrates such as polyimide films and ultra-thin glass films may be included.
  • the first metal layer 20 comprising a light-shielding layer 21 with a two-layer structure formed in the transistor region TD, and a first transparent conductive electrode 22 with a single-layer structure formed in the light-emitting region LD;
  • the first composite metal layer 91 is deposited on the substrate 10 , and the first composite metal layer 91 includes the first metal thin film 5 and the transparent conductive thin film 4 which are arranged in layers.
  • the first metal film 5 is located on the transparent conductive film 4, wherein the material of the first metal film 5 includes one or a combination of metals such as Mo, Al, Ti, and Cu.
  • the transparent conductive film 4 includes a film formed of a transparent conductive oxide, and the transparent conductive oxide includes doped transparent oxide materials such as indium-based, zinc-based, and titanium-based, such as In2O3:Sn (ITO for short, Indium tin for short).
  • NTO Niobium titanium titanium oxide, niobium titanium oxide
  • the transparent conductive film 4 is an ITO film
  • the first composite metal layer when the first composite metal layer is formed by compounding the ITO film and the first metal film 5, the first metal film 5 needs to be deposited at room temperature to prevent the ITO film from crystallizing and failing. patterned.
  • the deposition temperature of first metal thin film 5 is not limited.
  • the first halftone mask can be used to perform a yellow light process on the first composite metal layer 91 to form the first metal layer 20, which specifically includes the following steps:
  • the entire surface photoresist 90 is coated on the first composite metal layer 91;
  • the photoresist 90 is exposed and developed to form a plurality of photoresist patterns, including a first photoresist pattern 901 formed in the transistor area TD and a second photoresist pattern formed in the light emitting area LD 902 and the third photoresist pattern 903, the fourth photoresist pattern 904 formed in the external wiring area OA, wherein the thickness of the first photoresist pattern 901 and the fourth photoresist pattern 904 are the same, the thickness of the second photoresist pattern 902 and the first photoresist pattern 904 are the same.
  • the thicknesses of the three photoresist patterns 903 are the same, and the thicknesses of the first photoresist pattern 901 and the fourth photoresist pattern 904 are greater than the thicknesses of the second photoresist pattern 902 and the third photoresist pattern 903;
  • the first photoresist pattern 901 , the second photoresist pattern 902 , the third photoresist pattern 903 , and the fourth photoresist pattern 904 are used as shields to shield the first composite metal layer 91 .
  • secondary etching so that the first composite metal layer 91 forms a light shielding layer pattern in the transistor region TD, a first transparent conductive electrode pattern and a transparent wire pattern are formed in the light emitting region LD, and an external wiring pattern is formed in the external wiring region OA;
  • ashing is performed on the first photoresist pattern 901 , the second photoresist pattern 902 , the third photoresist pattern 903 and the fourth photoresist pattern 904 , so that the first photoresist pattern 901 , the third photoresist pattern 903 and the fourth photoresist pattern 904 are ashed.
  • the thicknesses of the four photoresist patterns 904 are reduced to form a thinned first photoresist pattern 901' and a thinned fourth photoresist pattern 904', and the second photoresist pattern 902 and the third photoresist pattern 903 are completely ashed , exposing the first transparent conductive electrode pattern and the transparent wire pattern;
  • the thinned first photoresist pattern 901 ′ and the thinned fourth photoresist pattern 904 ′ are used as shielding pairs for the light shielding layer pattern, the first transparent conductive electrode pattern, the transparent wire pattern and the external wiring pattern.
  • the line pattern is etched a second time to form a first metal layer 20, the first metal layer 20 includes a light shielding layer 21 formed in the transistor region TD, a first transparent conductive electrode 22 and a transparent wire 23 formed in the light emitting region LD, The external wiring 24 formed in the external wiring area OA.
  • the photoresist pattern is not covered on the first transparent conductive electrode pattern and the transparent wire pattern, after the second etching, the first metal film 5 on the transparent conductive film 4 is etched away, so that the formed first transparent conductive electrode 22 and The transparent wire 23 has only a single-layer transparent conductive film 4; while the light-shielding layer pattern and the external wiring pattern are covered with a photoresist pattern, after the second etching, the formed light-shielding layer 21 and the external wiring 24 include The first metal film 5 and the transparent conductive film 4 are stacked and arranged;
  • the thinned first photoresist pattern 901' and the thinned fourth photoresist pattern 904' are peeled off to expose the complete first metal layer 20.
  • the oxide semiconductor layer 30 includes an active region 31 of the thin film transistor formed in the transistor region TD, and an oxide semiconductor pattern formed in the light emitting region LD;
  • PECVD Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition method
  • other deposition processes to deposit a buffer layer 11 on the first metal layer 20 and the substrate 10
  • the material of the buffer layer 11 includes silicon oxide, silicon nitride , silicon oxynitride and other inorganic materials, such as one or more combinations of Si3N4, SiO2, SiON, etc.
  • the oxide semiconductor thin film is patterned to form an oxide semiconductor layer 30, the oxide semiconductor layer 30 includes an active region 31 of the thin film transistor formed in the transistor region TD, the active region 31 is connected to the The light shielding layer 21 is correspondingly disposed, and the oxide semiconductor patterns 34/35 formed in the light emitting region LD.
  • PVD Physical Vapor Deposition, physical vapor deposition method
  • the second metal layer 40 includes the gate electrode 41 of the thin film transistor formed in the transistor region TD, and conducts the conductorization of the oxide semiconductor layer 30, so that the oxide semiconductor pattern forms a second transparent conductive electrode 32;
  • a deposition process such as PECVD is used to deposit a gate dielectric material on the oxide semiconductor layer 30 and the buffer layer 11 , and the gate dielectric material includes inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride. Material.
  • a deposition process such as PVD is used to deposit a second metal film on the gate dielectric material, the second metal film is patterned to form a gate pattern in the transistor area TD, and an external trace is formed in the external wiring area OA. trace pattern.
  • the gate dielectric material is etched to form the gate 41 , the gate insulating layer 12 and the external wiring 42 .
  • the oxide semiconductor layer 30 that is not covered by the gate electrode 41 is subjected to conducting treatment, so that the active region 31 forms the channel region 311 , and the source region 313 and the drain electrode located on both sides of the channel region 311 In the region 312, the oxide semiconductor patterns 34/35 of the light emitting region LD form the second transparent conductive electrode 32 and the transparent wiring 33, as shown in FIG. 8 .
  • the resistivity of the source region 313 and the drain region 312 is smaller than that of the channel region 311 .
  • the active region 31 is disposed corresponding to the light shielding layer 21 , and the light shielding layer 21 is used to shield the active region 31 to prevent light from irradiating the channel region 311 .
  • the third metal layer 50 is formed by a yellow light process.
  • the third metal layer 50 includes a source electrode 51 and a drain electrode 52 of a two-layer structure formed in the transistor region TD, and a single layer formed in the light emitting region LD.
  • the electrode 32 forms the second plate 29 of the storage capacitor 2 .
  • an inorganic thin film is deposited on the second metal layer 40 , the oxide semiconductor layer 30 and the buffer layer 11 by a deposition process such as PECVD to form the interlayer insulating layer 13 .
  • the interlayer insulating layer 13 is patterned to form a second opening 131 , a third opening 132 , a fourth opening 111 and a fifth opening 112 , as shown in FIG. 9 .
  • the second opening 131 and the third opening 132 penetrate through the interlayer insulating layer 13 to expose part of the drain region 312 and the source region 313 respectively; the fourth opening 111 and the fifth opening 112 penetrates through the interlayer insulating layer 13 and the buffer layer 11 to expose part of the light shielding layer 21 and the first transparent conductive electrode 22 respectively.
  • a second composite metal layer is deposited on the interlayer insulating layer 13 by a deposition process such as PVD, and the material of the second composite metal layer is the same as that of the first composite metal layer 91 .
  • the second composite metal layer is patterned to form the third metal layer 50 using the same process as patterning the first composite metal layer 91 .
  • the third metal layer 50 is formed by performing a yellow light process on the second composite metal layer by using a second halftone mask, and the third metal layer 50 includes all the layers formed in the transistor region TD.
  • the source electrode 51, the drain electrode 52 and the external wiring 55 of the thin film transistor all include the stacked first metal film 5' and the transparent conductive film 4'; the third transparent conductive electrode 53 and the transparent wire 54 only include patterned The transparent conductive film 4'.
  • the drain 52 is connected to the drain region 312 through the second via hole 131 of the interlayer insulating layer 13 .
  • the source electrode 51 is connected to the source region 313 through the third via hole 132 of the interlayer insulating layer 13 , and the source electrode 51 also penetrates through the interlayer insulating layer 13 and the buffer layer 11
  • the fourth via hole 111 is connected to the light shielding layer 21 .
  • the third transparent conductive electrode 53 is connected to the first transparent conductive electrode 22 through the fifth via hole 112 penetrating the interlayer insulating layer 13 and the buffer layer 11 to form the first transparent conductive electrode 22 of the storage capacitor 2 .
  • the electrode plate 28 , the second transparent conductive electrode 32 forms the second electrode plate 29 of the storage capacitor 2 .
  • a deposition process such as PECVD is used to deposit an inorganic thin film on the third metal layer 50 and the interlayer insulating layer 13 as the passivation layer 14 , and a color film is prepared on the passivation layer 14 A film layer 80, the color filter layer 80 is disposed corresponding to the light emitting area LD.
  • an organic photoresist is coated on the color filter layer 80 and the passivation layer 14 to form a planarization layer 15 , and the planarization layer 15 is patterned to form sixth via holes 151 .
  • the sixth via hole 151 penetrates through the planarization layer 15 and the passivation layer 14 to expose the source electrode 51 .
  • a transparent conductive film such as an ITO film, is deposited on the planarization layer 15, and the transparent conductive film is patterned to form a pixel electrode 60.
  • the pixel electrode 60 is disposed corresponding to the color filter layer 80, and the The pixel electrode 60 is connected to the source electrode 51 through the sixth via hole 151 of the planarization layer 15 , as shown in FIG. 13 .
  • the pixel electrode 60 may also be connected to the drain electrode 52 .
  • a pixel definition layer 16 is prepared on the pixel electrode 60 and the planarization layer 15, the pixel definition layer 16 is formed with a first via hole, and the first via hole exposes the pixel electrode 60, so The light-emitting unit 3 is arranged in the first via hole, and the light-emitting unit 3 is arranged corresponding to the color filter layer 80;
  • an organic photoresist is coated on the pixel electrode 60 and the planarization layer 15 to form the pixel definition layer 16 , and the organic photoresist may be a PI-based (polyimide) ), acrylic and other organic photoresist.
  • the pixel definition layer 16 is patterned to form a first via hole 161 at a position corresponding to the pixel electrode 60 , and the pixel electrode 60 is exposed by the first via hole 161 .
  • the light-emitting unit 3 is disposed in the first via hole 161 , and the light-emitting unit 3 is disposed corresponding to the color filter layer 80 .
  • the color filter layer 80 includes a red color filter, a green color filter, and a blue color filter, and each light-emitting unit 3 corresponds to a color filter of one color.
  • the white light emitted by the light-emitting unit 3 is converted into red light through a red color film, into green light through a green color film, and into blue light through a blue color film, thereby realizing the color display of the display panel.
  • a cathode 70 is prepared on the light-emitting unit 3 and the pixel definition layer 16 .
  • a third metal thin film is deposited on the light-emitting unit 3 and the pixel definition layer 16 , and the third metal thin film is patterned to form a cathode 70 , as shown in FIG. 4 .
  • the light-emitting unit 3 emits light under the joint action of the pixel electrode 60 and the cathode 70 . Since the display panel of the present application is bottom light-emitting, the cathode 70 can be a reflective electrode, so as to improve the light utilization rate of the light-emitting unit 3 .
  • the display panel preparation method further includes fabricating an encapsulation layer on the cathode 70, the encapsulation layer may be encapsulated by a thin film, and the thin film encapsulation may be composed of a first inorganic encapsulation layer, an organic encapsulation layer, and a second encapsulation layer.
  • Two inorganic encapsulation layers and three layers of thin films are sequentially stacked to form a laminated structure or a multi-layer laminated structure, which is used to protect the light-emitting unit 3 and prevent the light-emitting material of the light-emitting unit 3 from failing due to water and oxygen intrusion.
  • the light-emitting surface of the light-emitting unit 3 faces the storage capacitor 2, that is, the display panel adopts bottom light-emitting.
  • the capacitors 2 are all formed of transparent electrode materials, the light emitted by the light-emitting unit 3 can penetrate the pixel electrode 60 and the storage capacitor 2, and the storage capacitor 2 is arranged in the light-emitting area, which reduces the size of the display.
  • the non-light emitting area of the panel increases the aperture ratio of the display panel.
  • the connecting wires in the pixel driving circuit are made into transparent wires and arranged in the light emitting area LD, which can further reduce the area of the non-light emitting area of the display panel and further improve the aperture ratio of the display panel.
  • the method for fabricating a display panel of the present application is not limited to fabricating the display panel of this embodiment, and the method for fabricating a display panel of the present application can be used to fabricate any display panel in the foregoing embodiments.
  • An embodiment of the present application further provides a display device, which includes the display panel of one of the foregoing embodiments, a device such as a circuit board bound to the display panel, and a cover plate covering the display panel.
  • the present application provides a display panel, a preparation method thereof, and a display device; the first metal layer and the third metal layer of the display panel adopt a composite film layer of a first metal film and a transparent conductive film, and use a halftone mask to The first metal layer and the second metal layer are subjected to a yellow light process.
  • the first electrode plate of the transparent storage capacitor is formed in the light emitting area, and the oxide semiconductor layer is formed when the active area is formed.
  • the second plate of the transparent storage capacitor is formed in the area, so that the light emitted by the light-emitting unit can pass through the storage capacitor, the aperture ratio of the display panel is improved, and the storage capacity of the storage capacitor is increased.
  • transparent first electrode plate and the transparent second electrode plate of the storage capacitor are formed, transparent wires are also formed in the corresponding light-emitting regions, thereby further improving the aperture ratio of the display panel.

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Abstract

一种显示面板(100)及其制备方法、显示装置，显示面板(100)的第一金属层(20)和第三金属层(50)均由复合金属层图案化形成，对复合金属层进行黄光工艺在发光区(LD)形成存储电容(2)的第一极板(28)，同时处理透明氧化物半导体层(30)在发光区(LD)形成存储电容(2)的第二极板(29)，其中第一极板(28)和第二极板(29)均为透明导电薄膜，以缓解现有底发光AMOLED器件开口率低的问题。

Description

显示面板及其制备方法、显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及其制备方法、显示装置。
 背景技术
有源矩阵有机发光二极管显示（Active Matrix Organic Light Emitting Display，AMOLED）相较于液晶显示（Liquid Crystal Display，LCD），具备高色域、高对比度、可柔性及可穿戴等优点，逐渐成为显示行业的发展趋势。AMOLED器件根据出光方向不同可以分为顶发光和底发光，而底发光AMOLED器件受限于存储电容的不透光性，导致开口率较低。
因此，现有底发光AMOLED器件开口率低的问题需要解决。
 技术问题
本申请提供一种显示面板及其制备方法、显示装置，以缓解现有底发光AMOLED器件开口率低的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种显示面板，其包括多个子像素，每个所述子像素包括晶体管区和发光区，所述晶体管区设置有薄膜晶体管，所述发光区设置有存储电容和发光单元，所述发光单元位于所述存储电容上方，且所述发光单元的出光面朝向所述存储电容；所述显示面板包括衬底、第一金属层、氧化物半导体层、第二金属层以及第三金属层；所述第一金属层设置于所述衬底上，包括在所述晶体管区形成的两层结构的遮光层，在所述发光区形成的单层结构的第一透明导电电极；所述氧化物半导体层设置于所述第一金属层上，包括在所述晶体管区形成的所述薄膜晶体管的有源区，在所述发光区形成的第二透明导电电极；所述第二金属层设置于所述氧化物半导体层上，包括在所述晶体管区形成的所述薄膜晶体管的栅极；所述第三金属层设置于所述第二金属层上，包括在所述晶体管区形成的两层结构的源极和漏极，在所述发光区形成的单层结构的第三透明导电电极；其中，所述第一透明导电电极和所述第三透明导电电极电连接，形成所述存储电容的第一极板，所述第二透明导电电极形成所述存储电容的第二极板。
在本申请实施例提供的显示面板中，所述源极、所述漏极以及所述遮光层均包括叠层设置的透明导电薄膜和第一金属薄膜，所述第一金属薄膜位于所述透明导电薄膜上。
在本申请实施例提供的显示面板中，所述第一透明导电电极和所述第二透明电极均包括所述透明导电薄膜。
在本申请实施例提供的显示面板中，在所述发光区，所述第一金属层、所述氧化物半导体层以及所述第三金属层中的至少一层还包括单层结构的透明导线，所述透明导线与所述发光单元对应设置。
在本申请实施例提供的显示面板中，还包括外部走线区，所述发光区位于所述晶体管区和所述外部走线区之间，所述第一金属层、所述第三金属层中的至少一层还包括在所述外部走线区形成的两层结构的外部走线。
在本申请实施例提供的显示面板中，所述透明导电薄膜包括铟基、锌基或钛基掺杂的透明氧化物材料形成的薄膜。
在本申请实施例提供的显示面板中，所述第一金属薄膜的材料包括Mo、Al、Ti、Cu中的一种或者几种的组合。
在本申请实施例提供的显示面板中，所述显示面板还包括层叠设置于所述第三金属层上的钝化层、平坦化层、像素电极以及像素定义层，其中所述像素定义层形成有第一过孔，所述第一过孔裸露出所述像素电极，所述发光单元设置于所述第一过孔内。
在本申请实施例提供的显示面板中，所述显示面板在述钝化层和所述平坦化层之间还设置有彩膜层，所述彩膜层对应所述第一过孔设置。
在本申请实施例提供的显示面板中，所述彩膜层在所述衬底上的正投影覆盖所述发光单元在所述衬底上的正投影。
本申请实施例还提供一种显示面板制备方法，显示面板包括多个子像素，每个所述子像素包括晶体管区和发光区，所述晶体管区设置有薄膜晶体管，所述发光区设置有存储电容和发光单元，所述发光单元位于所述存储电容上方，且所述发光单元的出光面朝向所述存储电容；所述显示面板制备方法包括：
提供衬底；
在所述衬底上制备第一复合金属层，使用第一半色调掩膜板对所述第一复合金属层进行黄光工艺形成第一金属层，所述第一金属层包括在所述晶体管区形成的两层结构的遮光层，在所述发光区形成的单层结构的第一透明导电电极；
在所述第一金属层上制备缓冲层，并在所述缓冲层上制备氧化物半导体薄膜，对所述氧化物半导体薄膜进行黄光工艺形成氧化物半导体层，所述氧化物半导体层包括在所述晶体管区形成的所述薄膜晶体管的有源区，在所述发光区形成的氧化物半导体图案；
在所述氧化物半导体层上制备栅极绝缘层，并在栅极绝缘层上制备第二金属薄膜，对所述第二金属薄膜进行黄光工艺形成第二金属层，所述第二金属层包括在所述晶体管区形成的所述薄膜晶体管的栅极，并对所述氧化物半导体层进行导体化，使所述氧化物半导体图案形成第二透明导电电极；
在所述第二金属层上制备层间绝缘层，并在所述层间绝缘层上制备第二复合金属层，使用第二半色调掩膜板对所述第二复合金属层进行黄光工艺形成第三金属层，所述第三金属层包括在所述晶体管区形成的两层结构的源极和漏极，在所述发光区形成的单层结构的第三透明导电电极，其中所述第三透明导电电极和所述第一透明导电电极电连接，以形成所述存储电容的第一极板，所述第二透明导电电极形成所述存储电容的第二极板。
在本申请实施例提供的显示面板制备方法中，所述显示面板制备方法还包括：
在所述第三金属层上制备钝化层，并在所述钝化层上制备彩膜层，所述彩膜层对应所述发光区设置；
在所述彩膜层及所述钝化层上制备平坦化层，并在所述平坦化层上制备像素电极，所述像素电极与所述源极或所述漏极连接；
在所述像素电极以及所述平坦化层上制备像素定义层，所述像素定义层形成有第一过孔，所述第一过孔裸露出所述像素电极，所述发光单元设置于所述第一过孔内，且所述发光单元与所述彩膜层对应设置；
在所述发光单元以及所述像素定义层上制备阴极。
在本申请实施例提供的显示面板制备方法中，所述第一复合金属层和所述第二复合金属层均包括叠层设置的透明导电薄膜和第一金属薄膜，所述第一金属薄膜位于所述透明导电薄膜上。
本申请实施例还提供一种显示装置，其包括显示面板、绑定于所述显示面板的电路板、覆盖在所述显示面板上的盖板，其中所述显示面板包括多个子像素，每个所述子像素包括晶体管区和发光区，所述晶体管区设置有薄膜晶体管，所述发光区设置有存储电容和发光单元，所述发光单元位于所述存储电容上方，且所述发光单元的出光面朝向所述存储电容；所述显示面板包括：
衬底；
第一金属层，设置于所述衬底上，包括在所述晶体管区形成的两层结构的遮光层，在所述发光区形成的单层结构的第一透明导电电极；
氧化物半导体层，设置于所述第一金属层上，包括在所述晶体管区形成的所述薄膜晶体管的有源区，在所述发光区形成的第二透明导电电极；
第二金属层，设置于所述氧化物半导体层上，包括在所述晶体管区形成的所述薄膜晶体管的栅极；以及
第三金属层，设置于所述第二金属层上，包括在所述晶体管区形成的两层结构的源极和漏极，在所述发光区形成的单层结构的第三透明导电电极；
其中，所述第一透明导电电极和所述第三透明导电电极电连接，形成所述存储电容的第一极板，所述第二透明导电电极形成所述存储电容的第二极板。
在本申请实施例提供的显示装置中，所述源极、所述漏极以及所述遮光层均包括叠层设置的透明导电薄膜和第一金属薄膜，所述第一金属薄膜位于所述透明导电薄膜上。
在本申请实施例提供的显示装置中，所述第一透明导电电极和所述第二透明电极均包括所述透明导电薄膜。
在本申请实施例提供的显示装置中，在所述发光区，所述第一金属层、所述氧化物半导体层以及所述第三金属层中的至少一层还包括单层结构的透明导线，所述透明导线与所述发光单元对应设置。
在本申请实施例提供的显示装置中，还包括外部走线区，所述发光区位于所述晶体管区和所述外部走线区之间，所述第一金属层、所述第三金属层中的至少一层还包括在所述外部走线区形成的两层结构的外部走线。
在本申请实施例提供的显示装置中，所述透明导电薄膜包括铟基、锌基或钛基掺杂的透明氧化物材料形成的薄膜。
 有益效果
本申请提供的显示面板及其制备方法、显示装置中第一金属层和第三金属层均由复合金属层图案化形成，复合金属层包括叠层设置的第一金属薄膜和透明导电薄膜，使用半色调掩膜板对复合金属层进行黄光工艺去除发光区内的第一金属薄膜，在发光区形成存储电容的第一极板，同时处理透明氧化物半导体层形成有源区和位于发光区的存储电容的第二极板，使发光单元发出的光线能够穿过存储电容，提高了显示面板的开口率，增大了存储电容的存储量，而且采用半色调掩膜板制备存储电容的极板还可节省一道光罩。另外在形成存储电容的透明第一极板和透明第二极板的同时，在对应发光区还形成有透明导线，从而进一步提高了显示面板的开口率。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示面板的一种剖面结构示意图。
图2为本申请实施例提供的显示面板的另一种剖面结构示意图。
图3为本申请实施例提供的像素驱动电路示意图。
图4为本申请实施例提供的显示面板的又一种剖面结构示意图。
图5为本申请实施例提供的显示面板制备方法的流程示意图。
图6至图15为本申请实施例提供的显示面板制备方法中各步骤制得的显示面板的膜层结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。在附图中，为了清晰理解和便于描述，夸大了一些层和区域的厚度。即附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
在一种实施例中，请参照图1，图1为本申请实施例提供的显示面板的一种剖面结构示意图。所述显示面板100包括OLED显示面板等，例如可以为AMOLED显示面板。所述显示面板100包括多个子像素，每个所述子像素包括晶体管区TD和发光区LD，所述晶体管区TD设置有薄膜晶体管1，所述发光区LD设置有存储电容2和发光单元3，所述发光单元3位于所述存储电容2上方，且所述发光单元3的出光面朝向所述存储电容2。
具体地，所述显示面板100包括衬底10、设置于所述衬底10上的第一金属层20、设置于所述第一金属层20上的缓冲层11、设置于所述缓冲层11上的氧化物半导体层30、设置于所述氧化物半导体层30上栅极绝缘层12、设置于所述栅极绝缘层12上的第二金属层40、设置于所述第二金属层40上的层间绝缘层13、设置于所述层间绝缘层13第三金属层50。
可选地，所述衬底10可以为刚性基板或柔性基板，所述衬底10为刚性基板时，可包括玻璃基板等硬性基板；所述衬底10为柔性基板时，可包括聚酰亚胺（Polyimide，PI）薄膜、超薄玻璃薄膜等柔性基板。
所述第一金属层20包括在所述晶体管区TD形成的所两层结构的遮光层21，在所述发光区LD形成的单层结构的第一透明导电电极22。所述遮光层21包括层叠设置的第一金属薄膜5和透明导电薄膜4，所述第一金属薄膜5位于所述透明导电薄膜4上，所述第一透明导电电极22包括所述透明导电薄膜4。可以理解的，图案化之前的第一金属层是由第一金属薄膜5和透明导电薄膜4形成的第一复合金属层，而对第一复合金属层进行黄光工艺形成所述第一金属层20，所述第一金属层20包括在所述晶体管区TD形成的两层结构的遮光层21，在所述发光区LD形成的单层结构的第一透明导电电极22。
其中第一金属薄膜5的材料包括Mo、Al、Ti、Cu等金属中的一种或者几种的组合。所述透明导电薄膜4包括由透明导电氧化物（Transparent Conductive Oxide，TCO）形成的薄膜，所述透明导电氧化物包括铟基、锌基、钛基等掺杂的透明氧化物材料，例如In2O3:Sn（简称ITO，Indium tin oxide，铟锡氧化物）、ZnO:Al（简称AZO，Aluminium zinc oxide，铝锌氧化物）、TiO2:Nb（简称NTO，Niobium titanium oxide，铌钛氧化物）等。
具体地，可采用半色调掩膜板（Half-tone mask，HTM）对所述第一复合金属层进行黄光工艺形成所述第一金属层20，所述第一金属层20包括在所述晶体管区TD形成的由第一金属薄膜5和透明导电薄膜4叠层设置的遮光层21，以及在所述发光区LD形成的仅包括图案化的透明导电薄膜4的第一透明导电电极22。
所述缓冲层11设置于所述第一金属层20上，所述缓冲层11的材料可以包括氧化硅、氮化硅、氮氧化硅等无机材料，所述缓冲层11可以防止不期望的杂质或污染物（例如湿气、氧气等）从所述衬底10扩散至可能因这些杂质或污染物而受损的器件中，同时还可以提供平坦的顶表面。
所述氧化物半导体层30设置于所述缓冲层11上，所述氧化物半导体层30的材料包括IGZO、IZO、IZTO等非晶氧化物半导体材料。所述氧化物半导体层30包括在所述晶体管区TD形成的所述薄膜晶体管1的有源区31，在所述发光区LD形成的第二透明导电电极32。所述有源区31包括沟道区311以及沟道区311两侧的源极区313和漏极区312，其中所述源极区313和所述漏极区312以及所述第二透明导电电极32均是对所述氧化物半导体层30进行导体化形成。所述有源区31与所述遮光层21对应设置，所述遮光层21用于遮挡所述有源区31，避免光线照射沟道区311。
所述栅极绝缘层12设置于所述氧化物半导体层30上，所述第二金属层40设置于所述栅极绝缘层12上，所述第二金属层40包括在所述晶体管区TD形成的所述薄膜晶体管1的栅极41。所述栅极41和所述栅极绝缘层12均与所述有源区31的所述沟道区311对应设置。
所述层间绝缘层13设置于所述第二金属层40、所述第二透明导电电极32以及所述缓冲层11上，所述第三金属层50设置于所述层间绝缘层13上。所述第三金属层50包括在所述晶体管区TD形成两层结构的源极51和漏极52，在所述发光区LD形成的单层结构的第三透明导电电极53。
所述源极51和所述漏极52均包括层叠设置的第一金属薄膜5’和透明导电薄膜4’，所述第一金属薄膜5’位于所述透明导电薄膜4’上，所述第三透明导电电极53包括所述透明导电薄膜4’。所述第一金属薄膜5’和所述第一金属薄膜5的材料可以相同，所述透明导电薄膜4’和所述透明导电薄膜4的材料也可以相同。同样可以理解的，图案化之前的第三金属层是由第一金属薄膜5’和透明导电薄膜4’形成的第二复合金属层，而对第二复合金属层进行黄光工艺形成所述第三金属层50，所述第三金属层50包括在所述晶体管区TD形成的所两层结构的源极51和漏极52，在所述发光区LD形成的单层结构的第三透明导电电极53。
所述漏极52通过贯穿所述层间绝缘层13的第二过孔131与所述漏极区312连接。所述源极51通过贯穿所述层间绝缘层13的第三过孔132与所述源极区313连接，且所述源极51还通过贯穿所述层间绝缘层13和所述缓冲层11的第四过孔111与所述遮光层21连接。所述第三透明导电电极53通过贯穿所述层间绝缘层13和所述缓冲层11的第五过孔112与所述第一透明导电电极22连接。
可选地，采用半色调掩膜板对所述第二复合金属层进行黄光工艺形成所述第三金属层50，所述第三金属层50包括在所述晶体管区TD形成的由第一金属薄膜5’和透明导电薄膜4’叠层设置的源极51和漏极52，在所述发光区LD形成的仅包括图案化的透明导电薄膜4’的第三透明导电电极53。
其中，所述第一透明导电电极22和所述第三透明导电电极53电连接，以形成所述存储电容2的第一极板28，所述第二透明导电电极32形成所述存储电容2的第二极板29。所述第一极板28、所述第二极板29、所述缓冲层11和所述层间绝缘层13构成存储电容2。
当然地，所述显示面板100还包括层叠设置于所述第三金属层50上的钝化层14、平坦化层15、像素电极60以及像素定义层16。
具体地，所述钝化层14覆盖在所述第三金属层50以及所述层间绝缘层13上，所述平坦化层15覆盖在所述钝化层14上。所述平坦化层15的材料包括有机材料，所述平坦化层15可以提供平坦的顶表面。
所述像素电极60设置于所述平坦化层15上，且所述像素电极60通过贯穿所述平坦化层15和所述钝化层14的第六过孔151与所述源极51连接。所述像素电极60为透明电极，所述像素电极60的材料包括ITO（Indium tin oxide，铟锡氧化物）等透明导电材料。
所述像素定义层16设置于所述像素电极60以及所述平坦化层15上，所述像素定义层16的材料包括有机光阻，所述有机光阻可以是PI系（聚酰亚胺）、亚克力系等有机光阻中的一种。所述像素定义层16在对应所述像素电极60的位置设置有第一过孔161，所述第一过孔161裸露出所述像素电极60，所述发光单元3设置于所述第一过孔161内。
所述发光单元3的出光面朝向所述存储电容2，也即所述显示面板100采用底发光，由于所述像素电极60和所述存储电容2均采用透明电极材料形成，所述发光单元3发出的光线能够穿透所述像素电极60和所述存储电容2，而且把所述存储电容2设置于出光区，减小了所述显示面板100的非出光区面积，提高了显示面板100的开口率。
需要说明的是，为了实现所述发光单元3发光，还需要设置阴极70，所述阴极70覆盖在所述发光单元3及所述像素定义层16上。所述发光单元3在所述像素电极60和所述阴极70的共同作用下发光。因本申请的显示面板100为底发光，故所述阴极70可以为反射电极，以提高发光单元3的光线利用率。
另外，所述显示面板100还可包括设置于所述阴极70上的封装层（图未示），所述封装层可以采用薄膜封装，所述薄膜封装可以为由第一无机封装层、有机封装层、第二无机封装层三层薄膜依次层叠形成的叠层结构或更多层的叠层结构，用于保护所述发光单元3，避免水氧入侵导致发光单元3的发光材料失效。
在一种实施例中，请参照图2，图2为本申请实施例提供的显示面板的另一种剖面示意图。与上述实施例不同的是，所述显示面板101的所述第一金属层20、所述氧化物半导体层30以及所述第三金属层50中的至少一层还包括在所述发光区还形成的透明导线6，所述透明导线6与所述发光单元3对应设置。
如图2所示，所述第一金属层20、所述氧化物半导体层30以及所述第三金属层50的每一层均还包括在所述发光区形成的单层结构的透明导线6，其中所述第一金属层20的透明导线23与所述第一透明导电电极22同层设置且采用相同的工艺同时形成，所述氧化物半导体层30的透明导线33与所述第二透明导电电极32同层设置且采用相同的工艺同时形成，所述第三金属层50的透明导线54与所述第三透明导电电极53同层设置且采用相同的工艺同时形成。所述透明导线6包括用于连接像素驱动电路中的薄膜晶体管和/或存储电容的各种内部连接走线。
通过把像素驱动电路中连接薄膜晶体管和/或存储电容的各种内部连接走线设置为透明导线6，并把所述透明导线6对应所述发光单元3设置，可进一步减少所述显示面板100非出光区的面积，进而进一步提高所述显示面板100的开口率。
当然地，所述显示面板100还包括外部走线区OA，所述发光区LD位于所述晶体管区TD和所述外部走线区OA之间，所述外部走线区OA设置有各种外部走线7，所述外部走线7用于给像素驱动电路中的所述薄膜晶体管1提供驱动信号。可选地，所述外部走线7包括数据信号线、栅极扫描信号线、感测信号线等，其中所述第一金属层20、所述第二金属层40以及所述第三金属层50中的至少一层还包括所述外部走线7，所述外部走线7为不透明导线。如图2所示，所述外部走线7可以包括所述第一金属层20的外部走线24、所述第二金属层40的外部走线42、所述第三金属层50的外部走线55，其中所述第一金属层20的外部走线24和所述第三金属层50的外部走线55均为两层叠层金属结构，所述第一金属层20的外部走线24与遮光层21同层设置且采用相同的工艺同时形成；所述第三金属层50的外部走线55与所述源极51和漏极52同层设置且采用相同的工艺同时形成。
可选地，请参照图3，以3T1C像素驱动电路为例说明所述透明导线6和所述外部走线7的功能。所述像素驱动电路可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3、存储电容Cst。第一晶体管T1的第一端连接数据信号线Data，控制端连接第一栅极扫描信号线Scan1；第二晶体管T2的控制端连接所述第一晶体管T1的第二端，第一端连接电源信号线VDD，第二端连接发光单元3；存储电容Cst连接于所述第二晶体管T2的第二端与控制端之间；第三晶体管T3的控制端连接第二栅极扫描信号线Scan2，第一端连接感测信号线Sense，第二端连接所述第二晶体管T2的第二端。感测信号线Sense可以用于在第二晶体管T2导通时感测驱动晶体管的输出电流，以检测第二晶体管T2的阈值电压和迁移率。感测信号线Sense还可以用于在发光单元3发光阶段向第二晶体管T2的第二端输入恒定电压，以便通过第二晶体管T2的栅极电压控制其第二端的输出电流。
其中，所述第一栅极扫描信号线Scan1、所述第二栅极扫描信号线Scan2、所述数据信号线Data以及所述感测信号线Sense为所述外部走线7。所述第一晶体管T1、所述第二晶体管T2、所述第三晶体管T3与所述外部走线7以及所述存储电容Cst之间的连接线为所述透明导线6。其他说明请参照上述实施例，在此不再赘述。
在一种实施例中，请参照图4，图4为本申请实施例提供的显示面板的又一种剖面结构示意图。与上述实施例不同的是，显示面板102的所述钝化层14和所述平坦化层15之间还设置有彩膜层80，所述彩膜层80对应所述发光单元3设置，且所述彩膜层80在所述衬底10上的正投影覆盖所述发光单元3在所述衬底10上的正投影，以使所述发光单元3发出的光线能够全部射向所述彩膜层80。所述彩膜层80包括红色彩膜、绿色彩膜、蓝色彩膜，每个所述发光单元3对应一种颜色的彩膜。所述发光单元3发出的白光经过红色彩膜被转换成红光、经过绿色彩膜被转换成绿光、经过蓝色彩膜被转换成蓝光，进而实现显示面板102的彩色显示。其他说明请参照上述实施例，在此不再赘述。
在一种实施例中，本申请还提供一种显示面板制备方法，请参照图5至图13，图5为本申请实施例提供的显示面板制备方法的流程示意图，图6至图13为本申请实施例提供的显示面板制备方法中各步骤制得的显示面板的膜层结构示意图。本实施例以制备图4所示的显示面板102为例说明，请参照图4，显示面板102包括多个子像素，每个所述子像素包括晶体管区TD和发光区LD，所述晶体管区TD设置有薄膜晶体管1，所述发光区LD设置有存储电容2和发光单元3，所述发光单元3位于所述存储电容2上方，且所述发光单元3的出光面朝向所述存储电容2。所述显示面板制备方法包括以下步骤：
S301、提供衬底10；
具体地，请参照图6，提供衬底10，所述衬底10可以为刚性基板或柔性基板，所述衬底10为刚性基板时，可包括玻璃基板等硬性基板；所述衬底10为柔性基板时，可包括聚酰亚胺薄膜、超薄玻璃薄膜等柔性基板。
S302、在所述衬底10上制备第一复合金属层，使用第一半色调掩膜板对所述第一复合金属层进行黄光工艺形成第一金属层20，所述第一金属层20包括在所述晶体管区TD形成的两层结构的遮光层21，在所述发光区LD形成的单层结构的第一透明导电电极22；
具体地，请参照图6中的a，在所述衬底10上沉积所述第一复合金属层91，所述第一复合金属层91包括层叠设置的第一金属薄膜5和透明导电薄膜4，所述第一金属薄膜5位于所述透明导电薄膜4上，其中第一金属薄膜5的材料包括Mo、Al、Ti、Cu等金属中的一种或者几种的组合。所述透明导电薄膜4包括由透明导电氧化物形成的薄膜，所述透明导电氧化物包括铟基、锌基、钛基等掺杂的透明氧化物材料，例如In2O3:Sn（简称ITO，Indium tin oxide，铟锡氧化物）、ZnO:Al（简称AZO，Aluminium zinc oxide，铝锌氧化物）、TiO2:Nb（简称NTO，Niobium titanium oxide，铌钛氧化物）等。
可选地，所述透明导电薄膜4为ITO薄膜，由ITO薄膜和第一金属薄膜5复合形成第一复合金属层时，第一金属薄膜5需要在室温下沉积，以防止ITO薄膜结晶而无法图案化。当所述第一复合金属层由AZO薄膜与第一金属薄膜5复合而成或者由NTO薄膜与第一金属薄膜5复合而成时，对第一金属薄膜5的沉积温度无限制。
具体地，可采用第一半色调掩膜板对所述第一复合金属层91进行黄光工艺形成第一金属层20，具体地包括以下步骤：
如图6中b所示，在所述第一复合金属层91涂布整面光阻90；
如图6中c所示，对所述光阻90进行曝光、显影形成多个光阻图案，包括在晶体管区TD形成的第一光阻图案901，在发光区LD形成的第二光阻图案902和第三光阻图案903，在外部走线区OA形成的第四光阻图案904，其中第一光阻图案901和第四光阻图案904的厚度相同，第二光阻图案902和第三光阻图案903的厚度相同，且第一光阻图案901和第四光阻图案904的厚度大于第二光阻图案902和第三光阻图案903的厚度；
如图6中d所示，以第一光阻图案901、第二光阻图案902、第三光阻图案903以及第四光阻图案904为遮挡对所述第一复合金属层91进行第一次蚀刻，使所述第一复合金属层91在晶体管区TD形成遮光层图案，在发光区LD形成第一透明导电电极图案和透明导线图案，在外部走线区OA形成外部走线图案；
如图6中e所示，对第一光阻图案901、第二光阻图案902、第三光阻图案903以及第四光阻图案904进行灰化处理，使第一光阻图案901、第四光阻图案904的厚度减薄形成减薄的第一光阻图案901’和减薄的第四光阻图案904’，第二光阻图案902、第三光阻图案903完全被灰化掉，裸露出第一透明导电电极图案和透明导线图案；
如图6中f所示，以减薄的第一光阻图案901’和减薄的第四光阻图案904’为遮挡对遮光层图案、第一透明导电电极图案、透明导线图案以及外部走线图案进行第二次蚀刻以形成第一金属层20，所述第一金属层20包括在晶体管区TD形成的遮光层21，在发光区LD形成的第一透明导电电极22和透明导线23，在外部走线区OA形成的外部走线24。其中因第一透明导电电极图案、透明导线图案上面没有覆盖光阻图案，经过第二蚀刻后，透明导电薄膜4上面的第一金属薄膜5被蚀刻掉，使形成的第一透明导电电极22和透明导线23仅有单层结构的透明导电薄膜4；而遮光层图案和外部走线图案上面因覆盖有光阻图案，经过第二次蚀刻后，形成的遮光层21和外部走线24均包括层叠设置的第一金属薄膜5和透明导电薄膜4；
如图6中g所示，剥离掉减薄的第一光阻图案901’和减薄的第四光阻图案904’以裸露出完整的第一金属层20。
S303、在所述第一金属层20上制备缓冲层11，并在所述缓冲层11上制备氧化物半导体薄膜，对所述氧化物半导体薄膜进行黄光工艺形成氧化物半导体层30，所述氧化物半导体层30包括在所述晶体管区TD形成的所述薄膜晶体管的有源区31，在所述发光区LD形成的氧化物半导体图案；
具体地，请参照图7，采用PECVD (Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学的气相沉积法)等沉积工艺在所述第一金属层20以及所述衬底10上沉积缓冲层11，所述缓冲层11的材料包括氧化硅、氮化硅、氮氧化硅等无机材料，例如Si3N4、SiO2、SiON等中的一种或几种的组合物。
进一步地，采用PVD（Physical Vapor Deposition，物理气相沉积法）等沉积工艺在所述缓冲层11上沉积氧化物半导体薄膜，所述氧化物半导体薄膜的材料包括IGZO、IZO、IZTO等非晶氧化物半导体材料。图案化所述氧化物半导体薄膜形成氧化物半导体层30，所述氧化物半导体层30包括在所述晶体管区TD形成的所述薄膜晶体管的有源区31，所述有源区31与所述遮光层21对应设置，在所述发光区LD形成的氧化物半导体图案34/35。
S304、在所述氧化物半导体层30上制备栅极绝缘层12，并在栅极绝缘层12上制备第二金属薄膜，对所述第二金属薄膜进行黄光工艺形成第二金属层40，所述第二金属层40包括在所述晶体管区TD形成的所述薄膜晶体管的栅极41，并对所述氧化物半导体层30进行导体化，使所述氧化物半导体图案形成第二透明导电电极32；
具体地，采用PECVD等沉积工艺在所述氧化物半导体层30以及所述缓冲层11上沉积栅极介电材料，所述栅极介电材料包括氧化硅、氮化硅、氮氧化硅等无机材料。
进一步地，采用PVD等沉积工艺在所述栅极介电材料上沉积第二金属薄膜，图案化所述第二金属薄膜在所述晶体管区TD形成栅极图案，在外部走线区OA形成外部走线图案。利用所述栅极图案和所述外部走线图案做遮挡，对所述栅极介电材料进行蚀刻，形成栅极41、栅极绝缘层12、外部走线42。然后对未被所述栅极41覆盖的氧化物半导体层30进行导体化处理，使所述有源区31形成沟道区311、以及位于沟道区311两侧的源极区313和漏极区312，使所述发光区LD的氧化物半导体图案34/35形成第二透明导电电极32和透明走线33，如图8所示。其中源极区313和漏极区312的电阻率小于沟道区311的电阻率。所述有源区31与所述遮光层21对应设置，所述遮光层21用于遮挡所述有源区31，避免光线照射所述沟道区311。
S305、在所述第二金属层40上制备层间绝缘层13，并在所述层间绝缘层13上制备第二复合金属层，使用第二半色调掩膜板对所述第二复合金属层进行黄光工艺形成第三金属层50，所述第三金属层50包括在所述晶体管区TD形成的两层结构的源极51和漏极52，在所述发光区LD形成的单层结构的第三透明导电电极53，其中所述第三透明导电电极53和所述第一透明导电电极22电连接，以形成所述存储电容2的第一极板28，所述第二透明导电电极32形成所述存储电容2的第二极板29。
具体地，采用PECVD等沉积工艺在所述第二金属层40、所述氧化物半导体层30以及所述缓冲层11上沉积无机薄膜形成层间绝缘层13。图案化所述层间绝缘层13形成第二开孔131、第三开孔132、第四开孔111以及第五开孔112，如图9所示。其中第二开孔131、第三开孔132均贯穿所述层间绝缘层13以分别裸露出部分所述漏极区312和所述源极区313；第四开孔111和第五开孔112均贯穿所述层间绝缘层13以及所述缓冲层11以分别裸露出部分所述遮光层21和所述第一透明导电电极22。
进一步地，采用PVD等沉积工艺在所述层间绝缘层13上沉积第二复合金属层，所述第二复合金属层的材料和所述第一复合金属层91的材料相同。采用与图案化所述第一复合金属层91相同的工艺图案化所述第二复合金属层以形成所述第三金属层50。可选地，采用第二半色调掩膜板对所述第二复合金属层进行黄光工艺形成所述第三金属层50，所述第三金属层50包括在所述晶体管区TD形成的所述薄膜晶体管的源极51和漏极52，在所述发光区LD形成的第三透明导电电极53和透明导线54，以及在所述外部走线区OA形成的外部走线55，如图10所示。其中所述薄膜晶体管的源极51和漏极52、外部走线55均包括层叠设置的第一金属薄膜5’和透明导电薄膜4’；第三透明导电电极53和透明导线54仅包括图案化的透明导电薄膜4’。
可选地，所述漏极52通过所述层间绝缘层13的第二过孔131与所述漏极区312连接。所述源极51通过所述层间绝缘层13的第三过孔132与所述源极区313连接，且所述源极51还通过贯穿所述层间绝缘层13以及所述缓冲层11的第四过孔111与所述遮光层21连接。所述第三透明导电电极53通过贯穿所述层间绝缘层13以及所述缓冲层11的第五过孔112与所述第一透明导电电极22连接，以形成所述存储电容2的第一极板28，所述第二透明导电电极32形成所述存储电容2的第二极板29。
S306、在所述第三金属层50上制备钝化层14，并在所述钝化层14上制备彩膜层80，所述彩膜层80对应所述发光区LD设置；
具体地，请参见图11，采用PECVD等沉积工艺在所述第三金属层50以及所述层间绝缘层13上沉积无机薄膜作为钝化层14，并在所述钝化层14上制备彩膜层80，所述彩膜层80对应所述发光区LD设置。
S307、在所述彩膜层80及所述钝化层14上制备平坦化层15，并在所述平坦化层15上制备像素电极60，所述像素电极60与所述源极51或所述漏极52连接；
具体地，请参照图12，在所述彩膜层80及所述钝化层14上涂覆有机光阻以形成平坦化层15，图案化所述平坦化层15形成第六过孔151，所述第六过孔151贯穿所述平坦化层15以及所述钝化层14，以裸露出所述源极51。
进一步地，在所述平坦化层15上沉积透明导电薄膜，例如ITO薄膜等，图案化所述透明导电薄膜形成像素电极60，所述像素电极60与所述彩膜层80对应设置，且所述像素电极60通过所述平坦化层15的第六过孔151与所述源极51连接，如图13所示。
可选地，所述像素电极60还可以和所述漏极52连接。
S308、在所述像素电极60以及所述平坦化层15上制备像素定义层16，所述像素定义层16形成有第一过孔，所述第一过孔裸露出所述像素电极60，所述发光单元3设置于所述第一过孔内，且所述发光单元3与所述彩膜层80对应设置；
具体地，请参照图14，在所述像素电极60以及所述平坦化层15上涂覆有机光阻以形成所述像素定义层16，所述有机光阻可以是PI系（聚酰亚胺）、亚克力系等有机光阻中的一种。图案化所述像素定义层16，使其在对应所述像素电极60的位置形成第一过孔161，所述第一过孔161裸露出所述像素电极60。
进一步地，请参照图15，所述发光单元3设置于所述第一过孔161内，且所述发光单元3与所述彩膜层80对应设置。所述彩膜层80包括红色彩膜、绿色彩膜、蓝色彩膜，每个发光单元3对应一种颜色的彩膜。所述发光单元3发出的白光经过红色彩膜被转换成红光、经过绿色彩膜被转换成绿光、经过蓝色彩膜被转换成蓝光，进而实现显示面板的彩色显示。
S309、在所述发光单元3以及所述像素定义层16上制备阴极70。
具体地，在所述发光单元3以及所述像素定义层16上沉积第三金属薄膜，图案化所述第三金属薄膜形成阴极70，如图4所示。所述发光单元3在所述像素电极60和所述阴极70的共同作用下发光。因本申请的显示面板为底发光，故所述阴极70可以为反射电极，以提高发光单元3的光线利用率。
可选地，所述显示面板制备方法还包括在所述阴极70上制作所封装层，所述封装层可以采用薄膜封装，所述薄膜封装可以为由第一无机封装层、有机封装层、第二无机封装层三层薄膜依次层叠形成的叠层结构或更多层的叠层结构，用于保护所述发光单元3，避免水氧入侵导致发光单元3的发光材料失效。
需要说明的是，在本申请的显示面板制备方法中，所述发光单元3的出光面朝向所述存储电容2，也即所述显示面板采用底发光，由于所述像素电极60和所述存储电容2均采用透明电极材料形成，所述发光单元3发出的光线能够穿透所述像素电极60和所述存储电容2，而且把所述存储电容2设置于出光区，减小了所述显示面板的非出光区面积，提高了显示面板的开口率。同时把像素驱动电路中的连接导线做成透明导线，并设置于发光区LD，可进一步减少所述显示面板非出光区的面积，进而进一步提高所述显示面板的开口率。
另外，本申请的显示面板制备方法不限于制备本实施例示例的显示面板，本申请的显示面板制备方法可以用于制备上述实施例中的任一显示面板。
本申请实施例还提供一种显示装置，其包括前述实施例其中之一的显示面板、绑定于所述显示面板的电路板等器件以及覆盖在所述显示面板上的盖板等。
根据上述实施例可知：
本申请提供一种显示面板及其制备方法、显示装置；该显示面板的第一金属层和第三金属层采用第一金属薄膜和透明导电薄膜的复合膜层，并使用半色调掩膜板对第一金属层和第二金属层进行黄光工艺，在形成薄膜晶体管器件的同时，在发光区形成透明的存储电容的第一极板，氧化物半导体层在形成有源区的同时，在发光区形成透明的存储电容的第二极板，使发光单元发出的光线能够穿过存储电容，提高了显示面板的开口率，增大了存储电容的存储量。而且，在形成存储电容的透明第一极板和透明第二极板的同时，在对应发光区还形成有透明导线，从而进一步提高了显示面板的开口率。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其包括多个子像素，每个所述子像素包括晶体管区和发光区，所述晶体管区设置有薄膜晶体管，所述发光区设置有存储电容和发光单元，所述发光单元位于所述存储电容上方，且所述发光单元的出光面朝向所述存储电容；所述显示面板包括：
    衬底；
    第一金属层，设置于所述衬底上，包括在所述晶体管区形成的两层结构的遮光层，在所述发光区形成的单层结构的第一透明导电电极；
    氧化物半导体层，设置于所述第一金属层上，包括在所述晶体管区形成的所述薄膜晶体管的有源区，在所述发光区形成的第二透明导电电极；
    第二金属层，设置于所述氧化物半导体层上，包括在所述晶体管区形成的所述薄膜晶体管的栅极；以及
    第三金属层，设置于所述第二金属层上，包括在所述晶体管区形成的两层结构的源极和漏极，在所述发光区形成的单层结构的第三透明导电电极；
    其中，所述第一透明导电电极和所述第三透明导电电极电连接，形成所述存储电容的第一极板，所述第二透明导电电极形成所述存储电容的第二极板。
  2. 根据权利要求1所述的显示面板，其中，所述源极、所述漏极以及所述遮光层均包括叠层设置的透明导电薄膜和第一金属薄膜，所述第一金属薄膜位于所述透明导电薄膜上。
  3. 根据权利要求2所述的显示面板，其中，所述第一透明导电电极和所述第二透明电极均包括所述透明导电薄膜。
  4. 根据权利要求3所述的显示面板，其中，在所述发光区，所述第一金属层、所述氧化物半导体层以及所述第三金属层中的至少一层还包括单层结构的透明导线，所述透明导线与所述发光单元对应设置。
  5. 根据权利要求3所述的显示面板，其中，还包括外部走线区，所述发光区位于所述晶体管区和所述外部走线区之间，所述第一金属层、所述第三金属层中的至少一层还包括在所述外部走线区形成的两层结构的外部走线。
  6. 根据权利要求2所述的显示面板，其中，所述透明导电薄膜包括铟基、锌基或钛基掺杂的透明氧化物材料形成的薄膜。
  7. 根据权利要求2所述的显示面板，其中，所述第一金属薄膜的材料包括Mo、Al、Ti、Cu中的一种或者几种的组合。
  8. 根据权利要求1所述的显示面板，其中，所述显示面板还包括层叠设置于所述第三金属层上的钝化层、平坦化层、像素电极以及像素定义层，其中所述像素定义层形成有第一过孔，所述第一过孔裸露出所述像素电极，所述发光单元设置于所述第一过孔内。
  9. 根据权利要求8所述的显示面板，其中，所述显示面板在所述钝化层和所述平坦化层之间还设置有彩膜层，所述彩膜层对应所述第一过孔设置。
  10. 根据权利要求9所述的显示面板，其中，所述彩膜层在所述衬底上的正投影覆盖所述发光单元在所述衬底上的正投影。
  11. 一种显示面板制备方法，其中，显示面板包括多个子像素，每个所述子像素包括晶体管区和发光区，所述晶体管区设置有薄膜晶体管，所述发光区设置有存储电容和发光单元，所述发光单元位于所述存储电容上方，且所述发光单元的出光面朝向所述存储电容；所述显示面板制备方法包括：
    提供衬底；
    在所述衬底上制备第一复合金属层，使用第一半色调掩膜板对所述第一复合金属层进行黄光工艺形成第一金属层，所述第一金属层包括在所述晶体管区形成的两层结构的遮光层，在所述发光区形成的单层结构的第一透明导电电极；
    在所述第一金属层上制备缓冲层，并在所述缓冲层上制备氧化物半导体薄膜，对所述氧化物半导体薄膜进行黄光工艺形成氧化物半导体层，所述氧化物半导体层包括在所述晶体管区形成的所述薄膜晶体管的有源区，在所述发光区形成的氧化物半导体图案；
    在所述氧化物半导体层上制备栅极绝缘层，并在栅极绝缘层上制备第二金属薄膜，对所述第二金属薄膜进行黄光工艺形成第二金属层，所述第二金属层包括在所述晶体管区形成的所述薄膜晶体管的栅极，并对所述氧化物半导体层进行导体化，使所述氧化物半导体图案形成第二透明导电电极；
    在所述第二金属层上制备层间绝缘层，并在所述层间绝缘层上制备第二复合金属层，使用第二半色调掩膜板对所述第二复合金属层进行黄光工艺形成第三金属层，所述第三金属层包括在所述晶体管区形成的两层结构的源极和漏极，在所述发光区形成的单层结构的第三透明导电电极，其中所述第三透明导电电极和所述第一透明导电电极电连接，以形成所述存储电容的第一极板，所述第二透明导电电极形成所述存储电容的第二极板。
  12. 根据权利要求11所述的显示面板制备方法，其中，所述在所述衬底上制备第一复合金属层，使用第一半色调掩膜板对所述第一复合金属层进行黄光工艺形成第一金属层的步骤，包括：
    在所述衬底上沉积所述第一复合金属层；
    在所述第一复合金属层涂布整面光阻；
    通过所述第一半色调掩膜板对所述光阻进行曝光、显影形成多个光阻图案，所述多个光阻图案包括在晶体管区形成的第一光阻图案，在发光区形成的第二光阻图案和第三光阻图案，在外部走线区形成的第四光阻图案；
    以所述多个光阻图案为遮挡对所述第一复合金属层进行第一次蚀刻；
    对所述多个光阻图案进行灰化处理，使所述第一光阻图案、所述第四光阻图案的厚度减薄，所述第二光阻图案、所述第三光阻图案完全被灰化掉；
    以减薄的第一光阻图案和减薄的第四光阻图案为遮挡对所述第一复合金属层进行第二次蚀刻以形成第一金属层；
    剥离掉所述减薄的第一光阻图案和所述减薄的第四光阻图案以裸露出完整的所述第一金属层。
  13. 根据权利要求11所述的显示面板制备方法，其中，所述显示面板制备方法还包括：
    在所述第三金属层上制备钝化层，并在所述钝化层上制备彩膜层，所述彩膜层对应所述发光区设置；
    在所述彩膜层及所述钝化层上制备平坦化层，并在所述平坦化层上制备像素电极，所述像素电极与所述源极或所述漏极连接；
    在所述像素电极以及所述平坦化层上制备像素定义层，所述像素定义层形成有第一过孔，所述第一过孔裸露出所述像素电极，所述发光单元设置于所述第一过孔内，且所述发光单元与所述彩膜层对应设置；
    在所述发光单元以及所述像素定义层上制备阴极。
  14. 根据权利要求11所述的显示面板制备方法，其中，所述第一复合金属层和所述第二复合金属层均包括叠层设置的透明导电薄膜和第一金属薄膜，所述第一金属薄膜位于所述透明导电薄膜上。
  15. 一种显示装置，其包括显示面板、绑定于所述显示面板的电路板、覆盖在所述显示面板上的盖板，其中所述显示面板包括多个子像素，每个所述子像素包括晶体管区和发光区，所述晶体管区设置有薄膜晶体管，所述发光区设置有存储电容和发光单元，所述发光单元位于所述存储电容上方，且所述发光单元的出光面朝向所述存储电容；所述显示面板包括：
    衬底；
    第一金属层，设置于所述衬底上，包括在所述晶体管区形成的两层结构的遮光层，在所述发光区形成的单层结构的第一透明导电电极；
    氧化物半导体层，设置于所述第一金属层上，包括在所述晶体管区形成的所述薄膜晶体管的有源区，在所述发光区形成的第二透明导电电极；
    第二金属层，设置于所述氧化物半导体层上，包括在所述晶体管区形成的所述薄膜晶体管的栅极；以及
    第三金属层，设置于所述第二金属层上，包括在所述晶体管区形成的两层结构的源极和漏极，在所述发光区形成的单层结构的第三透明导电电极；
    其中，所述第一透明导电电极和所述第三透明导电电极电连接，形成所述存储电容的第一极板，所述第二透明导电电极形成所述存储电容的第二极板。
  16. 根据权利要求15所述的显示装置，其中，所述源极、所述漏极以及所述遮光层均包括叠层设置的透明导电薄膜和第一金属薄膜，所述第一金属薄膜位于所述透明导电薄膜上。
  17. 根据权利要求16所述的显示装置，其中，所述第一透明导电电极和所述第二透明电极均包括所述透明导电薄膜。
  18. 根据权利要求17所述的显示装置，其中，在所述发光区，所述第一金属层、所述氧化物半导体层以及所述第三金属层中的至少一层还包括单层结构的透明导线，所述透明导线与所述发光单元对应设置。
  19. 根据权利要求17所述的显示装置，其中，还包括外部走线区，所述发光区位于所述晶体管区和所述外部走线区之间，所述第一金属层、所述第三金属层中的至少一层还包括在所述外部走线区形成的两层结构的外部走线。
  20. 根据权利要求16所述的显示装置，其中，所述透明导电薄膜包括铟基、锌基或钛基掺杂的透明氧化物材料形成的薄膜。
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CN110534549A (zh) * 2019-08-08 2019-12-03 深圳市华星光电半导体显示技术有限公司 阵列基板、显示面板及阵列基板的制作方法
CN110491886A (zh) * 2019-08-23 2019-11-22 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置
CN110931510A (zh) * 2019-11-26 2020-03-27 深圳市华星光电半导体显示技术有限公司 阵列基板、显示面板及阵列基板的制备方法
CN110890408A (zh) * 2019-11-28 2020-03-17 京东方科技集团股份有限公司 一种显示面板、显示装置
CN111668242A (zh) * 2020-07-02 2020-09-15 深圳市华星光电半导体显示技术有限公司 Oled显示面板及其制备方法

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