WO2022017050A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022017050A1
WO2022017050A1 PCT/CN2021/099442 CN2021099442W WO2022017050A1 WO 2022017050 A1 WO2022017050 A1 WO 2022017050A1 CN 2021099442 W CN2021099442 W CN 2021099442W WO 2022017050 A1 WO2022017050 A1 WO 2022017050A1
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region
electrode
layer
active layer
drain
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PCT/CN2021/099442
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English (en)
French (fr)
Inventor
刘宁
张大成
耿军
张沣
潘洋
周斌
闫梁臣
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Publication of WO2022017050A1 publication Critical patent/WO2022017050A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • Exemplary embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular, relate to a display substrate, a method for manufacturing the same, and a display device.
  • OLED Organic Light Emitting Diode
  • PM Passive Matrix
  • AM Active Matrix
  • TFT Thin Film Transistor
  • pixel aperture ratio is one of the important parameters, and it is also an important factor to improve the resolution of display devices, especially for bottom emission OLEDs.
  • the electrode plate of the storage capacitor needs a large area.
  • PPI high-resolution
  • a display substrate comprising a first conductive layer, a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer and a second metal layer stacked on a base;
  • the metal oxide layer includes a first an active layer
  • the second metal layer includes a first gate electrode, a first source electrode and a first drain electrode
  • the first active layer includes a channel region and source transitions located on both sides of the channel region region and drain transition region, as well as a source connection region located on the side of the source transition region away from the channel region and a drain connection region located on the side of the drain transition region away from the channel region;
  • the source connection region and the first A source electrode is connected, and the drain connection region is connected to the first drain electrode;
  • the source transition region and the drain transition region both include a first region away from the channel region and a second region adjacent to the channel region area;
  • the conductivity of the first active layer corresponding to the first area is higher than the conductivity of the first active layer corresponding to the
  • the conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to the source connection region and the drain connection region, or, the first The oxygen content of the first active layer corresponding to the region is less than the oxygen content of the first active layer corresponding to the source connection region and the drain connection region, or the thickness of the first active layer corresponding to the first region It is smaller than the thickness of the first active layer corresponding to the source connection region and the drain connection region.
  • the boundary of the orthographic projection of the first gate electrode on the substrate is located within the boundary of the orthographic projection of the second insulating layer on the substrate; the boundary of the orthographic projection of the channel region on the substrate is located at The second insulating layer is within the boundary range of the orthographic projection on the substrate.
  • the display substrate includes a plurality of sub-pixels arranged regularly, each sub-pixel includes a pixel driving circuit and an organic electroluminescent diode electrically connected to the pixel driving circuit, and the pixel driving circuit includes a storage capacitor , the storage capacitor includes a first pole plate and a second pole plate, and the orthographic projection of the first pole plate on the substrate and the orthographic projection of the second pole plate on the substrate have an overlapping area.
  • the pixel driving circuit further includes a first transistor, a second transistor and a third transistor; the gate electrode of the first transistor is coupled to the second electrode of the second transistor, and the first transistor
  • the first pole of the OLED is coupled to the first power line
  • the second pole of the first transistor is coupled to the first pole of the OLED
  • the second pole of the OLED is coupled to the second power line
  • the gate electrode of the second transistor is coupled to the first scan line
  • the first electrode of the second transistor is coupled to the data line
  • the gate electrode of the third transistor is coupled to the second scan line line
  • the first pole of the third transistor is coupled to the compensation line
  • the second pole of the third transistor is coupled to the second pole of the first transistor
  • the first pole of the storage capacitor is coupled to The gate electrode of the first transistor and the second electrode of the storage capacitor are coupled to the second electrode of the first transistor.
  • the first conductive layer includes a first plate of the storage capacitor
  • the metal oxide layer includes a second plate of the storage capacitor
  • the material of the first electrode plate includes a transparent conductive material, and the overlapping area is located in the light emitting area of the display substrate.
  • the first metal layer includes a first plate of the storage capacitor, and the metal oxide layer includes a second plate of the storage capacitor.
  • the second metal layer includes a first plate of the storage capacitor, and the metal oxide layer includes a second plate of the storage capacitor.
  • the first metal layer includes a first plate of the storage capacitor
  • the second metal layer includes a second plate of the storage capacitor
  • the conductivity of the metal oxide layer corresponding to the second electrode plate is higher than that of the first active layer corresponding to the second region, or, the conductivity of the metal oxide layer corresponding to the second electrode plate is higher than that of the first active layer corresponding to the second region.
  • the oxygen element content of the metal oxide layer is smaller than the oxygen element content of the first active layer corresponding to the second region, or the thickness of the metal oxide layer corresponding to the second electrode plate is smaller than the thickness of the metal oxide layer corresponding to the second region. Thickness of the first active layer.
  • the first metal layer includes a first power line and a first connection electrode, the first connection electrode is connected to the first electrode plate, and a transparent layer is provided between the first metal layer and the substrate A conductive thin film; the orthographic projection of the first connection electrode on the substrate and the orthographic projection of the channel region of the first active layer on the substrate have an overlapping area.
  • the first source electrode and the first drain electrode are disposed on the first insulating layer; the first drain electrode is disposed on the drain connection region of the first active layer, and passes through the first insulating layer.
  • a via hole is connected to the first connection electrode; the first end of the first source electrode is connected to the first power line through a second via hole, and the second end of the first source electrode is laid on the first source electrode on the source connection area of the active layer.
  • the first source electrode and the first drain electrode are disposed on the second insulating layer; the first drain electrode is connected to the first active layer through a first active via hole.
  • the drain connection area is connected and connected to the first connection electrode through the first via hole; the first end of the first source electrode is connected to the first power line through the second via hole, and the first end of the first source electrode is connected to the first power supply line through the second via hole.
  • the two terminals are connected to the source connection region of the first active layer through the second active via hole.
  • a display device includes the above-mentioned display substrate.
  • a preparation method of a display substrate comprising:
  • first conductive layer forming a first conductive layer, a first metal layer and a metal oxide layer in sequence on the substrate, the metal oxide layer including a first active layer;
  • a second insulating layer and a second metal layer are formed in sequence, and the first active layer forms a channel region, a source transition region and a drain transition region on both sides of the channel region, and a source connection region on the side of the source transition region away from the channel region and a drain connection region on the side of the drain transition region away from the channel region;
  • the second metal layer includes a first gate electrode, a first source electrode and a first drain electrode, the source connection region is connected to the first source electrode, the drain connection region is connected to the first drain electrode; both the source transition region and the drain transition region include a region away from the channel The first region and the second region adjacent to the channel region; the conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to the second region, or , the oxygen content of the first active layer corresponding to the first region is less than the oxygen content of the first active layer corresponding to the second region, or, the oxygen content of the first active layer corresponding to the first region The thickness is smaller than
  • the first conductive layer includes a first electrode plate
  • the metal oxide layer further includes a second electrode plate
  • the orthographic projection of the second electrode plate on the substrate is the same as that of the first electrode plate.
  • the orthographic projection of the plate on the substrate has an overlapping area.
  • a first conductive layer, a first metal layer and a metal oxide layer are sequentially formed on the substrate, including:
  • a transparent first electrode plate and a first metal layer are formed on the substrate, and a transparent conductive film is arranged between the first metal layer and the substrate;
  • the first metal layer includes a first power line and a first connection electrode, so the first connection electrode is connected to the first plate;
  • a metal oxide layer is formed on the first insulating layer, the metal oxide layer includes a first active layer and a second electrode plate, and the orthographic projection of the second electrode plate on the substrate is the same as the first electrode plate
  • the orthographic projection of the plate on the substrate has an overlapping area, and the orthographic projection of the channel region of the first active layer on the substrate and the orthographic projection of the first connection electrode on the substrate have an overlapping area.
  • a second insulating layer and a second metal layer are sequentially formed, and the first active layer is formed into a channel region and source transition regions located on both sides of the channel region through two conductorization processes. and drain transition regions, and a source connection region located on the side of the source transition region away from the channel region and a drain connection region located at the side of the drain transition region away from the channel region, including:
  • a second insulating layer is formed on the first active layer, and a first via hole and a second via hole are formed on the first insulating layer; the second insulating layer covers the middle of the first active layer area; the first via hole and the second via hole respectively expose the first connection electrode and the first power line;
  • the second electrode plate and the two side regions of the first active layer that are not covered by the second insulating layer are subjected to the first conductorization treatment to form a conductorized second electrode plate.
  • a source connection region and a drain connection region are respectively formed on both sides of the active layer;
  • the second metal layer includes a first gate electrode, a first source electrode and a first drain electrode;
  • the first gate electrode is located on the In the middle region of the first active layer, the first drain electrode is placed on the drain connection region and connected to the first connection electrode through the first via hole;
  • the terminal is connected to the first power line through the second via hole, and the second terminal of the first source electrode is laid on the source connection area;
  • the first active layer covered by the second insulating layer is subjected to a second conductorization process to form a channel region of the first active layer and source transition regions and drain transition regions located on both sides of the channel region.
  • both the source transition region and the drain transition region include a first region away from the channel region and a second region adjacent to the channel region; the first active region corresponding to the first region
  • the conductivity of the layer is higher than that of the first active layer corresponding to the second region, or the oxygen content of the first active layer corresponding to the first region is smaller than that of the first active layer corresponding to the second region.
  • the oxygen element content of the active layer, or the thickness of the first active layer corresponding to the first region is smaller than the thickness of the first active layer corresponding to the second region.
  • a second insulating layer and a second metal layer including a first gate electrode are sequentially formed, and the first active layer is formed into a channel region and located in the channel region through two conductorization processes.
  • the source transition region and the drain transition region on both sides, the source connection region located on the side of the source transition region away from the channel region, and the drain connection region located at the side of the drain transition region away from the channel region, include:
  • a second insulating layer covering the first active layer is formed, a first via hole, a second via hole, a first active via hole and a second active via hole are formed on the second insulating layer, and the second active via hole is formed on the second insulating layer.
  • the first via hole and the second via hole respectively expose the first connection electrode and the first power supply line, and the first active via hole and the second active via hole respectively expose the two parts of the first active layer. part of the area on the side;
  • the second electrode plate and the first active layer exposed in the first active via hole and the second active via hole are subjected to a first conductorization treatment to form a conductorized second electrode plate and the first active layer exposed in the second active via hole.
  • the second metal layer includes a first gate electrode, a first source electrode and a first drain electrode;
  • the first gate electrode is located on the In the middle region of the active layer, the first drain electrode is connected to the drain connection region through the second active via hole, and is connected to the first connection electrode through the first via hole;
  • a first end of a source electrode is connected to the first power line through the second via hole, and a second end of the first source electrode is connected to the source connection region through the first active via hole;
  • the second insulating layer not covered by the second metal layer is etched;
  • the first active layer covered by the second insulating layer is subjected to a second conductorization process to form a channel region of the first active layer and source transition regions and drain transition regions located on both sides of the channel region.
  • both the source transition region and the drain transition region include a first region away from the channel region and a second region adjacent to the channel region; the first active region corresponding to the first region
  • the conductivity of the layer is higher than that of the first active layer corresponding to the second region, or the oxygen content of the first active layer corresponding to the first region is smaller than that of the first active layer corresponding to the second region.
  • the oxygen element content of the active layer, or the thickness of the first active layer corresponding to the first region is smaller than the thickness of the first active layer corresponding to the second region.
  • etching the second insulating layer not covered by the second metal layer includes:
  • the second insulating layer between the first gate electrode and the first source electrode and the second insulating layer between the first gate electrode and the first drain electrode are removed by self-aligned etching.
  • FIG. 1 is a schematic structural diagram of a display unit in an OLED according to an exemplary embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of an equivalent circuit of an OLED pixel driving circuit
  • FIG. 3 is a schematic diagram of an exemplary embodiment of the present disclosure after forming a first electrode plate pattern
  • Fig. 4 is the sectional view of A-A in Fig. 3;
  • FIG. 5 is a schematic diagram of forming a metal oxide layer pattern according to an exemplary embodiment of the present disclosure
  • Fig. 6 is the sectional view of A-A in Fig. 5;
  • FIG. 7 is a schematic diagram after forming a second insulating layer pattern according to an exemplary embodiment of the present disclosure.
  • Fig. 8 is the sectional view of A-A in Fig. 7;
  • FIG. 9 is a schematic diagram of an exemplary embodiment of the present disclosure after a first conductorization process
  • FIG. 10 is a schematic diagram after forming a second metal layer pattern according to an exemplary embodiment of the present disclosure.
  • Fig. 11 is the sectional view of A-A in Fig. 10;
  • FIG. 12 is a schematic diagram after a second etching process according to an exemplary embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of an exemplary embodiment of the present disclosure after a second conductorization process
  • FIG. 14 is a schematic diagram of an exemplary embodiment of the present disclosure after a third insulating layer pattern is formed;
  • FIG. 15 is a schematic diagram after forming a color filter layer pattern according to an exemplary embodiment of the present disclosure.
  • 16 is a schematic diagram of an exemplary embodiment of the present disclosure after forming a flat layer pattern
  • FIG. 17 is a schematic diagram after forming an anode pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 18 is a schematic diagram after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 19 is another schematic diagram after forming a second insulating layer pattern according to an exemplary embodiment of the present disclosure.
  • Figure 20 is a sectional view taken along A-A in Figure 19;
  • FIG. 21 is a schematic diagram of another exemplary embodiment of the present disclosure after the first conductorization process
  • FIG. 22 is another schematic diagram after forming a second metal layer pattern according to an exemplary embodiment of the present disclosure.
  • Figure 23 is a sectional view taken along A-A in Figure 22;
  • FIG. 24 is a schematic diagram after another second etching process according to an exemplary embodiment of the present disclosure.
  • FIG. 25 is a schematic diagram after another second conductorization process according to an exemplary embodiment of the present disclosure.
  • 70 color filter layer
  • 81 anode
  • 82 pixel definition layer
  • the terms “installed”, “connected” and “connected” should be construed broadly unless otherwise expressly specified and limited. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between the drain electrode (or drain electrode terminal, drain connection region or drain electrode) and the source electrode (or source electrode terminal, source connection region or source electrode), and current can flow through the drain electrode, channel region and source electrode.
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged. Therefore, herein, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together by means of elements having some electrical function.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • the “element having a certain electrical effect” may be, for example, electrodes or wirings, or switching elements such as transistors, or other functional elements such as resistors, inductors, and capacitors.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore, also includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • amorphous silicon (a-Si) thin film transistors to metal oxide (Oxide) thin film transistors.
  • the carrier mobility of the oxide active layer is 20 to 30 times that of the amorphous silicon active layer. It has the characteristics of large mobility, high on-state current, better switching characteristics, and better uniformity, which can greatly improve thin-film transistors.
  • the characteristics of the pixel can improve the response speed of the pixel and achieve a faster refresh rate, which can be suitable for applications that require fast response and large current.
  • Oxide thin film transistors include two types, bottom-gate thin-film transistors and top-gate thin-film transistors.
  • the structural characteristics of bottom-gate thin-film transistors are that the source and drain electrodes are covered on both sides of the oxide active layer, respectively.
  • a channel region is formed between the source electrode and the drain electrode.
  • the structure of the top-gate thin film transistor is characterized in that the source electrode and the drain electrode are respectively connected to the oxide active layer through via holes. Since the top-gate thin film transistor has a short channel, the on-state current (Ion) can be effectively improved, so the display effect can be significantly improved and power consumption can be effectively reduced.
  • the generated parasitic capacitance is small, the circuit delay is small and the switching speed is high, so the gate-drain short circuit (GDS) occurs. ) is less likely to be defective.
  • FIG. 1 is a schematic structural diagram of a display unit in an OLED according to an exemplary embodiment of the disclosure, and the OLED is a bottom emission type. As shown in FIG.
  • each display unit in a plane parallel to the display substrate, includes a light-emitting structure area and a driving circuit area, the light-emitting structure area is provided with a light-emitting structure, the light-emitting structure is configured to emit light, and the driving circuit area is provided with a pixel driving circuit,
  • the pixel driving circuit is configured to drive the light emitting structure, and the pixel driving circuit may include a plurality of thin film transistors and a storage capacitor.
  • the driving circuit area may include a circuit area and a capacitor area, a plurality of thin film transistors for driving the light emitting structure are disposed in the circuit area, an electrode plate of a storage capacitor is disposed in the capacitor area, an electrode plate of the storage capacitor and a plurality of thin films The transistors are arranged side by side.
  • the storage capacitor is a transparent capacitor structure, and a transparent conductive layer and a conductive metal oxide are used as two electrode plates of the storage capacitor.
  • the light-emitting structure region and the capacitor region together constitute a light-emitting region, which can not only ensure the capacity of the storage capacitor, but also improve the pixel aperture ratio.
  • the pixel driving circuit may adopt a driving structure such as 3T1C, 4T1C, 5T1C, 6T1C, or 7T1C, which is not limited in the present disclosure.
  • FIG. 2 is a schematic diagram of an equivalent circuit of an OLED pixel driving circuit, illustrating a 3T1C driving structure.
  • the pixel driving circuit is electrically connected to the first scan line GN, the second scan line SN, the data line DN, the first power supply line VDD and the compensation line SE, and the pixel driving circuit includes a first transistor T1, a second transistor T2, the third transistor T3 and the storage capacitor C ST .
  • the first transistor T1 is a driving transistor
  • the second transistor T2 is a switching transistor
  • the third transistor T3 is a compensation transistor.
  • the gate electrode of the first transistor T1 is connected to the second electrode of the second transistor T2 and the first electrode of the storage capacitor C ST , the first electrode of the first transistor T1 is connected to the first power supply line VDD, the first The second electrode of the transistor T1 is connected to the second electrode of the storage capacitor C ST and the second electrode of the third transistor T3 .
  • the gate electrode of the second transistor T2 is connected to the scan line GN, the first electrode of the second transistor T2 is connected to the data line DN; the gate electrode of the third transistor T3 is connected to the second scan line SN, and the first electrode of the third transistor T3 is connected to the compensation line SE.
  • the anode of the OLED is connected to the second pole of the first transistor T1
  • the cathode of the OLED is connected to the second power line VSS
  • the OLED is configured to emit light with corresponding brightness in response to the current of the second pole of the first transistor T1.
  • the third transistor T3 can extract the threshold voltage Vth and the mobility of the first transistor T1 in response to the timing of compensation to compensate for the threshold voltage Vth
  • the storage capacitor C ST is configured to maintain a light-emitting period of one frame Internal N1 node and N2 node voltage.
  • the display substrate of the bottom emission type top gate structure includes a stacked first conductive layer, a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer and a second metal layer;
  • the metal oxide layer includes a first active layer
  • the second metal layer includes a first gate electrode, a first source electrode and a first drain electrode;
  • the first active layer includes a channel region, located in A source transition region and a drain transition region on both sides of the channel region, a source connection region on the side of the source transition region away from the channel region, and a drain connection region on the side of the drain transition region away from the channel region ;
  • the source connection region is connected to the first source electrode, and the drain connection region is connected to the first drain electrode;
  • the source transition region and the drain transition region both include a first region away from the channel region and a second region adjacent to the channel region;
  • the conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to
  • the conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to the source connection region and the drain connection region, or, the first The oxygen content of the first active layer corresponding to the region is less than the oxygen content of the first active layer corresponding to the source connection region and the drain connection region, or the thickness of the first active layer corresponding to the first region It is smaller than the thickness of the first active layer corresponding to the source connection region and the drain connection region.
  • the boundary of the orthographic projection of the first gate electrode on the substrate is located within the boundary of the orthographic projection of the second insulating layer on the substrate; the boundary of the orthographic projection of the channel region on the substrate is located at The second insulating layer is within the boundary range of the orthographic projection on the substrate.
  • the first conductive layer includes a first electrode plate disposed on a substrate
  • the metal oxide layer includes a second electrode plate that has undergone two conductorization treatments
  • the second electrode plate is The orthographic projection on the substrate and the orthographic projection of the first electrode plate on the substrate have an overlapping area.
  • the material of the first electrode plate includes a transparent conductive material, and the overlapping area is located in the light emitting area of the display substrate.
  • the first metal layer includes a first power line and a first connection electrode, the first connection electrode is connected to the first electrode plate, and a transparent layer is provided between the first metal layer and the substrate A conductive thin film; the orthographic projection of the first connection electrode on the substrate and the orthographic projection of the channel region of the first active layer on the substrate have an overlapping area.
  • the first source electrode and the first drain electrode are disposed on the first insulating layer; the first drain electrode is disposed on the drain connection region of the first active layer, and It is connected to the first connection electrode through a first via hole; the first end of the first source electrode is connected to the first power line through a second via hole, and the second end of the first source electrode is placed on the on the source connection region of the first active layer.
  • the first source electrode and the first drain electrode are disposed on the second insulating layer; the first drain electrode is connected to the first active layer through a first active via hole.
  • the drain connection area is connected and connected to the first connection electrode through the first via hole; the first end of the first source electrode is connected to the first power line through the second via hole, and the first end of the first source electrode is connected to the first power supply line through the second via hole.
  • the two terminals are connected to the source connection region of the first active layer through the second active via hole.
  • the source transition region of the first active layer is located between the first gate electrode and the first source electrode, and the drain transition region of the first active layer is located at the first gate between the electrode and the first drain electrode.
  • each sub-pixel includes a light-emitting region and a circuit region, a plurality of transistors in the pixel driving circuit are arranged in the circuit region, and the orthographic projection of the storage capacitor in the pixel driving circuit on the substrate is the same as the There are overlapping areas of the light emitting areas.
  • the source connection region and the drain connection region of the first active layer are formed through a first conductorization process, and the channel region of the first active layer is formed through a self-aligned second conductorization process formed in.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process” mentioned in this disclosure includes photoresist coating, mask exposure, development, etching, stripping photoresist and other treatments, for organic materials, including Processes such as coating organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spraying, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings are not limited in the present disclosure.
  • “Film” refers to a thin film made of a material on a substrate by deposition, coating or other processes.
  • the "thin film” may also be referred to as a "layer”. If the "thin film” needs a patterning process in the whole manufacturing process, it is called a "thin film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A is the same as the boundary of the orthographic projection of B.
  • the projected boundaries overlap.
  • the manufacturing process of the display substrate may include the following operations, as shown in FIGS. 3 to 18 .
  • forming the pattern of the first electrode plate and the first metal layer may include: sequentially depositing a first transparent conductive film and a first metal film on a substrate, and applying a halftone patterning process to the first transparent conductive film Patterning with the first metal film, forming a first electrode plate 61 and a first metal layer pattern on the substrate 10, the first metal layer pattern at least includes the first power supply line VDD, data line DN, compensation line SE, first connection electrode 51 and the second connection electrode 52, the first connection electrode 51 is connected with the first electrode plate 61, as shown in FIG. 3 and FIG. 4, FIG.
  • patterning the first transparent conductive film and the first metal film through a halftone patterning process may include: firstly coating a layer of photoresist on the first metal film, and using a halftone mask The plate (Halftone Mask) exposes the photoresist, and after developing, a photoresist pattern is formed.
  • the photoresist pattern includes an unexposed area, a partially exposed area and a fully exposed area, and the unexposed area includes the first power line VDD, data line DN , where the compensation line SE, the pattern of the first connection electrode 51 and the second connection electrode 52 are located, the photoresist in the unexposed area has a first thickness.
  • the partially exposed area includes the position where the first electrode plate 61 is located, and the photoresist in the partially exposed area has a second thickness, and the second thickness is smaller than the first thickness.
  • the other areas are fully exposed areas, and the photoresist in the fully exposed areas is completely removed to expose the surface of the first metal film.
  • the first transparent conductive film and the first metal film in the fully exposed area are removed by a first etching process.
  • an ashing process is used to remove the photoresist in the partially exposed area, so that the surface of the first metal thin film is exposed in the partially exposed area.
  • a second etching process is used to remove the first metal film in the partially exposed area, and the first transparent conductive film in the partially exposed area is exposed.
  • the remaining photoresist is peeled off to form a first electrode plate and a first metal layer pattern on the substrate.
  • a transparent conductive film remains under the first metal layer (the first power line VDD, the data line DN, the compensation line SE, the first connection electrode 51 and the second connection electrode 52 ).
  • the first power supply line VDD, the data line DN and the compensation line SE are parallel to each other and extend in a vertical direction, the first power supply line VDD is provided on one side of the sub-pixel, and the data line DN and the compensation line SE are provided on the other side of the subpixel.
  • the first power supply line VDD is configured to provide a power supply signal to the first source electrode of the first transistor
  • the data line DN is configured to provide a data line number to the second source electrode of the second transistor
  • the compensation line SE is configured to supply the first source electrode of the third transistor.
  • Three source electrodes provide compensation signals.
  • the first plate 61 is configured to form a storage capacitor with the second plate in a subsequently formed metal oxide layer.
  • the first connection electrode 51 is connected to the first electrode plate 61 .
  • the first connection electrode 51 is configured to connect the first drain electrode of the first transistor and the third drain electrode of the third transistor to be formed later, so as to realize the first electrode plate 61 .
  • the connection with the first drain electrode and the third drain electrode acts as a shielding layer for the first transistor T1.
  • the second connection electrode 52 is configured to connect the third gate electrode of the third transistor to be formed later.
  • the thickness of the first transparent conductive film is about 40nm-150nm, and the thickness of the first metal film is about 100nm-1000nm.
  • the first electrode plate of the first conductive layer may be configured to form a storage capacitor with the second metal layer formed subsequently.
  • the first electrode plate of the first conductive layer may be configured to form a storage capacitor with a subsequently formed pixel electrode, and the pixel electrode and the anode are disposed in the same layer and formed by the same patterning process.
  • the first electrode plate may be disposed on the first metal layer, and the first electrode plate of the first metal layer is configured to form a storage capacitor with the second metal layer formed subsequently, or the first metal layer The first electrode plate is configured to form a storage capacitor with the pixel electrode formed subsequently.
  • forming the metal oxide layer pattern may include: sequentially depositing a first insulating film and a metal oxide film on the substrate on which the aforementioned pattern is formed, and patterning the metal oxide film through a patterning process to form a cover
  • the pattern of the diode plate 62 is shown in FIG. 5 and FIG. 6 , and FIG. 6 is a cross-sectional view taken along the AA direction in FIG. 5 .
  • the first active layer 12 serves as the active layer of the driving TFT (the first transistor T1 ), and the first active layer 12 is orthographically projected on the substrate with the first connection electrode 51 on the substrate
  • the second active layer 22 serves as the active layer of the switching TFT (the second transistor T2)
  • the second active layer 22 is connected to the second plate 62
  • the third active layer 32 serves as the compensation TFT ( In the active layer of the third transistor T3)
  • the position of the second electrode plate 62 corresponds to the position of the first electrode plate 61, that is, the orthographic projection of the second electrode plate 62 on the substrate is the same as that of the first electrode plate 61 on the substrate.
  • the orthographic projections overlap, so that the first electrode plate 61 and the second electrode plate 62 form a storage capacitor with a transparent structure.
  • the orthographic projection of the second polar plate 62 on the substrate is within the range of the orthographic projection of the first polar plate 61 on the substrate.
  • the metal oxide layer may employ oxides including indium and tin, oxides including tungsten and indium, oxides including tungsten and indium and zinc, oxides including titanium and indium, oxides including titanium and Oxides of indium and tin, oxides containing indium and zinc, oxides containing silicon and indium and tin, oxides containing indium and gallium and zinc, and the like.
  • the metal oxide layer may be transparent indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO).
  • the thickness of the first insulating film is about 200 nm ⁇ 1000 nm, and the thickness of the metal oxide film is about 20 nm ⁇ 200 nm.
  • the second electrode plate in the metal oxide layer may be configured to form a storage capacitor with a subsequently formed second metal layer, or may be configured to form a storage capacitor with a subsequently formed pixel electrode, or may be configured For forming a storage capacitor with the first metal layer.
  • a second insulating layer pattern is formed.
  • forming the second insulating layer pattern may include: depositing a second insulating film on the substrate on which the foregoing pattern is formed, and patterning the second insulating film through a halftone patterning process to form the second insulating layer 42 pattern and a plurality of via patterns opened on the first insulating layer 41, the second insulating layer 42 pattern is located at the positions of the first active layer 12, the second active layer 22 and the third active layer 32, and a plurality of The via pattern includes at least a first via hole K1, a second via hole K2, a third via hole K3, a fourth via hole K4, a fifth via hole K5 and a sixth via hole K6, as shown in FIG. 7 and FIG. 8 , FIG. 8 is a cross-sectional view taken along the line AA in FIG. 7 .
  • the patterning of the second insulating film by a halftone patterning process may include: firstly coating a layer of photoresist on the second insulating film, and using a halftone mask to pattern the photoresist Expose and develop a photoresist pattern, the photoresist pattern includes an unexposed area, a partially exposed area and a fully exposed area, and the unexposed area includes the first active layer 12, the second active layer 22 and the third active layer At 32, the photoresist in the unexposed areas has a first thickness.
  • the fully exposed area includes the position of the via hole pattern, and the photoresist in the fully exposed area is completely removed to expose the surface of the second insulating film.
  • the other areas are partially exposed areas, and the photoresist in the partially exposed areas has a second thickness, and the second thickness is smaller than the first thickness.
  • a first etching process is used to remove the second insulating film and the first insulating layer 41 in the fully exposed area to form a plurality of via patterns.
  • an ashing process is used to remove the photoresist in the partially exposed area, so that the second insulating film is exposed in the partially exposed area.
  • a second etching process is used to remove the second insulating film in the partially exposed area.
  • the remaining photoresist is stripped to form a pattern of the second insulating layer 42 and a plurality of via patterns opened on the first insulating layer 41 .
  • the plurality of via patterns include at least a first via K1 , a second via K2 , a third via K3 , a fourth via K4 , a fifth via K5 and a sixth via K6 .
  • the first via hole K1 is located at the position of the first connection electrode 51 , exposing the surface of the first connection electrode 51 , and the first via hole K1 is configured to make the first drain electrode of the first transistor and the third drain electrode of the third transistor formed subsequently.
  • the drain electrode is connected to the first connection electrode 51 to realize the connection between the first electrode plate 61 and the first drain electrode and the third drain electrode.
  • the second via hole K2 is located at the position of the first power supply line VDD, exposing the surface of the first power supply line VDD, and the second via hole K2 is configured to connect the first source electrode of the subsequently formed first transistor to the first power supply line VDD .
  • the third via hole K3 and the fourth via hole K4 are located at two ends of the second connection electrode 52 respectively, exposing the surface of the second connection electrode 52 , and the third via hole K3 and the fourth via hole K4 are respectively configured to connect the subsequently formed
  • the second scan line SN and the third gate electrode of the third transistor realize the connection between the second scan line SN and the third gate electrode.
  • the fifth via hole K5 is located at the position of the data line DN, exposing the surface of the data line DN, and the fifth via hole K5 is configured to connect the second source electrode of the second transistor formed subsequently, so as to realize the connection between the data line DN and the second source electrode. connect.
  • the sixth via hole K6 is located at the position of the compensation line SE, exposing the surface of the compensation line SE, and the sixth via hole K6 is configured to connect the third source electrode of the third transistor formed subsequently, so as to realize the connection between the compensation line SE and the third source electrode. connect.
  • the second insulating layer 42 where the second electrode plate 62 is located is removed to expose the second electrode plate 62 .
  • the second insulating layer 42 located at the positions of the first active layer 12 , the second active layer 22 and the third active layer 32 respectively covers part of the first active layer 12 , the second Part of the active layer 22 and part of the third active layer 32 .
  • the second insulating layer 42 located at the position of the first active layer 12 covers the middle region of the first active layer 12 , and the covering width is larger than the design width of the channel region of the first active layer 12 , and is not covered by the second insulating layer 42 .
  • the covered two side regions expose the surface of the first active layer 12 .
  • the second insulating layer 42 located at the position of the second active layer 22 covers the middle region of the second active layer 22, and the covering width is larger than the design width of the channel region of the second active layer 22, and is not covered by the second insulating layer 42.
  • the covered two side regions expose the surface of the second active layer 22 .
  • the second insulating layer 42 located at the position of the third active layer 32 covers the middle region of the third active layer 32, and the covering width is larger than the design width of the channel region of the third active layer 32, and is not covered by the second insulating layer 42.
  • the covered two side regions expose the surface of the third active layer 32 . In this way, when the first conductive process is performed subsequently, the first active layer 12 , the second active layer 22 and the third active layer 32 can all form a wider channel region.
  • the thickness of the second insulating film is about 100 nm ⁇ 500 nm.
  • the first conductorization process may include: on the substrate on which the aforementioned pattern is formed, the first active layer 12 , the second active layer 22 and the third active layer 32 are not second insulated The regions on both sides covered by the layer 42 and the second electrode plate 62 are subjected to conductorization treatment to form a conductorized second electrode plate 62 .
  • the first active layer 12 , the second active layer 22 and the third active layer 32 are The middle region covered by the second insulating layer 42 forms the channel region, and the regions on both sides not covered by the second insulating layer 42 are processed into conductive regions 12 ′.
  • the source and drain connection regions, the source and drain connection regions of the second active layer 22 and the source and drain connection regions of the third active layer 32 are shown in FIG. 9 .
  • Forming a second metal layer pattern may include depositing a second metal thin film on the substrate formed with the aforementioned pattern. A layer of photoresist is coated on the second metal film, a photoresist pattern is formed by masking, exposing and developing, and the second metal film is etched by the first etching process to form a second metal layer pattern, and the first Photoresist 100 on the two metal layers.
  • the second metal layer pattern includes at least a first scan line GN, a second scan line SN, a first gate electrode 11, a second gate electrode 21, a third gate electrode 31, a first source electrode 13, a first drain electrode 14, a
  • the patterns of the two source electrodes 23 , the second drain electrodes 24 , the third source electrodes 33 and the third drain electrodes 34 are shown in FIGS. 10 and 11 , and FIG. 11 is a cross-sectional view taken along the AA direction in FIG. 10 .
  • the first scan line GN and the second scan line SN are parallel to each other, extend in the horizontal direction, and are both disposed on the lower side of the sub-pixels.
  • the first scan line GN may be a switch scan line configured to provide an on/off signal for controlling the second transistor to the second gate electrode of the second transistor
  • the second scan line SN may be a compensation scan line configured to provide the third transistor with an on/off signal.
  • the third gate electrode of SN provides an on/off signal for controlling the third transistor
  • the second scan line SN is connected to the second connection electrode 52 through the fourth via hole K4.
  • the first gate electrode 11 is an integral structure interconnected with the second drain electrode 24
  • the second gate electrode 21 is an integral structure interconnected with the first scan line GN
  • the third gate electrode 31 is interconnected through the The three via holes K3 are connected to the second connection electrode 52 , and since the second connection electrode 52 is connected to the second scan line SN through the fourth via hole K4 , the third gate electrode 31 is connected to the second scan line through the second connection electrode 52 . SN connection.
  • the first end of the first source electrode 13 is connected to the first power supply line VDD through the second via hole K2 , and the second end is placed on the source connection region of the first active layer 12 that has undergone conductive processing.
  • the first source electrode 13 connected to the first power supply line VDD is formed.
  • the first end of the first drain electrode 14 is placed on the conductive drain connection region of the first active layer 12, and is connected to the first connection electrode 51 through the first via K1 to realize the connection between the first drain electrode 14 and the first connection electrode 51.
  • the second end of the first drain electrode 14 is placed on the drain connection region of the third active layer 32 after conducting treatment to form the first drain electrode 14 and the third drain electrode 34 in an integrated structure.
  • the first end of the second source electrode 23 is connected to the data line DN through the fifth via hole K5 , and the second end is placed on the source connection region of the second active layer 22 that has undergone conduction treatment to form The second source electrode 23 connected to the data line DN.
  • the first end of the second drain electrode 24 is placed on the drain connection region of the second active layer 22 that has undergone the conducting treatment, and the second end is placed on the channel region of the second active layer 22 that has not undergone the conducting treatment.
  • the second drain electrode 24 and the first gate electrode 11 are integrally formed, and the connection between the second drain electrode 24 and the second electrode plate 62 is realized.
  • the first end of the third source electrode 33 is connected to the compensation line SE through the sixth via hole K6, and the second end is placed on the source connection region of the third active layer 32 that has undergone conduction treatment to form The third source electrode 33 connected to the compensation line SE.
  • the third drain electrode 34 is disposed on the drain connection region of the third active layer 32 that has undergone the conductorization treatment, and is an integral structure connected with the first drain electrode 14 .
  • the first gate electrode 11, the first active layer 12, the first source electrode 13 and the first drain electrode 14 constitute the first transistor T1
  • the second source electrode 23 and the second drain electrode 24 constitute the second transistor T2
  • the third gate electrode 31, the third active layer 32, the third source electrode 33 and the third drain electrode 34 constitute the second transistor T2
  • the plate 61 and the conductive second plate 62 constitute a storage capacitor of a transparent structure.
  • the thickness of the second metal thin film is about 100 nm ⁇ 1000 nm.
  • the second metal layer may form a capacitor plate, may be configured to form a storage capacitor with the first conductive layer, or may be configured to form a storage capacitor with the first metal layer, or may be configured to form a storage capacitor with the metal oxide
  • the material layer forms a storage capacitor, or can be configured to form a storage capacitor with a subsequently formed pixel electrode.
  • the second etching process may include: using the second metal layer pattern and the photoresist 100 remaining on the second metal layer as masks, performing self-alignment through the second etching process
  • the second insulating layer 42 is etched below, and the second insulating layer 42 that is not covered by the second metal layer pattern on the first active layer 12, the second active layer 22 and the third active layer 32 is removed, as shown in FIG. 12 . Show.
  • the widths of the first gate electrode 11 , the second gate electrode 21 and the third gate electrode 31 are very small, about 6 ⁇ m ⁇ 10 ⁇ m, the width of the second insulating layer 42 that is finally retained is the same as the width of the first gate electrode 11 , the second gate electrode 21 and the third gate electrode 31
  • the widths of the two metal layers are close, and the widths of the second insulating layers 42 on the first active layer 12 , the second active layer 22 and the third active layer 32 are close to the design widths of the corresponding active layer channel regions.
  • the boundary of the orthographic projection of the first gate electrode 11 on the substrate is located within the boundary of the orthographic projection of the second insulating layer 42 on the substrate, and the boundary of the orthographic projection of the active layer channel region on the substrate is located in the first The two insulating layers 42 are within the boundary range of the orthographic projection on the substrate.
  • the second conductorization process may include: a second insulating layer 42, a second metal layer pattern disposed on the second insulating layer 42, and a photoresist 100 remaining on the second metal layer
  • the first active layer 12, the second active layer 22 and the third active layer 32 are subjected to the second conductorization treatment, and the second electrode plate 62 is simultaneously subjected to the second conductorization treatment to form the corresponding The channel region of the active layer and the second electrode plate 62 made of secondary conductors are stripped of the remaining photoresist, as shown in FIG. 13 .
  • the width of the finally formed channel is respectively the same as that of the first conductor.
  • the widths of the first gate electrode 11, the second gate electrode 21 and the third gate electrode 31 are substantially the same.
  • the orthographic projection of the channel region of the first active layer 12 on the substrate overlaps with the orthographic projection of the first connection electrode 51 on the substrate, so that the first connection electrode 51 shields the channel region of the first active layer 12 .
  • the exemplary embodiment of the present disclosure greatly improves the alignment accuracy between the gate electrode and the underlying channel region through the self-aligned conductorization process, and greatly improves the electrical characteristics of the thin film transistor.
  • the first active layer undergoes two conductorization processes, so that the first active layer forms three regions: a channel region in the middle, a source transition region and a drain transition on both sides of the channel region region, a source connection region located on the side of the source transition region away from the channel region, and a drain connection region located on the side of the drain transition region away from the channel region.
  • the boundary of the orthographic projection of the channel region on the substrate substantially overlaps with the boundary of the orthographic projection of the first gate electrode on the substrate, the source connection region is connected to the first source electrode and is covered by the first source electrode, and the drain connection region is connected to the first leakage current electrode connection, covered by the first drain electrode, the source transition region is located between the channel region and the source connection region, that is, the region between the first gate electrode and the first source electrode, the drain transition region is located between the channel region and the drain connection between the regions, that is, the region between the first gate electrode and the first drain electrode.
  • the second active layer and the third active layer also form three regions.
  • the region of the first conductorization treatment overlaps with the region of the second conductorization treatment (as shown by the black area in Figure 13), so both the source transition region and the drain transition region contain
  • the first region 12A that has undergone two conductorization treatments and the second region 12B that has undergone only the second conductorization treatment the first region 12A is far away from the channel region, and the second region 12B is adjacent to the channel region.
  • the first region 12A that has undergone two conductorization treatments is subjected to two helium (He) plasma treatments, the oxygen content in the film layer is further reduced, and the oxygen content of the first active layer corresponding to the first region 12A is further reduced.
  • He helium
  • the element content is less than the oxygen element content of the first active layer corresponding to the second region 12B, which is beneficial to improve the electrical characteristics of the thin film transistor.
  • the resistance of the first region 12A that has undergone two conductorization treatments is lower and the conductivity is stronger, and the conductivity of the first active layer corresponding to the first region 12A is higher than that of the second region 12B.
  • the conductivity of the first active layer is beneficial to improve the electrical characteristics of the thin film transistor.
  • the oxygen element content of the first active layer corresponding to the first region 12A is smaller than the oxygen element content of the first active layer corresponding to the second region 12B, and the first active layer corresponding to the first region 12A
  • the conductivity of the layer is higher than that of the first active layer corresponding to the second region 12B. Since the source connection region and the drain connection region are only subjected to the first conductorization process, the conductivity of the first active layer corresponding to the first region 12A is higher than that of the first active layer corresponding to the source connection region and the drain connection region.
  • the oxygen content of the first active layer corresponding to the first region 12A is lower than the oxygen content of the first active layer corresponding to the source connection region and the drain connection region.
  • the conductivity of the second electrode plate 62 is improved, which is beneficial to improve the driving characteristics of the pixel driving circuit.
  • the conductivity of the metal oxide layer corresponding to the second electrode plate 62 is higher than the conductivity of the first active layer corresponding to the second region 12B, or, the metal oxide layer corresponding to the second electrode plate 62
  • the oxygen element content of the layer is smaller than that of the first active layer corresponding to the second region 12B.
  • the second insulating layer is etched twice, and the over-etching of the etching process will etch away part of the thickness of the first active layer 12 , so the first The thickness of the first active layer corresponding to the region 12A becomes thinner, the thickness of the first active layer corresponding to the first region 12A is smaller than the thickness of the first active layer corresponding to the second region 12B, and the thickness of the first active layer corresponding to the first region 12A
  • the thickness of the active layer is smaller than the thickness of the first active layer corresponding to the source connection region and the drain connection region, the thickness of the first active layer corresponding to the first region 12A is smaller than the thickness of the first active layer corresponding to the channel region, Conducive to improving the conductivity effect.
  • the thickness of the metal oxide layer corresponding to the second electrode plate 62 is smaller than the thickness of the first active layer corresponding to the second region 12B.
  • a third insulating layer pattern is formed.
  • forming the third insulating layer pattern may include: depositing a third insulating film on the substrate formed with the foregoing pattern to form a third insulating layer 43 covering the foregoing structure, as shown in FIG. 14 .
  • the thickness of the third insulating film is about 200 nm ⁇ 1000 nm.
  • forming the color filter layer pattern may include: on the substrate formed with the foregoing pattern, sequentially forming a first color unit, a second color unit and a third color unit through a patterning process to form a color filter layer 70, as shown in Figure 15.
  • the color filter layer 70 is formed in the light emitting area and the capacitance area
  • the first color unit may be a green unit
  • the second color unit may be a red unit
  • the third color unit may be a blue unit.
  • the color filter layer 70 may include other color units, such as white or yellow.
  • a flat layer pattern is formed.
  • forming the flat layer pattern may include: coating a flat film on the substrate formed with the foregoing pattern, using the flat film as a photoresist, after masking, exposing and developing, applying a third insulating layer
  • the layer 43 is etched to form a flat layer 44 covering the aforementioned structure.
  • a seventh via hole K7 is formed on the flat layer 44.
  • the seventh via hole K7 is located at the position of the first drain electrode 14, and the flat layer in the seventh via hole K7 is formed. 44 and the third insulating layer 43 are removed, exposing the surface of the first drain electrode 14, as shown in FIG. 16 .
  • An anode pattern is formed.
  • forming the anode pattern may include: depositing a second transparent conductive film on the substrate on which the aforementioned pattern is formed, patterning the second transparent conductive film through a patterning process to form an anode 81 pattern, and the anode 81 passes through the first transparent conductive film.
  • the seven via holes K7 are connected to the first drain electrode 14 , as shown in FIG. 17 .
  • anode 81 is a transparent anode.
  • a pixel definition layer pattern is formed.
  • forming a pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, and forming a pixel definition layer (Pixel Define Layer) 82 pattern through masking, exposing and developing processes, and the pixel definition layer Layer 82 defines an open area exposing anode 81 as shown in FIG. 18 .
  • Patterns such as an organic light-emitting layer, a cathode, and an encapsulation layer are formed, and the preparation method is the same as that of the related art, which will not be repeated here.
  • the cathode is a reflective cathode.
  • the organic light-emitting layer may include a first light-emitting sublayer, a first charge-generating layer, a second light-emitting sublayer, a second charge-generating layer, and a third light-emitting sublayer, which are sequentially stacked.
  • the first light-emitting sub-layer is configured to emit light of a first color, and includes a first hole transport layer (HTL), a first light-emitting material layer (EML) and a first electron transport layer (ETL) stacked in sequence.
  • the second light-emitting sub-layer is configured to emit light of the second color, and includes a second hole transport layer, a second light-emitting material layer, and a second electron transport layer that are stacked in sequence.
  • the third light-emitting sub-layer is configured to emit light of a third color, and includes a third hole transport layer, a third light-emitting material layer and a third electron transport layer stacked in sequence.
  • the first charge generation layer is disposed between the first light-emitting sublayer and the second light-emitting sublayer, and is configured to connect the two light-emitting sublayers in series to realize carrier transfer.
  • the second charge generation layer is disposed between the second light-emitting sublayer and the third light-emitting sublayer, and is configured to connect the two light-emitting sublayers in series to realize carrier transfer.
  • the organic light-emitting layer includes the first light-emitting material layer that emits light of the first color, the second light-emitting material layer that emits light of the second color, and the third light-emitting material layer that emits light of the third color
  • the light finally emitted from the organic light-emitting layer is mixed light.
  • the first light-emitting material layer can be set to be a red light-emitting material layer that emits red light
  • the second light-emitting material layer is a green light-emitting material layer that emits green light
  • the third light-emitting material layer is a blue light material layer that emits blue light.
  • the layers eventually emit white light.
  • the structure of the organic light-emitting layer can be designed according to actual needs.
  • a hole injection layer (HIL) and an electron injection layer (EIL) may be provided in each light-emitting sublayer.
  • the first electron transport layer, the first charge generation layer and the second hole transport layer can be eliminated, that is, the second light-emitting material layer can be directly disposed on the first light-emitting material layer.
  • the first insulating layer, the second insulating layer and the third insulating layer may adopt any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON). species, which can be single-layer, multi-layer or composite.
  • the first insulating layer is called a buffer layer and is configured to improve the water and oxygen resistance of the substrate
  • the second insulating layer is called a gate insulating (GI) layer
  • the third insulating layer is called a passivation (PVX) layer.
  • the first metal film and the second metal film can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or the above Metal alloy materials, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti and the like.
  • the first transparent conductive film and the second transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the display substrate formed by the foregoing preparation process may include:
  • the orthographic projection overlaps with the orthographic projection of the first polar plate 61 on the substrate 10 to form a transparent storage capacitor;
  • the first active layer 12 includes three regions: a channel region in the middle, and two sides of the channel region.
  • the source transition region and the drain transition region of the The orthographic projection on the substrate 10 overlaps with the orthographic projection of the first connection electrode 51 on the substrate 10;
  • the first source electrode 13 and the first drain electrode 14 are arranged on the first insulating layer 41.
  • the first end of the first source electrode 13 is connected to the first power supply line VDD through the second via K2.
  • the second end is placed on the source connection region of the first active layer 12 ;
  • the first drain electrode 14 is placed on the drain connection region of the first active layer 12 and is connected to the first connection electrode 51 through the first via K1 ;
  • the flat layer 44 is provided with a seventh via hole K7 exposing the first drain electrode 14;
  • the anode 81 disposed on the flat layer 44 is connected to the first drain electrode 14 through the seventh via K7.
  • the display substrate may further include a pixel definition layer, an organic light emitting layer, a cathode and an encapsulation layer, and the like.
  • the source transition region of the first active layer 12 is located between the first gate electrode 11 and the first source electrode 13
  • the drain transition region of the first active layer 12 is located between the first gate electrode 11 and the first source electrode 13 .
  • the source transition region and the second insulating layer 42 of the drain transition region are removed by self-aligned etching.
  • the source connection region and the drain connection region of the first active layer 12 are formed by the first conductive process, and the channel region of the first active layer 12 is formed by the self-aligned second conductive process. formed during processing.
  • a pixel circuit layer of a display substrate with a transparent capacitance structure includes a shielding layer, a transparent conductive layer, a buffer layer, a semiconductor layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer and a source-drain metal layer, which requires six patterning processes , the patterning process is many times, the process flow is complex, the production cost is high, and the production capacity is low.
  • the first conductive layer and the first metal layer are formed by the same patterning process, and the gate electrode, the source electrode and the drain electrode are arranged in the same layer and are patterned by the same time
  • Process formation requires only four patterning processes, which minimizes the number of patterning processes.
  • the exemplary method for preparing a display substrate of the present disclosure reduces the number of patterning processes, shortens the process time, reduces the process cost, has good process compatibility, high process achievability, strong practicability, is very mass-producible, and has good application prospects.
  • conducting treatment is performed after the second insulating layer is formed and before the second metal layer is formed to form a channel region with a fixed position and length.
  • the gate electrode pattern is subsequently formed, due to the limitation of the alignment accuracy of the patterning process, the position of the gate electrode is easily deviated from the position of the channel region, and it is difficult to align the gate electrode directly above the channel region, and the gate electrode and the channel are difficult to be aligned.
  • Area alignment accuracy is low. The deviation of the alignment between the gate electrode and the channel region will reduce the electrical characteristics of the thin film transistor, resulting in an increase in turn-on voltage and a decrease in current, which affects product performance.
  • the exemplary embodiment of the present disclosure proposes a scheme of conducting two conductorization treatments.
  • the first conductorization treatment is to form a wider channel region through the first conductorization treatment before forming the second metal layer, and the second conductorization treatment is performed to form a wider channel region.
  • the conductorization process is that after the formation of the second metal layer, the channel region and the gate electrode formed during the second self-aligned conductorization process have high alignment accuracy, which greatly improves the gate electrode and the underlying trench.
  • the alignment accuracy between the channel regions greatly improves the electrical properties of the thin film transistor.
  • the present disclosure exemplarily uses the first electrode plate and the second electrode plate of the transparent material to form a storage capacitor with a transparent structure, which saves the area occupied by the capacitor, effectively improves the pixel aperture ratio, and is suitable for high PPI display.
  • the resistance of the source connection region and the drain connection region on both sides of the channel region is lower and the electrical conductivity is stronger, which is beneficial to improve the thin film Electrical properties of transistors.
  • the manufacturing process of the display substrate may include the following operations, as shown in FIGS. 19 to 25 .
  • a second insulating layer pattern is formed.
  • forming the second insulating layer pattern may include: depositing a second insulating film on the substrate on which the foregoing pattern is formed, patterning the second insulating film through a patterning process, and forming a covering of the first active layer 12 , the second active layer 22 and the second insulating layer 42 of the third active layer 32, the second insulating layer 42 is provided with a plurality of via patterns, and the plurality of vias at least include a first via K1, a second via The hole K2, the third via K3, the fourth via K4, the fifth via K5, the sixth via K6, the first active via V1 and the second active via V2, as shown in FIG. 19 and FIG. 20 .
  • 20 is a cross-sectional view taken along the AA direction in FIG. 10 .
  • the second insulating layer 42 where the second electrode plate 62 is located is removed to expose the second electrode plate 62 .
  • the first insulating layer 41 and the The second insulating layer 42 is etched away.
  • the first via hole K1 is located at the position of the first connection electrode 51 , exposing the surface of the first connection electrode 51 , and the first via hole K1 is configured to connect the first drain electrode and the third drain electrode formed subsequently to the first connection electrode 51 . connection to realize the connection between the first electrode plate 61 and the first drain electrode and the third drain electrode.
  • the second via hole K2 is located at the position of the first power supply line VDD and exposes the surface of the first power supply line VDD.
  • the second via hole K2 is configured to connect the subsequently formed first source electrode to the first power supply line VDD.
  • the third via hole K3 and the fourth via hole K4 are located at two ends of the second connection electrode 52 respectively, exposing the surface of the second connection electrode 52 , and the third via hole K3 and the fourth via hole K4 are respectively configured to connect the subsequently formed
  • the second scan line SN and the third gate electrode realize the connection between the second scan line SN and the third gate electrode.
  • the fifth via hole K5 is located at the position of the data line DN, exposing the surface of the data line DN.
  • the fifth via hole K5 is configured to connect the second source electrode formed subsequently to realize the connection between the data line DN and the second source electrode.
  • the sixth via hole K6 is located at the position of the compensation line SE, exposing the surface of the compensation line SE.
  • the sixth via hole K6 is configured to connect the third source electrode formed subsequently to realize the connection between the compensation line SE and the third source electrode.
  • the second insulating layer 42 in the first active via hole V1 and the second active via hole V2 is etched away, exposing the first active layer 12 and the second active layer 22 respectively. and partial surfaces of the regions on both sides of the third active layer 32 .
  • the distance between the first active via hole V1 and the second active via hole V2 is greater than the designed width of the channel regions of the first active layer 12 , the second active layer 22 and the third active layer 32 . In this way, when the first conductive process is performed subsequently, the first active layer 12 , the second active layer 22 and the third active layer 32 can all form a wider channel region.
  • the first conductorization treatment may include: on the substrate on which the aforementioned pattern is formed, exposing the second electrode plate 62 and the first active via V1 and the second active via V2.
  • the active layer is subjected to conductive treatment to form a conductive second electrode plate 62, and conductive regions 12' are formed on both sides of the first active layer 12, the second active layer 22 and the third active layer 32, and conductive
  • the regions 12 ′ serve as source connection regions and drain connection regions of the first active layer 12 , source connection regions and drain connection regions of the second active layer 22 , and source connection regions and drain connection regions of the third active layer 32 , respectively, As shown in Figure 21.
  • Forming a second metal layer pattern may include depositing a second metal thin film on the substrate formed with the aforementioned pattern. A layer of photoresist is coated on the second metal film, a photoresist pattern is formed by masking, exposing and developing, and the second metal film is etched by the first etching process to form a second metal layer pattern, and the first Photoresist 100 on the two metal layers.
  • the second metal layer pattern includes at least a first scan line GN, a second scan line SN, a first gate electrode 11, a second gate electrode 21, a third gate electrode 31, a first source electrode 13, a first drain electrode 14, a
  • the patterns of the two source electrodes 23 , the second drain electrodes 24 , the third source electrodes 33 and the third drain electrodes 34 are shown in FIG. 22 and FIG. 23 , and FIG.
  • the first scan line GN and the second scan line SN are parallel to each other, extend in the horizontal direction, and are both disposed on the lower side of the sub-pixels.
  • the first scan line GN may be a switch scan line configured to provide an on/off signal for controlling the second transistor to the second gate electrode of the second transistor
  • the second scan line SN may be a compensation scan line configured to provide the third transistor with an on/off signal.
  • the third gate electrode of SN provides an on/off signal for controlling the third transistor
  • the second scan line SN is connected to the second connection electrode 52 through the fourth via hole K4.
  • the first gate electrode 11 is an integral structure interconnected with the second drain electrode 24
  • the second gate electrode 21 is an integral structure interconnected with the first scan line GN
  • the third gate electrode 31 is interconnected through the The three via holes K3 are connected to the second connection electrode 52 , and since the second connection electrode 52 is connected to the second scan line SN through the fourth via hole K4 , the third gate electrode 31 is connected to the second scan line through the second connection electrode 52 . SN connection.
  • the first end of the first source electrode 13 is connected to the first power supply line VDD through the second via hole K2 , and the second end is connected to the source of the first active layer 12 through the second active via hole V2
  • the connection regions are connected to form the first source electrode 13 connected to the first power supply line VDD.
  • the first end of the first drain electrode 14 is connected to the drain connection region of the first active layer 12 through the first active via V1, and is connected to the first connection electrode 51 through the first via K1 to realize the first drain electrode 14 is connected to the first electrode plate 61, and the second end is connected to the third active layer 32 through the first active via V1 to form the first drain electrode 14 and the third drain electrode 34 in an integrated structure.
  • the first end of the second source electrode 23 is connected to the data line DN through the fifth via hole K5 , and the second end is connected to the source connection region of the second active layer 22 through the second active via hole V2 connected to form a second source electrode 23 connected to the data line DN.
  • the first end of the second drain electrode 24 is connected to the drain connection region of the second active layer 22 through the first active via V1, and the second end is placed on the channel region of the second active layer 22 that has not undergone conductorization treatment.
  • the second drain electrode 24 and the first gate electrode 11 in an integrated structure are formed, and the connection between the second drain electrode 24 and the second electrode plate 62 is realized.
  • the first end of the third source electrode 33 is connected to the compensation line SE through the sixth via hole K6, and the second end is connected to the source connection region of the third active layer 32 through the second active via hole V2 connected to form the third source electrode 33 connected to the compensation line SE.
  • the third drain electrode 34 is connected to the drain connection region of the third active layer 32 through the first active via V1 , and is an integral structure connected with the first drain electrode 14 .
  • the first gate electrode 11, the first active layer 12, the first source electrode 13 and the first drain electrode 14 constitute the first transistor T1
  • the second source electrode 23 and the second drain electrode 24 constitute the second transistor T2
  • the third gate electrode 31, the third active layer 32, the third source electrode 33 and the third drain electrode 34 constitute the second transistor T2
  • the plate 61 and the conductive second plate 62 constitute a storage capacitor of a transparent structure.
  • the second etching process may include: using the second metal layer pattern and the photoresist 100 remaining on the second metal layer as masks, performing self-alignment through the second etching process
  • the second insulating layer 42 is etched below, and the second insulating layer 42 that is not covered by the second metal layer pattern on the first active layer 12, the second active layer 22 and the third active layer 32 is removed, as shown in FIG. 24 . Show.
  • the sides of the first source electrode 13 and the first drain electrode 14 facing the first gate electrode 11 may be partially removed by an appropriate amount of overetching, not only the first source electrode 13 and the first drain electrode 14
  • the side facing the first gate electrode 11 is flush, and the partially conductive region 12' in the first active via and the partially conductive region 12' in the second active via are exposed.
  • the second conductive process may include: using the second insulating layer 42, the second metal layer pattern disposed on the second insulating layer 42, and the photoresist 100 remaining on the second metal layer as mask, the first active layer 12, the second active layer 22 and the third active layer 32 are subjected to the second conductorization treatment, and the second electrode plate 62 is also subjected to the second conductorization treatment to form corresponding The channel of the source layer and the second electrode plate 62 of the secondary conductorization are stripped of the remaining photoresist, as shown in FIG. 25 .
  • the width of the channel finally formed is the same as that of the first conductor.
  • the gate electrode 11, the second gate electrode 21 and the third gate electrode 31 have substantially the same width.
  • the orthographic projection of the channel region of the first active layer 12 on the substrate overlaps with the orthographic projection of the first connection electrode 51 on the substrate, so that the first connection electrode 51 shields the channel region of the first active layer 12 .
  • the exemplary embodiment of the present disclosure greatly improves the alignment accuracy between the gate electrode and the underlying channel through the self-aligned conductorization process, and greatly improves the electrical characteristics of the thin film transistor.
  • the first active layer undergoes two conductorization processes, so that the first active layer forms three regions: a channel region in the middle, a source transition region and a drain transition on both sides of the channel region region, a source connection region located on the side of the source transition region away from the channel region, and a drain connection region located on the side of the drain transition region away from the channel region.
  • the boundary of the orthographic projection of the channel region on the substrate substantially overlaps with the boundary of the orthographic projection of the first gate electrode on the substrate, the source connection region is connected to the first source electrode, the drain connection region is connected to the first drain electrode, and the source transition region is located at Between the channel region and the source connection region, that is, the region between the first gate electrode and the first source electrode, the drain transition region is between the channel region and the drain connection region, that is, between the first gate electrode and the first drain the region between the poles.
  • the second active layer and the third active layer also form three regions.
  • the region of the first conductorization treatment overlaps with the region of the second conductorization treatment (as shown by the black area 12" in Figure 25), so the source transition region and the drain transition region are both Both include a first region 12A that has undergone two conductorization treatments and a second region 12B that has undergone only a second conductorization treatment.
  • the first region 12A that has undergone two conductorization treatments is subjected to two helium (He) plasma treatments,
  • the oxygen content in the film layer is further reduced, the oxygen content of the first active layer corresponding to the first region 12A is smaller than that of the first active layer corresponding to the second region 12B, the resistance is lower, and the electrical conductivity is stronger,
  • the conductivity of the first active layer corresponding to the first region 12A is higher than that of the first active layer corresponding to the second region 12B, which is beneficial to improve the electrical characteristics of the thin film transistor.
  • the conductivity of the first active layer corresponding to the first region 12A is higher than the conductivity of the first active layer corresponding to the source connection region and the drain connection region, and the conductivity of the first active layer corresponding to the first region 12A
  • the oxygen content of the active layer is less than the oxygen content of the first active layer corresponding to the source connection region and the drain connection region.
  • the second electrode plate 62 has undergone two conductorization treatments, the The conductivity is beneficial to improve the driving characteristics of the pixel driving circuit.
  • the conductivity of the metal oxide layer corresponding to the second electrode plate 62 is higher than that of the first active layer corresponding to the second region 12B.
  • the oxygen element content of the metal oxide layer corresponding to the second electrode plate 62 is smaller than the oxygen element content of the first active layer corresponding to the second region 12B.
  • the second insulating layer is etched twice, and the over-etching of the etching process will etch away part of the thickness of the first active layer 12 , so the first The thickness of the first active layer corresponding to the region 12A becomes thinner, the thickness of the first active layer corresponding to the first region 12A is smaller than the thickness of the first active layer corresponding to the second region 12B, and the thickness of the first active layer corresponding to the first region 12A
  • the thickness of the active layer is smaller than the thickness of the first active layer corresponding to the source connection region and the drain connection region, the thickness of the first active layer corresponding to the first region 12A is smaller than the thickness of the first active layer corresponding to the channel region, Conducive to improving the conductivity effect.
  • the thickness of the metal oxide layer corresponding to the second electrode plate 62 is smaller than the thickness of the first active layer corresponding to the second region 12B.
  • the display substrate formed by the foregoing preparation process may include:
  • the first insulating layer 41 covering the first electrode plate 61 and the first metal layer;
  • the orthographic projection overlaps with the orthographic projection of the first polar plate 61 on the substrate 10 to form a transparent storage capacitor;
  • the first active layer 12 includes three regions: a channel region in the middle, and two sides of the channel region.
  • the source transition region and the drain transition region of the The orthographic projection on the substrate 10 overlaps with the orthographic projection of the first connection electrode 51 on the substrate 10;
  • the second insulating layer 42 is provided on the first active layer 12, and the second insulating layer 42 is provided with a first via hole K1, a second via hole K2, a first active via hole V1 and a second active via hole V2 , the first via hole K1 exposes the first connection electrode 51, the second via hole K2 exposes the first power supply line VDD, and the first active via hole V1 exposes the conductive drain connection region of the first active layer 12 , the second active via V2 exposes the source connection region of the first active layer 12 subjected to the conductorization treatment;
  • the via hole K2 is connected to the first power supply line VDD, and the second end of the first source electrode 13 is connected to the source connection region of the first active layer 12 through the second active via hole V2;
  • the source via hole V1 is connected to the drain connection region of the first active layer 12, and is connected to the first connection electrode 51 through the first via hole K1;
  • the flat layer 44 is provided with a seventh via hole K7 exposing the first drain electrode 14;
  • the anode 81 is provided on the flat layer 44, and the anode 81 is connected to the first drain electrode 14 through the seventh via K7.
  • the display substrate may further include a pixel definition layer, an organic light emitting layer, a cathode and an encapsulation layer, and the like.
  • the source transition region of the first active layer 12 is located between the first gate electrode 11 and the first source electrode 13
  • the drain transition region of the first active layer 12 is located between the first gate electrode 11 and the first source electrode 13 .
  • the source transition region and the second insulating layer 42 of the drain transition region are removed by self-aligned etching.
  • the source connection region and the drain connection region of the first active layer 12 are formed by the first conductive process, and the channel region of the first active layer 12 is formed by the self-aligned second conductive process. formed during processing.
  • An exemplary embodiment of the present disclosure proposes a scheme of forming a pixel circuit layer of a display substrate through four patterning processes.
  • the first conductive layer and the first metal layer are formed through the same patterning process, and the gate electrode, the source electrode and the drain electrode are in the same layer. It is set up and formed by the same patterning process, which reduces the number of patterning processes, shortens the process time, reduces the process cost, has good process compatibility, high process achievability, strong practicability, very mass production, and good application prospects.
  • the exemplary embodiment of the present disclosure proposes a scheme of conducting two conductorization treatments.
  • the first conductorization treatment is to form a wider channel region through the first conductorization treatment before forming the second metal layer, and the second conductorization treatment is performed to form a wider channel region.
  • the conductorization process is that after the formation of the second metal layer, the channel region and the gate electrode formed during the second self-aligned conductorization process have high alignment accuracy, which greatly improves the gate electrode and the underlying trench.
  • the alignment accuracy between the channel regions greatly improves the electrical properties of the thin film transistor.
  • Exemplary embodiments of the present disclosure also provide a method of fabricating a display substrate.
  • the manufacturing method of the display substrate may include:
  • a second insulating layer and a second metal layer are formed in sequence, and a channel region, a source transition region and a drain transition region located on both sides of the channel region are formed on the first active layer through two conductorization treatments, and a source connection region located on the side of the source transition region away from the channel region and a drain connection region located on the side of the drain transition region away from the channel region;
  • the second metal layer includes a first gate electrode, a first source an electrode and a first drain electrode, the source connection region is connected to the first source electrode, the drain connection region is connected to the first drain electrode; both the source transition region and the drain transition region include a distance from the trench A first region of the channel region and a second region adjacent to the channel region; the conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to the second region , or, the oxygen content of the first active layer corresponding to the first region is less than the oxygen content of the first active layer corresponding to the second region, or, the first active
  • the first conductive layer includes a first electrode plate
  • the metal oxide layer further includes a second electrode plate
  • the orthographic projection of the second electrode plate on the substrate is the same as that of the first electrode plate.
  • the orthographic projection of the plate on the substrate has an overlapping area.
  • step S1 may include:
  • a transparent first electrode plate and a first metal layer are formed on the substrate, and a transparent conductive film is arranged between the first metal layer and the substrate;
  • the first metal layer includes a first power line and a first connection electrode, so the first connection electrode is connected to the first plate;
  • a metal oxide layer is formed on the first insulating layer, the metal oxide layer includes a first active layer and a second electrode plate, and the orthographic projection of the second electrode plate on the substrate is the same as the first electrode plate
  • the orthographic projection of the plate on the substrate has an overlapping area, and the orthographic projection of the channel region of the first active layer on the substrate and the orthographic projection of the first connection electrode on the substrate have an overlapping area.
  • step S2 may include:
  • a second insulating layer is formed on the first active layer, and a first via hole and a second via hole are formed on the first insulating layer; the second insulating layer covers the middle of the first active layer area; the first via hole and the second via hole respectively expose the first connection electrode and the first power line;
  • the second electrode plate and the two side regions of the first active layer that are not covered by the second insulating layer are subjected to the first conductorization treatment to form a conductorized second electrode plate.
  • a source connection region and a drain connection region are respectively formed on both sides of the active layer;
  • the second metal layer includes a first gate electrode, a first source electrode and a first drain electrode;
  • the first gate electrode is located on the In the middle region of the first active layer, the first drain electrode is placed on the drain connection region and connected to the first connection electrode through the first via hole;
  • the terminal is connected to the first power line through the second via hole, and the second terminal of the first source electrode is laid on the source connection area;
  • the first active layer covered by the second insulating layer is subjected to a second conductorization process to form a channel region of the first active layer and source transition regions and drain transition regions located on both sides of the channel region.
  • both the source transition region and the drain transition region include a first region away from the channel region and a second region adjacent to the channel region; the first active region corresponding to the first region
  • the conductivity of the layer is higher than that of the first active layer corresponding to the second region, or the oxygen content of the first active layer corresponding to the first region is smaller than that of the first active layer corresponding to the second region.
  • the oxygen element content of the active layer, or the thickness of the first active layer corresponding to the first region is smaller than the thickness of the first active layer corresponding to the second region.
  • step S2 may include:
  • a second insulating layer covering the first active layer is formed, a first via hole, a second via hole, a first active via hole and a second active via hole are formed on the second insulating layer, and the second active via hole is formed on the second insulating layer.
  • the first via hole and the second via hole respectively expose the first connection electrode and the first power supply line, and the first active via hole and the second active via hole respectively expose the two parts of the first active layer. part of the area on the side;
  • the second electrode plate and the first active layer exposed in the first active via hole and the second active via hole are subjected to a first conductorization treatment to form a conductorized second electrode plate and the first active layer exposed in the second active via hole.
  • the second metal layer includes a first gate electrode, a first source electrode and a first drain electrode;
  • the first gate electrode is located on the In the middle region of the active layer, the first drain electrode is connected to the drain connection region through the second active via hole, and is connected to the first connection electrode through the first via hole;
  • a first end of a source electrode is connected to the first power line through the second via hole, and a second end of the first source electrode is connected to the source connection region through the first active via hole;
  • the first active layer covered by the second insulating layer is subjected to a second conductorization process to form a channel region of the first active layer and source transition regions and drain transition regions located on both sides of the channel region.
  • both the source transition region and the drain transition region include a first region away from the channel region and a second region adjacent to the channel region; the first active region corresponding to the first region
  • the conductivity of the layer is higher than that of the first active layer corresponding to the second region, or the oxygen content of the first active layer corresponding to the first region is smaller than that of the first active layer corresponding to the second region.
  • the oxygen element content of the active layer, or the thickness of the first active layer corresponding to the first region is smaller than the thickness of the first active layer corresponding to the second region.
  • etching the second insulating layer not covered by the second metal layer includes:
  • the second insulating layer between the first gate electrode and the first source electrode and the second insulating layer between the first gate electrode and the first drain electrode are removed by self-aligned etching.
  • Exemplary embodiments of the present disclosure provide a display substrate, a method for fabricating the same, and a display device.
  • the gate electrode, the source electrode, and the drain electrode are arranged in the same layer and formed through the same patterning process. Only four patterning processes are required, and the maximum The number of patterning processes is greatly reduced. Through two conductorization treatments, the alignment accuracy between the gate electrode and the lower channel region is greatly improved, and the electrical characteristics of the thin film transistor are greatly improved.
  • Exemplary embodiments of the present disclosure show that the preparation method of the substrate reduces the number of patterning processes, shortens the process time, reduces the process cost, has good process compatibility, high process achievability, strong practicability, is very mass-producible, and has good application prospects.
  • the present disclosure also provides a display device including the aforementioned display substrate.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种显示基板及其制备方法、显示装置。显示基板包括在基底上叠设的第一导电层、第一金属层、金属氧化物层和第二金属层，金属氧化物层包括第一有源层，第一有源层包括沟道区域、源过渡区域和漏过渡区域，源过渡区域和漏过渡区域均包括第一区域和第二区域，第一区域对应的第一有源层的导电率高于第二区域对应的第一有源层的导电率，或者，第一区域对应的第一有源层的氧元素含量小于第二区域对应的第一有源层的氧元素含量，或者，第一区域对应的第一有源层的厚度小于第二区域对应的第一有源层的厚度。

Description

显示基板及其制备方法、显示装置
本申请要求于2020年7月23日提交中国专利局、申请号为202010719363.6、发明名称为“显示基板及其制备方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开示例性实施例涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管显示装置(Organic Light Emitting Diode，简称OLED)具有超薄、大视角、主动发光、高亮度、发光颜色连续可调、成本低、响应速度快、低功耗、工作温度范围宽及可柔性显示等优点，已逐渐成为极具发展前景的下一代显示技术。依据驱动方式的不同，OLED可以分为无源矩阵驱动(Passive Matrix，简称PM)型和有源矩阵驱动(Active Matrix，简称AM)型两种，AM OLED是电流驱动器件，采用独立的薄膜晶体管(Thin Film Transistor，简称TFT)控制每个子像素，每个子像素皆可以连续且独立的驱动发光。依据出光方向的不同，OLED可分为顶发射型OLED和底发射型OLED，底发射型OLED是最早被使用的结构。
OLED设计中，像素开口率是重要参数之一，也是提高显示装置分辨率的重要因素，尤其对于底发射型OLED。为了保证存储电容的容量，存储电容的电极板需要较大面积。随着高分辨率(PPI)显示技术的发展，子像素尺寸越来越小，使得驱动电路区域占用像素面积的比例越来越大，导致像素开口率大幅度降低。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一种显示基板，包括在基底上叠设的第一导电层、第一金属层、第一绝缘层、金属氧化物层、第二绝缘层和第二金属层；所述金属氧化物层包括第一有源层，所述第二金属层包括第一栅电极、第一源电极和第一漏电极；所述第一有源层包括沟道区域、位于所述沟道区域两侧的源过渡区域和漏过渡区域、以及位于所述源过渡区域远离沟道区域一侧的源连接区域和位于所述漏过渡区域远离沟道区域一侧的漏连接区域；所述源连接区域与所述第一源电极连接，所述漏连接区域与所述第一漏电极连接；所述源过渡区域和漏过渡区域均包括远离所述沟道区域的第一区域和邻近所述沟道区域的第二区域；所述第一区域对应的第一有源层的导电率高于所述第二区域对应的第一有源层的导电率，或者，所述第一区域对应的第一有源层的氧元素含量小于所述第二区域对应的第一有源层的氧元素含量，或者，所述第一区域对应的第一有源层的厚度小于所述第二区域对应的第一有源层的厚度。
在示例性实施方式中，所述第一区域对应的第一有源层的导电率高于所述源连接区域和漏连接区域对应的第一有源层的导电率，或者，所述第一区域对应的第一有源层的氧元素含量小于所述源连接区域和漏连接区域对应的第一有源层的氧元素含量，或者，所述第一区域对应的第一有源层的厚度小于所述源连接区域和漏连接区域对应的第一有源层的厚度。
在示例性实施方式中，所述第一栅电极在基底上正投影的边界位于所述第二绝缘层在基底上正投影的边界范围内；所述沟道区域在基底上正投影的边界位于所述第二绝缘层在基底上正投影的边界范围内。
在示例性实施方式中，所述显示基板包括规则排布的多个子像素，每个子像素包括像素驱动电路和电连接所述像素驱动电路的有机电致发光二极管，所述像素驱动电路包括存储电容，所述存储电容包括第一极板和第二极板，所述第一极板在基底上的正投影与所述第二极板在基底上的正投影存在交叠区域。
在示例性实施方式中，所述像素驱动电路还包括第一晶体管、第二晶体管和第三晶体管；所述第一晶体管的栅电极耦接于第二晶体管的第二极，所 述第一晶体管的第一极耦接于第一电源线，所述第一晶体管的第二极耦接于所述有机电致发光二极管的第一极，所述有机电致发光二极管的第二极耦接于第二电源线；所述第二晶体管的栅电极耦接于第一扫描线，所述第二晶体管的第一极耦接于数据线；所述第三晶体管的栅电极耦接于第二扫描线，所述第三晶体管的第一极耦接于补偿线，所述第三晶体管的第二极耦接于所述第一晶体管的第二极；所述存储电容的第一极耦接于所述第一晶体管的栅电极，所述存储电容的第二极耦接于所述第一晶体管的第二极。
在示例性实施方式中，所述第一导电层包括所述存储电容的第一极板，所述金属氧化物层包括所述存储电容的第二极板。
在示例性实施方式中，所述第一极板的材料包括透明导电材料，所述交叠区域位于所述显示基板的发光区域。
在示例性实施方式中，所述第一金属层包括所述存储电容的第一极板，所述金属氧化物层包括所述存储电容的第二极板。
在示例性实施方式中，所述第二金属层包括所述存储电容的第一极板，所述金属氧化物层包括所述存储电容的第二极板。
在示例性实施方式中，所述第一金属层包括所述存储电容的第一极板，所述第二金属层包括所述存储电容的第二极板。
在示例性实施方式中，所述第二极板对应的金属氧化物层的导电率高于所述第二区域对应的第一有源层的导电率，或者，所述第二极板对应的金属氧化物层的氧元素含量小于所述第二区域对应的第一有源层的氧元素含量，或者，所述第二极板对应的金属氧化物层的厚度小于所述第二区域对应的第一有源层的厚度。
在示例性实施方式中，所述第一金属层包括第一电源线和第一连接电极，所述第一连接电极与第一极板连接，所述第一金属层与基板之间设置有透明导电薄膜；所述第一连接电极在基底上的正投影与所述第一有源层的沟道区域在基底上的正投影存在交叠区域。
在示例性实施方式中，所述第一源电极和第一漏电极设置在第一绝缘层上；所述第一漏电极搭设在所述第一有源层的漏连接区域上，且通过第一过 孔与第一连接电极连接；所述第一源电极的第一端通过第二过孔与所述第一电源线连接，所述第一源电极的第二端搭设在所述第一有源层的源连接区域上。
在示例性实施方式中，所述第一源电极和第一漏电极设置在所述第二绝缘层上；所述第一漏电极通过第一有源过孔与所述第一有源层的漏连接区域连接，且通过第一过孔与第一连接电极连接；所述第一源电极的第一端通过第二过孔与所述第一电源线连接，所述第一源电极的第二端通过第二有源过孔与所述第一有源层的源连接区域连接。
一种显示装置，包括上述显示基板。
一种显示基板的制备方法，包括：
在基底上依次形成第一导电层、第一金属层和金属氧化物层，所述金属氧化物层包括第一有源层；
依次形成第二绝缘层和第二金属层，通过两次导体化处理使所述第一有源层形成沟道区域、位于所述沟道区域两侧的源过渡区域和漏过渡区域、以及位于所述源过渡区域远离沟道区域一侧的源连接区域和位于所述漏过渡区域远离沟道区域一侧的漏连接区域；所述第二金属层包括第一栅电极、第一源电极和第一漏电极，所述源连接区域与所述第一源电极连接，所述漏连接区域与所述第一漏电极连接；所述源过渡区域和漏过渡区域均包括远离所述沟道区域的第一区域和邻近所述沟道区域的第二区域；所述第一区域对应的第一有源层的导电率高于所述第二区域对应的第一有源层的导电率，或者，所述第一区域对应的第一有源层的氧元素含量小于所述第二区域对应的第一有源层的氧元素含量，或者，所述第一区域对应的第一有源层的厚度小于所述第二区域对应的第一有源层的厚度。
在示例性实施方式中，所述第一导电层包括第一极板，所述金属氧化物层还包括第二极板，所述第二极板在基底上的正投影与所述第一极板在基底上的正投影存在交叠区域。
在示例性实施方式中，在基底上依次形成第一导电层、第一金属层和金属氧化物层，包括：
在基底上形成透明的第一极板和第一金属层，所述第一金属层与基板之间设置有透明导电薄膜；所述第一金属层包括第一电源线和第一连接电极，所述第一连接电极与第一极板连接；
形成覆盖所述第一极板和第一金属层的第一绝缘层；
在所述第一绝缘层上形成金属氧化物层，所述金属氧化物层包括第一有源层和第二极板，所述第二极板在基底上的正投影与所述第一极板在基底上的正投影存在交叠区域，所述第一有源层的沟道区域在基底上的正投影与所述第一连接电极在基底上的正投影存在交叠区域。
在示例性实施方式中，依次形成第二绝缘层和第二金属层，通过两次导体化处理使所述第一有源层形成沟道区域、位于所述沟道区域两侧的源过渡区域和漏过渡区域、以及位于所述源过渡区域远离沟道区域一侧的源连接区域和位于所述漏过渡区域远离沟道区域一侧的漏连接区域，包括：
在所述第一有源层上形成第二绝缘层，在所述第一绝缘层上形成第一过孔和第二过孔；所述第二绝缘层覆盖所述第一有源层的中部区域；所述第一过孔和第二过孔分别暴露出所述第一连接电极和第一电源线；
对所述第二极板和所述第一有源层未被所述第二绝缘层覆盖的两侧区域进行第一次导体化处理，形成导体化的第二极板，在所述第一有源层的两侧分别形成源连接区域和漏连接区域；
形成第二金属层，保留所述第二金属层上的光刻胶；所述第二金属层包括第一栅电极、第一源电极和第一漏电极；所述第一栅电极位于所述第一有源层的中部区域，所述第一漏电极搭设在所述漏连接区域上，并通过所述第一过孔与所述第一连接电极连接；所述第一源电极的第一端通过所述第二过孔与所述第一电源线连接，所述第一源电极的第二端搭设在所述源连接区域上；
以所述第二金属层和设置在所述第二金属层上的光刻胶为掩膜，刻蚀未被所述第二金属层覆盖的第二绝缘层；
以所述第二绝缘层、设置在所述第二绝缘层上的第二金属层以及设置在所述第二金属层上的光刻胶为掩膜，对所述第二极板和未被所述第二绝缘层 覆盖的第一有源层进行第二次导体化处理，形成第一有源层的沟道区域以及位于沟道区域两侧的源过渡区域和漏过渡区域，所述第一栅电极在基底上正投影的边界位于所述第二绝缘层在基底上正投影的边界范围内；所述沟道区域在基底上正投影的边界位于所述第二绝缘层在基底上正投影的边界范围内，所述源过渡区域和漏过渡区域均包括远离所述沟道区域的第一区域和邻近所述沟道区域的第二区域；所述第一区域对应的第一有源层的导电率高于所述第二区域对应的第一有源层的导电率，或者，所述第一区域对应的第一有源层的氧元素含量小于所述第二区域对应的第一有源层的氧元素含量，或者，所述第一区域对应的第一有源层的厚度小于所述第二区域对应的第一有源层的厚度。
在示例性实施方式中，依次形成第二绝缘层和包括第一栅电极的第二金属层，通过两次导体化处理使所述第一有源层形成沟道区域、位于所述沟道区域两侧的源过渡区域和漏过渡区域、以及位于所述源过渡区域远离沟道区域一侧的源连接区域和位于所述漏过渡区域远离沟道区域一侧的漏连接区域，包括：
形成覆盖所述第一有源层的第二绝缘层，所述第二绝缘层上形成有第一过孔、第二过孔、第一有源过孔和第二有源过孔，所述第一过孔和第二过孔分别暴露出所述第一连接电极和第一电源线，所述第一有源过孔和第二有源过孔分别暴露出所述第一有源层两侧的部分区域；
对所述第二极板以及所述第一有源过孔和第二有源过孔内暴露出的第一有源层进行第一次导体化处理，形成导体化的第二极板以及所述第一有源层的源连接区域和漏连接区域；
形成第二金属层，保留所述第二金属层上的光刻胶；所述第二金属层包括第一栅电极、第一源电极和第一漏电极；所述第一栅电极位于所述有源层的中部区域，所述第一漏电极通过所述第二有源过孔与所述漏连接区域连接，并通过所述第一过孔与所述第一连接电极连接；所述第一源电极的第一端通过所述第二过孔与所述第一电源线连接，所述第一源电极的第二端通过所述第一有源过孔与所述源连接区域连接；
以所述第二金属层和设置在所述第二金属层上的光刻胶为掩膜，刻蚀未 被所述第二金属层覆盖的第二绝缘层；
以所述第二绝缘层、设置在所述第二绝缘层上的第二金属层以及设置在所述第二金属层上的光刻胶为掩膜，对所述第二极板和未被所述第二绝缘层覆盖的第一有源层进行第二次导体化处理，形成第一有源层的沟道区域以及位于沟道区域两侧的源过渡区域和漏过渡区域，所述第一栅电极在基底上正投影的边界位于所述第二绝缘层在基底上正投影的边界范围内；所述沟道区域在基底上正投影的边界位于所述第二绝缘层在基底上正投影的边界范围内，所述源过渡区域和漏过渡区域均包括远离所述沟道区域的第一区域和邻近所述沟道区域的第二区域；所述第一区域对应的第一有源层的导电率高于所述第二区域对应的第一有源层的导电率，或者，所述第一区域对应的第一有源层的氧元素含量小于所述第二区域对应的第一有源层的氧元素含量，或者，所述第一区域对应的第一有源层的厚度小于所述第二区域对应的第一有源层的厚度。
在示例性实施方式中，刻蚀未被所述第二金属层覆盖的第二绝缘层，包括：
通过自对准刻蚀方式去除所述第一栅电极与第一源电极之间的第二绝缘层以及所述第一栅电极与第一漏电极之间的第二绝缘层。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开示例性实施例一种OLED中显示单元的结构示意图；
图2为一种OLED像素驱动电路的等效电路示意图；
图3为本公开示例性实施例一种形成第一极板图案后的示意图；
图4为图3中A-A向的剖面图；
图5为本公开示例性实施例一种形成金属氧化物层图案后的示意图；
图6为图5中A-A向的剖面图；
图7为本公开示例性实施例一种形成第二绝缘层图案后的示意图；
图8为图7中A-A向的剖面图；
图9为本公开示例性实施例一种第一次导体化处理后的示意图；
图10为本公开示例性实施例一种形成第二金属层图案后的示意图；
图11为图10中A-A向的剖面图；
图12为本公开示例性实施例一种第二次刻蚀处理后的示意图；
图13为本公开示例性实施例一种第二次导体化处理后的示意图；
图14为本公开示例性实施例一种形成第三绝缘层图案后的示意图；
图15为本公开示例性实施例一种形成彩膜层图案后的示意图；
图16为本公开示例性实施例一种形成平坦层图案后的示意图；
图17为本公开示例性实施例一种形成阳极图案后的示意图；
图18为本公开示例性实施例一种形成像素定义层图案后的示意图；
图19为本公开示例性实施例另一种形成第二绝缘层图案后的示意图；
图20为图19中A-A向的剖面图；
图21为本公开示例性实施例另一种第一次导体化处理后的示意图；
图22为本公开示例性实施例另一种形成第二金属层图案后的示意图；
图23为图22中A-A向的剖面图；
图24为本公开示例性实施例另一种第二次刻蚀处理后的示意图；
图25为本公开示例性实施例另一种第二次导体化处理后的示意图。
附图标记说明:
10—基底；             11—第一栅电极；       12—第一有源层；
13—第一源电极；        14—第一漏电极；        21—第二栅电极；
22—第二有源层；        23—第二源电极；        24—第二漏电极；
31—第三栅电极；        32—第三有源层；        33—第三源电极；
34—第三漏电极；        41—第一绝缘层；        42—第二绝缘层；
43—第三绝缘层；        44—平坦层；            51—第一连接电极；
52—第二连接电极；      61—第一极板；          62—第二极板；
70—彩膜层；            81—阳极；              82—像素定义层；
100—光刻胶。
具体实施方式
本文中的实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是实现方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，可能夸大表示了构成要素的大小、层的厚度或区域。因此，本公开的任意一个实现方式并不一定限定于图中所示尺寸，附图中部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的任意一个实现方式不局限于附图所示的形状或数值等。
本文中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本文中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述实施方式和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系可根据描述的构成要素的方向进行适当地改变。因此，不局限于在文中说明的词句，根据情况可以适当地更换。
在本文中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本文中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(或称漏电极端子、漏连接区域或漏电极)与源电极(或称源电极端子、源连接区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本文中，沟道区域是指电流主要流过的区域。
在本文中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况下，“源电极”及“漏电极”的功能有时可以互相调换。因此，在本文中，“源电极”和“漏电极”可以互相调换。
在本文中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”例如可以是电极或布线，或者是晶体管等开关元件，或者是电阻器、电感器或电容器等其它功能元件等。
在本文中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本文中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本文中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
随着显示技术的快速发展，薄膜晶体管技术由非晶硅(a-Si)薄膜晶体管发展到金属氧化物(Oxide)薄膜晶体管。氧化物有源层的载流子迁移率是非晶硅有源层的20～30倍，具有迁移率大、开态电流高、开关特性更优、均匀性更好的特点，可以大大提高薄膜晶体管的特性，提高像素的响应速度，实现更快的刷新率，可以适用于需要快速响应和较大电流的应用。
氧化物薄膜晶体管包括两种类型，分别是底栅型薄膜晶体管和顶栅型薄膜晶体管，底栅型薄膜晶体管的结构特点是，源电极和漏电极分别覆盖在氧化物有源层的两侧，源电极与漏电极之间形成沟道(channel)区域，顶栅型薄膜晶体管的结构特点是，源电极和漏电极分别通过过孔与氧化物有源层连接。由于顶栅型薄膜晶体管具有短沟道的特点，开态电流(Ion)得以有效提升，因而可以显著提升显示效果，有效降低功耗。由于顶栅型薄膜晶体管中栅电极与源漏电极之间交叠面积小，产生的寄生电容较小，具有较小的电路延迟和较高的开关速度，因而发生栅极与漏极短路(GDS)等不良的可能性较低。
本公开示例性实施例提供了一种底发射型的显示基板，包括规则排布的多个显示单元(子像素)。图1为本公开示例性实施例一种OLED中显示单元的结构示意图，OLED为底发射型。如图1所示，在平行于显示基板的平面内，每个显示单元包括发光结构区和驱动电路区，发光结构区设置发光结构，发光结构配置为出射光线，驱动电路区设置像素驱动电路，像素驱动电路配置为驱动发光结构，像素驱动电路可以包括多个薄膜晶体管和存储电容。
在示例性实施方式中，驱动电路区可以包括电路区和电容区，驱动发光结构的多个薄膜晶体管设置在电路区，存储电容的电极板设置在电容区，存储电容的电极板和多个薄膜晶体管并列设置。
在示例性实施方式中，存储电容为透明电容结构，采用透明导电层和导体化的金属氧化物作为存储电容的两个电极板。这样，发光结构区和电容区共同构成发光区域，既可以保证存储电容的容量，又可以提高像素开口率。
在示例性实施方式中，像素驱动电路可以采用3T1C、4T1C、5T1C、6T1C、或7T1C等驱动结构，本公开对此不做限定。
图2为一种OLED像素驱动电路的等效电路示意图，示意了一种3T1C的驱动结构。如图2所示，像素驱动电路与第一扫描线GN、第二扫描线SN、数据线DN、第一电源线VDD以及补偿线SE电连接，像素驱动电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容C ST。在示例性实施方式中，第一晶体管T1为驱动晶体管，第二晶体管T2为开关晶体管，第三晶体管T3为补偿晶体管。在示例性实施方式中，第一晶体管T1的栅电极连接第二晶体管T2的第二极和存储电容C ST的第一极，第一晶体管T1的第一极连接第一电源线VDD，第一晶体管T1的第二极连接存储电容C ST的第二极以及第三晶体管T3的第二极。第二晶体管T2的栅电极连接扫描线GN，第二晶体管T2的第一极连接数据线DN；第三晶体管T3的栅电极连接第二扫描线SN，第三晶体管T3的第一极连接补偿线SE。OLED的阳极连接第一晶体管T1的第二极，OLED的阴极连接第二电源线VSS，OLED被配置为响应第一晶体管T1的第二极的电流而发出相应亮度的光。在示例性实施方式中，第三晶体管T3能够响应补偿的时序提取第一晶体管T1的阈值电压Vth以及迁移率，以对阈值电压Vth进行补偿，存储电容C ST被配置为保持在一帧发光周期内N1节点和N2节点电压。
在本公开示例性实施例中，底发射型顶栅结构的显示基板包括叠设的第一导电层、第一金属层、第一绝缘层、金属氧化物层、第二绝缘层和第二金属层；所述金属氧化物层包括第一有源层，所述第二金属层包括第一栅电极、第一源电极和第一漏电极；所述第一有源层包括沟道区域、位于所述沟道区域两侧的源过渡区域和漏过渡区域、以及位于所述源过渡区域远离沟道区域一侧的源连接区域和位于所述漏过渡区域远离沟道区域一侧的漏连接区域；所述源连接区域与所述第一源电极连接，所述漏连接区域与所述第一漏电极连接；所述源过渡区域和漏过渡区域均包括远离所述沟道区域的第一区域和邻近所述沟道区域的第二区域；所述第一区域对应的第一有源层的导电率高于所述第二区域对应的第一有源层的导电率，或者，所述第一区域对应的第一有源层的氧元素含量小于所述第二区域对应的第一有源层的氧元素含量，或者，所述第一区域对应的第一有源层的厚度小于所述第二区域对应的第一有源层的厚度。
在示例性实施方式中，所述第一区域对应的第一有源层的导电率高于所述源连接区域和漏连接区域对应的第一有源层的导电率，或者，所述第一区域对应的第一有源层的氧元素含量小于所述源连接区域和漏连接区域对应的第一有源层的氧元素含量，或者，所述第一区域对应的第一有源层的厚度小于所述源连接区域和漏连接区域对应的第一有源层的厚度。
在示例性实施方式中，所述第一栅电极在基底上正投影的边界位于所述第二绝缘层在基底上正投影的边界范围内；所述沟道区域在基底上正投影的边界位于所述第二绝缘层在基底上正投影的边界范围内。
在示例性实施方式中，所述第一导电层包括设置在基底上的第一极板，所述金属氧化物层包括经过两次导体化处理的第二极板，所述第二极板在基底上的正投影与所述第一极板在基底上的正投影存在交叠区域。
在示例性实施方式中，所述第一极板的材料包括透明导电材料，所述交叠区域位于所述显示基板的发光区域。
在示例性实施方式中，所述第一金属层包括第一电源线和第一连接电极，所述第一连接电极与第一极板连接，所述第一金属层与基板之间设置有透明导电薄膜；所述第一连接电极在基底上的正投影与所述第一有源层的沟道区域在基底上的正投影存在交叠区域。
在示例性实施方式中，所述第一源电极和第一漏电极设置在所述第一绝缘层上；所述第一漏电极搭设在所述第一有源层的漏连接区域上，且通过第一过孔与第一连接电极连接；所述第一源电极的第一端通过第二过孔与所述第一电源线连接，所述第一源电极的第二端搭设在所述第一有源层的源连接区域上。
在示例性实施方式中，所述第一源电极和第一漏电极设置在所述第二绝缘层上；所述第一漏电极通过第一有源过孔与所述第一有源层的漏连接区域连接，且通过第一过孔与第一连接电极连接；所述第一源电极的第一端通过第二过孔与所述第一电源线连接，所述第一源电极的第二端通过第二有源过孔与所述第一有源层的源连接区域连接。
在示例性实施方式中，所述第一有源层的源过渡区域位于所述第一栅电极与第一源电极之间，所述第一有源层的漏过渡区域位于所述第一栅电极与 第一漏电极之间。
在示例性实施方式中，每个子像素包括发光区域和电路区域，所述像素驱动电路中的多个晶体管设置在所述电路区域，所述像素驱动电路中的存储电容在基底上的正投影与发光区域存在重叠区域。
在示例性实施方式中，第一有源层的源连接区域和漏连接区域通过第一次导体化处理形成，第一有源层的沟道区域在自对准的第二次导体化处理过程中形成。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“A的正投影包含B的正投影”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在一种示例性实施方式中，显示基板的制备过程可以包括如下操作，如图3～图18所示。
(1)形成第一极板和第一金属层图案。在示例性实施方式中，形成第一极板和第一金属层图案可以包括：在基底上依次沉积第一透明导电薄膜和第一金属薄膜，通过半色调的图案化工艺对第一透明导电薄膜和第一金属薄膜进行构图，在基底10上形成第一极板61和第一金属层图案，第一金属层图案至少包括第一电源线VDD、数据线DN、补偿线SE、第一连接电极51和第二连接电极52，第一连接电极51与第一极板61连接，如图3和图4所示， 图4为图3中A-A向的剖面图。
在示例性实施方式中，通过半色调的图案化工艺对第一透明导电薄膜和第一金属薄膜进行构图可以包括：先在第一金属薄膜上涂覆一层光刻胶，采用半色调掩膜板(Halftone Mask)对光刻胶进行曝光，显影后形成光刻胶图案，光刻胶图案包括未曝光区域、部分曝光区域和完全曝光区域，未曝光区域包括第一电源线VDD、数据线DN、补偿线SE、第一连接电极51和第二连接电极52图案所在位置，未曝光区域的光刻胶具有第一厚度。部分曝光区域包括第一极板61所在位置，部分曝光区域的光刻胶具有第二厚度，第二厚度小于第一厚度。其它区域为完全曝光区域，完全曝光区域的光刻胶被完全去除，暴露出第一金属薄膜的表面。随后，采用第一次刻蚀工艺去除完全曝光区域的第一透明导电薄膜和第一金属薄膜。随后，采用灰化工艺去除部分曝光区域的光刻胶，使部分曝光区域暴露出第一金属薄膜的表面。随后，采用第二次刻蚀工艺去除部分曝光区域的第一金属薄膜，暴露出部分曝光区域的第一透明导电薄膜。最后，剥离剩余的光刻胶，在基底上形成第一极板和第一金属层图案。本次图案化工艺后，第一金属层(第一电源线VDD、数据线DN、补偿线SE、第一连接电极51和第二连接电极52)的下方保留有透明导电薄膜。
在示例性实施方式中，第一电源线VDD、数据线DN和补偿线SE相互平行，沿垂直方向延伸，第一电源线VDD设置在子像素的一侧，数据线DN和补偿线SE设置在子像素的另一侧。第一电源线VDD配置为向第一晶体管的第一源电极提供电源信号，数据线DN配置为向第二晶体管的第二源电极提供数据线号，补偿线SE配置为向第三晶体管的第三源电极提供补偿信号。
在示例性实施方式中，第一极板61配置为与后续形成的金属氧化物层中的第二极板形成存储电容。第一连接电极51与第一极板61连接，第一连接电极51一方面配置为连接后续形成的第一晶体管的第一漏电极和第三晶体管的第三漏电极，实现第一极板61与第一漏电极和第三漏电极的连接，另一方面作为第一晶体管T1的遮挡层。第二连接电极52配置为连接后续形成的第三晶体管的第三栅电极。
在示例性实施方式中，第一透明导电薄膜的厚度约为40nm～150nm，第 一金属薄膜的厚度约为100nm～1000nm。
在一些可能的实现方式中，第一导电层的第一极板可以配置为与后续形成的第二金属层形成存储电容。或者，第一导电层的第一极板可以配置为与后续形成的像素电极形成存储电容，像素电极与阳极同层设置，且通过同一次图案化工艺形成。
在一些可能的实现方式中，第一极板可以设置在第一金属层上，第一金属层的第一极板配置为与后续形成的第二金属层形成存储电容，或者，第一金属层的第一极板配置为与后续形成的像素电极形成存储电容。
(2)形成金属氧化物层图案。在示例性实施方式中，形成金属氧化物层图案可以包括：在形成前述图案的基底上，依次沉积第一绝缘薄膜和金属氧化物薄膜，通过图案化工艺对金属氧化物薄膜进行构图，形成覆盖第一极板61和第一金属层图案的第一绝缘层41，以及形成在第一绝缘层41上的第一有源层12、第二有源层22、第三有源层32和第二极板62图案，如图5和图6所示，图6为图5中A-A向的剖面图。
在示例性实施方式中，第一有源层12作为驱动TFT(第一晶体管T1)的有源(Active)层，第一有源层12在基底上正投影与第一连接电极51在基底上正投影存在交叠，第二有源层22作为开关TFT(第二晶体管T2)的有源层，第二有源层22与第二极板62连接，第三有源层32作为补偿TFT(第三晶体管T3)的有源层，第二极板62的位置与第一极板61的位置相对应，即第二极板62在基底上的正投影与第一极板61在基底上的正投影存在交叠，使第一极板61与第二极板62形成透明结构的存储电容。在一些可能的示例性实施方式中，第二极板62在基底上的正投影位于第一极板61在基底上的正投影范围之内。
在示例性实施方式中，金属氧化物层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物、包含铟和镓和锌的氧化物等。在一些可能的实现方式中，金属氧化物层可以采用透明的铟镓锌氧化物(IGZO)或铟锡锌氧化物(ITZO)。
在示例性实施方式中，第一绝缘薄膜的厚度约为200nm～1000nm，金属氧化物薄膜的厚度约为20nm～200nm。
在一些可能的实现方式中，金属氧化物层中的第二极板可以配置为与后续形成的第二金属层形成存储电容，或者可以配置为与后续形成的像素电极形成存储电容，或者可以配置为与第一金属层形成存储电容。
(3)形成第二绝缘层图案。在示例性实施方式中，形成第二绝缘层图案可以包括：在形成前述图案的基底上，沉积第二绝缘薄膜，通过半色调的图案化工艺对第二绝缘薄膜进行构图，形成第二绝缘层42图案以及开设在第一绝缘层41上的多个过孔图案，第二绝缘层42图案位于第一有源层12、第二有源层22和第三有源层32所在位置，多个过孔图案至少包括第一过孔K1、第二过孔K2、第三过孔K3、第四过孔K4、第五过孔K5和第六过孔K6，如图7和图8所示，图8为图7中A-A向的剖面图。
在示例性实施方式中，通过半色调的图案化工艺对第二绝缘薄膜进行构图可以包括：先在第二绝缘薄膜上涂覆一层光刻胶，采用半色调掩膜板对光刻胶进行曝光，显影后形成光刻胶图案，光刻胶图案包括未曝光区域、部分曝光区域和完全曝光区域，未曝光区域包括第一有源层12、第二有源层22和第三有源层32所在位置，未曝光区域的光刻胶具有第一厚度。完全曝光区域包括过孔图案所在位置，完全曝光区域的光刻胶被完全去除，暴露出第二绝缘薄膜的表面。其它区域为部分曝光区域，部分曝光区域的光刻胶具有第二厚度，第二厚度小于第一厚度。随后，采用第一次刻蚀工艺去除完全曝光区域的第二绝缘薄膜和第一绝缘层41，形成多个过孔图案。随后，采用灰化工艺去除部分曝光区域的光刻胶，使部分曝光区域暴露出第二绝缘薄膜。随后，采用第二次刻蚀工艺去除部分曝光区域的第二绝缘薄膜。最后，剥离剩余的光刻胶，形成第二绝缘层42图案以及开设在第一绝缘层41上的多个过孔图案。
在示例性实施方式中，多个过孔图案至少包括第一过孔K1、第二过孔K2、第三过孔K3、第四过孔K4、第五过孔K5和第六过孔K6。第一过孔K1位于第一连接电极51所在位置，暴露出第一连接电极51的表面，第一过孔K1配置为使后续形成的第一晶体管的第一漏电极和第三晶体管的第三漏 电极与第一连接电极51连接，实现第一极板61与第一漏电极和第三漏电极的连接。第二过孔K2位于第一电源线VDD所在位置，暴露出第一电源线VDD的表面，第二过孔K2配置为使后续形成的第一晶体管的第一源电极与第一电源线VDD连接。第三过孔K3和第四过孔K4分别位于第二连接电极52的两端，暴露出第二连接电极52的表面，第三过孔K3和第四过孔K4配置为分别连接后续形成的第二扫描线SN和第三晶体管的第三栅电极，实现第二扫描线SN与第三栅电极的连接。第五过孔K5位于数据线DN所在位置，暴露出数据线DN的表面，第五过孔K5配置为连接后续形成的第二晶体管的第二源电极，实现数据线DN与第二源电极的连接。第六过孔K6位于补偿线SE所在位置，暴露出补偿线SE的表面，第六过孔K6配置为连接后续形成的第三晶体管的第三源电极，实现补偿线SE与第三源电极的连接。
在示例性实施方式中，位于第二极板62所在位置的第二绝缘层42被去除，暴露出第二极板62。
在示例性实施方式中，位于第一有源层12、第二有源层22和第三有源层32所在位置的第二绝缘层42分别覆盖第一有源层12的部分区域、第二有源层22的部分区域和第三有源层32的部分区域。位于第一有源层12所在位置的第二绝缘层42覆盖第一有源层12的中部区域，且覆盖宽度大于第一有源层12沟道区域的设计宽度，未被第二绝缘层42覆盖的两侧区域暴露出第一有源层12的表面。位于第二有源层22所在位置的第二绝缘层42覆盖第二有源层22的中部区域，且覆盖宽度大于第二有源层22沟道区域的设计宽度，未被第二绝缘层42覆盖的两侧区域暴露出第二有源层22的表面。位于第三有源层32所在位置的第二绝缘层42覆盖第三有源层32的中部区域，且覆盖宽度大于第三有源层32沟道区域的设计宽度，未被第二绝缘层42覆盖的两侧区域暴露出第三有源层32的表面。这样，在后续进行第一次导体化处理时，第一有源层12、第二有源层22和第三有源层32均可以形成一个较宽的沟道区域。
在示例性实施方式中，第二绝缘薄膜的厚度约为100nm～500nm。
(4)第一次导体化处理。在示例性实施方式中，第一次导体化处理可以包括：在形成前述图案的基底上，对第一有源层12、第二有源层22和第三 有源层32未被第二绝缘层42覆盖的两侧区域以及第二极板62进行导体化处理，形成导体化的第二极板62，第一有源层12、第二有源层22和第三有源层32中被第二绝缘层42覆盖的中部区域形成沟道区域，未被第二绝缘层42覆盖的两侧区域均被处理成导体化区域12′，导体化区域12′分别作为第一有源层12的源连接区域和漏连接区域、第二有源层22的源连接区域和漏连接区域以及第三有源层32的源连接区域和漏连接区域，如图9所示。
(5)形成第二金属层图案。在示例性实施方式中，形成第二金属层图案可以包括：在形成有前述图案的基底上，沉积第二金属薄膜。在第二金属薄膜上涂覆一层光刻胶，通过掩膜、曝光和显影形成光刻胶图案，利用第一次刻蚀工艺刻蚀第二金属薄膜，形成第二金属层图案，保留第二金属层上的光刻胶100。第二金属层图案至少包括第一扫描线GN、第二扫描线SN、第一栅电极11、第二栅电极21、第三栅电极31、第一源电极13、第一漏电极14、第二源电极23、第二漏电极24、第三源电极33和第三漏电极34图案，如图10和图11所示，图11为图10中A-A向的剖面图。
在示例性实施方式中，第一扫描线GN和第二扫描线SN相互平行，沿水平方向延伸，均设置在子像素的下侧。第一扫描线GN可以是开关扫描线，配置为向第二晶体管的第二栅电极提供控制第二晶体管的开启/关闭信号，第二扫描线SN可以是补偿扫描线，配置为向第三晶体管的第三栅电极提供控制第三晶体管的开启/关闭信号，第二扫描线SN通过第四过孔K4与第二连接电极52连接。
在示例性实施方式中，第一栅电极11是与第二漏电极24相互连接的一体结构，第二栅电极21是与第一扫描线GN相互连接的一体结构，第三栅电极31通过第三过孔K3与第二连接电极52连接，由于第二连接电极52通过第四过孔K4与第二扫描线SN连接，因而使得第三栅电极31通过第二连接电极52与第二扫描线SN连接。
在示例性实施方式中，第一源电极13的第一端通过第二过孔K2与第一电源线VDD连接，第二端搭设在第一有源层12经过导体化处理的源连接区域上，形成与第一电源线VDD连接的第一源电极13。第一漏电极14的第一端搭设在第一有源层12经过导体化处理的漏连接区域上，且通过第一过孔 K1与第一连接电极51连接，实现第一漏电极14与第一极板61的连接，第一漏电极14的第二端搭设在第三有源层32经过导体化处理的漏连接区域上，形成一体结构的第一漏电极14和第三漏电极34。
在示例性实施方式中，第二源电极23的第一端通过第五过孔K5与数据线DN连接，第二端搭设在第二有源层22经过导体化处理的源连接区域上，形成与数据线DN连接的第二源电极23。第二漏电极24的第一端搭设在第二有源层22经过导体化处理的漏连接区域上，第二端搭设在第二有源层22未经过导体化处理的沟道区域上，形成一体结构的第二漏电极24和第一栅电极11，且实现第二漏电极24与第二极板62的连接。
在示例性实施方式中，第三源电极33的第一端通过第六过孔K6与补偿线SE连接，第二端搭设在第三有源层32经过导体化处理的源连接区域上，形成与补偿线SE连接的第三源电极33。第三漏电极34搭设在第三有源层32经过导体化处理的漏连接区域上，与第一漏电极14为相互连接的一体结构。
在示例性实施方式中，第一栅电极11、第一有源层12、第一源电极13和第一漏电极14构成第一晶体管T1，第二栅电极21、第二有源层22、第二源电极23和第二漏电极24构成第二晶体管T2，第三栅电极31、第三有源层32、第三源电极33和第三漏电极34构成第二晶体管T2，第一极板61和导体化的第二极板62构成透明结构的存储电容。
在示例性实施方式中，第二金属薄膜的厚度约为100nm～1000nm。
在一些可能的实现方式中，第二金属层可以形成电容极板，可以配置为与第一导电层形成存储电容，或者可以配置为与第一金属层形成存储电容，或者可以配置为与金属氧化物层形成存储电容，或者可以配置为与后续形成的像素电极形成存储电容。
(6)第二次刻蚀处理。在示例性实施方式中，第二次刻蚀处理可以包括：以第二金属层图案和保留在第二金属层上的光刻胶100为掩膜，通过第二次刻蚀工艺自对准向下刻蚀第二绝缘层42，去除第一有源层12、第二有源层22和第三有源层32上未被第二金属层图案覆盖的第二绝缘层42，如图12 所示。在示例性实施方式中，由于第一栅电极11、第二栅电极21和第三栅电极31的宽度很小，约为6μm～10μm，因而最终保留下来的第二绝缘层42的宽度与第二金属层的宽度接近，第一有源层12、第二有源层22和第三有源层32上第二绝缘层42的宽度与相应有源层沟道区域的设计宽度接近。在示例性实施例中，第一栅电极11在基底上正投影的边界位于第二绝缘层42在基底上正投影的边界范围内，有源层沟道区域在基底上正投影的边界位于第二绝缘层42在基底上正投影的边界范围内。
(7)第二次导体化处理。在示例性实施方式中，第二次导体化处理可以包括：以第二绝缘层42、设置在第二绝缘层42上的第二金属层图案以及保留在第二金属层上的光刻胶100为掩膜，对第一有源层12、第二有源层22和第三有源层32进行第二次导体化处理，同时对第二极板62进行第二次导体化处理，形成相应有源层的沟道区域和二次导体化的第二极板62，剥离剩余的光刻胶，如图13所示。由于第二次导体化处理是利用第二绝缘层42、第二金属层图案以及光刻胶100作为掩膜，是一种自对准导体化处理工艺，因而最终形成的沟道宽度分别与第一栅电极11、第二栅电极21和第三栅电极31的宽度基本上相同。第一有源层12的沟道区域在基底上正投影与第一连接电极51在基底上正投影存在交叠，使第一连接电极51遮挡第一有源层12的沟道区域。本公开示例性实施例通过自对准导体化处理工艺，大幅度提升了栅电极与下方沟道区域之间的对位精度，极大地提升了薄膜晶体管的电学特性。
在示例性实施方式中，第一有源层经过两次导体化处理，使得第一有源层形成三个区域：位于中部的沟道区域，位于沟道区域两侧的源过渡区域和漏过渡区域，以及位于源过渡区域远离沟道区域一侧的源连接区域和位于所述漏过渡区域远离沟道区域一侧的漏连接区域。沟道区域在基底上正投影的边界与第一栅电极在基底上正投影的边界基本上重叠，源连接区域与第一源电极连接，被第一源电极覆盖，漏连接区域与第一漏电极连接，被第一漏电极覆盖，源过渡区域位于沟道区域与源连接区域之间，即位于第一栅电极与第一源电极之间的区域，漏过渡区域位于沟道区域与漏连接区域之间，即位于第一栅电极与第一漏电极之间的区域。同样，第二有源层和第三有源层也 会形成三个区域。由于采用两次导体化处理，第一次导体化处理的区域与第二次导体化处理的区域有重叠(如图13中的黑色区域所示)，因而源过渡区域和漏过渡区域中均包含经过两次导体化处理的第一区域12A和只经过第二次导体化处理的第二区域12B，第一区域12A远离沟道区域，第二区域12B邻近沟道区域。在示例性实施方式中，经过两次导体化处理的第一区域12A受到两次氦(He)等离子处理，膜层内氧元素含量进一步降低，第一区域12A对应的第一有源层的氧元素含量小于第二区域12B对应的第一有源层的氧元素含量，有利于提高薄膜晶体管的电学特性。在示例性实施方式中，经过两次导体化处理的第一区域12A的电阻更低，导电能力更强，第一区域12A对应的第一有源层的导电率高于第二区域12B对应的第一有源层的导电率，有利于提高薄膜晶体管的电学特性。在示例性实施方式中，第一区域12A对应的第一有源层的氧元素含量小于第二区域12B对应的第一有源层的氧元素含量，以及第一区域12A对应的第一有源层的导电率高于第二区域12B对应的第一有源层的导电率。由于源连接区域和漏连接区域只经过第一次导体化处理，因而第一区域12A对应的第一有源层的导电率高于源连接区域和漏连接区域对应的第一有源层的导电率，第一区域12A对应的第一有源层的氧元素含量小于源连接区域和漏连接区域对应的第一有源层的氧元素含量。由于第二极板62是经过两次导体化处理，因而提高了第二极板62的导电能力，有利于提高像素驱动电路的驱动特性。在示例性实施方式中，第二极板62对应的金属氧化物层的导电率高于第二区域12B对应的第一有源层的导电率，或者，第二极板62对应的金属氧化物层的氧元素含量小于第二区域12B对应的第一有源层的氧元素含量。
本公开示例性实施例两次导体化处理过程中，对第二绝缘层进行了两次刻蚀处理，刻蚀过程的过刻会刻蚀掉第一有源层12的部分厚度，因而第一区域12A对应的第一有源层的厚度变薄，第一区域12A对应的第一有源层的厚度小于第二区域12B对应的第一有源层的厚度，第一区域12A对应的第一有源层的厚度小于源连接区域和漏连接区域对应的第一有源层的厚度，第一区域12A对应的第一有源层的厚度小于沟道区域对应的第一有源层的厚度，有利于提高导体化效果。在示例性实施方式中，第二极板62对应的金属氧化物层的厚度小于第二区域12B对应的第一有源层的厚度。
(8)形成第三绝缘层图案。在示例性实施方式中，形成第三绝缘层图案可以包括：在形成有前述图案的基底上，沉积第三绝缘薄膜，形成覆盖前述结构的第三绝缘层43，如图14所示。
在示例性实施方式中，第三绝缘薄膜的厚度约为200nm～1000nm。
(9)形成彩膜层图案。在示例性实施方式中，形成彩膜层图案可以包括：在形成有前述图案的基底上，依次通过图案化工艺分别形成第一颜色单元、第二颜色单元和第三颜色单元，形成彩膜层70，如图15所示。在示例性实施方式中，彩膜层70形成在发光区和电容区，第一颜色单元可以为绿色单元，第二颜色单元可以为红色单元，第三颜色单元可以为蓝色单元。在一些可能的实现方式中，彩膜层70可以包括其它颜色单元，例如白色或黄色。
(10)形成平坦层图案。在示例性实施方式中，形成平坦层图案可以包括：在形成有前述图案的基底上，涂覆一层平坦薄膜，利用平坦薄膜作为光刻胶，掩膜、曝光和显影后，对第三绝缘层43进行刻蚀，形成覆盖前述结构的平坦层44，平坦层44上形成有第七过孔K7，第七过孔K7位于第一漏电极14所在位置，第七过孔K7内的平坦层44和第三绝缘层43被去掉，暴露出第一漏电极14的表面，如图16所示。
(11)形成阳极图案。在示例性实施方式中，形成阳极图案可以包括：在形成前述图案的基底上，沉积第二透明导电薄膜，通过图案化工艺对第二透明导电薄膜进行构图，形成阳极81图案，阳极81通过第七过孔K7与第一漏电极14连接，如图17所示。在示例性实施方式中，阳极81为透明阳极。
(12)形成像素定义层图案。在示例性实施方式中，形成像素定义层图案可以包括：在形成前述图案的基底上涂覆像素定义薄膜，通过掩膜、曝光和显影工艺形成像素定义层(Pixel Define Layer)82图案，像素定义层82限定出暴露阳极81的开口区域，如图18所示。
(13)形成有机发光层、阴极和封装层等图案，制备方式与相关技术相同，这里不再赘述。在示例性实施方式中，阴极为反射阴极。
在示例性实施方式中，有机发光层可以包括依次叠设的第一发光子层、第一电荷产生层、第二发光子层、第二电荷产生层和第三发光子层。第一发 光子层配置为出射第一颜色光，包括依次叠设的第一空穴传输层(HTL)、第一发光材料层(EML)和第一电子传输层(ETL)。第二发光子层配置为出射第二颜色光，包括依次叠设的第二空穴传输层、第二发光材料层和第二电子传输层。第三发光子层配置为出射第三颜色光，包括依次叠设的第三空穴传输层、第三发光材料层和第三电子传输层。第一电荷产生层设置在第一发光子层与第二发光子层之间，配置为将两个发光子层串联起来，实现载流子的传递。第二电荷产生层设置在第二发光子层与第三发光子层之间，配置为将两个发光子层串联起来，实现载流子的传递。由于有机发光层包括出射第一颜色光的第一发光材料层、出射第二颜色光的第二发光材料层和出射第三颜色光的第三发光材料层，因而有机发光层最终出射的光为混合光。例如，可以设置第一发光材料层是出射红光的红光材料层，第二发光材料层是出射绿光的绿光材料层，第三发光材料层是出射蓝光的蓝光材料层，因而有机发光层最终出射白光。在示例性实施方式中，可以根据实际需要设计有机发光层的结构。例如，每个发光子层中，为了提高电子和空穴注入发光材料层的效率，可以设置空穴注入层(HIL)和电子注入层(EIL)。又如，为了简化有机发光层的结构，可以取消第一电子传输层、第一电荷产生层和第二空穴传输层，即第二发光材料层可以直接设置在第一发光材料层上。
在示例性实施方式中，第一绝缘层、第二绝缘层和第三绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，配置为提高基底的抗水氧能力，第二绝缘层称为栅绝缘(GI)层，第三绝缘层称为钝化(PVX)层。第一金属薄膜和第二金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者是多层复合结构，如Ti/Al/Ti等。第一透明导电薄膜和第二透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)。
如图3～图18所示，通过前述制备过程形成的显示基板可以包括：
基底10；
设置在基底10上的透明的第一极板61；
设置在基底10上的透明导电薄膜以及设置在透明导电薄膜上的第一金属层，第一金属层至少包括第一电源线VDD和第一连接电极51，第一连接电极51与第一极板61连接；
覆盖第一极板61和第一金属层的第一绝缘层41，第一绝缘层41上设置有第一过孔K1和第二过孔K2，第一过孔K1暴露出第一连接电极51，第二过孔K2暴露出第一电源线VDD；
设置在第一绝缘层41上的金属氧化物层，金属氧化物层至少包括第一有源层12和经过两次导体化处理的第二极板62，第二极板62在基底10上的正投影与第一极板61在基底10上的正投影存在交叠，以形成透明的存储电容；第一有源层12包括三个区域：位于中部的沟道区域、位于沟道区域两侧的源过渡区域和漏过渡区域、以及位于源过渡区域远离沟道区域一侧的源连接区域和位于漏过渡区域远离沟道区域一侧的漏连接区域；第一有源层12的沟道区域在基底10上的正投影与第一连接电极51在基底10上的正投影存在交叠；
设置在第一有源层12上的第二绝缘层42以及设置在第二绝缘层42上的第一栅电极11，第一栅电极11在基底上正投影的边界位于第二绝缘层42在基底上正投影的边界范围内，第一有源层12的沟道区域在基底上正投影的边界位于第二绝缘层42在基底上正投影的边界范围内。
设置在第一绝缘层41上的第一源电极13和第一漏电极14，第一源电极13的第一端通过第二过孔K2与第一电源线VDD连接，第一源电极13的第二端搭设在第一有源层12的源连接区域上；第一漏电极14搭设在第一有源层12的漏连接区域上，且通过第一过孔K1与第一连接电极51连接；
覆盖前述结构的第三绝缘层43；
设置在第三绝缘层43上的彩膜层70；
覆盖前述结构的平坦层44，平坦层44上设置有暴露出第一漏电极14的第七过孔K7；
设置在平坦层44上的阳极81，阳极81通过第七过孔K7与第一漏电极14连接。
在示例性实施方式中，显示基板还可以包括像素定义层、有机发光层、阴极和封装层等。
在示例性实施方式中，第一有源层12的源过渡区域位于第一栅电极11与第一源电极13之间，第一有源层12的漏过渡区域位于第一栅电极11与第一漏电极14之间，源过渡区域和漏过渡区域的第二绝缘层42通过自对准刻蚀方式被去除。
在示例性实施方式中，第一有源层12的源连接区域和漏连接区域通过第一次导体化处理形成，第一有源层12的沟道区域在自对准的第二次导体化处理过程中形成。
一种透明电容结构的显示基板的像素电路层包括遮挡层、透明导电层、缓冲层、半导体层、栅绝缘层、栅金属层、层间绝缘层和源漏金属层，需要6次图案化工艺，图案化工艺次数多，工艺流程复杂，生产成本较高，产能较低。本公开示例性实施例所提供的显示基板的像素电路层，第一导电层和第一金属层通过同一次图案化工艺形成，栅电极、源电极和漏电极同层设置且通过同一次图案化工艺形成，只需要4次图案化工艺，最大限度地减少了图案化工艺次数。本公开示例性示例性制备显示基板的方法减少了图案化工艺次数，缩短了工艺时间，降低了工艺成本，工艺兼容性好，工艺可实现性高，实用性强，非常具有量产性，具有良好的应用前景。
一种显示基板的制备工艺中，是在形成第二绝缘层之后、形成第二金属层之前进行导体化处理，形成固定位置和长度的沟道区域。但在后续形成栅电极图案时，由于图案化工艺的对位精度限制，栅电极的位置容易偏离沟道区域的位置，栅电极很难对位在沟道区域的正上方，栅电极与沟道区域对位精度低。栅电极与沟道区域对位出现偏差会降低薄膜晶体管的电学特性，导致开启电压增大、电流减小，影响了产品性能。本公开示例性实施例提出了两次导体化处理的方案，第一次导体化处理是在形成第二金属层之前，通过第一次导体化处理形成一个较宽的沟道区域，第二次导体化处理是在形成第二金属层后，在自对准的第二次导体化处理过程中形成的沟道区域与栅电极具有较高的对位精度，大幅度提升了栅电极与下方沟道区域之间的对位精度，极大地提升了薄膜晶体管的电学特性。
本公开示例性示例性通过采用透明材料的第一极板和第二极板，形成了透明结构的存储电容，节省了电容占用版图的面积，有效提高了像素开口率，适用于高PPI显示。
本公开示例性示例性通过两次第二绝缘层刻蚀和两次导体化处理，使得沟道区域两侧的源连接区域和漏连接区域的电阻更低，导电能力更强，有利于提高薄膜晶体管的电学特性。
在另一种示例性实施方式中，显示基板的制备过程可以包括如下操作，如图19～图25所示。
(21)形成第一极板和第一金属层图案，形成方式与前述工艺(1)相同。
(22)形成金属氧化物层图案，形成方式与前述工艺(2)相同。
(23)形成第二绝缘层图案。在示例性实施方式中，形成第二绝缘层图案可以包括：在形成前述图案的基底上，沉积第二绝缘薄膜，通过图案化工艺对第二绝缘薄膜进行构图，形成覆盖第一有源层12、第二有源层22和第三有源层32的第二绝缘层42，第二绝缘层42上开设有多个过孔图案，多个过孔至少包括第一过孔K1、第二过孔K2、第三过孔K3、第四过孔K4、第五过孔K5、第六过孔K6、第一有源过孔V1和第二有源过孔V2，如图19和图20所示，图20为图10中A-A向的剖面图。
在示例性实施方式中，位于第二极板62所在位置的第二绝缘层42被去除，暴露出第二极板62。
在示例性实施方式中，第一过孔K1、第二过孔K2、第三过孔K3、第四过孔K4、第五过孔K5和第六过孔K6内的第一绝缘层41和第二绝缘层42被刻蚀掉。第一过孔K1位于第一连接电极51所在位置，暴露出第一连接电极51的表面，第一过孔K1配置为使后续形成的第一漏电极和第三漏电极与第一连接电极51连接，实现第一极板61与第一漏电极和第三漏电极的连接。第二过孔K2位于第一电源线VDD所在位置，暴露出第一电源线VDD的表面，第二过孔K2配置为使后续形成的第一源电极与第一电源线VDD连接。第三过孔K3和第四过孔K4分别位于第二连接电极52的两端，暴露出第二连接电极52的表面，第三过孔K3和第四过孔K4配置为分别连接后续形成 的第二扫描线SN和第三栅电极，实现第二扫描线SN与第三栅电极的连接。第五过孔K5位于数据线DN所在位置，暴露出数据线DN的表面，第五过孔K5配置为连接后续形成的第二源电极，实现数据线DN与第二源电极的连接。第六过孔K6位于补偿线SE所在位置，暴露出补偿线SE的表面，第六过孔K6配置为连接后续形成的第三源电极，实现补偿线SE与第三源电极的连接。
在示例性实施方式中，第一有源过孔V1和第二有源过孔V2内的第二绝缘层42被刻蚀掉，分别暴露出第一有源层12、第二有源层22和第三有源层32两侧区域的部分表面。第一有源过孔V1和第二有源过孔V2之间的距离大于第一有源层12、第二有源层22和第三有源层32沟道区域的设计宽度。这样，在后续进行第一次导体化处理时，第一有源层12、第二有源层22和第三有源层32均可以形成一个较宽的沟道区域。
(24)第一次导体化处理。在示例性实施方式中，第一次导体化处理可以包括：在形成前述图案的基底上，对第二极板62以及第一有源过孔V1和第二有源过孔V2暴露出的有源层进行导体化处理，形成导体化的第二极板62，在第一有源层12、第二有源层22和第三有源层32的两侧形成导体化区域12′，导体化区域12′分别作为第一有源层12的源连接区域和漏连接区域、第二有源层22的源连接区域和漏连接区域以及第三有源层32的源连接区域和漏连接区域，如图21所示。
(25)形成第二金属层图案。在示例性实施方式中，形成第二金属层图案可以包括：在形成有前述图案的基底上，沉积第二金属薄膜。在第二金属薄膜上涂覆一层光刻胶，通过掩膜、曝光和显影形成光刻胶图案，利用第一次刻蚀工艺刻蚀第二金属薄膜，形成第二金属层图案，保留第二金属层上的光刻胶100。第二金属层图案至少包括第一扫描线GN、第二扫描线SN、第一栅电极11、第二栅电极21、第三栅电极31、第一源电极13、第一漏电极14、第二源电极23、第二漏电极24、第三源电极33和第三漏电极34图案，如图22和图23所示，图23为图22中A-A向的剖面图。
在示例性实施方式中，第一扫描线GN和第二扫描线SN相互平行，沿水平方向延伸，均设置在子像素的下侧。第一扫描线GN可以是开关扫描线， 配置为向第二晶体管的第二栅电极提供控制第二晶体管的开启/关闭信号，第二扫描线SN可以是补偿扫描线，配置为向第三晶体管的第三栅电极提供控制第三晶体管的开启/关闭信号，第二扫描线SN通过第四过孔K4与第二连接电极52连接。
在示例性实施方式中，第一栅电极11是与第二漏电极24相互连接的一体结构，第二栅电极21是与第一扫描线GN相互连接的一体结构，第三栅电极31通过第三过孔K3与第二连接电极52连接，由于第二连接电极52通过第四过孔K4与第二扫描线SN连接，因而使得第三栅电极31通过第二连接电极52与第二扫描线SN连接。
在示例性实施方式中，第一源电极13的第一端通过第二过孔K2与第一电源线VDD连接，第二端通过第二有源过孔V2与第一有源层12的源连接区域连接，形成与第一电源线VDD连接的第一源电极13。第一漏电极14的第一端通过第一有源过孔V1与第一有源层12的漏连接区域连接，且通过第一过孔K1与第一连接电极51连接，实现第一漏电极14与第一极板61的连接，第二端通过第一有源过孔V1与第三有源层32连接，形成一体结构的第一漏电极14和第三漏电极34。
在示例性实施方式中，第二源电极23的第一端通过第五过孔K5与数据线DN连接，第二端通过第二有源过孔V2与第二有源层22的源连接区域连接，形成与数据线DN连接的第二源电极23。第二漏电极24的第一端通过第一有源过孔V1与第二有源层22的漏连接区域连接，第二端搭设在第二有源层22未经过导体化处理的沟道区域上，形成一体结构的第二漏电极24和第一栅电极11，且实现第二漏电极24与第二极板62的连接。
在示例性实施方式中，第三源电极33的第一端通过第六过孔K6与补偿线SE连接，第二端通过第二有源过孔V2与第三有源层32的源连接区域连接，形成与补偿线SE连接的第三源电极33。第三漏电极34通过第一有源过孔V1与第三有源层32的漏连接区域连接，与第一漏电极14为相互连接的一体结构。
在示例性实施方式中，第一栅电极11、第一有源层12、第一源电极13和第一漏电极14构成第一晶体管T1，第二栅电极21、第二有源层22、第二 源电极23和第二漏电极24构成第二晶体管T2，第三栅电极31、第三有源层32、第三源电极33和第三漏电极34构成第二晶体管T2，第一极板61和导体化的第二极板62构成透明结构的存储电容。
(26)第二次刻蚀处理。在示例性实施方式中，第二次刻蚀处理可以包括：以第二金属层图案和保留在第二金属层上的光刻胶100为掩膜，通过第二次刻蚀工艺自对准向下刻蚀第二绝缘层42，去除第一有源层12、第二有源层22和第三有源层32上未被第二金属层图案覆盖的第二绝缘层42，如图24所示。
在示例性实施方式中，可以通过适量的过刻处理，部分去除第一源电极13和第一漏电极14朝向第一栅电极11的侧面，不仅使第一源电极13和第一漏电极14朝向第一栅电极11的侧面平齐，而且使第一有源过孔内的部分导体化区域12′和第二有源过孔内的部分导体化区域12′暴露出来。
(27)第二次导体化处理。在示例性实施方式中，第二次导体化处理可以包括：以第二绝缘层42、设置在第二绝缘层42的第二金属层图案和保留在第二金属层上的光刻胶100为掩膜，对第一有源层12、第二有源层22和第三有源层32进行第二次导体化处理，同时对第二极板62进行第二次导体化处理，形成相应有源层的沟道和二次导体化的第二极板62，剥离剩余的光刻胶，如图25所示。由于第二次导体化处理是利用第二绝缘层42、第二金属层图案以及光刻胶100作为掩膜，是一种自对准导体化处理工艺，因而最终形成的沟道宽度与第一栅电极11、第二栅电极21和第三栅电极31的宽度基本上相同。第一有源层12的沟道区域在基底上正投影与第一连接电极51在基底上正投影存在交叠，使第一连接电极51遮挡第一有源层12的沟道区域。本公开示例性实施例通过自对准导体化处理工艺，大幅度提升了栅电极与下方沟道之间的对位精度，极大地提升了薄膜晶体管的电学特性。
在示例性实施方式中，第一有源层经过两次导体化处理，使得第一有源层形成三个区域：位于中部的沟道区域，位于沟道区域两侧的源过渡区域和漏过渡区域，以及位于源过渡区域远离沟道区域一侧的源连接区域和位于所述漏过渡区域远离沟道区域一侧的漏连接区域。沟道区域在基底上正投影的边界与第一栅电极在基底上正投影的边界基本上重叠，源连接区域与第一源 电极连接，漏连接区域与第一漏电极连接，源过渡区域位于沟道区域与源连接区域之间，即位于第一栅电极与第一源电极之间的区域，漏过渡区域位于沟道区域与漏连接区域之间，即位于第一栅电极与第一漏电极之间的区域。同样，第二有源层和第三有源层也会形成三个区域。由于采用两次导体化处理，第一次导体化处理的区域与第二次导体化处理的区域有重叠(如图25中的黑色区域12”所示)，因而源过渡区域和漏过渡区域均中均包含经过两次导体化处理的第一区域12A和只经过第二次导体化处理的第二区域12B。经过两次导体化处理的第一区域12A受到两次氦(He)等离子处理，膜层内氧元素含量进一步降低，第一区域12A对应的第一有源层的氧元素含量小于第二区域12B对应的第一有源层的氧元素含量，电阻更低，导电能力更强，第一区域12A对应的第一有源层的导电率高于第二区域12B对应的第一有源层的导电率，有利于提高薄膜晶体管的电学特性。由于源连接区域和漏连接区域只经过第一次导体化处理，因而第一区域12A对应的第一有源层的导电率高于源连接区域和漏连接区域对应的第一有源层的导电率，第一区域12A对应的第一有源层的氧元素含量小于源连接区域和漏连接区域对应的第一有源层的氧元素含量。由于第二极板62是经过两次导体化处理，因而提高了第二极板62的导电能力，有利于提高像素驱动电路的驱动特性。在示例性实施方式中，第二极板62对应的金属氧化物层的导电率高于第二区域12B对应的第一有源层的导电率，或者，第二极板62对应的金属氧化物层的氧元素含量小于第二区域12B对应的第一有源层的氧元素含量。
本公开示例性实施例两次导体化处理过程中，对第二绝缘层进行了两次刻蚀处理，刻蚀过程的过刻会刻蚀掉第一有源层12的部分厚度，因而第一区域12A对应的第一有源层的厚度变薄，第一区域12A对应的第一有源层的厚度小于第二区域12B对应的第一有源层的厚度，第一区域12A对应的第一有源层的厚度小于源连接区域和漏连接区域对应的第一有源层的厚度，第一区域12A对应的第一有源层的厚度小于沟道区域对应的第一有源层的厚度，有利于提高导体化效果。在示例性实施方式中，第二极板62对应的金属氧化物层的厚度小于第二区域12B对应的第一有源层的厚度。
后续形成第三绝缘层、彩膜层、平坦层、阳极、像素定义层、有机发光 层、阴极和封装层等图案形成方式可以与前述工艺(8)～(13)相同。
如图19～图25所示，通过前述制备过程形成的显示基板可以包括：
基底10；
设置在基底10上的透明的第一极板61；
设置在基底10上的透明导电薄膜以及设置在透明导电薄膜上的第一金属层，第一金属层至少包括第一电源线VDD和第一连接电极51，第一连接电极51与第一极板61连接；
覆盖第一极板61和第一金属层的第一绝缘层41；
设置在第一绝缘层41上的金属氧化物层，金属氧化物层至少包括第一有源层12和经过两次导体化处理的第二极板62，第二极板62在基底10上的正投影与第一极板61在基底10上的正投影存在交叠，以形成透明的存储电容；第一有源层12包括三个区域：位于中部的沟道区域、位于沟道区域两侧的源过渡区域和漏过渡区域、以及位于源过渡区域远离沟道区域一侧的源连接区域和位于漏过渡区域远离沟道区域一侧的漏连接区域；第一有源层12的沟道区域在基底10上的正投影与第一连接电极51在基底10上的正投影存在交叠；
设置在第一有源层12的第二绝缘层42，第二绝缘层42上设置有第一过孔K1、第二过孔K2、第一有源过孔V1和第二有源过孔V2，第一过孔K1暴露出第一连接电极51，第二过孔K2暴露出第一电源线VDD，第一有源过孔V1暴露出第一有源层12经过导体化处理的漏连接区域，第二有源过孔V2暴露出第一有源层12经过导体化处理的源连接区域；
设置在第二绝缘层42上的第一栅电极11、第一源电极13和第一漏电极14；第一栅电极11在基底上正投影的边界位于第二绝缘层42在基底上正投影的边界范围内，第一有源层12的沟道区域在基底上正投影的边界位于第二绝缘层42在基底上正投影的边界范围内；第一源电极13的第一端通过第二过孔K2与第一电源线VDD连接，第一源电极13的第二端通过第二有源过孔V2与第一有源层12的源连接区域连接；第一漏电极14通过第一有源过孔V1与第一有源层12的漏连接区域连接，且通过第一过孔K1与第一连接 电极51连接；
覆盖前述结构的第三绝缘层43；
设置在第三绝缘层43上的彩膜层70；
覆盖前述结构的平坦层44，平坦层44上设置有暴露出第一漏电极14的第七过孔K7；
设置在平坦层44阳极81，阳极81通过第七过孔K7与第一漏电极14连接。
在示例性实施方式中，显示基板还可以包括像素定义层、有机发光层、阴极和封装层等。
在示例性实施方式中，第一有源层12的源过渡区域位于第一栅电极11与第一源电极13之间，第一有源层12的漏过渡区域位于第一栅电极11与第一漏电极14之间，源过渡区域和漏过渡区域的第二绝缘层42通过自对准刻蚀方式被去除。
在示例性实施方式中，第一有源层12的源连接区域和漏连接区域通过第一次导体化处理形成，第一有源层12的沟道区域在自对准的第二次导体化处理过程中形成。
本公开示例性实施例提出了四次图案化工艺形成显示基板的像素电路层的方案，第一导电层和第一金属层通过同一次图案化工艺形成，栅电极、源电极和漏电极同层设置且通过同一次图案化工艺形成，减少了图案化工艺次数，缩短了工艺时间，降低了工艺成本，工艺兼容性好，工艺可实现性高，实用性强，非常具有量产性，具有良好的应用前景。
本公开示例性实施例提出了两次导体化处理的方案，第一次导体化处理是在形成第二金属层之前，通过第一次导体化处理形成一个较宽的沟道区域，第二次导体化处理是在形成第二金属层后，在自对准的第二次导体化处理过程中形成的沟道区域与栅电极具有较高的对位精度，大幅度提升了栅电极与下方沟道区域之间的对位精度，极大地提升了薄膜晶体管的电学特性。
本公开示例性实施例还提供了一种显示基板的制备方法。在示例性实施方式中，显示基板的制备方法可以包括：
S1、在基底上依次形成第一导电层、第一金属层和金属氧化物层，所述金属氧化物层包括第一有源层；
S2、依次形成第二绝缘层和第二金属层，通过两次导体化处理使所述第一有源层形成沟道区域、位于所述沟道区域两侧的源过渡区域和漏过渡区域、以及位于所述源过渡区域远离沟道区域一侧的源连接区域和位于所述漏过渡区域远离沟道区域一侧的漏连接区域；所述第二金属层包括第一栅电极、第一源电极和第一漏电极，所述源连接区域与所述第一源电极连接，所述漏连接区域与所述第一漏电极连接；所述源过渡区域和漏过渡区域均包括远离所述沟道区域的第一区域和邻近所述沟道区域的第二区域；所述第一区域对应的第一有源层的导电率高于所述第二区域对应的第一有源层的导电率，或者，所述第一区域对应的第一有源层的氧元素含量小于所述第二区域对应的第一有源层的氧元素含量，或者，所述第一区域对应的第一有源层的厚度小于所述第二区域对应的第一有源层的厚度。
在示例性实施方式中，所述第一导电层包括第一极板，所述金属氧化物层还包括第二极板，所述第二极板在基底上的正投影与所述第一极板在基底上的正投影存在交叠区域。
在示例性实施方式中，步骤S1可以包括：
在基底上形成透明的第一极板和第一金属层，所述第一金属层与基板之间设置有透明导电薄膜；所述第一金属层包括第一电源线和第一连接电极，所述第一连接电极与第一极板连接；
形成覆盖所述第一极板和第一金属层的第一绝缘层；
在所述第一绝缘层上形成金属氧化物层，所述金属氧化物层包括第一有源层和第二极板，所述第二极板在基底上的正投影与所述第一极板在基底上的正投影存在交叠区域，所述第一有源层的沟道区域在基底上的正投影与所述第一连接电极在基底上的正投影存在交叠区域。
在一种示例性实施方式中，步骤S2可以包括：
在所述第一有源层上形成第二绝缘层，在所述第一绝缘层上形成第一过孔和第二过孔；所述第二绝缘层覆盖所述第一有源层的中部区域；所述第一过孔和第二过孔分别暴露出所述第一连接电极和第一电源线；
对所述第二极板和所述第一有源层未被所述第二绝缘层覆盖的两侧区域进行第一次导体化处理，形成导体化的第二极板，在所述第一有源层的两侧分别形成源连接区域和漏连接区域；
形成第二金属层，保留所述第二金属层上的光刻胶；所述第二金属层包括第一栅电极、第一源电极和第一漏电极；所述第一栅电极位于所述第一有源层的中部区域，所述第一漏电极搭设在所述漏连接区域上，并通过所述第一过孔与所述第一连接电极连接；所述第一源电极的第一端通过所述第二过孔与所述第一电源线连接，所述第一源电极的第二端搭设在所述源连接区域上；
以所述第二金属层和设置在所述第二金属层上的光刻胶为掩膜，刻蚀未被所述第二金属层覆盖的第二绝缘层；
以所述第二绝缘层、设置在所述第二绝缘层上的第二金属层以及设置在所述第二金属层上的光刻胶为掩膜，对所述第二极板和未被所述第二绝缘层覆盖的第一有源层进行第二次导体化处理，形成第一有源层的沟道区域以及位于沟道区域两侧的源过渡区域和漏过渡区域，所述第一栅电极在基底上正投影的边界位于所述第二绝缘层在基底上正投影的边界范围内；所述沟道区域在基底上正投影的边界位于所述第二绝缘层在基底上正投影的边界范围内，所述源过渡区域和漏过渡区域均包括远离所述沟道区域的第一区域和邻近所述沟道区域的第二区域；所述第一区域对应的第一有源层的导电率高于所述第二区域对应的第一有源层的导电率，或者，所述第一区域对应的第一有源层的氧元素含量小于所述第二区域对应的第一有源层的氧元素含量，或者，所述第一区域对应的第一有源层的厚度小于所述第二区域对应的第一有源层的厚度。
在另一种示例性实施方式中，步骤S2可以包括：
形成覆盖所述第一有源层的第二绝缘层，所述第二绝缘层上形成有第一 过孔、第二过孔、第一有源过孔和第二有源过孔，所述第一过孔和第二过孔分别暴露出所述第一连接电极和第一电源线，所述第一有源过孔和第二有源过孔分别暴露出所述第一有源层两侧的部分区域；
对所述第二极板以及所述第一有源过孔和第二有源过孔内暴露出的第一有源层进行第一次导体化处理，形成导体化的第二极板以及所述第一有源层的源连接区域和漏连接区域；
形成第二金属层，保留所述第二金属层上的光刻胶；所述第二金属层包括第一栅电极、第一源电极和第一漏电极；所述第一栅电极位于所述有源层的中部区域，所述第一漏电极通过所述第二有源过孔与所述漏连接区域连接，并通过所述第一过孔与所述第一连接电极连接；所述第一源电极的第一端通过所述第二过孔与所述第一电源线连接，所述第一源电极的第二端通过所述第一有源过孔与所述源连接区域连接；
以所述第二金属层和设置在所述第二金属层上的光刻胶为掩膜，刻蚀未被所述第二金属层覆盖的第二绝缘层；
以所述第二绝缘层、设置在所述第二绝缘层上的第二金属层以及设置在所述第二金属层上的光刻胶为掩膜，对所述第二极板和未被所述第二绝缘层覆盖的第一有源层进行第二次导体化处理，形成第一有源层的沟道区域以及位于沟道区域两侧的源过渡区域和漏过渡区域，所述第一栅电极在基底上正投影的边界位于所述第二绝缘层在基底上正投影的边界范围内；所述沟道区域在基底上正投影的边界位于所述第二绝缘层在基底上正投影的边界范围内，所述源过渡区域和漏过渡区域均包括远离所述沟道区域的第一区域和邻近所述沟道区域的第二区域；所述第一区域对应的第一有源层的导电率高于所述第二区域对应的第一有源层的导电率，或者，所述第一区域对应的第一有源层的氧元素含量小于所述第二区域对应的第一有源层的氧元素含量，或者，所述第一区域对应的第一有源层的厚度小于所述第二区域对应的第一有源层的厚度。
在示例性实施方式中，刻蚀未被所述第二金属层覆盖的第二绝缘层，包括：
通过自对准刻蚀方式去除所述第一栅电极与第一源电极之间的第二绝缘层以及所述第一栅电极与第一漏电极之间的第二绝缘层。
本公开示例性实施例提供了一种显示基板及其制备方法、显示装置，栅电极、源电极和漏电极同层设置且通过同一次图案化工艺形成，只需要4次图案化工艺，最大限度地减少了图案化工艺次数。通过两次导体化处理，大幅度提升了栅电极与下方沟道区域之间的对位精度，极大地提升了薄膜晶体管的电学特性。本公开示例性实施例显示基板的制备方法减少了图案化工艺次数，缩短了工艺时间，降低了工艺成本，工艺兼容性好，工艺可实现性高，实用性强，非常具有量产性，具有良好的应用前景。
有关显示基板的制备过程，已在之前的实施例中详细说明，这里不再赘述。
本公开还提供了一种显示装置，包括前述的显示基板。显示装置可以是手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本申请的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种显示基板，包括在基底上叠设的第一导电层、第一金属层、金属氧化物层、第二绝缘层和第二金属层；所述金属氧化物层包括第一有源层，所述第二金属层包括第一栅电极、第一源电极和第一漏电极；所述第一有源层包括沟道区域、位于所述沟道区域两侧的源过渡区域和漏过渡区域、以及位于所述源过渡区域远离沟道区域一侧的源连接区域和位于所述漏过渡区域远离沟道区域一侧的漏连接区域；所述源连接区域与所述第一源电极连接，所述漏连接区域与所述第一漏电极连接；所述源过渡区域和漏过渡区域均包括远离所述沟道区域的第一区域和邻近所述沟道区域的第二区域；所述第一区域对应的第一有源层的导电率高于所述第二区域对应的第一有源层的导电率，或者，所述第一区域对应的第一有源层的氧元素含量小于所述第二区域对应的第一有源层的氧元素含量，或者，所述第一区域对应的第一有源层的厚度小于所述第二区域对应的第一有源层的厚度。
  2. 根据权利要求1所述的显示基板，其中，所述第一区域对应的第一有源层的导电率高于所述源连接区域和漏连接区域对应的第一有源层的导电率，或者，所述第一区域对应的第一有源层的氧元素含量小于所述源连接区域和漏连接区域对应的第一有源层的氧元素含量，或者，所述第一区域对应的第一有源层的厚度小于所述源连接区域和漏连接区域对应的第一有源层的厚度。
  3. 根据权利要求1所述的显示基板，其中，所述第一栅电极在基底上正投影的边界位于所述第二绝缘层在基底上正投影的边界范围内；所述沟道区域在基底上正投影的边界位于所述第二绝缘层在基底上正投影的边界范围内。
  4. 根据权利要求1所述的显示基板，其中，所述显示基板包括规则排布的多个子像素，每个子像素包括像素驱动电路和电连接所述像素驱动电路的有机电致发光二极管，所述像素驱动电路包括存储电容，所述存储电容包括第一极板和第二极板，所述第一极板在基底上的正投影与所述第二极板在基底上的正投影存在交叠区域。
  5. 根据权利要求4所述的显示基板，其中，所述像素驱动电路还包括第一晶体管、第二晶体管和第三晶体管；所述第一晶体管的栅电极耦接于第二 晶体管的第二极，所述第一晶体管的第一极耦接于第一电源线，所述第一晶体管的第二极耦接于所述有机电致发光二极管的第一极，所述有机电致发光二极管的第二极耦接于第二电源线；所述第二晶体管的栅电极耦接于第一扫描线，所述第二晶体管的第一极耦接于数据线；所述第三晶体管的栅电极耦接于第二扫描线，所述第三晶体管的第一极耦接于补偿线，所述第三晶体管的第二极耦接于所述第一晶体管的第二极；所述存储电容的第一极耦接于所述第一晶体管的栅电极，所述存储电容的第二极耦接于所述第一晶体管的第二极。
  6. 根据权利要求4所述的显示基板，其中，所述第一导电层包括所述存储电容的第一极板，所述金属氧化物层包括所述存储电容的第二极板。
  7. 根据权利要求6所述的显示基板，其中，所述第一极板的材料包括透明导电材料，所述交叠区域位于所述显示基板的发光区域。
  8. 根据权利要求4所述的显示基板，其中，所述第一金属层包括所述存储电容的第一极板，所述金属氧化物层包括所述存储电容的第二极板。
  9. 根据权利要求4所述的显示基板，其中，所述第二金属层包括所述存储电容的第一极板，所述金属氧化物层包括所述存储电容的第二极板。
  10. 根据权利要求4所述的显示基板，其中，所述第一金属层包括所述存储电容的第一极板，所述第二金属层包括所述存储电容的第二极板。
  11. 根据权利要求6至9任一项所述的显示基板，其中，所述第二极板对应的金属氧化物层的导电率高于所述第二区域对应的第一有源层的导电率，或者，所述第二极板对应的金属氧化物层的氧元素含量小于所述第二区域对应的第一有源层的氧元素含量，或者，所述第二极板对应的金属氧化物层的厚度小于所述第二区域对应的第一有源层的厚度。
  12. 根据权利要求1至10任一项所述的显示基板，其中，所述第一金属层包括第一电源线和第一连接电极，所述第一连接电极与第一极板连接，所述第一金属层与基板之间设置有透明导电薄膜；所述第一连接电极在基底上的正投影与所述第一有源层的沟道区域在基底上的正投影存在交叠区域。
  13. 根据权利要求1至10任一项所述的显示基板，其中，所述第一源电 极和第一漏电极设置在第一绝缘层上；所述第一漏电极搭设在所述第一有源层的漏连接区域上，且通过第一过孔与第一连接电极连接；所述第一源电极的第一端通过第二过孔与所述第一电源线连接，所述第一源电极的第二端搭设在所述第一有源层的源连接区域上。
  14. 根据权利要求1至10任一项所述的显示基板，其中，所述第一源电极和第一漏电极设置在所述第二绝缘层上；所述第一漏电极通过第一有源过孔与所述第一有源层的漏连接区域连接，且通过第一过孔与第一连接电极连接；所述第一源电极的第一端通过第二过孔与所述第一电源线连接，所述第一源电极的第二端通过第二有源过孔与所述第一有源层的源连接区域连接。
  15. 一种显示装置，包括如权利要求1～14任一所述的显示基板。
  16. 一种显示基板的制备方法，包括：
    在基底上依次形成第一导电层、第一金属层和金属氧化物层，所述金属氧化物层包括第一有源层；
    依次形成第二绝缘层和第二金属层，通过两次导体化处理使所述第一有源层形成沟道区域、位于所述沟道区域两侧的源过渡区域和漏过渡区域、以及位于所述源过渡区域远离沟道区域一侧的源连接区域和位于所述漏过渡区域远离沟道区域一侧的漏连接区域；所述第二金属层包括第一栅电极、第一源电极和第一漏电极，所述源连接区域与所述第一源电极连接，所述漏连接区域与所述第一漏电极连接；所述源过渡区域和漏过渡区域均包括远离所述沟道区域的第一区域和邻近所述沟道区域的第二区域；所述第一区域对应的第一有源层的导电率高于所述第二区域对应的第一有源层的导电率，或者，所述第一区域对应的第一有源层的氧元素含量小于所述第二区域对应的第一有源层的氧元素含量，或者，所述第一区域对应的第一有源层的厚度小于所述第二区域对应的第一有源层的厚度。
  17. 根据权利要求16所述的显示基板的制备方法，其中，在基底上依次形成第一导电层、第一金属层和金属氧化物层，包括：
    在基底上形成透明的第一极板和第一金属层，所述第一金属层与基板之间设置有透明导电薄膜；所述第一金属层包括第一电源线和第一连接电极， 所述第一连接电极与第一极板连接；
    形成覆盖所述第一极板和第一金属层的第一绝缘层；
    在所述第一绝缘层上形成金属氧化物层，所述金属氧化物层包括第一有源层和第二极板，所述第二极板在基底上的正投影与所述第一极板在基底上的正投影存在交叠区域，所述第一有源层的沟道区域在基底上的正投影与所述第一连接电极在基底上的正投影存在交叠区域。
  18. 根据权利要求16所述的显示基板的制备方法，其中，依次形成第二绝缘层和第二金属层，通过两次导体化处理使所述第一有源层形成沟道区域、位于所述沟道区域两侧的源过渡区域和漏过渡区域、以及位于所述源过渡区域远离沟道区域一侧的源连接区域和位于所述漏过渡区域远离沟道区域一侧的漏连接区域，包括：
    在所述第一有源层上形成第二绝缘层，在所述第一绝缘层上形成第一过孔和第二过孔；所述第二绝缘层覆盖所述第一有源层的中部区域；所述第一过孔和第二过孔分别暴露出所述第一连接电极和第一电源线；
    对所述第二极板和所述第一有源层未被所述第二绝缘层覆盖的两侧区域进行第一次导体化处理，形成导体化的第二极板，在所述第一有源层的两侧分别形成源连接区域和漏连接区域；
    形成第二金属层，保留所述第二金属层上的光刻胶；所述第二金属层包括第一栅电极、第一源电极和第一漏电极；所述第一栅电极位于所述第一有源层的中部区域，所述第一漏电极搭设在所述漏连接区域上，并通过所述第一过孔与所述第一连接电极连接；所述第一源电极的第一端通过所述第二过孔与所述第一电源线连接，所述第一源电极的第二端搭设在所述源连接区域上；
    以所述第二金属层和设置在所述第二金属层上的光刻胶为掩膜，刻蚀未被所述第二金属层覆盖的第二绝缘层；
    以所述第二绝缘层、设置在所述第二绝缘层上的第二金属层以及设置在所述第二金属层上的光刻胶为掩膜，对所述第二极板和未被所述第二绝缘层覆盖的第一有源层进行第二次导体化处理，形成第一有源层的沟道区域以及 位于沟道区域两侧的源过渡区域和漏过渡区域，所述第一栅电极在基底上正投影的边界位于所述第二绝缘层在基底上正投影的边界范围内；所述沟道区域在基底上正投影的边界位于所述第二绝缘层在基底上正投影的边界范围内，所述源过渡区域和漏过渡区域均包括远离所述沟道区域的第一区域和邻近所述沟道区域的第二区域；所述第一区域对应的第一有源层的导电率高于所述第二区域对应的第一有源层的导电率，或者，所述第一区域对应的第一有源层的氧元素含量小于所述第二区域对应的第一有源层的氧元素含量，或者，所述第一区域对应的第一有源层的厚度小于所述第二区域对应的第一有源层的厚度。
  19. 根据权利要求16所述的显示基板的制备方法，其中，依次形成第二绝缘层和包括第一栅电极的第二金属层，通过两次导体化处理使所述第一有源层形成沟道区域、位于所述沟道区域两侧的源过渡区域和漏过渡区域、以及位于所述源过渡区域远离沟道区域一侧的源连接区域和位于所述漏过渡区域远离沟道区域一侧的漏连接区域，包括：
    形成覆盖所述第一有源层的第二绝缘层，所述第二绝缘层上形成有第一过孔、第二过孔、第一有源过孔和第二有源过孔，所述第一过孔和第二过孔分别暴露出所述第一连接电极和第一电源线，所述第一有源过孔和第二有源过孔分别暴露出所述第一有源层两侧的部分区域；
    对所述第二极板以及所述第一有源过孔和第二有源过孔内暴露出的第一有源层进行第一次导体化处理，形成导体化的第二极板以及所述第一有源层的源连接区域和漏连接区域；
    形成第二金属层，保留所述第二金属层上的光刻胶；所述第二金属层包括第一栅电极、第一源电极和第一漏电极；所述第一栅电极位于所述有源层的中部区域，所述第一漏电极通过所述第二有源过孔与所述漏连接区域连接，并通过所述第一过孔与所述第一连接电极连接；所述第一源电极的第一端通过所述第二过孔与所述第一电源线连接，所述第一源电极的第二端通过所述第一有源过孔与所述源连接区域连接；
    以所述第二金属层和设置在所述第二金属层上的光刻胶为掩膜，刻蚀未被所述第二金属层覆盖的第二绝缘层；
    以所述第二绝缘层、设置在所述第二绝缘层上的第二金属层以及设置在所述第二金属层上的光刻胶为掩膜，对所述第二极板和未被所述第二绝缘层覆盖的第一有源层进行第二次导体化处理，形成第一有源层的沟道区域以及位于沟道区域两侧的源过渡区域和漏过渡区域，所述第一栅电极在基底上正投影的边界位于所述第二绝缘层在基底上正投影的边界范围内；所述沟道区域在基底上正投影的边界位于所述第二绝缘层在基底上正投影的边界范围内，所述源过渡区域和漏过渡区域均包括远离所述沟道区域的第一区域和邻近所述沟道区域的第二区域；所述第一区域对应的第一有源层的导电率高于所述第二区域对应的第一有源层的导电率，或者，所述第一区域对应的第一有源层的氧元素含量小于所述第二区域对应的第一有源层的氧元素含量，或者，所述第一区域对应的第一有源层的厚度小于所述第二区域对应的第一有源层的厚度。
  20. 根据权利要求18或19所述的显示基板的制备方法，其中，刻蚀未被所述第二金属层覆盖的第二绝缘层，包括：
    通过自对准刻蚀方式去除所述第一栅电极与第一源电极之间的第二绝缘层以及所述第一栅电极与第一漏电极之间的第二绝缘层。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010055841A1 (en) * 2000-04-17 2001-12-27 Shunpei Yamazaki Light emitting device and manufacturing method thereof
US20140291636A1 (en) * 2013-03-26 2014-10-02 Lg Display Co., Ltd. Organic Light Emitting Diode Display Device and Method for Manufacturing the Same
CN106024813A (zh) * 2016-08-09 2016-10-12 京东方科技集团股份有限公司 一种低温多晶硅tft阵列基板的制作方法及相应装置
CN111403488A (zh) * 2020-03-31 2020-07-10 合肥鑫晟光电科技有限公司 薄膜晶体管及其制备方法、显示用基板及显示装置
CN111415995A (zh) * 2020-04-01 2020-07-14 合肥鑫晟光电科技有限公司 一种显示面板、其制作方法及显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013167374A1 (en) * 2012-05-09 2013-11-14 Imec Method for increasing the electrical conductivity of metal oxide semiconductor layers
CN106941121B (zh) * 2017-05-16 2019-11-26 厦门天马微电子有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示装置
CN208738252U (zh) * 2018-09-07 2019-04-12 北京京东方技术开发有限公司 像素结构以及阵列基板
CN210607259U (zh) * 2019-12-13 2020-05-22 北京京东方技术开发有限公司 显示基板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010055841A1 (en) * 2000-04-17 2001-12-27 Shunpei Yamazaki Light emitting device and manufacturing method thereof
US20140291636A1 (en) * 2013-03-26 2014-10-02 Lg Display Co., Ltd. Organic Light Emitting Diode Display Device and Method for Manufacturing the Same
CN106024813A (zh) * 2016-08-09 2016-10-12 京东方科技集团股份有限公司 一种低温多晶硅tft阵列基板的制作方法及相应装置
CN111403488A (zh) * 2020-03-31 2020-07-10 合肥鑫晟光电科技有限公司 薄膜晶体管及其制备方法、显示用基板及显示装置
CN111415995A (zh) * 2020-04-01 2020-07-14 合肥鑫晟光电科技有限公司 一种显示面板、其制作方法及显示装置

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