WO2013167374A1

WO2013167374A1 - Method for increasing the electrical conductivity of metal oxide semiconductor layers

Info

Publication number: WO2013167374A1
Application number: PCT/EP2013/058390
Authority: WO
Inventors: Robert Müller
Original assignee: Imec; Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek (Tno)
Priority date: 2012-05-09
Filing date: 2013-04-23
Publication date: 2013-11-14
Also published as: KR20150018501A; CN104272461B; TWI593118B; KR102056407B1; TW201403828A; JP2015519745A; CN104272461A; JP6077109B2

Abstract

A method for increasing the electrical conductivity of a metal oxide semiconductor layer at predetermined locations, wherein the method comprises: providing a reducing agent in physical contact with the metal oxide semiconductor layer at the predetermined locations and inducing a chemical reduction reaction between the reducing agent and the metal oxide semiconductor layer, thereby affecting the chemical composition of the metal oxide semiconductor layer at the predetermined locations; and uses of the method.

Description

Method for increasing the electrical conductivity of metal oxide semiconductor layers

Field of the disclosure

The disclosed technology relates to methods for locally increasing the electrical conductivity of metal oxide semiconductor layers, to metal oxide semiconductor based thin film transistors, and to methods for fabricating metal oxide semiconductor based thin film transistors. Description of the related technology

When fabricating metal oxide semiconductor thin film transistors, such as for example gallium-indium-zinc-oxide (acronym: GIZO or IGZO) thin film transistors, there is a need for locally increasing the electrical conductivity of the semiconductor material, more in particular at locations corresponding to source and drain contact regions, in order to improve charge injection and to reduce contact resistance.

Several methods for (locally) increasing the electrical conductivity of GIZO are known in the art, such as for example doping by ion implantation or diffusion of impurities, or performing an argon plasma treatment or a NH₃ plasma treatment.

In US 2012/0001 167, a method for fabricating metal oxide semiconductor thin film transistors is described, wherein an alternative method is used for locally increasing the electrical conductivity of the metal oxide semiconductor layer. After depositing a metal oxide semiconductor layer, a gate insulator and a gate electrode, a metal film made of a metal such as Ti, Al or In is provided, the metal film having a thickness of 10 nm or less. Next a heat treatment is performed, for example at a temperature of 300°C, in an oxygen containing atmosphere. As a result of this heat treatment the metal film is oxidized. In the oxidation reaction of the metal film, part of the oxygen included in a source region and a drain region of the metal oxide semiconductor layer is transferred to the metal film. As a result the oxygen concentration in the source region and the drain region decreases, leading to the formation of low-resistance regions in an upper portion of the metal oxide semiconductor layer. The thickness of the metal film is preferably 10 nm or less, such that the metal film may be completely oxidized during the heat treatment in the oxygen containing atmosphere. This removes the need for performing an etching step to remove non-oxidized metal. The method described in US 2012/0001 167 requires temperatures of at least 200°C, e.g. in the order of 300°C. Therefore this method is not compatible with some low cost flexible substrates, such as for example PET (polyethylene terephthalate), PEN (polyethylene naphthalate) and PC (polycarbonate), and might require higher prized plastic foils with increased heat stability and/or chemical stability such as PI (polyimide), PES (polyethersulfone) or PEEK (polyetheretherketone). The method also requires a good control of the thickness of the metal layer, so as to avoid the need for performing an etching step to remove non-oxidized metal.

Summary of certain inventive aspects

Certain inventive aspects relate to a method for locally increasing the electrical conductivity of a metal oxide semiconductor layer, wherein the method can be performed at temperatures not exceeding 200°C, or not exceeding about 200°C, or smaller than 200°C, and wherein the process complexity is reduced as compared to prior art methods.

According to a first aspect of the present disclosure, a method is disclosed for increasing the electrical conductivity of a metal oxide semiconductor layer at predetermined locations, wherein the method comprises: providing a reducing agent in physical contact with the metal oxide semiconductor layer at the predetermined locations and inducing a chemical reduction reaction between the reducing agent and the metal oxide semiconductor layer, thereby affecting the chemical composition of the metal oxide semiconductor layer at the predetermined locations.

A first inventive sub aspect relates to a method for increasing the electrical conductivity of a metal oxide semiconductor layer at predetermined locations, wherein the method comprises: providing a reducing layer comprising an alkaline metal (e.g. any of or any combination of Li, Na, K, Rb, Cs or Fr) or an alkaline earth metal (e.g. any of or any combination of Be, Mg, Ca, Sr, Ba or Ra) in physical contact with the metal oxide semiconductor layer at the predetermined locations; inducing a chemical reduction reaction between the reducing layer and the metal oxide semiconductor layer, thereby affecting the chemical composition of the metal oxide semiconductor layer at the predetermined locations, for instance decreasing the oxygen content of the metal oxide semiconductor layer at the predetermined locations ; and performing a rinsing step for removing the reducing layer, or excess of reducing layer and reaction products or by-products from the reduction reaction.

A rinsing step is a step of removing by washing lightly in a liquid, e.g. water. In one aspect, inducing a chemical reduction reaction between the reducing layer and the metal oxide semiconductor layer may comprise performing an annealing step at a temperature in the range between about 20°C and 200°C. The annealing step may be performed under an inert atmosphere or in vacuum (e.g. at a pressure in the range between about 10^"6 Torr and 10^"8 Torr, i.e. in the range between about 1 .33 10^"4 Pa and 1 .33 10^"6 Pa).

In another aspect, inducing a chemical reduction reaction between the reducing layer and the metal oxide semiconductor layer may comprise waiting for a predetermined time period after providing the reducing layer, for example for a time period in the range between about 1 minute and 5 hours, for example between about 15 minutes and 2 hours. The waiting step can for example comprise keeping the sample in a chamber wherein the reducing layer has been provided . The waiting step may be performed under vacuum, at a pressure in the range between about 10^"6 Torr and 10^"8 Torr, i.e. in the range between about 1 .33 10^"4 Pa and 1 .33 10^"6 Pa. The waiting step can for example be done at a temperature in the range between about - 50°C and +50°C.

Inducing a chemical reduction reaction between the reducing layer and the metal oxide semiconductor layer may comprise performing a waiting step in accordance with an aspect of the present disclosure, followed by an annealing step in accordance with an aspect of the present disclosure.

In one aspect, increasing the electrical conductivity of the metal oxide semiconductor layer can comprise increasing the electrical conductivity in a surface portion of the metal oxide semiconductor layer, e.g. in a surface portion having a thickness of about 10 nm to a few tens of nm, such as a thickness of about 10 nm to 40 nm, for instance a thickness in between 10 nm and 40 nm . In another aspect, increasing the electrical conductivity of the metal oxide semiconductor layer can comprise increasing the electrical conductivity throughout the whole thickness of the metal oxide semiconductor layer.

In one aspect, the method can advantageously be used in a fabrication process for thin film transistors having a metal oxide semiconductor active layer, for locally increasing the electrical conductivity at predetermined locations corresponding to source regions and drain regions, thereby improving charge injection from the source and drain contacts. In one aspect the method can be used in a fabrication process for self-aligned top-gate thin film transistors.

In one aspect, the method may also be used in a fabrication process for other metal oxide semiconductor based devices, e.g. diodes or transistor-diodes, for improving charge injection from contacts.

The metal oxide semiconductor layer can for example comprise gallium- indium-zinc-oxide (GIZO), or other metal oxide based semiconductors, e.g. of following compositions (without indication of the stoichiometry): ZnO, ZnSnO, InO, InZnO, InZnSnO, LalnZnO, GalnO, HflnZnO, MgZnO, LalnZnO, TiO, TilnSnO, SclnZnO, SilnZnO and ZrlnZnO, ZrZnSnO. However, the present disclosure is not limited thereto and the method in one aspect can be used with other suitable metal oxide semiconductors known to a person skilled in the art. These semiconductor layers of typical thickness between 5 nm and 50 nm can be provided by a multitude of methods such as for example sputtering, thermal evaporation, pulsed laser deposition, and spin-casting, ink-jet printing or drop casting of precursor solutions.

The reducing layer comprising the alkaline metal or alkaline earth metal can be a continuous layer. In one aspect the reducing layer can be a non-continuous layer, e.g. it can be a layer formed of a plurality of (nano) islands.

The reducing layer comprising the alkaline metal or alkaline earth metal can for example consist of the alkaline metal or alkaline earth metal. Alternatively, the reducing layer may comprise an alloy containing an alkaline metal or an alkaline earth metal.

In one aspect, a chemical reduction reaction may be induced by bringing the metal oxide semiconductor layer at the predetermined locations in physical contact with a chemical reducing agent dissolved in a liquid, such as for example an aqueous solution of sodium thiosulfate (Na₂S₂O₃) or hydrazine, or a solution of sodium naphthalenide or sodium acenaphthenide in an organic solvent (such as an ethereal solvent) or a chemical reducing agent in gas phase (eg. hydrazine).

The thickness of the layer comprising the alkaline metal or alkaline earth metal can for example be in the range between about 1 nm and 100 nm, such as between about 5 nm and 50 nm, or between about 5 nm and 25 nm.

The annealing step may be performed at a temperature in the range between about 20°C and 200°C, for example with an annealing time in the range between about 1 minute and 1 hour. In one aspect, in order to avoid consumption of the alkaline or earth alkaline metal by undesired reactions with the atmosphere, the annealing step is performed under inert atmosphere, allowing preventing for example oxidation by oxygen from residual water or moisture. The annealing may for example be performed in an argon or nitrogen (or Helium, Neon, Krypton, Xenon) filled glovebox with moisture and oxygen absorbers. Other gases such as helium may also be used to create an inert atmosphere. In embodiments using reducing layers comprising chemically less reactive metals (such as for example calcium) also nitrogen gas may be used as an inert atmosphere. In another aspect, in order to avoid consumption of the alkaline or earth alkaline metal by undesired reactions with the atmosphere (e.g. oxygen, moisture, water), the sample may be kept in vacuum (waiting step) for a predetermined time period (e.g. between about 1 minute and 5 hours, for example between about 15 minutes and 2 hours) at a pressure in the range between about 1 .33 10^"4 Pa and 1 .33 10^"6 Pa and at a temperature in the range between about -50°C and +50°C.

In one aspect, the rinsing process may be done with a rinsing means, e.g. the rinsing means being water. However, the present disclosure is not limited thereto and the rinsing process may be done using other liquids, such as for example an alcohol.

It is an advantage of one inventive aspect that the conductivity of the metal oxide semiconductor layer can be improved significantly, e.g. by at least about three orders of magnitude, at temperatures lower than about 200°C, e.g. about at 150°C or less. Therefore, the method in one aspect is compatible with the use of low-cost flexible substrates, such as for example PET, PEN or PC.

It is an advantage of one inventive aspect that unreacted metal can be easily removed by performing a rinsing step, e.g. with water. It is an advantage of one inventive aspect that that need for performing an oxidation step in an atmosphere comprising oxygen or ozone or an etching step to remove unreacted metal can be avoided.

It is an advantage of one inventive aspect that also the reaction products (e.g. reacted metal) can be removed by performing a rinsing step. In some embodiments the reaction products (e.g. reacted metal) can be easily removed by performing a rinsing step with water. For example, when using a reducing layer comprising Ca, the chemical reduction reaction between the reducing layer and the metal oxide layer results in the formation of calcium oxide, which has a good solubility in water. In other embodiments, such as for example when using a reducing layer comprising Mg, the reaction products (e.g. magnesium oxide) can be removed by performing a rinsing step with an acid.

It is an advantage that the metals used in a method according to one aspect do not form a compact oxide layer at the interface between the metal of the reducing layer and the metal oxide semiconductor that could block or prevent further reaction with the underlying metal oxide semiconductor layer. Therefore there is no need for a good thickness control of the layer comprising the metal.

It is an advantage of one inventive aspect that the chemical reduction reaction between the reducing layer and the metal oxide semiconductor layer may be not self- limiting (no formation of compact oxide layer that could block or prevent further reaction) thus allowing increasing the electrical conductivity of the metal oxide semiconductor layer in a larger portion (into the depth, i.e. in a direction substantially orthogonal to the surface plane of the metal oxide semiconductor layer) as compared to other methods. This larger portion can comprise a portion larger than 50%, or larger than 60%, or larger than 70%, or larger than 80%, or larger than 90%, or 100% into the depth.

In a second sub aspect of the present invention, the use of a reducing layer can be avoided. The method may then be such that providing a reducing agent in physical contact with the metal oxide semiconductor layer at the predetermined locations and inducing a chemical reduction reaction between the reducing agent and the metal oxide semiconductor layer comprises bringing the metal oxide semiconductor layer at the predetermined locations in physical contact with a chemical reducing agent dissolved in a liquid. The effects can be similar to the effects described in relationship with the first sub aspect.

In a third sub aspect, also without the use of a reducing layer, providing a reducing agent in physical contact with the metal oxide semiconductor layer at the predetermined locations and inducing a chemical reduction reaction between the reducing agent and the metal oxide semiconductor layer comprises bringing the metal oxide semiconductor layer at the predetermined locations in physical contact with a chemical reducing agent in gas phase. The effects can be similar to the effects described in relationship with the first sub aspect.

In one inventive aspect the chemical reduction reaction may increase the electrical conductivity throughout the whole thickness of the metal oxide semiconductor layer, and in addition it may increase the electrical conductivity of (a portion of) an insulating layer, e.g. dielectric layer, such as a silicon oxide layer or an aluminium oxide layer, underlying the metal oxide semiconductor layer. In case of a top-gate transistor configuration such a reduction reaction of the insulating layer, e.g. dielectric layer, e.g. silicon oxide layer or aluminium oxide layer, underlying the oxide semiconductor layer may be advantageous, because it could lead to a higher conductivity of source and drain contacts and it may allow making self-aligned bottom contacts. In a second aspect of the present invention, the use of the method according to the first aspect is disclosed, for fabricating thin film transistors having a metal oxide semiconductor active layer, for locally increasing the electrical conductivity at predetermined locations corresponding to source regions and drain regions, thereby improving charge injection from the source and drain contacts, the latter typically being provided on the source and drain regions

The method according to the first aspect can be used for fabricating self- aligned top-gate thin film transistors.

Certain objects and advantages of various inventive aspects have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the disclosure. Thus, for example, those skilled in the art will recognize that the disclosure may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein. Further, it is understood that this summary is merely an example and is not intended to limit the scope of the disclosure. The disclosure, both as to organization and method of operation, together with features and advantages thereof, may best be understood by reference to the following detailed description when read in conjunction with the accompanying drawings.

Brief description of the drawings

Figure 1 shows the measured resistance of a GIZO layer after different treatments and for different annealing times at 150°C.

Figure 2 shows the measured resistance of a GIZO layer before and after evaporation of a Ca layer as a function of annealing temperature.

Figure 3 to Figure 7 illustrate steps of a fabrication method of a metal oxide semiconductor thin film transistor in accordance with a method in one embodiment. Figure 8 shows an optical micrograph of a substrate (GIZO on SiO2) after calcium treatment in accordance with one embodiment. Calcium was evaporated through a shadow mask. The darker areas correspond to the openings of the shadow mask.

Figure 9 shows electrical measurements performed on a transistor with Ca treated GIZO source/drain contacts. Top graph: transfer characteristics; bottom graph: output characteristics.

Figure 10 shows the electrical resistivity of Ca treated GIZO (on SiO2 dielectric) between two gold top contact pads in function of the GIZO thickness and the gap between the contact pads.

Figure 1 1 shows the elemental depth profile (by time-of-flight secondary ion mass spectrometry) of indium, gallium, zinc, and calcium for a Ca treated GIZO substrate (60 nm GIZO on SiO2 dielectric).

Figure 12 shows transfer curves of five by lithography patterned transistors with Ca treated GIZO source/drain contacts.

Any reference signs shall not be construed as limiting the scope of the present disclosure.

In the different drawings, the same reference signs refer to the same or analogous elements.

Detailed description of certain illustrative embodiments

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure and how it may be practiced in particular embodiments. However, it will be understood that the present disclosure may be practiced without these specific details. In other instances, well- known methods, procedures and techniques have not been described in detail, so as not to obscure the present disclosure. While the present disclosure will be described with respect to particular embodiments and with reference to certain drawings, the disclosure is not limited hereto. The drawings included and described herein are schematic and are not limiting the scope of the disclosure. It is also noted that in the drawings, the size of some elements may be exaggerated and, therefore, not drawn to scale for illustrative purposes.

Furthermore, the terms first, second, third and the like in the description, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the disclosure described herein are capable of operation in other sequences than described or illustrated herein.

Moreover, the terms top, bottom, over, under and the like in the description are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the disclosure described herein are capable of operation in other orientations than described or illustrated herein.

It is to be noticed that the term "comprising" should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B.

A method according to one embodiment for increasing the electrical conductivity of a metal oxide semiconductor layer at predetermined locations comprises: providing a reducing layer comprising an alkaline metal (Li, Na, K, Rb, Cs or Fr) or an alkaline earth metal (Be, Mg, Ca, Sr, Ba or Ra) in physical contact with the metal oxide semiconductor layer at the predetermined locations; inducing a chemical reduction reaction between the reducing layer and the metal oxide semiconductor layer, thereby affecting the chemical composition of the metal oxide semiconductor layer, for instance decreasing the oxygen content of the metal oxide semiconductor layer, or decreasing the oxidation state of the metal ions of the metal oxide semiconductor layer, at the predetermined locations; and performing a rinsing step for removing the reducing layer (in another view the possible excess of the reducing layer) and reaction products (in another view reaction by-products) from the reduction reaction.

In one aspect, inducing a chemical reduction reaction between the reducing layer and the metal oxide semiconductor layer may comprise performing an annealing step at a temperature in the range between about 20°C and 200°C. The annealing step may be performed under an inert atmosphere or in vacuum (e.g. at a pressure in the range between about 10^"6 Torr and 10^"8 Torr, particularly in the range between about 1 .33 10^"4 Pa and 1 .33 10^"6 Pa). The duration of the annealing step can for example be between 5 minutes and 30 minutes.

In another aspect, inducing a chemical reduction reaction between the reducing layer and the metal oxide semiconductor layer may comprise waiting for a predetermined time period after providing the reducing layer, for example for a time period in the range between about 1 minute and 5 hours, for example between about 15 minutes and 2 hours. The waiting step can for example comprise keeping the sample in a chamber wherein the reducing layer has been provided. The waiting step may be performed under vacuum, at a pressure in the range between about 10^"6 Torr and 10^"8 Torr, or in the range between about 1 .33 10^"4 Pa and 1 .33 10^"6 Pa. The waiting step can for example be done at a temperature in the range between about - 50°C and +50°C.

The method in one embodiment can advantageously be used in a fabrication process for thin film transistors having a metal oxide semiconductor active layer, for locally increasing the electrical conductivity at predetermined locations e.g. corresponding to source regions and drain regions, thereby improving charge injection.

The method in one embodiment is further described for embodiments wherein the metal oxide semiconductor layer is a gallium-indium-zinc-oxide (GIZO or IGZO) layer and wherein the reducing layer is a Ca layer. However, the present disclosure is not limited thereto and other metal oxide semiconductor layers and/or reducing layers can be used.

Experiments were performed wherein a nominal 15 nm thick GIZO layer was sputtered from a 1 :1 :1 ratio of Ga:ln:Zn target on a 100 nm thick silicon oxide layer on a 2 cm x 2 cm square substrate. The resistance of the as-deposited GIZO layer (measured between one corner of the substrate and an opposite corner of the substrate) was found to be higher than 200 Mega-ohm, being the upper scale limit of the multimeter used. Figure 1 illustrates the measured resistance of the GIZO layer after different sequential treatments and for different annealing times on a hot plate at 150°C (0 min = no annealing) inside a nitrogen filled glove box: after thermal evaporation of a 20 nm thick Ca layer (evaporation rate: one Angstrom per second) followed by short rinsing in water and drying in nitrogen; after additional rinsing in water for 5 minutes and drying with nitrogen; after additional storage during 1 night in air; after additional treatment for 2 hours in 70°C water and drying with nitrogen; and after various storage times in air (6 days, 12 days and 19 days). The results show a drastic decrease of the resistance directly after Ca deposition. However, extended air storage leads again to a significant loss of conductivity. The longer the annealing time, the smaller is the loss of conductivity.

Figure 2 shows the measured resistance of a nominal 15 nm thick GIZO layers sputtered from a 1 :1 :1 ratio of Ga:ln:Zn target on a 100 nm thick silicon oxide layer on a 2 cm x 2 cm square substrate. The full line shows the initial resistance, without Ca evaporation. The filled squares show the resistance after evaporation (at 25°C) of a 20 nm thick Ca layer (obtained by thermal evaporation at a rate of one Angstrom per second) followed by annealing for 15 minutes on a hot plate at different temperatures inside a nitrogen filled glove box, rinsing afterwards with water and drying under nitrogen flow. A decrease in resistance is already observed for an annealing temperature of 25°C. Lower resistances are observed after annealing at 100°C and at 150°C.

The method in one embodiment is further described in the context of a fabrication process for thin film transistors wherein source and drain regions are self- aligned to the gate (self-aligned top-gate structure). It is an advantage of such fabrication process that it allows reducing the parasitic capacitance between the gate and the source/drain regions. However, the present disclosure is not limited thereto and the method can be used for fabricating other thin film transistors and/or other metal oxide semiconductor based devices.

Figure 3 to Figure 7 illustrate process steps of a method for fabricating a metal oxide semiconductor thin film transistor in accordance with one embodiment.

In a first step, illustrated in Figure 3, a metal oxide semiconductor layer, such as a GIZO layer, is provided on a substrate 10, e.g. by sputtering, laser ablation or spin-coating from a precursor solution. The thickness of the GIZO layer can for example be in the order of about 10 nm or about 15 nm to 20 nm, for instance in between 10 nm and 20 nm, but other suitable thicknesses can be used. In the example shown in Figure 3, the GIZO layer is patterned at this stage of the fabrication process to form an active layer 1 1 of a transistor. However, the present disclosure is not limited thereto. For example, the GIZO layer can also be patterned in a later stage of the fabrication process, such as for example after the formation of source and drain contacts.

Next, a gate insulating layer and subsequently a gate electrode layer are provided on top of the substrate 10 and the active layer 1 1 . The gate electrode layer and the gate insulating layer are then patterned to form a gate electrode 13 and a gate insulator 12, thereby defining a channel region 1 10 in the active layer 1 1 underneath the gate (Figure 4), a source region 1 1 1 and a drain region 1 12.

Next, the source region 1 1 1 and the drain region 1 12 of the metal oxide semiconductor layer 1 1 are treated using a method according to one embodiment. As illustrated in Figure 5, a reducing layer 14 comprising an alkaline metal or an alkaline earth metal such as e.g. Ca is provided on top of the substrate 10, source region 1 1 1 , drain region 1 12 and gate electrode 13. Next an annealing step is performed at a temperature in the range between about 20°C and 200°C, leading to a local chemical reduction of the metal oxide semiconductor layer 1 1 where it is in direct physical contact with the reducing layer 14, i.e. in the source region 1 1 1 and the drain region 1 12 of the metal oxide semiconductor layer 1 1 . This reduction results in the formation of regions 151 , 152 with increased conductivity in (a surface portion of) the metal oxide semiconductor layer 1 1 in the source region 1 1 1 and the drain region 1 12 (Figure 6). These regions of increased conductivity are automatically aligned (self-aligned) to the gate region.

In a next step the reducing layer 14 is rinsed away (Figure 7) (in another view, the unreacted portion or excess of reducing layer material), e.g. in water, and further process steps can be performed to finalize the thin film transistor. For example, a dielectric layer or an encapsulation layer can be provided on top of the structure shown in Figure 7, followed by the formation of vias into this dielectric layer or encapsulation layer at the location where contacts need to be formed, and filling of the vias with a suitable metal to form e.g. source contacts and drain contacts (not depicted). However, other suitable process steps can be used for finalizing the transistor structure.

Experiments illustrating the usefulness of a method of one embodiment to GIZO transistors were done using a substrate including a semiconducting GIZO layer on top of an about 120 nm thick thermal S1O2 dielectric layer on a doped silicon die with an aluminum backgate. The substrate was first cleaned by successive rinsing with acetone and isopropylalcohol before drying under a nitrogen flow. Metallic calcium (about 20 nm thickness) was evaporated at a rate of one Angstrom per second through a shadow mask under high vacuum (about 10^"7 Torr) on top of the semiconductive GIZO (obtained by sputtering from a 1 :1 :1 Ga:ln:Zn target). After the evaporation of the metal the substrate was kept for about 30 additional minutes inside the high vacuum chamber in order to allow the chemical reduction reaction to occur. Then the substrate was removed from the glove box and placed directly - without anneal step - for about 10 minutes in a rinsing desionized water bath. After drying with a nitrogen flow, a clear difference could already be observed by naked eye between the regions of the substrate which had been in contact with the metallic calcium and those not exposed to the metal. This is illustrated in Figure 8, showing an optical micrograph of a substrate (GIZO on S1O2) after complete calcium treatment. The darker areas correspond to the openings of the shadow mask through which Ca was evaporated. Electrical measurements of the corresponding transistors were performed under controlled atmosphere, in a nitrogen filled glove box with both oxygen and water contents below about 1 ppm. The common backgate was contacted with the measurement chuck, and the calcium treated areas, serving as source and drain contacts, were directly contacted by stainless steel probe needles. In the nitrogen filled glovebox, an additional hotplate bake was done for 45 minutes at 100°C, in order to remove any water traces from the substrate, e.g. resulting from the rinsing step described above. Transistors with nominal channel lengths of 200 micrometer achieved apparent saturation mobilities of up to around 19 cm²/(V.s), as illustrated in Figure 9. The top graph of Figure 9 shows the transistor transfer characteristics, while the bottom graphs shows the transistor output characteristics. Reproducibility of the mobility and also the threshold voltage for several transistors of the same substrate was good.

Further experiments were carried out in order to investigate the influence of the optional rest or waiting period under high vacuum. GIZO (sputtered from a 1 :1 :1 ratio of Ga:ln:Zn target) substrates of various nominal thicknesses (13 nm, 26 nm, 40 nm and 60 nm) on 130 nm thick SiO₂ dielectric were submitted to Ca treatment (20 nm evaporated at a rate of one Angstrom per second). Directly after Ca deposition substrates of one run were taken out of the vacuum chamber, and heated to 150°C for 30 minutes on a hotplate inside a nitrogen filled glove box. In a different, second run the substrates were left under high vacuum for 30 minutes, and were not submitted to a heat treatment on a hot plate. Substrates of both runs were afterwards treated in a similar way by a ten minutes rinsing step in a desionized water bath followed by drying under a nitrogen flow. Inspection by optical microscopy (100 times magnification objective) revealed the presence of dark spots in the case of substrates kept 30 minutes under vacuum, whereas no similar spots could be observed for substrates submitted to the heat treatment directly after Ca deposition. Investigation of the substrates by scanning electron microscopy revealed the presence of large amounts of hillocks and voids for the substrates kept under vacuum - in contrast to the substrates submitted to the heat treatment directly with Ca deposition. Electrical resistivity, measured by contacting the probe tips of a multimeter (in ohmmeter position), was also lower for the substrates of the run involving the heat treatment directly after Ca deposition. More precise resistance measurements were carried out for the run involving the heat treatment by depositing rectangular gold contact pads (50 nm thick evaporated gold, 2 millimeter length, and 1 00 urn or 200 urn nominal gap length between the pads) onto the Ca treated substrates with different GIZO thicknesses. As illustrated in Figure 10, the resistance decreases largely from the 13 nm GIZO substrate to the 26 nm GIZO substrate, whereas only little variation of resistance is observed for thicker GIZO layers.

The Ca treated substrate with nominal 60 nm thick GIZO layer was furthermore submitted to time-of-f light secondary ion mass spectrometry (TOF-SIMS) analysis. As shown in the TOF-SIMS profile displayed in Figure 1 1 , calcium is present in the GIZO layer, and its concentration decreases quickly from the top of the GIZO to a depth of approximately 20 to 30 nm.

Experiments illustrating the usefulness of a method of one embodiment to GIZO transistors were done using a substrate including a semiconducting GIZO layer (obtained by sputtering from a 1 :1 :1 Ga:ln:Zn target) on top of an about 130 nm thick thermal SiO₂ dielectric layer on a doped silicon die with an aluminum back gate. The substrate was first cleaned by successive rinsing with acetone and isopropylalcohol before drying under a nitrogen flow. Then photoresist was deposited onto the substrate by spin-casting and baked at 120°C for 2 minutes. The photoresist was then patterned by photolithography and developed in a developer, such that areas corresponding to the source and drain fingers and contact pads became open. Calcium (about 20 nm thick) was then evaporated under high vacuum (about 10^"7 Torr) at a rate of one Angstrom per second through the photoresist acting as shadow mask on the substrate. Directly after the evaporation of the metal the substrate was taken out of the vacuum chamber and heated to 120°C during 30 minutes on a hot plate inside a nitrogen filled glove box. Then the substrate was removed from the glove box and rinsed for about 10 minutes in a desionized water bath. After drying with a nitrogen flow, the substrate was heated on a hot plate inside a nitrogen filled glove box during 100 minutes at 100°C, in order to remove any water traces from the substrate, e.g. resulting from the rinsing step described above. Although the patterned photoresist was still present at this moment for practical purposes in order to identify the source and drain contacts back on the substrate, its presence is not required for the operation of the GIZO transistors with Ca treated GIZO source and drain contacts. Electrical measurements of the corresponding transistors were performed under controlled atmosphere, in a nitrogen filled glove box with both oxygen and water contents below about 1 ppm. The common backgate was contacted with the measurement chuck, and the calcium treated areas corresponding to the source and drain contacts were directly contacted by stainless steel probe needles. Transistors with nominal channel lengths of 5 micrometer achieved apparent saturation mobilities in the range of 1 .2 cm²/(V.s). Reproducibility of the mobility and also the threshold voltage for several transistors of the same substrate was good, as illustrated for 5 different transistors in Figure 12.

The foregoing description details certain embodiments of the disclosure. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the disclosure may be practiced in many ways. It should be noted that the use of particular terminology when describing certain features or aspects of the disclosure should not be taken to imply that the terminology is being re-defined herein to be restricted to including any specific characteristics of the features or aspects of the disclosure with which that terminology is associated.

While the above detailed description has shown, described, and pointed out novel features of the invention as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the technology without departing from the invention.

Claims

1 . A method for increasing the electrical conductivity of a metal oxide semiconductor layer at predetermined locations, wherein the method comprises: providing a reducing agent in physical contact with the metal oxide semiconductor layer at said predetermined locations and inducing a chemical reduction reaction between the reducing agent and the metal oxide semiconductor layer, thereby affecting the chemical composition of the metal oxide semiconductor layer at said predetermined locations.

2. A method according to claim 1 , wherein the metal oxide semiconductor layer comprises gallium-indium-zinc-oxide (GIZO), or other metal oxide based semiconductors, e.g. of following compositions: ZnO, ZnSnO, InO, InZnO, InZnSnO, LalnZnO, GalnO, HflnZnO, MgZnO, LalnZnO, TiO, TilnSnO, SclnZnO, SilnZnO and ZrlnZnO, ZrZnSnO.

3. Method according to claim 1 or 2, wherein said metal oxide semiconductor layer has a thickness between 5 nm and 50 nm.

4. A method according to any of claims 1 to 3, wherein providing a reducing agent in physical contact with the metal oxide semiconductor layer at said predetermined locations comprises providing a reducing layer comprising an alkaline metal, an alkaline earth metal, or an alloy of both types of metals, in physical contact with the metal oxide semiconductor layer at said predetermined locations; and wherein inducing a chemical reduction reaction between the reducing agent and the metal oxide semiconductor layer comprises inducing a chemical reduction reaction between the reducing layer and the metal oxide semiconductor layer, the method further comprising:

- performing a rinsing step for removing said reducing layer and reaction by-products from the reduction reaction.

5. Method according to claim 4, wherein said reducing layer comprises Ca.

6. A method according to any of claims 4 or 5, wherein said reducing layer has a thickness in the range between about 1 nm and 100 nm.

7. A method according to any of claims 4 to 6, wherein said affecting the chemical composition of said metal oxide semiconductor layer at said predetermined locations comprises chemically reducing metal ions of said metal oxide semiconductor layer into the reducing layer.

8. A method according to any of the previous claims 4 to 7, wherein inducing a chemical reduction reaction between the reducing layer and the metal oxide semiconductor layer may comprise performing an annealing step at a temperature in the range between about 20°C and 200°C for a duration between 1 and 60 minutes.

9. A method according to claim 8, wherein said anneal ing step is performed under an inert atmosphere or in vacuum.

10. A method according to any of the previous claims 4 to 7, wherein inducing a chemical reduction reaction between the reducing layer and the metal oxide semiconductor layer comprises waiting for a predetermined time period after providing the reducing layer, said predetermined time period being in the range between 1 minute and 5 hours.

1 1 . A method according to claim 10, wherein waiting comprises keeping the sample in a chamber wherein the reducing layer has been provided.

12. A method according to claim 10 or 1 1 , wherein said waiting step is performed under vacuum, or in the range between about 1 .33 10^"4 Pa and 1 .33 10^"6 Pa, and at a temperature within the range between about -50°C and +50°C.

13. A method according to any of the previous claims 10 to 12, wherein said waiting step is followed by an annealing step at a temperature in the range between about 20°C and 200°C for a duration between 1 and 60 minutes.

14. A method according to any of the previous claims 4 to 13, wherein said rinsing step comprises rinsing in water or alcohol.

15. A method according to claim 1 , wherein providing a reducing agent in physical contact with the metal oxide semiconductor layer at said predetermined locations and inducing a chemical reduction reaction between the reducing agent and the metal oxide semiconductor layer comprises bringing the metal oxide semiconductor layer at the predetermined locations in physical contact with a chemical reducing agent dissolved in a liquid .

16. A method according to claim 1 , wherein providing a reducing agent in physical contact with the metal oxide semiconductor layer at said predetermined locations and inducing a chemical reduction reaction between the reducing agent and the metal oxide semiconductor layer comprises bringing the metal oxide semiconductor layer at the predetermined locations in physical contact with a chemical reducing agent in gas phase.

17. A method according to any of the previous claims, performed on a low- cost flexible substrate of the PET type, PEN type or PC type.

18. A method according to any of the previous claims, wherein said affecting the chemical composition of said metal oxide semiconductor layer at said predetermined locations comprises decreasing the oxygen content of said metal oxide semiconductor layer.

19. A method according to any of the previous claims, wherein increasing the electrical conductivity of the metal oxide semiconductor layer comprises increasing the electrical conductivity in a surface portion of the metal oxide semiconductor layer, said surface portion having a thickness of about 10 nm to 40 nm.

20. A method according to any of the previous claims, wherein increasing the electrical conductivity of the metal oxide semiconductor layer comprises increasing the electrical conductivity throughout the whole thickness of the metal oxide semiconductor layer.

21 . A method according to any of the previous claims, further comprising providing said metal oxide semiconductor layer on an insulating layer, and wherein increasing the electrical conductivity of the metal oxide semiconductor layer comprises increasing the electrical conductivity throughout the whole thickness of the metal oxide semiconductor layer and in at least a portion of said insulating layer.

22. Use of the method according to any of the previous claims, for fabricating thin film transistors having a metal oxide semiconductor active layer, for locally increasing the electrical conductivity at predetermined locations corresponding to source regions and drain regions, thereby improving charge injection from the source and drain contacts.

23. Use according to claim 22 for fabricating self-aligned top-gate thin film transistors.