KR101073786B1 - Method for manufacturing thin film transistors - Google Patents

Method for manufacturing thin film transistors Download PDF

Info

Publication number
KR101073786B1
KR101073786B1 KR1020100035420A KR20100035420A KR101073786B1 KR 101073786 B1 KR101073786 B1 KR 101073786B1 KR 1020100035420 A KR1020100035420 A KR 1020100035420A KR 20100035420 A KR20100035420 A KR 20100035420A KR 101073786 B1 KR101073786 B1 KR 101073786B1
Authority
KR
South Korea
Prior art keywords
electrode layer
active layer
gate electrode
layer
transparent
Prior art date
Application number
KR1020100035420A
Other languages
Korean (ko)
Inventor
남형진
조남인
Original Assignee
선문대학교 산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 선문대학교 산학협력단 filed Critical 선문대학교 산학협력단
Priority to KR1020100035420A priority Critical patent/KR101073786B1/en
Application granted granted Critical
Publication of KR101073786B1 publication Critical patent/KR101073786B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

A method of manufacturing a thin film transistor of the present invention, comprising: forming a pattern of a transparent active layer on a portion of a transparent substrate; Forming a lamination mask on the substrate such that a window is positioned on a portion of the pattern of the active layer; Sequentially forming a transparent gate insulating film and a transparent gate electrode layer on an active layer in the window of the lamination mask; Removing the stacked mask, the gate insulating layer, and the gate electrode layer to expose the pattern of the substrate and the active layer; And forming a transparent source / drain electrode layer on the pattern of the active layer so as to self-align with the gate electrode layer while still self-aligning the gate electrode layer and the source / drain electrode layer, the gate electrode layer, and the source / drain An electrode layer is formed.

Description

Method for manufacturing thin film transistors

The present invention relates to a method for manufacturing a thin film transistor (TFT), and more particularly, to form a transparent active layer, a gate electrode layer, and a source / drain electrode layer while self-aligning a gate electrode layer and a source / drain electrode layer. It relates to a method for manufacturing a thin film transistor.

The structure of the thin film transistor is largely divided into a coplanar structure and a staggered structure. The stacked structure is divided into a bottom-gate structure and a top-gate structure, and the bottom gate structure is also a bottom-contact depending on the position of the source / drain electrode. It is divided into a structure and a top-contact structure.

Although each structure has advantages and disadvantages, it is essential to minimize parasitic capacitance between the gate and the source / drain in applications requiring high operating speed and low power. Among the methods for minimizing the parasitic capacitance, the self-aligning method is the most efficient, and in the case of the conventional silicon device, a device structure such as a salicide structure adopting the self-aligning method is widely used.

However, in the case of thin film transistors, the bottom gate structure is the most widely used structure in related companies. However, the bottom gate structure is difficult to adopt a self-aligning method, since the active layer of the thin film transistor is likely to be deteriorated due to exposure to plasma or the like during the subsequent process. Accordingly, there is a need to develop a method for applying a flat structure and a self-aligning method, which are well known in conventional silicon devices, to a thin film transistor.

On the other hand, the recent trend in the field of flat display, the need for a transparent thin film transistor need not be added. Due to these factors, researches on transparent electrodes and transparent semiconductors have been actively conducted. That is, a transparent metal oxide such as ZnO has been mainly studied as a semiconductor to be used as an active layer, and AZO and ITO have been mainly studied as a transparent electrode to be used as an electrode.

Accordingly, a transparent metal oxide film such as ZnO is used as an active layer and a transparent metal oxide film such as AZO is used as an electrode, while a self-aligning method is adopted to minimize parasitic capacitance between the gate and the source / drain. There is a need for a thin film transistor.

Accordingly, an object of the present invention is to provide a method of manufacturing a thin film transistor, wherein the active layer is formed of a transparent metal oxide film, and the gate electrode layer and the source / drain electrode layer are formed of a transparent metal oxide film.

Another object of the present invention is to provide a method of manufacturing a thin film transistor which minimizes parasitic capacitance between the gate electrode layer and the source / drain electrode layer by self-aligning the gate electrode layer and the source / drain electrode layer.

In order to achieve the above object, a method of manufacturing a thin film transistor according to an embodiment of the present invention, forming a pattern of a transparent active layer on a portion of a transparent substrate; Forming a lamination mask on the substrate such that a window is positioned on a portion of the pattern of the active layer; Sequentially forming a transparent gate insulating film and a transparent gate electrode layer on an active layer in the window of the lamination mask; Removing the stacked mask, the gate insulating layer, and the gate electrode layer to expose the pattern of the substrate and the active layer; And forming a transparent source / drain electrode layer on the pattern of the active layer to self-align with the gate electrode layer.

Preferably, the width of the lower part of the window of the laminated mask can be wider than the width of the upper part of the window.

Preferably, the laminated mask can be formed as a photosensitive film.

Preferably, the active layer can be formed of any one of zinc oxide (ZnO) and a compound based on zinc oxide (ZnO).

According to the present invention, the active layer, the gate electrode layer, and the source / drain electrode layer of the thin film transistor can be formed of a transparent metal oxide film, and parasitic between the gate electrode layer and the source / drain electrode layer by self-aligning the gate electrode layer and the source / drain electrode layer. Capacitance can be minimized.

1 to 6 are process flowcharts showing a method of manufacturing a thin film transistor according to a preferred embodiment of the present invention.

Hereinafter, a method of manufacturing a thin film transistor according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 to 6 are cross-sectional process diagrams showing the steps applied to the method of manufacturing a thin film transistor according to an embodiment of the present invention, respectively.

Referring to FIG. 1, first, a transparent substrate 10 for forming a thin film transistor of the present invention, for example, a transparent flat glass substrate is prepared. Of course, instead of the glass substrate, other transparent substrates can be used that can maintain the characteristics as the substrate at the high temperature of each process during the various processes for manufacturing the thin film transistor of the present invention.

Next, a pattern of the transparent active layer 20 is formed on a portion of the upper surface of the substrate 10, that is, the transparent active layer forming portion.

In more detail, for example, using a deposition process such as sputtering deposition, atomic layer deposition, metal-organic chemical vapor deposition (MOCVD), pulsed laser deposition, etc. On the surface of the substrate 10, a transparent metal oxide film made of, for example, zinc oxide (ZnO) or a compound based on zinc oxide (ZnO) such as GIZO (GaInZnO), has a thickness of 20 nm to 100 nm. Laminated. Subsequently, a photomask (not shown) for the active layer pattern is formed on the active layer pattern forming portion of the metal oxide layer by using a photolithography process, and the exposed metal outside the photomask is used as an etching mask. Remove the oxide film. Accordingly, the transparent active layer 20 may be formed on the active layer pattern forming portion of the substrate 10.

Instead of forming a pattern of the active layer 20 by sequentially performing a sputtering lamination process and a photolithography process, a shadow mask (not shown) in which an opening for an active layer pattern forming portion is formed is formed on the substrate 10. After being disposed on the surface, the active layer (only on the active layer pattern forming portion of the substrate 10 by laminating a transparent metal oxide film to a thickness of 20 nm to 100 nm on the surface of the substrate 10 using a sputtering deposition process) 20) may be formed.

After the pattern of the active layer 20 is formed, in order to improve the thin film characteristics of the active layer 20, the active layer 20 is about 400 ℃ ~ 500 ℃ in an inert gas atmosphere such as nitrogen gas, argon gas, etc. The heat treatment is performed for about 10 minutes at the temperature.

Referring to FIG. 2, a photoresist layer 30, for example, a negative photoresist layer is coated on the substrate 10 including the pattern of the active layer 20 by using a photographic process, and then the active layer 20 is coated. A gate electrode formation window 31 positioned on the gate electrode formation portion of the film is formed.

Here, the photoresist film 30 is coated with a relatively thick thickness, for example, a thickness of 2 μm to 3 μm, which is formed during the formation of the gate electrode formation window 31 of the photoresist film 30. In order to undercut the inner wall (33) of the. Therefore, the width of the gate electrode forming window 31 becomes wider from the upper portion of the gate electrode forming window 31 toward the lower portion, so that the width W2 of the lower portion is wider than the width W1 of the upper portion.

Referring to FIG. 3, a dielectric material such as, for example, a dielectric having a high relative dielectric constant, ie, Al 2 O 3 , is formed on the substrate 10 masked by the photosensitive film 30 using a sputtering deposition process or the like. The transparent gate insulating film 40 is laminated to a thickness of 20 to 50 nm. At this time, the pattern of the gate insulating film 40 is laminated in a pattern corresponding to the pattern of the gate electrode formation window 31 on the gate electrode formation portion of the active layer 20 in the gate electrode formation window 31. At the same time, the gate insulating film 40 is also laminated on the photosensitive film 30 outside the gate electrode formation window 31.

Subsequently, a transparent conductive gate electrode layer 50, for example, aluminum zinc oxide (AZO), indium tin oxide (ITO), or the like is deposited on the gate insulating film 40 by using a sputtering deposition process, depending on the deposition temperature. It is laminated to a thickness of ㎚. At this time, the pattern of the gate electrode layer 50 is laminated in a pattern corresponding to the pattern of the gate electrode formation window 31 on the pattern of the gate electrode 40 in the gate electrode formation window 31. At the same time, the gate electrode layer 50 is also laminated on the gate insulating film 40 outside the gate electrode formation window 31.

Therefore, conventionally, when the gate electrode layer is formed by the photolithography process, the surface of the active layer outside the gate electrode layer is etched. However, the present invention uses the photolithography process instead of the photolithography process to form the active layer in the gate electrode forming window 31. Since the gate electrode layer 50 is formed on the layer 20, the etching damage of the active layer 20 may be prevented, and defects on the surface of the active layer 20 may be minimized. This minimizes the contact resistance between the active layer 20 and the source / drain electrode layer 70 shown in FIG.

Referring to FIG. 4, the photosensitive film 30 shown in FIG. 3 is removed using, for example, a lift-off method. 3, the gate insulating film 40 and the gate electrode layer 50 on the photosensitive film 30 are separated and removed from the substrate 10 at the same time as the photosensitive film 30 is removed. Therefore, the substrate 10, the active layer 20, and the gate electrode layer 50 are exposed.

Referring to FIG. 5, a metal layer for a source / drain electrode layer, for example, on the substrate 10 including the active layer 20 and the gate electrode layer 50 is then used, for example, using a vacuum deposition process or the like. For example, a pure aluminum layer 60 is laminated to a thickness of 1 to 5 nm.

Referring to FIG. 6, the pure aluminum of the aluminum layer 60 is then thermally treated by heating the aluminum layer 60 shown in FIG. 5, for example, in an oxygen gas atmosphere at a temperature of about 450 ° C. for about 1 to 5 minutes. Since the active layer 20 and the gate electrode layer 50 are diffused to dop the surfaces of the active layer 20 and the gate electrode layer 50, a transparent source / drain region 70 is formed on the active layer 20. In this case, the gate insulating layer 40 and the gate electrode layer 50 serve as a mask so that the source / drain regions are self-aligned with the gate electrode layer 50. Therefore, parasitic capacitance between the gate electrode 50 and the source / drain region 70 can be minimized.

On the other hand, the aluminum of the aluminum layer 60 deposited on the side surface portion of the gate insulating film 40 reacts with the oxide of the gate insulating film 40, for example, Al 2 O 3 , simultaneously with diffusion to form an oxide film.

Subsequently, the pure aluminum remaining on the substrate 10, the active layer 20, and the gate electrode layer 50, which has not reacted in the heat treatment process, is completely removed by the aluminum etchant, so that the gate electrode layer and the source / drain electrode of the transparent thin film transistor are removed. To form.

Then, the usual additional process such as source / drain electrode layer formation is carried out, but since it is less relevant to the gist of the present invention, description thereof will be omitted.

On the other hand, the present invention has been described in connection with the above-mentioned preferred embodiment, it is possible to make various modifications or variations without departing from the spirit and scope of the present invention. Accordingly, the appended claims will cover such modifications and variations as fall within the spirit of the invention.

10: Substrate
20: active layer
30: photosensitive film
31: gate electrode forming window
33: inner wall
40: gate insulating film
50: gate electrode layer
60: aluminum layer
70: source / drain electrode layer

Claims (4)

Forming a pattern of a transparent active layer on a portion of the transparent substrate;
Forming a lamination mask on the substrate such that a window is positioned on a portion of the pattern of the active layer;
Sequentially forming a transparent gate insulating film and a transparent gate electrode layer on an active layer in the window of the lamination mask;
Removing the stacked mask, the gate insulating layer, and the gate electrode layer to expose the pattern of the substrate and the active layer;
Forming a transparent source / drain electrode layer on the pattern of the active layer to self-align with the gate electrode layer.
The method of manufacturing a thin film transistor according to claim 1, wherein the width of the lower part of the window of the laminated mask is wider than the width of the upper part of the window.
The method of claim 2, wherein the multilayer mask is formed of a photosensitive film. The method of manufacturing a thin film transistor according to claim 1, wherein the active layer is formed of one of zinc oxide (ZnO) and a compound based on zinc oxide (ZnO).
KR1020100035420A 2010-04-16 2010-04-16 Method for manufacturing thin film transistors KR101073786B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100035420A KR101073786B1 (en) 2010-04-16 2010-04-16 Method for manufacturing thin film transistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100035420A KR101073786B1 (en) 2010-04-16 2010-04-16 Method for manufacturing thin film transistors

Publications (1)

Publication Number Publication Date
KR101073786B1 true KR101073786B1 (en) 2011-10-13

Family

ID=45032859

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100035420A KR101073786B1 (en) 2010-04-16 2010-04-16 Method for manufacturing thin film transistors

Country Status (1)

Country Link
KR (1) KR101073786B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200045100A (en) * 2018-10-22 2020-05-04 엘지디스플레이 주식회사 Thin film trnasistor, method for manufacturing the same and display device comprising the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100678739B1 (en) 2005-10-21 2007-02-02 비오이 하이디스 테크놀로지 주식회사 Method for forming nanocrystalline-si thin film transistor with top gate structure
KR100763913B1 (en) 2006-04-27 2007-10-05 삼성전자주식회사 Method of fabricating a thin film transistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100678739B1 (en) 2005-10-21 2007-02-02 비오이 하이디스 테크놀로지 주식회사 Method for forming nanocrystalline-si thin film transistor with top gate structure
KR100763913B1 (en) 2006-04-27 2007-10-05 삼성전자주식회사 Method of fabricating a thin film transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200045100A (en) * 2018-10-22 2020-05-04 엘지디스플레이 주식회사 Thin film trnasistor, method for manufacturing the same and display device comprising the same
KR102599741B1 (en) * 2018-10-22 2023-11-07 엘지디스플레이 주식회사 Thin film trnasistor, method for manufacturing the same and display device comprising the same

Similar Documents

Publication Publication Date Title
US10615266B2 (en) Thin-film transistor, manufacturing method thereof, and array substrate
JP5417332B2 (en) Method for manufacturing field effect transistor
US9252285B2 (en) Display substrate including a thin film transistor and method of manufacturing the same
JP5584960B2 (en) Thin film transistor and display device
KR101980196B1 (en) Transistor, method of manufacturing the same and electronic device including transistor
US8455310B2 (en) Methods of manufacturing thin film transistor devices
WO2018149171A1 (en) Array substrate and manufacturing method thereof, and display device
CN107195641B (en) Array substrate, preparation method thereof and display panel
JP2007220817A (en) Thin-film transistor and manufacturing method thereof
KR20110028385A (en) Treatment of gate dielectric for making high performance metal oxide and metal oxynitride thin film transistors
US8664051B2 (en) Thin-film transistor and manufacturing method thereof and display
TW201513369A (en) Thin film transistor and method of manufacturing the same
US9704998B2 (en) Thin film transistor and method of manufacturing the same, display substrate, and display apparatus
KR102091444B1 (en) Display substrate and method of manufacturing a display substrate
KR20150018501A (en) Method for increasing the electrical conductivity of metal oxide semiconductor layers
EP3621105A1 (en) Oled display panel and method for manufacturing same
WO2018223476A1 (en) Manufacturing method for indium gallium zinc oxide thin film transistor
US20120280235A1 (en) Thin film fet device and method for forming the same
KR20170119294A (en) Method for fabricating fully self-aligned dual-gate thin film transistors
US9252284B2 (en) Display substrate and method of manufacturing a display substrate
US10115745B2 (en) TFT array substrate and method of forming the same
JP6106024B2 (en) Thin film transistor manufacturing method and thin film transistor
KR101073786B1 (en) Method for manufacturing thin film transistors
KR100458702B1 (en) Manufacturing apparatus and method of semiconductor device
KR102280449B1 (en) Method for manufacturing oxide thin film transistor

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20141106

Year of fee payment: 4

FPAY Annual fee payment

Payment date: 20161107

Year of fee payment: 6

FPAY Annual fee payment

Payment date: 20181001

Year of fee payment: 8

FPAY Annual fee payment

Payment date: 20191001

Year of fee payment: 9