TWI593118B - Method for increasing the electrical conductivity of metal oxide semiconductor layers - Google Patents

Description

Method of increasing conductivity of a metal oxide semiconductor layer

The disclosed technology relates to a method of locally increasing the conductivity of a metal oxide semiconductor layer, a thin film transistor based on a metal oxide semiconductor, and a method of manufacturing a thin film transistor based on a metal oxide semiconductor.

When manufacturing a metal oxide semiconductor thin film transistor such as a gallium-indium-zinc-oxide (abbreviation: GIZO or IGZO) thin film transistor, it is required to be more specifically located at a position corresponding to the source and drain contact regions. The conductivity of the semiconductor material is locally increased to improve charge injection and reduce contact resistance.

(Local) increase in conductivity GIZO several methods known in the art it is, such as by ion implantation or diffusion of an impurity or doping as argon plasma process or NH ₃ plasma process.

In US 2012/0001167, a method of manufacturing a metal oxide semiconductor thin film transistor is described in which an alternative method is used to locally increase the conductivity of the metal oxide semiconductor layer. After depositing the metal oxide semiconductor layer, the gate insulator, and the gate electrode, a metal thin film made of a metal such as Ti, Al or In is provided, the metal thin film having a thickness of 10 nm or less. The heat treatment is then carried out in an oxygen-containing atmosphere, for example, at a temperature of 300 °C. Due to this heat treatment, the metal thin film is oxidized. In the oxidation reaction of the metal thin film, a part of oxygen included in the source region and the drain region of the metal oxide semiconductor layer is transferred to the metal thin film. therefore, The oxygen concentration in the source region and the drain region is lowered, so that a low resistance region is formed on the upper portion of the metal oxide semiconductor layer. The thickness of the metal thin film is preferably 10 nm or less, so that the metal thin film can be completely oxidized during heat treatment in an oxygen-containing atmosphere. This eliminates the need to perform an etching step to remove unoxidized metal. The process described in US 2012/0001167 requires a temperature of at least 200 ° C, for example about 300 ° C. Therefore, this method is incompatible with some low-cost flexible substrates such as PET (polyethylene terephthalate), PEN (polyethylene naphthalate) and PC (polycarbonate), and may There is a need for higher value plastic foils with increased thermal and/or chemical stability, such as PI (polyimide), PES (polyether oxime) or PEEK (polyether ether ketone). The method also requires good control of the thickness of the metal layer in order to avoid the need to perform an etching step to remove unoxidized metal.

Some aspects of the invention relate to a locally increased metal oxide semiconductor layer A method of electrical conductivity, wherein the method can be performed at a temperature of no more than 200 ° C or no more than about 200 ° C or less than 200 ° C, and wherein the method is less complex than prior art methods.

According to a first aspect of the present invention, there is disclosed an increase in metal oxygen at a predetermined position A method of conducting conductivity of a semiconductor layer, wherein the method comprises: providing a reducing agent in physical contact with the metal oxide semiconductor layer at a predetermined position and inducing a chemical reduction reaction between the reducing agent and the metal oxide semiconductor layer, thereby affecting The chemical composition of the metal oxide semiconductor layer at a predetermined position.

The first sub-state of the invention relates to an increase in metal oxidation at a predetermined position A method of electrical conductivity of a semiconductor layer, wherein the method comprises: providing an alkali metal (eg, Li, Na, K, Rb, Cs, or Fr) in physical contact with the metal oxide semiconductor layer at a predetermined location or a reduction layer of any combination) or an alkaline earth metal (for example, any one or any combination of Be, Mg, Ca, Sr, Ba or Ra); inducing a chemical reduction reaction between the reduction layer and the metal oxide semiconductor layer, thereby affecting The chemical composition of the metal oxide semiconductor layer at a predetermined position, For example, reducing the oxygen content of the metal oxide semiconductor layer at the predetermined position; and performing a rinsing step to remove the reduction layer or the excess reduction layer and the reaction product or by-product of the reduction reaction.

The rinsing step is a step of removing by gently washing in a liquid such as water. Step.

In one aspect, the chemical reduction reaction between the induced reduction layer and the metal oxide semiconductor layer can include performing an annealing step at a temperature ranging between about 20 ° C and 200 ° C. The annealing step can be carried out under an inert atmosphere or in a vacuum (for example, in the range between about 10 ^-6 Torr and 10 ^-8 Torr, that is, between about 1.33 10 ^-4 Pa and 1.33 10 ^-6 Pa). Next) Execution.

In another aspect, the chemical reduction reaction between the induced reduction layer and the metal oxide semiconductor layer can include waiting for a predetermined period of time after providing the reduction layer, for example, a period ranging between about 1 minute and 5 hours, such as at about Between 15 minutes and 2 hours. The waiting step can, for example, comprise holding the sample in a chamber in which the reducing layer has been provided. The waiting step can be carried out under vacuum at a pressure in the range between about 10 ^-6 Torr and 10 ^-8 Torr (i.e., in the range between about 1.33 10 ^-4 Pa and 1.33 10 ^-6 Pa). The waiting step can be carried out, for example, at a temperature in the range between about -50 ° C and +50 ° C.

Inducing a chemical reduction reaction between the reduction layer and the metal oxide semiconductor layer A step of performing a wait in accordance with an aspect of the present invention is performed, followed by performing an annealing step in accordance with an aspect of the present invention.

In one aspect, increasing the conductivity of the metal oxide semiconductor layer may include increasing The surface portion of the metal oxide semiconductor layer (for example, a surface portion having a thickness of about 10 nm to several tens of nm (such as a thickness of about 10 nm to 40 nm, for example, a thickness of between 10 nm and 40 nm) is added. In another aspect, increasing the conductivity of the metal oxide semiconductor layer can include increasing conductivity throughout the thickness of the metal oxide semiconductor layer.

In one aspect, the method can be advantageously used with a metal oxide semiconductor In the method for fabricating a thin film transistor of an active layer, it is used to locally increase the conductivity at a predetermined position corresponding to the source region and the drain region, thereby improving charge injection of the source contact and the drain contact. In a In one aspect, the method can be used in a method of fabricating a self-aligned top gate thin film transistor.

In one aspect, the method can also be used based on other metal oxide semiconductors. In the method of fabricating a device such as a diode or a transistor-diode, it is used to improve charge injection of a contact.

The metal oxide semiconductor layer may, for example, comprise gallium-indium-zinc-oxide (GIZO) Or, for example, a semiconductor based on other metal oxides having the following composition (not indicating stoichiometry): ZnO, ZnSnO, InO, InZnO, InZnSnO, LaInZnO, GaInO, HfInZnO, MgZnO, LaInZnO, TiO, TiInSnO, ScInZnO, SiInZnO, and ZrInZnO , ZrZnSnO. However, the invention is not limited thereto, and in one aspect, the method can be used with other suitable metal oxide semiconductors known to those skilled in the art. Such semiconductor layers having a typical thickness between 5 nm and 50 nm can be provided by a variety of methods such as sputtering, thermal evaporation, pulsed laser deposition, and spin casting of precursor solutions, ink jet printing or drop casting (drop Casting).

The reducing layer comprising an alkali metal or alkaline earth metal may be a continuous layer. In one aspect The reducing layer may be a discontinuous layer, for example, it may be a layer formed of a plurality of (nano) islands.

A reducing layer comprising an alkali metal or an alkaline earth metal may be, for example, an alkali metal or an alkaline earth gold Is a component. Alternatively, the reducing layer may comprise an alloy containing an alkali metal or an alkaline earth metal.

In one aspect, the chemical reduction reaction can be carried out by causing the metal oxide semiconductor layer to be at a predetermined position with a chemical reducing agent dissolved in the liquid, such as an aqueous solution of sodium thiosulfate (Na ₂ S ₂ O ₃ ) or hydrazine, Or a physical contact of sodium naphthalenide or sodium acenaphthenide in an organic solvent such as an ether solvent or a chemical reducing agent such as hydrazine in the gas phase.

The thickness of the layer comprising an alkali metal or alkaline earth metal may, for example, be in the range between about 1 nm and 100 nm, such as between about 5 nm and 50 nm or between about 5 nm and 25 nm.

The annealing step can be performed at a temperature in the range between about 20 ° C and 200 ° C, and for example, the annealing time is in the range between about 1 minute and 1 hour. In one aspect, to avoid consumption of an alkali or alkaline earth metal by an undesired reaction in the atmosphere, an annealing step is performed under an inert atmosphere such that oxidation, for example, due to oxygen from residual water or moisture is prevented. Annealing can be performed, for example, in a glove box filled with moisture and an oxygen absorber filled with argon or nitrogen (or helium, neon, xenon, xenon). Other gases, such as helium, can also be used to form an inert atmosphere. In a specific example using a reducing layer containing a chemically less reactive metal such as calcium, nitrogen gas may also be used as an inert atmosphere. In another aspect, to avoid consumption of an alkali or alkaline earth metal by an undesired reaction under the atmosphere (e.g., oxygen, moisture, water), the sample can be held in a vacuum (waiting step) at about 1.33 10 ^{- 4} Pa and a pressure in the range between 1.33 10 ^-6 Pa and at a temperature in the range between about -50 ° C and +50 ° C for a predetermined period of time (for example between about 1 minute and 5 hours, for example about 15 minutes) Between 2 hours).

In one aspect, the rinsing process can use a rinsing tool (eg, a rinsing tool Water). However, the invention is not limited thereto and the rinsing process can be carried out using other liquids such as alcohols.

An advantage of an aspect of the invention is that at temperatures below about 200 ° C (eg The conductivity of the metal oxide semiconductor layer at about 150 ° C or less can be significantly increased, for example, by at least about three orders of magnitude. Thus, in one aspect, the method is compatible with the use of low cost flexible substrates such as PET, PEN or PC.

An advantage of an aspect of the invention is that unreacted metal can be rinsed by The steps (eg water) are easily removed. An advantage of an aspect of the invention is that the need to perform an oxidation step or an etching step in an atmosphere containing oxygen or ozone to remove unreacted metal can be avoided.

An advantage of an aspect of the invention is the reaction product (eg, reacted metal) It can also be removed by performing a rinsing step. In some embodiments, the reaction product (eg, the reacted metal) can be easily removed by performing a rinsing step with water. For example, when a reducing layer containing Ca is used, a chemical reduction reaction between the reducing layer and the metal oxide layer causes oxidation to form Calcium, which has good solubility in water. In other embodiments, such as when a reducing layer comprising Mg is used, the reaction product (eg, magnesium oxide) can be removed by performing a rinsing step with an acid.

One advantage is that the metal used in the method of the reduction layer is metal A dense oxide layer is not formed at the interface with the metal oxide semiconductor, which can block or prevent further reaction with the underlying metal oxide semiconductor layer. Therefore, it is not necessary to perform good thickness control on the layer containing metal.

An advantage of the aspect of the invention is that the reduction layer and the metal oxide semiconductor layer The chemical reduction reaction between them may not be self-limiting (does not form a dense oxide layer that blocks or prevents further reactions), and thus allows for a larger portion (into the deeper, ie, substantially positive) compared to other methods. The conductivity of the metal oxide semiconductor layer is increased in the direction of the surface plane of the metal oxide semiconductor layer. This larger portion may comprise an entry depth greater than 50%, or greater than 60%, or greater than 70%, or greater than 80%, or greater than 90%, or 100%.

In a second sub-embodiment of the invention, the use of a reducing layer can be avoided. Then the method can This is performed by providing a reducing agent in physical contact with the metal oxide semiconductor layer at a predetermined position and inducing a chemical reduction reaction between the reducing agent and the metal oxide semiconductor layer, comprising: dissolving the metal oxide semiconductor layer and the liquid at a predetermined position The chemical reducing agent in the physical contact. The effect can be similar to that described with respect to the first sub-state.

In the third sub-state, the reduction layer is also not used, and the gold is provided at the predetermined position. The reducing agent that is in physical contact with the oxide semiconductor layer and inducing a chemical reduction reaction between the reducing agent and the metal oxide semiconductor layer includes physically contacting the metal oxide semiconductor layer with a chemical reducing agent in a gas phase at a predetermined position. The effect can be similar to that described with respect to the first sub-state.

In one aspect of the invention, the chemical reduction reaction can increase the conductivity throughout the thickness of the metal oxide semiconductor layer, and in addition it can increase the (part of) the insulating layer (eg, a dielectric layer, such as a dielectric layer, such as a lower layer of the metal oxide semiconductor layer Conductivity of a cerium oxide layer or an aluminum oxide layer). In the case of a top gate transistor configuration, the underlying layer of the oxide semiconductor layer (eg, Such a reduction reaction of an electrical layer, such as a hafnium oxide layer or an aluminum oxide layer, can be advantageous because it can produce higher conductivity of the source and drain contacts and can allow for the fabrication of a self-aligned bottom contact.

In a second aspect of the invention, the use of the method according to the first aspect is disclosed Manufacturing a thin film transistor having a metal oxide semiconductor active layer for locally increasing conductivity at predetermined positions corresponding to the source region and the drain region, thereby improving charge injection of the source contact and the drain contact, the latter Typically provided on the source and drain regions.

According to the first aspect, the method can be used to manufacture a self-aligned top gate film Crystal.

Certain objects and advantages of various aspects of the invention have been described above. when It should be understood, however, that not all such objects or advantages may be practiced in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the present invention can be implemented or carried out in a manner that achieves or optimizes an advantage or a group of advantages as disclosed herein without necessarily achieving a teaching or suggestion as herein. Other goals or advantages. In addition, it should be understood that this summary is only an example and is not intended to limit the scope of the invention. The invention (with respect to the organization and method of operation) as well as its features and advantages can be best understood by reference to the following embodiments in conjunction with the accompanying drawings.

10‧‧‧Substrate

11‧‧‧Working layer

12‧‧‧ gate insulator

13‧‧‧ gate electrode

14‧‧‧Reducing layer

110‧‧‧Channel area

111‧‧‧ source area

112‧‧‧Bungee Area

151‧‧‧ areas with increased conductivity

152‧‧‧Area with increased conductivity

Figure 1 shows the electrical resistance of a GIZO layer measured after different treatments at 150 °C and for different annealing times.

Figure 2 shows the resistance of the GIZO layer as measured as a function of annealing temperature before and after evaporation of the Ca layer.

3 to 7 illustrate the steps of a method of manufacturing a metal oxide semiconductor thin film transistor according to a method in one embodiment.

Figure 8 shows an optical micrograph of a substrate (GIZO on SiO ₂ ) after calcium treatment according to a specific example. Calcium is evaporated through a shadow mask. The darker area corresponds to the opening of the shadow mask.

Figure 9 shows the results of electrical measurements performed on a transistor having a Ca-treated GIZO source/drain junction. Top graph: Transfer characteristics; bottom graph: Output characteristics.

Figure 10 shows the Ca-treated GIZO (on SiO ₂ dielectric) resistivity as a function of the gap between the GIZO thickness and the contact pad between the two gold top contact pads.

Figure 11 shows the elemental depth distribution of indium, gallium, zinc and calcium in a Ca-treated GIZO substrate (60 nm GIZO on SiO ₂ dielectric) (by time-of-flight secondary ion mass spectrometry).

Figure 12 shows five transfer curves produced by lithographically patterned transistors with Ca-treated GIZO source/drain contacts.

Any reference signs should not be construed as limiting the scope of the invention.

In the different figures, the same reference symbols refer to the same or similar elements.

In the following embodiments, numerous specific details are set forth in order to provide a comprehensive understanding of the invention and its embodiments. However, it is understood that the invention may be practiced without such specific details. In other instances, well-known methods, procedures, and techniques have not been described in detail so as not to obscure the invention. Although the invention will be described with respect to particular embodiments and with reference to certain drawings, the invention is not limited thereto. The drawings included and described herein are illustrative and not limiting of the scope of the invention. It is also noted that the size of some of the elements may be exaggerated in the drawings and, therefore, are not drawn to scale for illustrative purposes.

In addition, in the present specification, the terms first, second, third and similar terms are used to distinguish similar elements and are not necessarily used to describe a sequence in time, space, grade or in any other manner. It is understood that the terms so used are interchangeable under appropriate circumstances and the specific embodiments of the invention described herein are capable of operation other than the sequence described or illustrated herein.

Moreover, in this specification, the terms top, bottom, over, under, and the like are used for descriptive purposes and are not necessarily used to describe relative positions. It should be understood that the use of such a technique The language is interchangeable under appropriate circumstances, and the specific embodiments of the invention described herein can be practiced in other aspects than those described or illustrated herein.

It should be noted that the term "comprising" should not be construed as being limited to Components listed later; it does not exclude other components or steps. Therefore, it should be interpreted as indicating the existence of the described features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components or groups thereof. Therefore, the expression "a device includes components A and B" is not limited to the device consisting of only components A and B.

According to a specific example for increasing metal oxide semiconductivity at a predetermined location The method of electrical conductivity of a bulk layer comprises: providing an alkali metal (Li, Na, K, Rb, Cs or Fr) or an alkaline earth metal (Be, Mg, Ca, Sr, in physical contact with a metal oxide semiconductor layer at a predetermined position) a reducing layer of Ba or Ra); inducing a chemical reduction reaction between the reducing layer and the metal oxide semiconductor layer, thereby affecting the chemical composition of the metal oxide semiconductor layer, for example, reducing the oxygen content of the metal oxide semiconductor layer at a predetermined position Or reducing the oxidation state of the metal ion of the metal oxide semiconductor layer; and performing a rinsing step to remove the reduction layer (a reducing layer which may be excessively increased from another angle) and a reaction product of the reduction reaction (from another point of view Reaction by-product).

In one aspect, the chemical reduction reaction between the induced reduction layer and the metal oxide semiconductor layer can include performing an annealing step at a temperature ranging between about 20 ° C and 200 ° C. The annealing step can be carried out under an inert atmosphere or in a vacuum (for example, at a pressure in the range between about 10 ^-6 Torr and 10 ^-8 Torr, especially between about 1.33 10 ^-4 Pa and 1.33 10 ^-6 Pa) )carried out. The duration of the annealing step can be, for example, between 5 minutes and 30 minutes.

In another aspect, the chemical reduction reaction between the induced reduction layer and the metal oxide semiconductor layer can include waiting for a predetermined period of time after providing the reduction layer, for example, a period ranging between about 1 minute and 5 hours, such as at about Between 15 minutes and 2 hours. The waiting step can, for example, comprise holding the sample in a chamber in which the reducing layer has been provided. The waiting step can be performed under vacuum, between about 10 ^-6 Torr and 10 ^-8 Torr, or at a pressure in the range between about 1.33 10 ^-4 Pa and 1.33 10 ^-6 Pa. The waiting step can be carried out, for example, at a temperature in the range between about -50 ° C and +50 ° C.

Inducing a chemical reduction reaction between the reduction layer and the metal oxide semiconductor layer A step of performing a wait in accordance with an aspect of the present invention is performed, followed by performing an annealing step in accordance with an aspect of the present invention.

In one embodiment, the method can be advantageously used with a metal oxide half In the method of manufacturing a thin film transistor of a conductor action layer, it is used to locally increase conductivity at a predetermined position corresponding to, for example, a source region and a drain region, thereby improving charge injection.

In one embodiment, the method is further described as a specific example in which the metal oxide semiconductor layer is a gallium-indium-zinc-oxide (GIZO or IGZO) layer and the reduction layer is a Ca layer. However, the invention is not limited thereto and other metal oxide semiconductor layers and/or reduction layers may be used.

An experiment was performed in which a nominal 15 nm thick GIZO layer was sputtered on a 100 nm thick yttria layer on a 100 nm thick yttrium oxide layer from a 1:1:1 ratio Ga:In:Zn target. It was found that the resistance of the deposited GIZO layer (measured between one corner of the substrate and the opposite of the substrate) was higher than 200 megohms, which is the upper limit of the scale of the multimeter used. Figure 1 shows the resistance of a GIZO layer measured after a different continuous treatment at 150 ° C on a hot plate inside a nitrogen-filled glove box and continued for different annealing times (0 min = no annealing): 20 nm thick Ca in thermal evaporation After the layer (evaporation rate: 1 angstrom/second), it was then briefly rinsed in water and dried under nitrogen; rinsed again in water for 5 minutes and dried with nitrogen; stored in air for another night; in water at 70 °C After 2 hours of treatment and drying with nitrogen; and after storage in air for various times (6 days, 12 days and 19 days). The results show that the resistance is rapidly reduced immediately after Ca deposition. However, extended air storage again causes a significant loss of electrical conductivity. The longer the annealing time, the smaller the conductivity loss.

2 shows the measured resistance values of a nominal 15 nm thick GIZO layer sputtered on a 100 nm thick yttrium oxide layer on a 100 nm thick yttrium oxide layer by a 1:1:1 ratio Ga:In:Zn target. The solid line shows the initial resistance without Ca evaporation. The filled square shows a 20 nm thick Ca layer (obtained by thermal evaporation at a rate of 1 angstrom/second) at evaporation (at 25 ° C) and then filled with nitrogen. The inside of the work box was annealed on a hot plate at different temperatures for 15 minutes, followed by rinsing with water and drying after drying under a stream of nitrogen. A decrease in electrical resistance has been observed at an annealing temperature of 25 °C. Lower resistance was observed after annealing at 100 ° C and at 150 ° C.

In a specific example, the gate and the drain are self-aligned with the gate (self-aligned) The method is further described in the context of a method of fabricating a thin film transistor of a quasi-top gate structure. An advantage of this fabrication method is that it allows for a reduction in parasitic capacitance between the gate and source/drain regions. However, the invention is not limited thereto and the method can be used to fabricate other thin film transistors and/or other metal oxide semiconductor based devices.

3 to 7 illustrate the fabrication of a metal oxide semiconductor thin film according to a specific example. Process steps of the method of film transistor.

In the first step illustrated in FIG. 3, a metal oxide semiconductor layer (such as a GIZO layer) is provided on the substrate 10, for example, by sputtering, laser ablation or spin coating from a precursor solution. The thickness of the GIZO layer can be, for example, about 10 nm or about 15 nm to 20 nm, such as between 10 nm and 20 nm, although other suitable thicknesses can be used. In the embodiment shown in Figure 3, the GIZO layer is patterned at this stage of the fabrication process to form the active layer 11 of the transistor. However, the invention is not limited thereto. For example, the GIZO layer can also be patterned in a stage after the fabrication process, such as after forming the source and drain contacts.

Next, a gate insulating layer and a gate electrode layer are sequentially provided on the substrate 10 and the active layer 11. The gate electrode layer and the gate insulating layer are then patterned to form the gate electrode 13 and the gate insulator 12, thereby defining the channel region 110 (FIG. 4), the source region 111, and the drain region under the gate in the active layer 11. 112.

Next, the source region 111 and the drain region 112 of the metal oxide semiconductor layer 11 are processed by a specific example. As illustrated in FIG. 5, a reduction layer 14 comprising an alkali metal or an alkaline earth metal such as Ca is provided over the substrate 10, the source region 111, the drain region 112, and the gate electrode 13. Next, an annealing step is performed at a temperature in the range between about 20 ° C and 200 ° C, in gold The direct chemical contact between the oxide semiconductor layer 11 and the reduction layer 14 (i.e., in the source region 111 and the drain region 112 of the metal oxide semiconductor layer 11) causes local chemical reduction. This reduction causes regions 151, 152 (Fig. 6) having increased conductivity in the source region 111 and the drain region 112 in the surface portion of the metal oxide semiconductor layer 11. These regions of increased electrical conductivity automatically align (self-align) the gate regions.

In the next step, for example, the reducing layer 14 is rinsed off in water (Fig. 7) (from another One point of view is the unreacted portion or excess of the reducing layer material), and other processing steps can be performed to complete the thin film transistor. For example, a dielectric layer or an encapsulation layer may be provided over the structure shown in FIG. 7, and then a via hole into the dielectric layer or encapsulation layer may be formed at a location where a contact is required to be formed, and a suitable metal is used. The vias are filled to form, for example, source contacts and drain contacts (not depicted). However, other suitable processing steps can be used to complete the transistor structure.

An experiment illustrating the usefulness of a method of a specific example for a GIZO transistor is to use a substrate comprising a semiconductor GIZO layer over a thick thermal SiO ₂ dielectric layer of about 120 nm on a doped germanium die having an aluminum backgate. Come on. The substrate was first cleaned by continuous rinsing with acetone and isopropanol and then dried under a stream of nitrogen. Evaporation of metal calcium at a rate of 1 angstrom/second via a shadow mask over a high-vacuum vacuum (approximately 10 ^-7 Torr) over a semiconductor GIZO (obtained by sputtering from a 1:1:1 Ga:In:Zn target) (about 20nm thick). After evaporating the metal, the substrate was held for an additional 30 minutes inside the high vacuum chamber to allow a chemical reduction reaction to occur. Next, the substrate was removed from the glove box and placed directly (without annealing step) in a rinsed deionized water bath for about 10 minutes. After drying with a stream of nitrogen, significant differences have been observed by the naked eye between the areas of the substrate that have been in contact with the metal calcium and those that have not been exposed to the metal. This is illustrated in FIG 8, shows the optical micrograph of calcium after completion of processing a substrate (GIZO on SiO ₂₎ of the. The darker region corresponds to the opening of the shadow mask through which Ca evaporates.

The electrical measurements of the respective transistors were performed under controlled atmosphere in a nitrogen filled glove box with oxygen and water levels below about 1 ppm. The common back gate is in contact with the measurement chuck, and the calcium treatment zone serving as the source and drain contacts is in direct contact with the stainless steel probe. Hot plate baking was further carried out at 100 ° C for 45 minutes in a nitrogen-filled glove box to remove any water marks such as those produced by the above-described rinsing step from the substrate. As illustrated in Figure 9, a transistor having a nominal channel length of 200 microns achieves an apparent saturation mobility of up to about 19 cm ² /(Vs). The top view of Figure 9 shows the transistor transfer characteristics, while the bottom view shows the transistor output characteristics. The mobility of a plurality of transistors having the same substrate and the reproducibility of the threshold voltage are good.

Additional experiments were conducted to investigate the effects of standing or waiting time under high vacuum, as appropriate. Ca treatment of GIZO (sprayed by 1:1:1 ratio Ga:In:Zn target) substrate with various nominal thicknesses (13 nm, 26 nm, 40 nm, and 60 nm) on a 130 nm thick SiO ₂ dielectric (Evaporation of 20 nm at a rate of 1 angstrom/second). After Ca deposition, an operating substrate was taken directly from the vacuum chamber and heated to 150 ° C on a hot plate inside a nitrogen filled glove box for 30 minutes. In a different manner, the second operation allowed the substrate to be held under high vacuum for 30 minutes and was not heat treated on a hot plate. The two operating substrates were then treated in a similar manner in a deionized water bath by a ten minute rinse step and then dried under a stream of nitrogen. A dark spot was observed by an optical microscope (100-fold magnification objective lens) showing that the substrate was kept under vacuum for 30 minutes, and a similar point was not observed in the substrate directly subjected to heat treatment after Ca deposition. Investigation of the substrate by scanning electron microscopy revealed that a large number of hillocks and pores existed in the substrate held under vacuum as compared with the substrate directly subjected to heat treatment by Ca deposition. For substrates that involve direct heat treatment after Ca deposition, the resistivity measured by the end of the probe in contact with the multimeter (at the ohmmeter position) is also low. For involving deposition of rectangular gold contact pads (evaporated 50 nm thick gold, 2 mm long with a nominal gap length between pads of 100 μm or 200 μm) onto a Ca-treated substrate having a different GIZO thickness The heat treatment operation performs a more accurate resistance measurement. As illustrated in Figure 10, the resistance from the 13 nm GIZO substrate to the 26 nm GIZO substrate was greatly reduced, while for the thicker GIZO layer only minimal changes in resistance were observed.

In addition, the Ca-treated substrate with a nominal 60 nm thick GIZO layer is introduced. Time-of-flight secondary ion mass spectrometry (TOF-SIMS) analysis. As shown by the TOF-SIMS curve shown in Fig. 11, calcium is present in the GIZO layer, and its concentration rapidly decreases from the top of GIZO to a depth of about 20 to 30 nm.

An experiment illustrating the usefulness of a method of a specific example for a GIZO transistor is performed on a doped germanium die having an aluminum back gate using a semiconductor GIZO layer over a about 130 nm thick thermal SiO ₂ dielectric layer (by 1 : 1:1 Ga: In: Zn target is obtained by sputtering the substrate. The substrate was first cleaned by continuous rinsing with acetone and isopropanol and then dried under a stream of nitrogen. Next, a photoresist was deposited on the substrate by spin casting and baked at 120 ° C for 2 minutes. Next, the photoresist is patterned by photolithography and developed in the developer such that the regions corresponding to the source and drain fingers and the contact pads become open. Next, calcium (about 20 nm thick) was evaporated on the substrate at a rate of 1 angstrom/second via a photoresist acting as a shadow mask under high vacuum (about 10 ^-7 Torr). After evaporating the metal, the substrate was taken directly from the vacuum chamber and heated to 120 ° C on a hot plate within 30 minutes in a nitrogen filled glove box. Next, the substrate was removed from the glove box and rinsed in a deionized water bath for about 10 minutes. After drying with a stream of nitrogen, the substrate was heated at 100 ° C for 100 minutes on a hot plate inside a nitrogen filled glove box to remove any traces of water, such as produced by the rinsing step described above, from the substrate. Although the patterned photoresist is still present for practical purposes to identify the source and drain contacts on the back of the substrate, it operates for GIZO transistors with Ca-treated GIZO source and drain contacts. Words do not need to exist. The electrical measurements of the respective transistors were performed under controlled atmosphere in a nitrogen filled glove box with oxygen and water levels below about 1 ppm. The common back gate is in contact with the measurement chuck, and the calcium treatment zone corresponding to the source and drain contacts is in direct contact with the stainless steel probe. A transistor with a nominal channel length of 5 microns achieves an apparent saturation mobility in the range of 1.2 cm ² /(Vs). As illustrated with respect to five different transistors in Fig. 12, the mobility of a plurality of transistors having the same substrate and the reproducibility of the threshold voltage are good.

The above description details some specific examples of the invention. However, it should be understood that regardless of How the above is presented in detail in the text, the invention can be implemented in many ways. It should be noted that The use of a particular term in the description of certain features or aspects of the invention is not intended to be construed as being limited to the specific features of the features or aspects of the invention.

While the above-described embodiments have shown, described and illustrated the novel features of the invention in the various embodiments of the present invention, it will be understood by those skilled in the art And the details are omitted, replaced and changed.

10‧‧‧Substrate

11‧‧‧Metal Oxide Semiconductor Layer/Working Layer

12‧‧‧ gate insulator

13‧‧‧ gate electrode

14‧‧‧Reducing layer

110‧‧‧Channel area

111‧‧‧ source area

112‧‧‧Bungee Area

151‧‧‧Area

152‧‧‧ area

Claims (23)

A method of increasing conductivity of a metal oxide semiconductor layer at a predetermined location, wherein the method comprises: providing a reducing agent in physical contact with the metal oxide semiconductor layer at the predetermined locations and inducing oxidation of the reducing agent with the metal A chemical reduction reaction between the semiconductor layers, thereby affecting the chemical composition of the metal oxide semiconductor layer at the predetermined positions, and performing a rinsing step to remove the reducing agent and reaction by-products of the chemical reduction reaction. The method of claim 1, wherein the metal oxide semiconductor layer comprises gallium-indium-zinc-oxide (GIZO) or a semiconductor based on other metal oxides having the following composition: ZnO, ZnSnO, InO, InZnO InZnSnO, LaInZnO, GaInO, HfInZnO, MgZnO, LaInZnO, TiO, TiInSnO, ScInZnO, SiInZnO, and ZrInZnO, ZrZnSnO. The method of claim 1, wherein the metal oxide semiconductor layer has a thickness between 5 nm and 50 nm. The method of claim 1, wherein providing a reducing agent in physical contact with the metal oxide semiconductor layer at the predetermined locations comprises providing a base in physical contact with the metal oxide semiconductor layer at the predetermined locations a reducing layer of a metal, an alkaline earth metal or an alloy of two types of metals; and wherein inducing a chemical reduction reaction between the reducing agent and the metal oxide semiconductor layer comprises inducing a chemistry between the reducing layer and the metal oxide semiconductor layer Reduction reaction. The method of claim 4, wherein the reducing layer comprises Ca. The method of claim 4, wherein the thickness of the reduced layer is in a range between about 1 nm and 100 nm. The method of claim 4, wherein the effect of the chemical composition of the metal oxide semiconductor layer at the predetermined position comprises removing the metal of the metal oxide semiconductor layer The child is chemically reduced to the reduced layer. The method of claim 4, wherein inducing a chemical reduction reaction between the reduction layer and the metal oxide semiconductor layer comprises performing an annealing step at a temperature in a range between about 20 ° C and 200 ° C for 1 minute. Duration between 60 minutes. The method of claim 8, wherein the annealing step is performed under an inert atmosphere or in a vacuum. The method of claim 4, wherein inducing a chemical reduction reaction between the reduction layer and the metal oxide semiconductor layer comprises waiting for a predetermined period of time after providing the reduction layer, the predetermined period of time being between 1 minute and 5 hours In the range. The method of claim 10, wherein the waiting comprises holding the sample in a chamber in which the reducing layer has been provided. The method of claim 10, wherein the waiting step is in a vacuum or in a range between about 1.33 10 ^-4 Pa and 1.33 10 ^-6 Pa and in a range between about -50 ° C and +50 ° C Executed at the temperature. The method of claim 10, wherein the waiting step is followed by an annealing step of a duration between 1 minute and 60 minutes at a temperature in the range between about 20 ° C and 200 ° C. The method of claim 4, wherein the rinsing step comprises rinsing in water or alcohol. The method of claim 1, wherein providing a reducing agent in physical contact with the metal oxide semiconductor layer at the predetermined positions and inducing a chemical reduction reaction between the reducing agent and the metal oxide semiconductor layer are included in The metal oxide semiconductor layer is in physical contact with the chemical reducing agent dissolved in the liquid at the predetermined positions. The method of claim 1, wherein providing a reducing agent in physical contact with the metal oxide semiconductor layer at the predetermined positions and inducing a chemical reduction reaction between the reducing agent and the metal oxide semiconductor layer are included in The metal oxide is half at the predetermined positions The conductor layer is in physical contact with a chemical reducing agent in the gas phase. The method of claim 1, which is carried out on a low-cost flexible substrate of PET type, PEN type or PC type. The method of claim 1, wherein the effect of the chemical composition of the metal oxide semiconductor layer at the predetermined locations comprises reducing the oxygen content of the metal oxide semiconductor layer. The method of claim 1, wherein increasing the conductivity of the metal oxide semiconductor layer comprises increasing the conductivity of a surface portion of the metal oxide semiconductor layer, the surface portion having a thickness of about 10 nm to 40 nm. The method of claim 1, wherein increasing the conductivity of the metal oxide semiconductor layer comprises increasing conductivity throughout the thickness of the metal oxide semiconductor layer. The method of claim 1, further comprising providing the metal oxide semiconductor layer on the insulating layer, and wherein increasing the conductivity of the metal oxide semiconductor layer comprises increasing the entire thickness of the metal oxide semiconductor layer and Conductivity of at least a portion of the insulating layer. Use of the method of claim 1, for producing a thin film transistor having a metal oxide semiconductor active layer for locally increasing conductivity at predetermined positions corresponding to the source region and the drain region, Thereby improving the charge injection of the source and the drain contacts. For use in the scope of claim 22, it is used to fabricate a self-aligned top gate thin film transistor.