WO2011160937A1

WO2011160937A1 - Method of manufacturing thin film transistors and transistor circuits

Info

Publication number: WO2011160937A1
Application number: PCT/EP2011/059269
Authority: WO
Inventors: Wan-Yu Lin; Robert Muller
Original assignee: Imec; Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek (Tno); Katholieke Universiteit Leuven
Priority date: 2010-06-21
Filing date: 2011-06-06
Publication date: 2011-12-29
Also published as: TW201205810A; KR20130112854A; JP2013535110A

Abstract

The present invention relates to a method for fabricating a structure such as a transistor, said method comprising the steps of: a. providing a continuous metal layer on an insulating substrate; b. providing a dielectric layer on the continuous metal layer, thereby forming a continuous dielectric layer on top of the continuous metal layer; and c. patterning the metal layer and the dielectric layer, wherein said patterning comprises a wet etching step with an etchant that etches the metal layer substantially faster than the dielectric layer, wherein step (c) is performed after step (b). The present invention further relates to structures thereby obtained.

Description

Method of manufacturing thin film transistors and transistor circuits

Technical field of the invention

The present invention relates to methods for fabricating thin film transistors, such as for example thin film transistors comprising a gate dielectric layer formed by anodization of a gate metal layer, and to methods for fabricating electronic circuits comprising such transistors.

Background of the invention

Anodization is an electrolytic process wherein a metal surface is oxidized, leading to the formation of a metal oxide film at the metal surface. It provides the possibility for low temperature, low cost and large area processing. Anodization is a very promising method to produce dense dielectric layers, for example in flexible organic field effect transistors (OFET) or in amorphous oxide transistors. It is also successfully used in amorphous silicon field effect transistors.

Starting from a substrate covered with a metal, the anodization process results in a stack of the original metal covered with a metal oxide layer having dielectric properties. The metal oxide layer can be used as an insulator layer in electronic applications, for example as a gate dielectric layer in field effect transistors (FET). In order to be useful in electronic applications, the anodized metal oxide layers is preferably uniform in thickness and in electrical properties. To achieve uniformity, it is particularly advantageous to start the process with a clean uniform metal layer covering the whole substrate. Pre-patterning of the metal layer would lead to field concentrations generated by uneven currents at edges of the metal patterns, producing detrimental non-uniformities in the oxide layer.

In addition, process steps used for pre-patterning a metal layer, such as for example providing and removing a photoresist layer, exposing the photoresist layer, and etching the metal layer, may lead to contamination of the metal layer surface. Since the uniformity and the quality of the metal layer have a strong influence on the uniformity and the quality of the anodized layer, it would create an imperfect oxide layer and an irregular metal-oxide interface. In addition, in devices wherein a semiconductor layer is provided on top of the metal oxide layer, the quality (cleanliness, roughness) of the interface between the dielectric layer and the semiconductor layer is also important.

The metal layer underneath the anodized metal oxide layer can for example be used as the gate in a transistor, e.g. a field effect transistor (FET) and the metal oxide layer can be used as a gate dielectric layer. Most electronic circuits comprising a plurality of transistors require separated gate electrodes with different voltages. Patterning of the gate metal layer is therefore required when fabricating circuits. In organic semiconductor industry usually the metal gate electrodes are first patterned, followed by deposition of a continuous insulator layer on top of the gate electrodes. It is an advantage of this approach that it results in a good isolation of the gate electrodes from the source and drain contacts provided on top of the insulator layer.

In order to build an electronic circuit using anodization of gate electrodes for forming a gate insulator, the process needs to be inversed (i.e. patterning of the gate metal layer is preferably done after oxidation) to avoid edge effects during anodization. In such an inverse process, a continuous (non-patterned) metal layer is provided and anodized in order to form a uniform insulating metal oxide layer. Afterwards, the metal-insulator stack is patterned. In the patterned metal-insulator stack, the insulator layer is only present at a top surface of the metal layer and it does not cover the sidewalls of the patterned gate metal layer. This approach presents a problem when providing source and drain electrodes on the insulator layer, because there is a high risk of contacting (short circuits) between the gate electrode and the source-drain contacts.

Summary of the invention

It is an object of the present invention to provide electronic structures of good quality and methods for fabricating such structures.

In a first aspect, the present invention relates to a method for fabricating structures.

In a second aspect, the present invention relates said structures.

Examples of such structures are transistors and transistor circuits.

Examples of such transistors are amorphous oxide field effect transistors (e.g. thin film transistors) or organic field effect transistors.

Examples of such transistor circuits are amorphous oxide field effect transistor circuits (e.g. thin film transistor circuits) or organic electronic circuits. Examples of organic electronic circuits are organic field effect transistors circuits.

Particular examples of such transistor circuits (whether amorphous oxide field effect transistor circuits or organic electronic circuits) are inverters and oscillators.

Certain inventive embodiments of the first aspect relate to a method for fabricating thin film transistors wherein anodization of a gate electrode is used for forming a gate dielectric layer, wherein the gate dielectric layer may have a uniform thickness (see layer 31 in figure 5) and a smooth surface (e.g. has a RMS of 3 nm or less or of 2 nm or less) and wherein the gate dielectric layer provides a good electrical isolation between the gate electrode and a source and drain electrode formed on the gate dielectric layer such that the risk of short circuits is avoided. In embodiments of the first aspect, a method allows fabricating electronic circuits comprising a plurality of separated gate electrodes, wherein the gate electrodes are covered with a gate dielectric layer formed by anodization of the gate electrode material and wherein the gate dielectric layer provides a good electrical isolation between the gate electrodes and source-drain contacts.

Embodiments of the first aspect relate to a method for fabricating structures comprising a patterned metal layer and a patterned dielectric layer overlaying the patterned metal layer, the patterned dielectric layer insulating the patterned metal layer from its environment at a surface and at the sides of the patterned metal layer. One aspect relates to structures fabricated according to this method.

In embodiments of the first aspect, a method comprises: providing a continuous metal layer on a substrate; providing a dielectric layer on the continuous metal layer, thereby forming a continuous dielectric layer on top of the continuous metal layer; and patterning the metal layer and the dielectric layer, wherein patterning comprises a wet etching step with an etchant that etches the metal layer substantially faster (i.e. at a substantially higher etch rate) than the dielectric layer. In embodiments, after performing the wet etching step, the patterned dielectric layer may extend over the edges of the underlying patterned metal layer and the overhanging parts of the dielectric layer collapse such that they come into contact with the substrate, resulting in a fully isolated underlying metal pattern.

In certain embodiments, the substrate may be an insulating substrate.

In certain embodiments, providing a dielectric layer on the continuous metal layer may comprise providing a metal oxide layer by performing an anodization step.

In certain embodiments, the substrate may be an insulating substrate, and providing a dielectric layer on the continuous metal layer may comprise providing a metal oxide layer by performing an anodization step. In embodiments, the ratio between the etch rate of the metal layer and the etch rate of the dielectric layer, e.g. metal oxide layer, may preferably be larger than about 1 0, more preferably larger than about 20.

In embodiments, a lateral size of the overhanging parts of the dielectric layer may be at least a factor of about 2 larger, preferably at least a factor of about 4 larger, more preferably at least a factor of about 10 larger, for example a factor of about 50 to 1 00 times larger than the thickness of the metal layer (e.g. of the metal layer remaining after its anodization to form the dielectric layer).

Methods according to embodiments of the first aspect can advantageously be used for fabricating transistors and transistor circuits, wherein anodization of a gate electrode is used for forming a gate dielectric layer of good quality, e.g. having good thickness uniformity and a smooth surface. Methods according to embodiments of the first aspect further result in a good electrical isolation between the gate electrode and a source and/or drain electrode formed on top of the dielectric layer formed by anodization.

An embodiment of the first aspect relates to a method for fabricating thin film transistors and thin film transistor circuits wherein the gate and gate electrode are fabricated according to a method for fabricating structures comprising a patterned metal layer and a patterned dielectric layer overlaying the patterned metal layer according to one aspect.

In an embodiment of the first aspect, the present invention relates to a method for fabricating a structure according to the second aspect, said method comprising the steps of:

a. providing a continuous metal layer on an substrate (preferably an insulating substrate);

b. providing a dielectric layer on the continuous metal layer, thereby forming a continuous dielectric layer on top of the continuous metal layer; and c. patterning the metal layer and the dielectric layer, wherein said patterning comprises a wet etching step with an etchant that etches the metal layer substantially faster than the dielectric layer, wherein step (c) is performed after step (b).

The dielectric layer may be provided by anodization of the metal layer or by other methods.

In an embodiment, said metal may be suitable for being anodized (e.g. aluminum, titanium, zinc, magnesium, niobium, or tantalum).

In one embodiment, the method may be used with dielectric layers provided by other methods than anodization, such as for example dielectric layers provided by means of evaporation, Atomic Layer Deposition, sputtering or Chemical Vapor Deposition. In this case, the interest of the proposed process flow is that it permits a deposition of the dielectric layer right after the metal deposition, which avoids contamination generated by patterning and etching.

In another embodiment, when anodization of the metal layer is used to provide the dielectric layer, it is an advantage of a method according to one embodiment that, although patterning is done after anodization, a good electrical isolation of the gate electrodes can be obtained. In prior art methods, wherein the gate metal layer is first patterned, a constant current and a constant voltage need to be provided to each gate electrode during the anodization step in order to achieve a stable anodization for a plurality of separated gate electrodes. However, contacting each separated gate electrode may be very difficult because of the small size of the gate electrodes and the large number of gate electrodes that may be present in a circuit. Moreover, the area where a wire is connected to a gate electrode is not anodized. An advantage of performing the anodization step on a continuous metal layer is that there is a negligible voltage drop over the metal layer and that the current is uniformly distributed and that undesired edge effects are avoided (a synergy exists between anodization, making step (c) after step (b) and making more than one transistor). In an embodiment, the anodization process may be performed on a clean, continuous metal layer, such that a metal oxide layer of uniform thickness and having a smooth surface may be obtained.

In an embodiment, said anodization may be performed by contacting said uniform metal layer with an electrolyte comprising from 0.01 to 0.1 M (e.g. 0.05 M) of a solution comprising a K2 Citric acid (HK₂0₄P · 3H₂0) solution and a K3 Citric acid (C₆H₅K₃O₇ · H₂0) solution], i.e. a solution being a mixture of citrates containing potassium phosphate dibasic trihydrate an potassium citrate tribasic monohydrate. The molar ratio HK₂0₄P on C₆H₅K₃O₇ is preferably 1/1 .

For the deposition of the metal layer, the thickness of the metal layer is preferably such that after anodization a metal layer with a suitable thickness for forming a gate electrode layer remains. In an embodiment, the thickness of said metal layer as provided may be from 20 to 1000 nm, preferably from 50 to 150 nm.

The roughness of the metal layer surface is preferably as small as possible such that a smooth oxide layer can be formed by anodization. In an embodiment, said metal layer may have a RMS roughness preferably lower than about 3 nm, e.g. between about 2 nm and 3 nm.

In an embodiment, said continuous metal layer may be provided by vacuum evaporation.

In an embodiment, after performing the wet etching step, the patterned dielectric layer may extend over the edges of the underlying patterned metal layer and the overhanging parts of the dielectric layer may collapse in such a way that they come into contact with the substrate, resulting in a fully isolated underlying metal pattern. As soon as the underetching is sufficiently large for causing a collapsing of the overhanging parts, the underetching stops automatically.

In an embodiment of the present invention, providing a dielectric layer on the continuous metal layer may comprise providing a metal oxide layer by performing an anodization of a top portion of said continuous metal layer. It is an advantage of using an anodization process for forming a gate dielectric layer that it allows forming dielectric layers of good quality, with a high dielectric constant at low processing temperatures. The low processing temperature allows processing on a broad range of substrates, including flexible substrates such as for example plastics (e.g. PET (polyethylene terephthalate), PE (polyethylene), BOPP (biaxial ly oriented polypropylene)) or aluminum foil. As compared to other low temperature techniques such as for example ALD (atomic layer deposition), it is an advantage of anodization that its cost is substantially lower and that it can be used in large area processing.

In an embodiment, the anodization process may be performed in two stages wherein in a first stage a constant current is used and the voltage is increased linearly until a certain voltage and in a second stage the voltage is kept constant at said certain voltage and the current is decreased exponentially down to a value lower than said constant current used in said first stage. The second stage leads to an increased density and an increased quality (filling of pinholes) of the metal oxide layer. This two-stage process results in a transformation of a top part of the metal layer in a metal oxide layer (e.g. a transformation of a top part of the Al layer in an Al₂0₃ layer). Said certain voltage can for instance be 1 V or higher, preferably 5 V or higher, more preferably, 10 V or higher and most preferably 25V or higher. Said certain voltage can be 1000 V or lower, preferably from 500 V or lower, more preferably 200 V or lower and most preferably from 50 V or lower. For instance, it can be from 25 V to 35 V. Values of 25 V or higher and especially 30 V or higher are advantageous as they permit to achieve low leakage current between the gate and the source/drain electrodes.

Said constant current can for instance be 25 mA/cm² or lower, preferably

10 mA/cm² or lower, more preferably 1 mA/cm² or lower and most preferably 0.10 mA/cm² or lower.

Said constant current can for instance be 0.01 mA/cm² or higher, preferably 0.03 mA/cm² or higher and more preferably 0.05 mA/cm² or higher. The best quality for the oxide layer was obtained by using a constant current of from 0.05 to 0.09 mA/cm².

Said value lower than said constant current is typically from 5 to 15% of the value of said constant current. For instance, it can be about 10% of the value of said constant current. In an embodiment, the anodization process may be performed in two stages wherein in a first stage a constant current of 0.07 mA/cm² is used and the voltage is increased linearly until 30 V and in a second stage the voltage is kept constant at 30 V and the current decreased exponentially till 0.006 mA/cm². In an example, this two-stage process resulted in a transformation of a top part of the Al layer in an Al₂0₃ layer, wherein the thickness of the Al₂0₃ layer was 50 nm.

In an embodiment, during step (c), a patterned photoresist layer 50 may be provided over the dielectric layer before performing said wet etching step. Providing said patterned photoresist layer may form a gate mask.

In an embodiment, said patterned photoresist layer may be provided by lithography.

In an embodiment, the etchant may be a mixture of phosphoric acid, nitric acid and acetic acid.

In an embodiment, the ratio between the etch rate of the metal layer and the etch rate of the dielectric layer may be larger than about 1 0, more preferred larger than about 20.

In an embodiment, the etching may be performed for from 100 seconds to 300 seconds.

In an embodiment, said etching may be performed at a temperature of from 20 °C to 80 °C, preferably from 35 °C to 65 °C.

In an embodiment, a lateral size of the overhanging parts of the patterned dielectric layer may be at least a factor of about 2 larger, preferably at least a factor of about 4 larger, more preferably at least a factor of about 10 larger, most preferably a factor of from 50 to 100 larger than the thickness of the underlying patterned metal layer. Under such conditions the overhanging parts 32 of the metal oxide layer may collapse.

In an embodiment, the amount of underetching ("u" in Fig. 1 ) may be in the range between about 1 μππ and 10 μππ, preferably 2 and 5 μππ. This gives a modest bending of the oxide layer without cracks,

In an embodiment, said collapsing may result in the formation of closed cavities, preferably completely surrounding the patterned metal layer, such that the patterned metal layer is fully electrically isolated from its environment (by the insulating substrate and the patterned metal oxide layer).

In an embodiment, said structure may be a field effect transistors (e.g. a thin film transistor), wherein said patterning of said metal layer provides a gate electrode, wherein said metal oxide layer is a gate dielectric layer (the gate dielectric layer has a uniform thickness and a smooth surface), said method further comprising the steps of forming a source and a drain electrode above said gate dielectric layer, and wherein the gate dielectric layer provides electrical isolation between the gate electrode and said source and drain electrode such that the risk of short circuits is avoided. Because of the collapsing of the metal oxide layer and the formation of closed cavities surrounding the gate electrode layer, the source and drain contacts remain efficiently electrically isolated from the bottom gates, enabling the fabrication of circuits with patterned gates.

In an embodiment, said source and drains can be made of a second metal (e.g. gold). For instance, they may for instance have a thickness of from 15 to 45 nm.

In an embodiment, in addition to step (a), (b) and (c), the method may further comprise the step of providing an amorphous oxide semiconductor layer on top of said metal oxide layer between step (b) and step (c). A method according to this embodiment leads to an improvement of the cleanliness and the quality of both the metal-dielectric interface and the dielectric-semiconductor interface. In this embodiment, in step (c), the amorphous oxide semiconductor layer, the metal oxide layer and the metal layer may all be patterned in a single patterning step. It is an advantage of such an approach that the interfaces between the different layers can be very clean.

In an alternative embodiment wherein source and drain contacts have been provided on said dielectric layer, instead of providing an amorphous oxide semiconductor layer, the method may further comprise in addition to steps (a), (b), and (c), the step of providing a patterned organic semiconductor layer on top of said metal oxide layer and part of said source contact and said drain contact. An example of such an organic semiconductor is pentacene or a pentacene derivative.

In an embodiment, said structure may be an electronic circuit and said step of patterning the metal layer may form separated gate electrodes.

In an embodiment, an etch-stop layer may be provided on the substrate before performing step (a), and step (a) may result in the provision of said continuous metal layer on said insulating substrate and on said etch-stop layer, wherein after step (c), said method may comprise:

d. a step of providing a patterned photoresist above said patterned dielectric layer wherein said patterned photoresist comprises openings where said underlying etch stop layer is present, and

e. a step of etching the patterned metal oxide layer (31 ), the patterned metal layer (22) and, if present, the amorphous semiconductor layer, using the patterned photoresist layer (53) as a mask, and using an etchant that has a higher etching speed for the metal than for the metal oxide.

In a second aspect, the present invention relates said structures.

Embodiments of the second aspect relates to transistors and transistor circuits fabricated via the methods of the first aspect. In an embodiment, the second aspect relates to a structure comprising a metal layer on an insulating substrate (e.g. a glass substrate) and a dielectric layer overlaying the metal layer, the dielectric layer insulating electrically the metal layer from its environment at a surface (the surface opposite to the substrate) and at the sides (all sides) of the metal layer, said overlaying dielectric layer defining closed cavities around said metal layer. The metal layer and the dielectric layer being the result of a patterning step, they may be called patterned metal layer and patterned dielectric layer respectively. The patterned metal layer covers only part of the substrate.

In an embodiment, said closed cavities may be completely surrounding the metal layer.

In an embodiment, said metal may be selected from the group consisting of aluminum, titanium, zinc, magnesium, niobium, and tantalum.

In an embodiment, said metal may be aluminum.

In an embodiment, said metal layer may have a thickness of from 10 to 500 nm, preferably 25 to 75 nm.

In an embodiment, said dielectric layer may be obtainable by anodization of the metal layer.

In an embodiment, said dielectric layer may have a uniform thickness.

In an embodiment, said dielectric layer may have a thickness of from 10 to

500 nm, preferably 25 to 75 nm.

In an embodiment, said metal layer may have a RMS roughness preferably lower than about 3 nm, e.g. between about 2 nm and 3 nm. The roughness of the metal layer surface is preferably as small as possible such that a smooth oxide layer can be formed by anodization.

In an embodiment, said dielectric layer may comprise an oxide of said metal. For instance said dielectric layer may comprise aluminum oxide if said metal is aluminum. In an embodiment, said structure may be a transistor such as a field effect transistor or an amorphous oxide field effect transistor (e.g. a thin film transistor). An aspect of the present invention therefore relates to field effect transistors comprising a structure according to any embodiment of the second aspect, wherein source and drain contacts are provided above said dielectric layer.

In an embodiment, an amorphous oxide semiconductor layer may present on said metal oxide layer and said source and drain contacts may be provided on said amorphous oxide semiconductor layer. In this embodiment, said structure is an amorphous oxide field effect transistor.

In an embodiment, said source and drain contacts may be provided on said dielectric layer and an organic semiconductor layer may present on top of said metal oxide layer and part of said source and drain contacts. Such an embodiment provides for an organic field effect transistor having excellent electrical characteristics with low voltage operation, high charge carrier mobility and close to 0 V onset and threshold voltages.

In an embodiment, said dielectric layer may be insulating electrically said metal layer from said source and drain contacts.

In an embodiment, said patterned metal layer may be a gate electrode, wherein the gate electrode is covered with said patterned dielectric layer being a gate dielectric layer formed by anodization of the gate electrode material, wherein source-drain contacts are provide on said gate dielectric layer and wherein the gate dielectric layer is insulating electrically said gate electrode from said source- drain contacts.

In an embodiment, the field effect transistor may further comprise a via through said metal oxide layer and, if present, through said amorphous oxide semiconductor layer such that an electrical contact can be provided between said source or said drain contact and said metal layer.

In an embodiment, said structure may be an electronic circuit. An aspect of the present invention therefore relates to an electronic circuit comprising one or more structures and/or field effect transistors according to any embodiment of the second aspect of the present invention.

In an embodiment, the electronic circuit may comprise a plurality of said structures, e.g. a plurality or field effect transistors, wherein a corresponding plurality of metal layers are present and separated from one another.

In a further aspect, the present invention relates to an electronic circuit comprising a structure according to any corresponding embodiments above.

Certain objects and advantages of the invention have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein. Further, it is understood that this summary is merely an example and is not intended to limit the scope of the invention. The invention, both as to organization and method of operation, together with features and advantages thereof, may best be understood by reference to the following detailed description when read in conjunction with the accompanying drawings.

Brief description of the drawings

Figure 1 schematically illustrates a method for forming a metal pattern covered with an anodized metal oxide layer according to one embodiment.

Figures 2A and 2B illustrate a process flow for fabricating an organic field effect transistor comprising a gate dielectric layer fabricated according to a method in one embodiment. Figure 3 is an optical microscope picture showing a top view of a patterned Al layer covered with an anodized Al₂0₃ layer formed according to a method in one embodiment.

Figure 4 shows an outline of the structure of Figure 3, illustrating underetching of the metal oxide layer.

Figure 5 is a TEM cross section of the structure of Figure 3.

Figure 6 shows the transfer characteristics of the transistor of Figure 3.

Figures 7A and 7B illustrate a process flow for fabricating an amorphous oxide field effect transistor comprising a gate dielectric layer fabricated according to a method in one embodiment.

Figures 8A, 8B, and 8C illustrate a process flow for fabricating an organic electronic circuit comprising transistors with a gate dielectric layer fabricated according to a method in one embodiment.

Figure 9 shows the measured characteristics of an inverter fabricated according to the process flow illustrated in Figure 8.

Figure 10 shows the measured characteristics of a 1 9-stage oscillator fabricated according to the process flow illustrated in Figure 8.

Figure 1 1 illustrates a process flow for fabricating an amorphous oxide semiconductor electronic circuit comprising transistors with a gate dielectric layer fabricated according to a method in one embodiment.

Figure 12 illustrates a process flow for fabricating an organic electronic circuit comprising transistors with a gate dielectric layer fabricated according to a method in one embodiment.

Figure 13 illustrates a process flow for fabricating an amorphous oxide semiconductor electronic circuit comprising transistors with a gate dielectric layer fabricated according to a method in one embodiment.

Figure 14 shows the transfer characteristics of a transistor according to an embodiment of the present invention. In the different drawings, the same reference signs refer to the same or analogous elements.

Detailed description of certain illustrative embodiments

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention and how it may be practiced in particular embodiments. However, it will be understood that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures and techniques have not been described in detail, so as not to obscure the present disclosure. While the present invention will be described with respect to particular embodiments and with reference to certain drawings, the invention is not limited hereto. The drawings included and described herein are schematic and are not limiting the scope of the invention. It is also noted that in the drawings, the size of some elements may be exaggerated and, therefore, not drawn to scale for illustrative purposes.

Furthermore, the terms first, second, third and the like in the description, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.

Moreover, the terms top, bottom, over, under and the like in the description are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein. It is to be noticed that the term "comprising" should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B.

As used herein and unless provided otherwise, the term "etch-stop" relates to a layer of material featuring more resistance to etching by the etching solution (due to different etch characteristics) than the material to be etched; a layer of "etch stop" material is typically placed underneath the material to be etched in order to stop the etching process. In embodiments of the present invention, It is a layer of material such that there exist an etching solution capable of etching the metal layer but not said layer of material.

Certain embodiments of the first aspect relate to a method for fabricating structures comprising a patterned metal layer and a patterned dielectric layer overlaying the patterned metal layer, the patterned dielectric layer insulating the patterned metal layer from its environment at a surface and at the sides of the patterned metal layer.

A method according to one embodiment of the first aspect comprises: providing a continuous metal layer on a substrate; providing a dielectric layer on the continuous metal layer, thereby forming a continuous dielectric layer on top of the continuous metal layer; and patterning the metal layer and the dielectric layer, wherein patterning comprises a wet etching step with an etchant that etches the metal layer substantially faster (i.e. at a substantially higher etch rate) than the dielectric layer. In a method according to one embodiment, after performing the wet etching step, the patterned dielectric layer extends over the edges of the underlying patterned metal layer and the overhanging parts of the dielectric layer collapse such that they come into contact with the substrate, resulting in a fully isolated underlying metal pattern.

In one embodiment, providing a dielectric layer on the continuous metal layer comprises providing a metal oxide layer by performing an anodization step. The present invention will be further described for this preferred embodiment. However, the invention is not limited thereto.

In one embodiment, the method can advantageously be used for fabricating transistors, wherein anodization of a gate electrode is used for forming a gate dielectric layer of good quality, e.g. having good thickness uniformity and a smooth surface. In one embodiment, a method may further result in a good electrical isolation between the gate electrode and a source and/or drain electrode formed on top of the dielectric layer formed by anodization.

It is an advantage of a method according to one embodiment that the anodization process is performed on a clean, continuous metal layer, such that a metal oxide layer of uniform thickness and having a smooth surface can be obtained. Patterning of the metal layer, e.g. for forming gate electrodes, is performed after the anodization step. It is an advantage of a method according to one embodiment that, although patterning is done after anodization, a good electrical isolation of the gate electrodes can be obtained.

It is an advantage of a method according to one embodiment that it allows fabricating electronic circuits comprising a plurality of separated gate electrodes, wherein the gate electrodes are covered with a gate dielectric layer formed by anodization of the gate electrode material. In prior art methods, wherein the gate metal layer is first patterned, a constant current and a constant voltage need to be provided to each gate electrode during the anodization step in order to achieve a stable anodization for a plurality of separated gate electrodes. However, contacting each separated gate electrode may be very difficult because of the small size of the gate electrodes and the large number of gate electrodes that may be present in a circuit. Moreover, the area where a wire is connected to a gate electrode is not anodized. In a method according to one embodiment the anodization is performed on a continuous metal layer and patterning (e.g. forming separated gate electrodes) is performed after anodization, such that the problems related to prior art methods can be avoided. It is an advantage of performing the anodization step on a continuous metal layer that there is a negligible voltage drop over the metal layer and that the current is uniformly distributed and that undesired edge effects are avoided.

It is an advantage of using an anodization process for forming a gate dielectric layer that it allows forming dielectric layers of good quality, with a high dielectric constant at low processing temperatures. The low processing temperature allows processing on a broad range of substrates, including flexible substrates such as for example PET (polyethylene terephthalate), PE (polyethylene), BOPP (bi-axially oriented polypropylene), and aluminum foil. As compared to other low temperature techniques such as for example ALD (atomic layer deposition), it is an advantage of anodization that its cost is substantially lower and that it can be used in large area processing.

In one embodiment, the method can also be used with dielectric layers provided by other methods than anodization, such as for example dielectric layers provided by means of evaporation, Atomic Layer Deposition, sputtering or Chemical Vapor Deposition. In this case, the proposed process flow is interesting because it permits a deposition of the dielectric layer right after the metal deposition, which avoids contamination generated by patterning and etching. In particular for devices with an oxide semiconductor, a method according to one embodiment leads to an improvement of the cleanliness and the quality of both the metal-dielectric interface and the dielectric-semiconductor interface.

A method according to one embodiment is illustrated in Figure 1 . In a first step, illustrated in Figure 1 (a), a continuous metal layer 20 is provided on an insulating substrate 10. Next an anodization step is performed, wherein a top portion of the metal layer 20 is transformed into a metal oxide. The results in a structure as shown in Figure 1 (b), the structure comprising a uniform metal oxide layer 30 on top of an anodized metal layer 21 , the anodized metal layer 21 having a reduced thickness as compared to the initial metal layer 20 (Figure 1 (b)).

After forming the metal oxide layer, the layer stack comprising the metal layer 21 and the metal oxide layer 30 is patterned, wherein the step of patterning comprises a wet etching step using an etchant that has a substantially slower etching speed for the metal oxide as compared to the etching speed for the underlying metal. For example, a mixture of phosphoric acid (H₃P0₄), nitric acid (HN0₃) and acetic acid (CH₃COOH) can be used for etching. However, the present invention is not limited thereto and any other etchant having a substantially higher etch rate or etching speed for the metal than for the metal oxide known to a person skilled in the art can be used. The ratio between the etch rate of the metal layer and the etch rate of the metal oxide layer is preferably larger than about 10, preferably larger than about 20, for example about 25. This difference in etching speed or etch rate leads to underetching of the metal oxide layer, leading to a patterned metal layer 22 covered with a patterned metal oxide layer 31 having overhanging parts 32, i.e. a patterned metal oxide layer 31 that extends beyond the underlying metal layer 22, at the periphery of the metal layer 22. This is schematically illustrated in Figure 1 (c). Preferably the amount of underetching (u in Figure 1 (c)) is substantially larger, for example at least a factor of about 2 larger, preferably at least a factor of about 4 larger, more preferred at least a factor of about 10 larger, for example a factor of about 50 to 100 larger than the thickness (d_m in Figure 1 (c)) of the metal layer 22. Under such conditions the overhanging parts 32 of the metal oxide layer 31 may collapse, resulting in a structure as shown in Figure 1 (d). After collapsing, the metal oxide layer 31 is in physical contact with the substrate 10 at all sides of the patterned metal layer 22. The collapsing results in the formation of closed cavities 40, preferably completely surrounding the patterned metal layer 22, such that the patterned metal layer 22 is fully electrically isolated from its environment (by the insulating substrate 10 and the patterned metal oxide layer 31 ).

When using this procedure for example in a transistor fabrication process, source and drain contacts are provided afterwards on top of the metal oxide layer 31 . Because of the collapsing of the metal oxide layer and the formation of closed cavities surrounding the gate electrode layer, the source and drain contacts remain efficiently electrically isolated from the bottom gates, enabling the fabrication of circuits with patterned gates.

In order to obtain a good isolation of the gate layer, it is advantageous to have a good control over the following successive steps: deposition of the metal layer, anodization of the metal layer and etching of the stack comprising the metal layer and the metal oxide layer. As for the deposition of the metal layer, the thickness of the metal layer is preferably such that after anodization a metal layer with a suitable thickness for forming a gate electrode layer remains. For example, the metal layer can be an Al layer with an initial thickness (before anodization) of about 1 00 nm, and anodization of this Al layer can result in transformation of a top layer into an AIO_x layer with a thickness of about 50 nm. However, thicker or thinner metal layers can be used. The roughness of the metal layer surface is preferably as small as possible such that a smooth oxide layer can be formed by anodization. For example, the RMS roughness is preferably lower than about 3 nm, e.g. between about 2 nm and 3 nm. Anodization of the metal layer results in a metal oxide layer, wherein the metal oxide layer has a uniform thickness, for example in the range between a few nm to several hundreds of nm. Etching of the stack comprising the metal layer and the metal oxide layer preferably results in a substantial underetching, for example at least a factor of about 2 larger, preferably at least a factor of about 4 larger, more preferred at least a factor of about 1 0 larger, for example a factor of about 50 to 100 larger than the thickness of the underlying metal layer. As soon as the underetching is sufficiently large for causing a collapsing of the overhanging parts, the underetching stops automatically.

In the further description examples of process flows are provided that may be used for fabricating field effect transistors such as organic field effect transistors and amorphous oxide field effect transistors, as well as examples of process flows that may be used for fabricating circuits based on organic semiconductors or on amorphous oxide semiconductors, wherein gate oxides are formed by anodization according to certain embodiments of the present invention. However, the present invention is not limited to the process flows described. The method of the present invention can also be used in other process flows known by a person skilled in the art.

Figure 2A and 2B illustrate a process flow for fabricating an organic field effect transistor, wherein a gate dielectric layer is formed using a method according to one embodiment. The process sequence comprises the following:

- Deposition of a continuous metal layer 20 which can be anodized on a substrate 10, e.g. a glass substrate (step (a)). A metal can be anodized if the oxidation potential of the metal is lower than the oxidation potential of water, and if no reaction with water occurs;

- Anodization of the metal layer, thereby forming a stack comprising a metal oxide layer 30 on top of an anodized metal layer 21 , the anodized metal layer 21 having a reduced thickness as compared to the initial metal layer 20 (step (b));

- Providing a patterned photoresist layer 50, e.g. by lithography, thereby forming a gate mask (step (c));

- Etching the metal oxide layer 30 and the metal layer 21 using the patterned photoresist layer 50 as a mask and using a wet etchant having a substantially higher etching speed for the metal than for the metal oxide, resulting in underetching of the metal oxide layer as illustrated in step (d). The weight of the photoresist layer 50 and the underetched metal oxide layer 31 leads to collapsing of the overhanging parts of the metal oxide layer, leading to the metal oxide layer 31 contacting the substrate as shown in step (e). The collapsing results in the formation of closed cavities 40, preferably completely surrounding the patterned metal layer 22;

- Removing the photoresist layer 50 (step (f));

- Providing a patterned photoresist layer 51 , thereby forming a source and drain mask (step (g));

- Deposition of a metal layer 25 (e.g. Au) for forming source and drain contacts (step (h)) and lift off, resulting in the structure as shown in step (i) with a source contact 26 and a drain contact 27;

- Optional surface treatment of the metal surface and/or the dielectric layer surface;

- Deposition of a patterned organic semiconductor layer 60 as shown in step (j)- Experiments were performed, wherein organic field effect transistors were fabricated according to the process flow illustrated in Figure 2A and 2B. On a substrate, a 100 nm thick Al layer was formed by vacuum evaporation. Next the Al layer was anodized in an electrolyte comprising 0.05 M of a solution comprising a K2 Citric acid (HK₂O₄P · 3H₂O) solution and a K3 Citric acid (CeHsKsOy · H₂O)], i.e. a solution being a mixture of citrates containing potassium phosphate dibasic trihydrate an potassium citrate tribasic monohydrate. The molar ratio HK₂O₄P on C₆H₅K₃O₇ was 1/1 . The anodization process was performed in two stages. In a first stage a constant current of 0.07 mA/cm² was used and the voltage was increased linearly until 30 V. In a second stage the voltage was kept constant at 30 V and the current decreased exponentially till 0.006 mA/cm². The second stage leads to an increased density and an increased quality (filling of pinholes) of the metal oxide layer. This two-stage process resulted in a transformation of a top part of the Al layer in an AI₂O₃ layer, wherein the thickness of the AI₂O₃ layer was 50 nm. Next a patterned photoresist layer was provided on the AI₂O₃ layer by photolithography. This was followed by a wet etching step, using a wet etchant (PES 77-19-04 (phosphoric acid etchant) from VWR) comprising a mixture of phosphoric acid (H₃P0₄), nitric acid (HN0₃) and acetic acid (CH₃COOH) in the proportion (77:19:4) . Etching was performed for 210 seconds at a temperature of 50^QC. After removing the photoresist layer, another patterned photoresist layer was provided by photolithography for forming a source and drain mask. A 30 nm thick Au layer was provided by evaporation and a lift-off step was performed, for forming source and drain contacts (fingers). Next a surface treatment step was done, comprising dipping the structure into a Pentafluorobenzenethiols 0.01 M solution in ethanol for at least 30 minutes and baking in a vacuum oven at 60 °C with 60 μΙ phenethyltrichlorosilane (PETS) for 30 minutes. Finally a 30 nm thick pentacene organic semiconductor layer was provided by thermal evaporation at a substrate temperature of 68^QC.

Figure 3 is an optical microscope picture showing a top view of this structure, comprising a patterned Al layer with an anodized Al₂0₃ layer on top of it, and with a source contact and a drain contact on top of the anodized Al₂0₃ layer. An outline of the structure is shown in Figure 4. It can be seen that the Al layer has a pattern that is smaller than the Al₂0₃ layer, evidencing underetching of the metal oxide layer. Based on Figure 3, it can be concluded that in this example the amount of underetching is in the range between about 2.3 micrometer and 4.7 micrometer. This scale of the underetching is much larger (factor of about 46 to 94) than the thickness of the oxide layer, which gives a modest bending of the oxide layer without cracks, which can be seen in the cross-section TEM picture in Figure 5.

Figure 6 shows the transfer characteristic of the transistor shown in Figure

3. This transistor comprises pentacene as a semiconductor layer. The plain line corresponds to the drain to source current. The dashed line corresponds to the gate to source current. The X-axis gives the gate voltage. This transistor presents excellent electrical characteristics with low voltage operation, high charge carrier mobility and close to 0 V onset and threshold voltages. The W/L ratio between the transistor channel width (W) and length (L) is 5000/1 0 μπνμΓη; the thickness of the insulator (ti_ns) is 50 nm; the dielectric constant of the insulator (ε_Γ or e_r) is 9; the voltage drain to source (V_Ds) is -2V; the tension above which the channel is created (V_T) is 0.5V; the charge carrier mobility (μ) is 9.42x10^"2 cm²/(V.s); the turn on current (l_on) is 1 .0x10^"8 A; the turn on voltage (V_on) is 0.7 V; the sub-threshold slope (S^"1) is 0.23 V/decade. More importantly, the dashed line in Figure 6 is the gate to source current showing no current going through between gate and source-drain fingers, confirming that (i) the metal oxide formed by anodization presents an excellent dielectric quality, (ii) the gate electrode is effectively electrically isolated from the source and drain contacts, thanks to the collapsed metal oxide according to one embodiment.

Figures 7A and 7B illustrate a process flow for fabricating an amorphous oxide field effect transistor, wherein a gate dielectric layer is formed using a method according to one embodiment. When using an amorphous oxide semiconductor, the process can be further simplified by patterning the amorphous oxide semiconductor layer, the metal oxide layer and the metal layer in a single patterning step. It is an advantage of such an approach that the interfaces between the different layers can be very clean. The process sequence comprises the following:

- Providing a substrate 10, e.g. a glass substrate (step (a));

- Deposition of a continuous metal layer 20 which can be anodized on the substrate 10 (step (b)) ;

- Anodization of the metal layer, thereby forming a stack comprising a metal oxide layer 30 on top of an anodized metal layer 21 , the anodized metal layer 21 having a reduced thickness as compared to the initial metal layer 20 (step (c));

- Deposition of an amorphous oxide semiconductor layer 70 on the metal oxide layer 30 as illustrated in step (d); - Providing a patterned photoresist layer 50, e.g. by lithography, thereby forming a gate mask (step (e));

- Etching the amorphous oxide semiconductor layer 70, the metal oxide layer 30 and the anodized metal layer 21 using the patterned photoresist layer 50 as a mask and using a wet etchant having a higher etching speed for the metal than for the metal oxide, resulting in underetching of the metal oxide layer as illustrated in step (f). The weight of the photoresist layer 50, the patterned (underetched) metal oxide layer 31 and the patterned oxide semiconductor layer 71 leads to collapsing of the overhanging parts of the metal oxide layer and of the oxide semiconductor layer, leading to the metal oxide layer 31 contacting the substrate 10 as shown in step (g));

- Removing the photoresist layer 50 (step (h));

- Providing a patterned photoresist layer 51 , thereby forming a source and drain mask (step (i));

- Deposition of a metal layer 25 for forming source and drain contacts (step (j)) and lift off, resulting in the structure as shown in step (k) with a source contact 26 and a drain contact 27.

Figure 8, Figure 1 1 , Figure 12 and Figure 13 illustrate process flows for fabricating electronic circuits comprising transistors having a gate dielectric layer fabricated according to a method of one embodiment. Such processes include the formation of vias through the metal oxide towards the underlying gate electrodes, such that an electrical contact can be provided between a source or drain electrode and a gate electrode. In prior art processes, forming a via comprises removing part of the gate dielectric layer using a selective etchant (i.e. an etchant that etches the gate dielectric layer and not the gate electrode) such that the underlying gate electrode can be contacted. However, when using anodization of the gate electrode layer for forming a gate dielectric layer as in embodiments of the present invention, it may be very difficult to etch the gate dielectric layer selectively with respect to the underlying gate electrode. In embodiments of the present invention, the formation of vias can be based on using an etch-stop layer (as illustrated in Figure 8 and Figure 1 1 ) or it can be based on a selective etching process (Figure 12 and Figure 13), for example using an etchant as described in US 4,087,367.

Figure 8A-C illustrates a process flow for fabricating organic electronic circuits comprising transistors having a gate dielectric layer fabricated according to a method of one embodiment, and using an etch stop layer for forming vias. The process flow comprises the following:

- Providing a substrate 10, such as for example a glass substrate (step (a)); - Providing a patterned photoresist layer 52 on the substrate 10, the patterned photoresist layer 52 being patterned such that it is removed at locations where an etch stop layer needs to be provided (step (b));

- Deposition of an etch-stop layer 80, as illustrated in step (c). For example, a Cr layer can be used as an etch-stop layer 80;

- Performing a lift-off step, resulting in a structure comprising a patterned etch stop layer 81 on the substrate 10, as shown in step (d);

- Deposition of a continuous metal layer 20 which can be anodized (step (e));

- Anodization of the metal layer, thereby forming a stack comprising a metal oxide layer 30 on top of an anodized metal layer 21 , the anodized metal layer 21 having a reduced thickness as compared to the initial metal layer 20 (step (f));

- Providing a patterned photoresist layer 50, thereby forming a gate mask (step (g));

- Etching the metal oxide layer 30 and the metal layer 21 using the patterned photoresist layer 50 as a mask and using a wet etchant having a higher etching speed for the metal than for the metal oxide, resulting in underetching of the metal oxide layer as illustrated in step (h). The weight of the photoresist layer 50 and the patterned (underetched) metal oxide layer 31 leads to collapsing of the overhanging parts of the metal oxide layer, leading to the metal oxide layer 31 contacting the substrate 10. This is illustrated in step (i), showing the structure after removal of the photoresist layer.

- Providing a patterned photoresist layer 53, for example by photolithography, thereby forming a via mask as illustrated in step (j). The via mask comprises openings where an underlying patterned etch stop layer 81 is present.

- Etching the patterned metal oxide layer 31 and the patterned metal layer 22, using the patterned photoresist layer 53 as a mask, using the patterned layer 81 as an etch stop layer, and using an etchant that has a higher etching speed for the metal than for the metal oxide (leading to underetching followed by collapsing of overhanging parts). The resulting structure, after removal of the photoresist layer 53, is shown in step (k). - Providing a patterned photoresist layer 51 , thereby forming a source-drain mask (step (I));

- Providing a metal layer (e.g. a Au layer) and lift off for forming a source contact 26 and a drain contact 27, resulting in a structure as shown in step

(m);

- Optional surface treatments of the metal surface and/or the dielectric layer surface.

- Providing a patterned organic semiconductor layer 60 as shown in step (n).

Experiments were performed wherein electronic circuits comprising a plurality of transistors were fabricated according to the process flow illustrated in Figure 8A-C. As an etch stop layer 81 , a 10 nm thick layer of Cr was provided by evaporation and lift-off. Next a 100 nm thick Al layer was formed by vacuum evaporation and the Al layer was anodized in an electrolyte comprising 0.05 M of a solution comprising a K2 Citric acid (HK₂O₄P · 3H₂O) solution and a K3 Citric acid (C₆H₅K₃O₇ · H₂O)], i.e. a solution being a mixture of citrates containing potassium phosphate dibasic trihydrate an potassium citrate tribasic monohydrate, to form a 50 nm thick Al₂0₃ layer. The molar ratio HK₂0₄P on C₆H₅K₃O₇ was 1 /1 . The anodization process was performed in two stages. In a first stage a constant current of 0.07 mA/cm² was used and the voltage was increased linearly until 30 V. In a second stage the voltage was kept constant at 30 V and the current decreased exponentially till 0.006 mA/cm². This process resulted in a transformation of a top part of the Al layer in an Al₂0₃ layer, wherein the thickness of the Al₂0₃ layer was 50 nm. Next a patterned photoresist layer was provided on the Al₂0₃ layer by photolithography. This was followed by a wet etching step, using a wet etchant (PES 77-19-04 (phosphoric acid etchant) from VWR) comprising a mixture of phosphoric acid (H₃P0₄), nitric acid (HN0₃) and acetic acid (CH₃COOH) in the proportion (77:19:4). Etching was performed for 210 seconds at a temperature of 50^QC. After removing the photoresist layer, another patterned photoresist layer was provided by photolithography for forming a via mask. The Al₂0₃ layer and the Al layer were then etched at locations were vias need to be formed, in a mixture of phosphoric acid (H₃P0₄), nitric acid (HN0₃) and acetic acid (CH₃COOH). Etching was performed for 210 seconds at a temperature of 50^QC. After removing the photoresist layer (via mask), another patterned photoresist layer was provided by photolithography for forming a source and drain mask. A 30 nm thick Au layer was provided by evaporation and a lift-off step was performed, for forming source and drain contacts. Next a surface treatment step was done, the surface treatment comprising dipping the structure into a Pentafluorobenzenethiols 0.01 M solution in ethanol for at least 30 minutes and baking in a vacuum oven at 60 °C with 60 μΙ phenethyltrichlorosilane (PETS) for 30 minutes. Finally a 30 nm thick pentacene organic semiconductor layer was provided by thermal evaporation at a substrate temperature of 68^QC.

Figure 9 shows the measured characteristics of an inverter (Big Zero Vgs Inverter with Ι_=3μπι), comprising several transistors and vias connected to these transistors, fabricated according to this process. These results show a good working inverter, indicating that the process flow in one embodiment is suitable for fabricating transistor circuits.

Figure 10 shows the measured characteristics of a 1 9 stage oscillator fabricated according to this process. As compared to an inverter, this is a more complex circuit combining tens of transistors and vias for connecting the transistors. These results show a good working oscillator, indicating that the process flow in one embodiment is also suitable for fabricating more complex circuits, with a good transistor yield.

A process flow for fabricating electronic circuits based on amorphous oxide semiconductors comprising transistors having a gate dielectric layer formed according to a method in one embodiment, and using an etch stop layer for forming the vias, can comprise the following, as illustrated in Figure 1 1 .

- Performing the process steps as illustrated in Figure 8(a) to Figure 8(f).

- Providing an amorphous oxide semiconductor layer 70 (Figure 1 1 (a));

- Providing a patterned photoresist layer 50, thereby forming a gate mask (Figure 1 1 (b));

- Etching the amorphous oxide semiconductor layer 70, the metal oxide layer 30 and the metal layer 21 using the patterned photoresist layer 50 as a mask and using a wet etchant having a higher etching speed for the metal than for the metal oxide, resulting in underetching of the metal oxide layer. The weight of the photoresist layer 50, the patterned amorphous oxide semiconductor layer 71 and the patterned metal oxide layer 31 leads to collapsing of the overhanging parts of the metal oxide layer, leading to the metal oxide layer 31 contacting the substrate 10. The resulting structure, after removal of the photoresist layer 50, is shown in Figure

1 1 (c);

- Providing a patterned photoresist layer 53, for example by photolithography, thereby forming a via mask as illustrated in Figure 1 1 (d). The via mask comprises openings where an underlying patterned etch stop layer 81 is present.

- Etching the patterned oxide semiconductor layer 71 , the patterned metal oxide layer 31 and the patterned metal layer 22, using the patterned photoresist layer 53 as a mask and using the patterned layer 81 as an etch stop layer, and using an etchant that has a higher etching speed for the metal than for the metal oxide (leading to underetching followed by collapsing of overhanging parts). The resulting structure, after removal of the photoresist layer, is shown in Figure 1 1 (e).

- Providing a patterned photoresist layer, thereby forming a source-drain mask (not illustrated);

- Providing a metal layer and lift off for forming a source contact 26 and a drain contact 27. The resulting structure is shown in Figure 1 1 (f).

Figure 12 illustrates a process flow for fabricating organic electronic circuits comprising transistors having a gate dielectric layer fabricated according to a method of one embodiment, and using selective etching for forming the vias. The process flow comprises the following:

- Performing the process steps as illustrated in Figure 2(a) to Figure 2(f);

- Providing a photoresist layer (not illustrated) having openings at locations where vias need to be formed, and performing an etching step using a selective etchant that etches the patterned metal oxide layer 31 and not the patterned metal layer 22, resulting in the structure shown in Figure 12 (a).

- Providing a patterned photoresist layer 51 , thereby forming a source- drain mask (Figure 12(b));

- Providing a metal layer 51 (e.g. a Au layer) for forming source and drain contacts as illustrated in Figure 1 2(c), the metal layer also filling the via;

- Performing a lift-off step, thereby forming a source contact 26 and a drain contact 27, resulting in a structure as shown in Figure 12(d), wherein an electrical contact is made between the gate 22 and the drain contact 27 through the via;

- Providing a patterned organic semiconductor layer 60 as shown in

Figure 12(e).

A process flow for fabricating amorphous oxide semiconductor electronic circuits comprising transistors having a gate dielectric layer fabricated according to a method of one embodiment and using selective etching for forming the vias can comprise the following, as illustrated in Figure 13.

- Performing the process steps as illustrated in Figure 7(a) to Figure 7(h);

- Providing a patterned photoresist layer 53, thereby forming a via mask as illustrated in Figure 13(a);

- Performing an etching step using a selective etchant that etches the patterned oxide semiconductor layer 71 and the patterned metal oxide layer 31 , leading to a structure as shown in Figure 13(b);

- Providing a metal layer (e.g. a Au layer) for forming source and drain contacts as illustrated in Figure 12(c), the metal layer also filling the via; and performing a lift-off step, thereby forming a source contact 26 and a drain contact 27, resulting in a structure as shown in Figure 13(c).

A method according to embodiments of the present invention can also be applied to low temperature processed inorganic materials. In the transistor characterized in Figure 14, the same process steps as for the transistor which characteristics are shown in Figure 6 where used. The plain line is the drain to source current while the dashed line represents the gate to source current. The X- axis is the gate voltage. The active material used for the transistor of Figure 14 was changed from evaporated pentacene to room temperature sputtered Ga-ln- Zn-0 and the substrate was changed from a glass substrate to a plastic foil. The results can be seen in Figure 14. The Ga-ln-Zn-0 transistor presented excellent electrical characteristics with low voltage operation, fairly high charge carrier mobility and close to 0 V onset and threshold voltages: the charge carrier mobility for the Ga-ln-Zn-0 transistor on a plastic foil was 0.91 cm²/Vs and the threshold voltages was 0.04 V. More importantly, the dashed line in Figure 14 is the gate to source current showing no current going through between gate and source-drain fingers, confirming that (i) the metal oxide formed by anodization presents an excellent dielectric quality, (ii) the gate electrode is effectively laterally isolated from the source and drain contacts, thanks to the collapsed metal oxide.

The foregoing description details certain embodiments of the invention. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the invention may be practiced in many ways. It should be noted that the use of particular terminology when describing certain features or aspects of the invention should not be taken to imply that the terminology is being re-defined herein to be restricted to including any specific characteristics of the features or aspects of the invention with which that terminology is associated.

While the above detailed description has shown, described, and pointed out novel features of the invention as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the technology without departing from the spirit of the invention.

Claims

A structure comprising a metal layer (22) on an insulating substrate (10) and a dielectric layer (31 ) overlaying the metal layer (22), the dielectric layer (31 ) insulating electrically the metal layer (22) from its environment at the surface opposite to the substrate (10) and at all sides of the metal layer (22), said overlaying dielectric layer (31 ) defining closed cavities (40) around said metal layer (22).

The structure according to claim 1 , wherein said closed cavities (40) are completely surrounding the metal layer (22).

The structure according to anyone of the preceding claims, wherein said dielectric layer (31 ) is obtainable by anodization of the metal constituting the metal layer (22).

The structure according to anyone of the preceding claims, wherein said dielectric layer (31 ) has a uniform thickness.

The structure according to anyone of the preceding claims, wherein said dielectric layer (31 ) comprises an oxide of the metal constituting said metal layer (22).

A field effect transistor comprising a structure according to anyone of claims 1 to 5, wherein source (26) and drain (27) contacts are provided above said dielectric layer (31 ).

The field effect transistor according to claim 6 further comprising a via through said dielectric layer (31 ) such that an electrical contact can be provided between said source (26) or said drain (27) contact and said metal layer (22).

An electronic circuit comprising one or more structures according to anyone of claims 1 to 5 or one or more field effect transistors according to claim 6 or 7.

9. A method for fabricating a structure according to claim 1 , said method comprising the steps of:

a. providing a continuous metal layer (20) on an insulating substrate (10);

b. providing a dielectric layer (30) on the continuous metal layer (20), thereby forming a continuous dielectric layer (30) on top of the continuous metal layer (20, 21 ); and

c. patterning the metal layer (20, 21 ) and the dielectric layer (30), wherein said patterning comprises a wet etching step with an etchant that etches the metal layer (20, 21 ) substantially faster than the dielectric layer (30), wherein step (c) is performed after step (b).

10. The method according to claim 9, wherein said metal layer (20) has a RMS roughness preferably lower than about 3 nm.

1 1 . The method according to claim 9 or claim 10, wherein after performing the wet etching step, the patterned dielectric layer (31 ) extends over the edges of the underlying patterned metal layer (22) and the overhanging parts (32) of the dielectric layer (31 ) collapse such that they come into contact with the insulating substrate (10), resulting in a fully isolated underlying patterned metal layer (22).

12. The method according to anyone of claims 9 to 1 1 , wherein providing a dielectric layer (30) on the continuous metal layer (20) comprises creating a metal oxide layer (30) on said continuous metal layer (20) by performing an anodization of a top portion of said continuous metal layer (20).

13. The method according to claim 12, wherein the anodization process is performed in two stages wherein in a first stage a constant current is used and the voltage is increased linearly until a certain voltage and in a second stage the voltage is kept constant at said certain voltage and the current is decreased exponentially until a value lower than said constant current used in said first stage.

14. The method according to anyone of claims 9 to 13, wherein the ratio between the etch rate of the metal layer (20, 21 ) and the etch rate of the dielectric layer (30) is larger than about 10, more preferred larger than about 20.

15. The method according to anyone of claims 9 to 14, wherein said structure is a field effect transistor, wherein said patterning of said metal layer (20) provides a gate electrode (22), wherein said metal oxide layer (30) is a gate dielectric layer (31 ), said method further comprising the steps of forming a source (26) and a drain (27) contact above said gate dielectric layer (31 ), and wherein the gate dielectric layer (31 ) provides electrical isolation between the gate electrode (22) and said source (26) and drain (27) contacts.