CN214012946U - Two-dimensional semiconductor transistor structure - Google Patents
Two-dimensional semiconductor transistor structure Download PDFInfo
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- CN214012946U CN214012946U CN202023163499.8U CN202023163499U CN214012946U CN 214012946 U CN214012946 U CN 214012946U CN 202023163499 U CN202023163499 U CN 202023163499U CN 214012946 U CN214012946 U CN 214012946U
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Abstract
The utility model belongs to the technical field of semiconductor device, specifically be a two-dimentional semiconductor transistor structure. The utility model comprises a substrate, a two-dimensional semiconductor material on the substrate, a source drain metal electrode, an oxide dielectric layer and a laminated metal grid on the dielectric layer; the oxide dielectric layer is a double-layer dielectric layer, and the laminated metal grid is a double-layer metal grid structure of bottom active metal and top inert metal. The utility model discloses utilize the active metal of bottom and oxide dielectric layer I direct contact, take place solid phase diffusion reaction and form double-deck dielectric layer, through the thickness of the active metal of control bottom, make two-dimensional semiconductor material's carrier concentration receive the accurate regulation and control of dipole effect. The utility model discloses can adjust two-dimensional semiconductor field effect transistor's threshold voltage, improve the switch ratio and the on-state current of device, have wide application prospect in large-scale digital integrated circuit's manufacturing.
Description
Technical Field
The utility model belongs to the technical field of semiconductor device, concretely relates to two dimension semiconductor transistor structure.
Background
Since the first discovery of graphene, two-dimensional semiconductor materials have attracted considerable attention due to their special layered structure and superior electrical properties. The two-dimensional semiconductor material has a larger forbidden band width range, can overcome short channel effect and quantum effect, keeps good switching frequency, and improves and promotes the performance of many existing electronic components. Two-dimensional semiconductor materials currently prepared by mechanical exfoliation or chemical vapor deposition and the like mainly comprise MoS2、MoTe2、WSe2、WS2h-BN, black phosphorus, and the like. The good electrical and photoelectric properties of the material are beneficial to preparing high-performance logic devices, sensors and memories, and the material is applied to manufacturing large-area cascade connectionA logic circuit.
The traditional semiconductor material utilizes an ion doping method to carry out carrier doping and electrical property regulation, however, due to the channel thickness and the stable crystal structure of the two-dimensional semiconductor material at the atomic level, the ion doping method is easy to cause lattice damage of the two-dimensional semiconductor material, and an interface state and a defect state are introduced, so that the improvement of the device performance is not facilitated.
Disclosure of Invention
An object of the utility model is to provide a controllable two-dimensional semiconductor transistor structure of performance to solve the technical problem that the two-dimensional semiconductor material who mentions in the background art exists is difficult to carry out the carrier doping.
The utility model provides a two-dimensional semiconductor transistor structure, which comprises a substrate, a two-dimensional semiconductor material positioned on the substrate, a source drain metal electrode, an oxide dielectric layer and a laminated metal grid positioned on the dielectric layer; the oxide dielectric layer is a double-layer dielectric layer and comprises a dielectric layer I and a dielectric layer II, the laminated metal gate is a double-layer metal gate structure of bottom active metal and top inert metal, and the dielectric layer II is formed through solid-phase diffusion reaction between the dielectric layer I and the bottom active metal.
The substrate is any one of a glass substrate, a sapphire substrate, a quartz substrate, a silicon substrate or a flexible substrate.
The dielectric layer I is an oxide dielectric layer with a high dielectric constant: any of hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, calcium oxide, strontium oxide, barium oxide, or tantalum oxide.
The bottom active metal grid is an active metal which is easy to oxidize: any of aluminum, magnesium, zinc, iron, or titanium; the top layer inert metal grid is made of inert metal: gold, platinum, silver or copper.
The thickness of the active metal on the bottom layer is accurately regulated and controlled according to the performance requirement of the required transistor, and the thickness range of the active metal is 0.1 nm to 5 nm; the thickness of the top layer inert metal is greater than 5 nm.
The thickness range of the dielectric layer II is 0.1 nm to 5 nm.
The two-dimensional semiconductor transistor structure with controllable performance is obtained by the following steps:
(1) preparing a two-dimensional semiconductor material on the surface of a substrate;
(2) defining a source-drain electrode area on the two-dimensional semiconductor material through the masking layer, and carrying out source-drain metal deposition to prepare a source-drain metal electrode;
(3) defining a channel region by using the masking layer and etching away the two-dimensional semiconductor material outside the channel;
(4) depositing a dielectric layer I on the surface of a two-dimensional semiconductor material in situ;
(5) defining a gate electrode area on the surface of the dielectric layer I by using a masking layer, depositing active metal on a bottom layer under a high vacuum condition, and immediately depositing inert metal on a top layer without damaging the high vacuum state to prepare a laminated gate structure;
(6) after the device is prepared, low-temperature annealing is carried out in an inert gas environment to promote the bottom active metal and the dielectric layer I to generate a solid-phase diffusion reaction;
(7) and standing the device obtained in the step for 7-15 days in an inert gas environment to enable the bottom active metal to have a solid-phase diffusion reaction with the dielectric layer I, and oxidizing the bottom active metal to form the dielectric layer II.
In the step (1), the preparation method of the two-dimensional semiconductor material comprises a bottom-up chemical vapor deposition, physical vapor deposition or atomic layer deposition method, and a bottom-up micro-mechanical stripping method, an ion intercalation stripping method or an ultrasonic stripping method.
In the step (2), the step (3) or the step (5), the masking layer is photoresist or a mask.
Preferably, the patterning method of the masking layer is to use a photolithography process to pattern the photoresist by means of exposure, development and the like; or using a mask plate, and closely attaching the mask plate containing the electrode pattern to the surface of the two-dimensional semiconductor material for patterning.
In the step (2) or the step (5), the metal electrode deposition method is a vacuum evaporation or sputtering coating method.
In the step (3), the channel etching method is dry etching commonly used in the field, such as plasma etching, reactive ion etching or ion sputter etching.
In the step (4), the growth method of the dielectric layer I is an atomic layer deposition method, a chemical vapor deposition method or a physical vapor deposition method.
In the step (6) or the step (7), the inert gas is argon, xenon, helium or neon.
In the step (6), the low-temperature annealing is performed at a temperature ranging from 50 ℃ to 80 ℃ for 10 minutes to 6 hours.
In the step (7), the forming method of the dielectric layer II comprises the following steps: and when the bottom active metal is directly contacted with the dielectric layer I, a solid-phase diffusion reaction is carried out, and metal atoms in the bottom active metal and oxygen atoms in the dielectric layer I are combined through solid-phase diffusion to form an oxide, namely a dielectric layer II.
Compared with the prior art, the utility model discloses a two-dimensional semiconductor transistor structure has following advantage and effect:
the method is characterized in that a bottom active metal is directly contacted with an oxide dielectric layer I to generate a solid-phase diffusion reaction to form a double-layer dielectric layer, and the number of oxygen atoms in the oxide dielectric layer I consumed by the oxidation reaction and the degree of an electric dipole effect generated by oxygen vacancies are controlled by controlling the thickness of the bottom active metal, so that the carrier concentration of the two-dimensional semiconductor material is accurately regulated and controlled by the electric dipole effect. The utility model discloses a control the thickness of active metal and cover with the inert metal, can the accurate carrier doping concentration who regulates and control two-dimensional semiconductor material to solve two-dimensional semiconductor field effect transistor electrical property and be difficult to the problem of adjusting. The utility model discloses can adjust two-dimensional semiconductor field effect transistor's threshold voltage, improve the switch ratio and the on-state current of device, have wide application prospect in large-scale digital integrated circuit's manufacturing.
Drawings
Fig. 1 is a schematic structural diagram of a semiconductor device and a stacked gate according to the present invention. Wherein (a) is a top view of the transistor, and (b) is a side view of the transistor.
Fig. 2 is a schematic diagram of the oxygen vacancy induced electric dipole effect generated in the oxide medium layer II and the medium layer I formed by the solid phase diffusion reaction between the active metal of the middle bottom layer and the medium layer I of the present invention.
Reference numbers in the figures: the structure comprises a substrate 1, a two-dimensional semiconductor material 2, source and drain metal electrodes 3, a medium layer I4, a bottom active metal 5, a top inert metal 6, an electric dipole 7 and a medium layer II 8.
Detailed Description
Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like or similar materials throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present invention, and should not be construed as limiting the present invention.
According to an embodiment of the present invention, a two-dimensional semiconductor transistor structure is provided. As shown in fig. 1, the two-dimensional semiconductor device comprises a substrate 1, a two-dimensional semiconductor material 2 located on the substrate, a source-drain metal electrode 3, a dielectric layer I4, a bottom active metal 5, and a top inert metal 6. The dielectric layer I4 is an oxide dielectric layer with a high dielectric constant, and the laminated metal gate is a double-layer metal gate structure with a bottom active metal 5 and a top inert metal 6.
Fig. 2 shows the oxygen vacancy induced electric dipole effect generated in the oxide dielectric layer II8 and the dielectric layer I4 formed by the solid phase diffusion reaction between the bottom active metal gate 5 and the dielectric layer I4 according to the present invention.
According to the device structure shown in fig. 1, the specific steps for preparation are as follows:
first, a two-dimensional semiconductor material 2 is prepared on a surface of a substrate 1. The substrate 1 is any one of substrates commonly used in the field, such as a sapphire substrate, a quartz substrate, a silicon substrate, a glass substrate or a flexible substrate; the preparation method of the two-dimensional semiconductor material 2 is a bottom-up chemical vapor deposition, physical vapor deposition or atomic layer deposition method, and a bottom-up micro-mechanical stripping method, an ion intercalation stripping method or an ultrasonic stripping method. As a specific example, in this embodiment, sapphire is selected as the substrate 1, and the two-dimensional semiconductor material 2 is prepared by a chemical vapor deposition method. The two-dimensional semiconductor material 2 selected in this embodiment is molybdenum disulfide.
Next, the structure of the source-drain metal electrode 3 is defined. And defining a source-drain electrode region on the two-dimensional semiconductor material 2 through a masking layer, wherein the masking layer is photoresist or a mask. The patterning method of the masking layer is to use a photoetching process to pattern the photoresist by means of exposure, development and the like; or, a mask containing an electrode pattern is formed by patterning the two-dimensional semiconductor material 2 by closely adhering the mask to the surface thereof. And then preparing the source and drain metal electrodes 3 by adopting a vacuum evaporation or sputtering coating method. As a specific example, in this embodiment, a photolithography process is selected, a photoresist is used as a masking layer, a pattern of a source/drain region is obtained on the surface of the two-dimensional semiconductor material 2, through exposure and development, and an electron beam evaporation coating method is used to prepare the source/drain metal electrode 3, where the source/drain metal electrode 3 is a gold electrode with a thickness of 35 nm.
Then, a channel pattern of the two-dimensional semiconductor material 2 is defined. A channel region is defined in the two-dimensional semiconductor material 2 by a masking layer, and the two-dimensional semiconductor material 2 outside the channel is etched away. The etching method is dry etching commonly used in the field, such as plasma etching, reactive ion etching or ion sputtering etching. As a specific example, in this embodiment, molybdenum disulfide is selected as the two-dimensional semiconductor material 2 other than the channel, and is etched by an inductively coupled plasma etching method.
Thirdly, in-situ depositing a dielectric layer I4 on the surface of the two-dimensional semiconductor material 2, wherein the dielectric layer I4 is an oxide dielectric layer with a high dielectric constant, such as any one of hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, calcium oxide, strontium oxide, barium oxide or tantalum oxide; the growth method of the dielectric layer I4 is an atomic layer deposition method, a chemical vapor deposition method or a physical vapor deposition method. As a specific example, in this embodiment, the dielectric layer I4 is prepared by an atomic layer deposition method, and the dielectric layer I4 in this embodiment is hafnium oxide.
Depositing on the surface of the dielectric layer I4The thickness of the gate structure is controlled by the stacked structure of the bottom active metal 5 and the top inert metal 6. The preparation method of the laminated grid structure comprises the following steps: defining a gate electrode region with a masking layer; depositing a bottom active metal 5 by adopting a vacuum evaporation or sputtering coating method under a high vacuum condition, wherein the bottom active metal 5 is any one of aluminum, magnesium, zinc, iron or titanium; and then, continuously depositing a top layer inert metal 6 by adopting a vacuum evaporation or sputtering coating method under the condition of not damaging high vacuum, wherein the top layer inert metal 6 is any one of gold, platinum, silver or copper. The thickness of the active metal on the bottom layer is accurately regulated and controlled according to the performance requirement of the required transistor, and the thickness range of the active metal is 0.1 nm to 5 nm; the thickness of the top layer inert metal is greater than 5 nm. As a specific example, in this embodiment, the gate electrode region is defined by the photolithography process at 1 × 10-5Depositing a bottom active metal 5 by adopting an electron beam evaporation coating method under the high vacuum condition of Pa, wherein the bottom active metal 5 selected in the implementation is aluminum with the thickness of 2nm, and the thickness can be accurately adjusted according to the carrier doping requirement of a transistor; then, under the condition of not destroying high vacuum, the target material in the cavity is automatically changed into inert metal target material by a mechanical control system in the electron beam evaporation device, and the inert metal target material is arranged at 1 x 10-5And (3) preparing top layer inert metal 6 by adopting an electron beam evaporation coating method under the high vacuum condition of Pa, wherein the top layer inert metal 6 selected in the implementation is gold with the thickness of 35 nm.
And then, the device is placed in an inert gas environment for low-temperature annealing, and solid-phase diffusion reaction between the bottom active metal 5 and the dielectric layer I4 is promoted. The inert gas is any one of argon, xenon, helium and neon, and the low-temperature annealing is performed within the temperature range of 50 ℃ to 80 ℃ for 10 minutes to 6 hours. As a specific example, in this example, the prepared device was annealed at 60 ℃ for 1 hour in argon gas.
And finally, standing the device obtained in the step for 7-15 days in an inert gas environment to enable the bottom active metal 5 and the medium layer I4 to generate a solid-phase diffusion reaction, and oxidizing the bottom active metal 5 to form a medium layer II 8. The inert gas is any one of argon, xenon, helium and neon; the forming method of the dielectric layer II8 comprises the following steps: when the bottom active metal 5 directly contacts the dielectric layer I4, a solid phase diffusion reaction occurs, and metal atoms in the bottom active metal 5 and oxygen atoms in the dielectric layer I4 are combined through solid phase diffusion to form an oxide, namely, the dielectric layer II 8; the thickness range of the dielectric layer II8 is 0.1 nm to 5 nm. As a specific example, in this example, the prepared device was left standing in argon gas for 10 days to form an alumina dielectric layer with a thickness of 2 nm.
Although the above description has been made in detail with respect to the one type of two-dimensional semiconductor transistor structure, the present invention is not limited to the above examples, and various improvements and modifications may be made without departing from the scope of the present invention.
Claims (4)
1. A two-dimensional semiconductor transistor structure is characterized by comprising a substrate, a two-dimensional semiconductor material positioned on the substrate, a source drain metal electrode, an oxide dielectric layer and a laminated metal gate positioned on the dielectric layer; the oxide dielectric layer is a double-layer dielectric layer and comprises a dielectric layer I and a dielectric layer II, the laminated metal gate is a double-layer metal gate structure of bottom active metal and top inert metal, and the dielectric layer II is formed after solid-phase diffusion reaction between the dielectric layer I and the bottom active metal; wherein:
the substrate is any one of a glass substrate, a sapphire substrate, a quartz substrate, a silicon substrate or a flexible substrate;
the dielectric layer I is an oxide dielectric layer with a high dielectric constant: any one of hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, calcium oxide, strontium oxide, barium oxide, or tantalum oxide;
the bottom active metal grid is an active metal which is easy to oxidize: any of aluminum, magnesium, zinc, iron, or titanium; the top layer inert metal grid is made of inert metal: gold, platinum, silver or copper.
2. The two-dimensional semiconductor transistor structure of claim 1, wherein the active metal has a thickness in the range of 0.1 nm to 5 nm.
3. A two-dimensional semiconductor transistor structure according to claim 1 or 2, wherein the thickness of the top layer inert metal is greater than 5 nm.
4. The two-dimensional semiconductor transistor structure according to claim 1 or 2, wherein the dielectric layer II has a thickness in the range of 0.1 nm to 5 nm.
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| CN202023163499.8U CN214012946U (en) | 2020-12-25 | 2020-12-25 | Two-dimensional semiconductor transistor structure |
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