WO2023184095A1 - 薄膜晶体管及其制备方法、显示基板、显示装置 - Google Patents

薄膜晶体管及其制备方法、显示基板、显示装置 Download PDF

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WO2023184095A1
WO2023184095A1 PCT/CN2022/083438 CN2022083438W WO2023184095A1 WO 2023184095 A1 WO2023184095 A1 WO 2023184095A1 CN 2022083438 W CN2022083438 W CN 2022083438W WO 2023184095 A1 WO2023184095 A1 WO 2023184095A1
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region
sub
layer
drain
source
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PCT/CN2022/083438
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English (en)
French (fr)
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王明
倪柳松
仵康康
胡迎宾
许晨
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to CN202280000584.5A priority Critical patent/CN117157767A/zh
Priority to PCT/CN2022/083438 priority patent/WO2023184095A1/zh
Publication of WO2023184095A1 publication Critical patent/WO2023184095A1/zh

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  • Embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular, to a thin film transistor and a preparation method thereof, a display substrate, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • LCD Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • embodiments of the present disclosure provide a thin film transistor, including: a substrate and a shielding layer, a buffer layer, an active layer, a gate insulating layer and a conductive layer stacked on the substrate; wherein,
  • the conductive layer includes: a gate electrode, a source electrode and a drain electrode;
  • the active layer includes: a channel region, a source transition region and a drain transition region located on both sides of the channel region, a source connection region located on a side of the source transition region away from the channel region, and a source connection region located on a side of the source transition region away from the channel region. a drain connection region on a side of the drain transition region away from the channel region;
  • the source connection area is connected to the source electrode, and the drain connection area is connected to the drain electrode;
  • Both the source transition region and the drain transition region include: a first sub-region, a second sub-region and a third sub-region connected in sequence, the first sub-region is located away from the second sub-region and away from the trench.
  • One side of the channel region, the third sub-region is located on a side of the second sub-region close to the channel region, and the thickness of the second sub-region is k times the thickness of the channel region, k is 0.8 to 1.5.
  • an embodiment of the present disclosure also provides a display substrate, including: the thin film transistor described in the above embodiment.
  • an embodiment of the present disclosure also provides a display device, including: the display substrate described in the above embodiment.
  • embodiments of the present disclosure also provide a method for manufacturing a thin film transistor, including:
  • a gate insulating layer and a conductive layer are sequentially formed on the active layer.
  • the active layer forms a channel region, a source transition region and a drain transition region located on both sides of the channel region.
  • the conductive layer includes: a gate electrode, a source electrode and a drain electrode; the source connection region is connected to the source electrode, and the drain connection region is connected to the drain electrode; both the source transition region and the drain transition region include: a first sub-region connected in sequence, a second sub-region and a third sub-region, the first sub-region is located on a side of the second sub-region away from the channel region, and the third sub-region is located close to the second sub-region On one side of the channel region, the thickness of the first sub-region and the thickness of the third sub-region are equal to the thickness of the channel region, and the thickness of the second sub-region
  • Figure 1A is a schematic diagram after the first conductorization process in some technologies
  • Figure 1B is a schematic diagram after forming a conductive layer pattern in some technologies
  • Figure 1C is a schematic diagram after the second conductorization process in some technologies
  • Figure 2 is a schematic structural diagram of a thin film transistor in an exemplary embodiment of the present disclosure
  • Figure 3 is another schematic structural diagram of a thin film transistor in an exemplary embodiment of the present disclosure.
  • Figure 4 is another structural schematic diagram of a thin film transistor in an exemplary embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram after forming a shielding layer pattern in an exemplary embodiment of the present disclosure
  • Figure 6 is a schematic diagram of depositing a second metal oxide film in an exemplary embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of the first metal oxide film and the second metal oxide film after the first etching process in an exemplary embodiment of the present disclosure
  • FIG. 8 is a schematic diagram after forming an active layer pattern in an exemplary embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram after forming the gate insulating layer pattern and the first conductorization process in an exemplary embodiment of the present disclosure.
  • Figure 10 is a schematic diagram after forming a conductive layer pattern in an exemplary embodiment of the present disclosure.
  • Figure 11 is a schematic diagram after the second etching of the gate insulating layer in an exemplary embodiment of the present disclosure
  • Figure 12 is a schematic diagram after the second conductorization process and the formation of a passivation layer pattern in an exemplary embodiment of the present disclosure
  • FIG. 13 is a schematic diagram after the second conductorization process in an exemplary embodiment of the present disclosure.
  • the scale of the drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, etc. can be adjusted according to actual needs.
  • the size of each component, the thickness of a layer, or the area may be exaggerated for clarity. Therefore, one aspect of the present disclosure is not necessarily limited to such dimensions, and the shape and size of each component in the drawings does not reflect true proportions.
  • ordinal numbers such as “first”, “second”, and “third” are provided to avoid confusion of constituent elements, but are not intended to limit the quantity.
  • the terms “installed”, “connected” and “connected” should be understood broadly unless otherwise explicitly stated and limited. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the "component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • “Elements with certain electrical effects” may be, for example, electrodes or wirings, switching elements such as transistors, or other functional elements such as resistors, inductors, or capacitors.
  • a transistor refers to a device that includes at least a gate electrode (gate electrode or control electrode), a drain electrode (drain electrode terminal, drain region, or drain electrode), and a source electrode (source electrode terminal, source region, or source electrode). ) components of these three terminals.
  • the transistor has a channel region between the drain electrode and the source electrode, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current mainly flows.
  • one pole is directly described as the first pole and the other pole is the second pole, wherein the first pole can be
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged with each other. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less, and therefore also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced by “conductive film.”
  • insulating film may sometimes be replaced by “insulating layer”.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not strictly speaking. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances. There can be leading angles, arc edges, deformations, etc.
  • amorphous silicon (a-Si) thin film transistors to oxide (Oxide) thin film transistors.
  • the active layer of the oxide thin film transistor uses an oxide active layer (Oxide).
  • the carrier mobility of the oxide active layer is 20 to 30 times that of the amorphous silicon active layer. It has high mobility and high on-state current. , better switching characteristics and better uniformity, which can greatly improve the characteristics of thin film transistors, increase the response speed of pixels, achieve faster refresh rates, and can be suitable for applications that require fast response and large current.
  • Oxide thin film transistors include two types, namely bottom gate thin film transistors and top gate thin film transistors.
  • the structural characteristics of bottom gate thin film transistors are: the source electrode and the drain electrode are respectively covered on both sides of the oxide active layer. On the other side, a channel region is formed between the source electrode and the drain electrode; the structural feature of the top-gate thin film transistor is that the source electrode and the drain electrode are respectively connected to the metal oxide active layer through via holes. Since the top-gate thin film transistor has the characteristics of a short channel, the on-state current (Ion) can be effectively increased, which can significantly improve the display effect and effectively reduce power consumption.
  • Ion on-state current
  • FIG. 1A is a schematic diagram after the first conductorization in some technologies.
  • FIG. 1B is a schematic diagram after forming a conductive layer pattern in some technologies.
  • FIG. 1C is a schematic diagram after the second conductorization in some technologies.
  • the oxide active layer uses IGZO as an example.
  • the first region 101 in the oxide active layer is IGZO that is not conductive.
  • the second region 102 in the layer is conductive IGZO (formed by the first conductorization process); in Figure 1C, the first region 101 in the oxide active layer is conductive IGZO (formed by the second conductorization process).
  • FIG. 1C is schematically illustrated by using arrows to indicate current flow directions.
  • a mask is usually used to etch (Etch) the gate insulating layer (GI) and buffer layer (Buffer) during the preparation of TFT. process, making the overall GI etching time longer, and in the overlap area between the gate electrode (Gate) 61 and the oxide active layer (eg, IGZO), the oxide active layer will undergo two dry etching processes and two Conductor treatment. Therefore, as shown in FIG. 1C , it is easy to cause partial loss of the metal oxide active layer.
  • Etch the gate insulating layer
  • Buffer buffer layer
  • Embodiments of the present disclosure provide a thin film transistor.
  • the thin film transistor may include: a substrate and a shielding layer, a buffer layer, an active layer, a gate insulating layer and a conductive layer stacked on the substrate; wherein,
  • the conductive layer may include: a gate electrode, a source electrode and a drain electrode;
  • the active layer may include: a channel region, a source transition region and a drain transition region located on both sides of the channel region, a source connection region located on a side of the source transition region away from the channel region, and a source connection region located on a side of the drain transition region away from the channel
  • the leaky connection area on one side of the area
  • the source connection area is connected to the source electrode, and the drain connection area is connected to the drain electrode;
  • Both the source transition region and the drain transition region may include: a first sub-region, a second sub-region and a third sub-region connected in sequence, the first sub-region is located on a side of the second sub-region away from the channel region, and the third sub-region The region is located on a side of the second sub-region close to the channel region, the thickness of the second sub-region may be k times the thickness of the channel region, and k may be 0.8 to 1.5.
  • k may include, but is not limited to, 0.8, 0.85, 0.9, 0.95, 1, 1.5, 1.2, 1.25, 1.3, 1.35, 1.4, 1.45 or 1.5, etc.
  • the embodiment of the present disclosure does not limit this.
  • the thickness of the film layer may refer to the dimensional characteristics of the film layer in a direction perpendicular to the plane of the thin film transistor.
  • the thickness of the channel region of the active layer may refer to the dimensional characteristics of the channel region of the active layer in a direction perpendicular to the plane of the thin film transistor
  • the thickness of the second sub-region in the source transition region of the active layer It may refer to the dimensional characteristics of the second sub-region in the source transition region of the active layer in a direction perpendicular to the plane of the thin film transistor
  • the thickness of the second sub-region in the drain transition region of the active layer may refer to the active layer. Dimensional characteristics of the second sub-region in the drain transition region of the layer in a direction perpendicular to the plane of the thin film transistor.
  • FIG. 2 is a schematic structural diagram of a thin film transistor in an exemplary embodiment of the present disclosure.
  • FIG. 3 is another schematic structural diagram of a thin film transistor in an exemplary embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a thin film transistor in an exemplary embodiment of the present disclosure. Another structural diagram of a thin film transistor. In FIG. 2 to FIG. 4 , the thickness of the second sub-region is greater than the thickness of the channel region.
  • the thin film transistor provided by exemplary embodiments of the present disclosure may include: a substrate 10 , a shield (SHL) layer 20 disposed on the substrate 10 , There is a buffer layer 30 on the side of the shielding layer 20 away from the substrate 10 , an active (Active, ACT) layer 40 on the side of the buffer layer 30 away from the substrate 10 , and a buffer layer 30 on the side of the active layer 40 away from the substrate 10 .
  • the conductive layer may include: gate electrode 61, source electrode 62 and drain electrode 63.
  • the active layer 40 may include: a channel region 41, a source transition region 42 and a drain transition region 44 located on both sides of the channel region 41, a source connection region 43 located on a side of the source transition region 42 away from the channel region 41, and The drain connection region 45 is located on the side of the drain transition region 44 away from the channel region 41; the source connection region 43 is connected to the source electrode 62, and the drain connection region 45 is connected to the drain electrode 63; both the source transition region 42 and the drain transition region 44 can be It includes: a first sub-region 1, a second sub-region 2 and a third sub-region 3 connected in sequence, the first sub-region 1 is located on the side of the second sub-region 2 away from the channel region 41, and the third sub-region 3 is located on On the side of the second sub-region 2 close to the channel region 41, the thickness of the second sub-region 2 may be k times the thickness of the channel region 41, and k may be approximately 0.8 to 1.5.
  • the thickness of the source transition region 42 in the active layer 40 and the second sub-region 2 in the drain transition region 44 of the thin film transistor is k times the thickness of the channel region 41, and k may be about 0.8 to 1.5, Deletion of the second sub-region 2 is avoided, thereby improving the conductivity of the source transition region 42 and the drain transition region 44, thereby improving the current output capability of the thin film transistor.
  • the source transition region 42 in the active layer and the second sub-region 2 in the drain transition region 44 are regions in the active layer that are subjected to double etching and double conductorization.
  • k may be set to 1 to 1.5, for example, k may be approximately 1, 1.5, 1.2, 1.25, 1.3, 1.35, 1.4, 1.45, or 1.5, etc. In this way, thin film transistor defects caused by double conductionization can be more effectively prevented.
  • both the thickness of the first sub-region 1 and the thickness of the third sub-region 3 may be equal to the thickness of the channel region 41 .
  • the thickness of the first sub-region 1 may be approximately 20 nm to 200 nm
  • the thickness of the second sub-region 2 may be approximately 16 nm to 300 nm
  • the thickness of the third sub-region 3 may be approximately 20 nm to 200 nm
  • the thickness of the channel region 41 may be approximately 20 nm to 200 nm.
  • the embodiment of the present disclosure does not limit this.
  • the gate electrode 61, the source electrode 62 and the drain electrode 63 are arranged in the same layer of materials.
  • the number of patterning processes can be reduced, the process time can be shortened, and the process cost can be reduced.
  • “same layer arrangement” may refer to structures formed by patterning two (or more than two) structures through the same patterning process, and their materials may be the same or different.
  • the precursor materials used to form multiple structures arranged in the same layer are the same, and the final materials formed may be the same or different.
  • the conductivity of the second sub-region 2 is greater than the conductivity of the first sub-region 1 , and the conductivity of the second sub-region 2 is greater than the conductivity of the third sub-region 3 . In this way, it is beneficial to improve the electrical characteristics of the thin film transistor.
  • the oxygen element content of the second sub-region 2 is less than the oxygen element content of the first sub-region 1
  • the oxygen element content of the second sub-region 2 is less than the oxygen element content of the third sub-region 3 . In this way, it is beneficial to improve the electrical characteristics of the thin film transistor.
  • the conductivity of the second sub-region 2 is greater than the conductivity of the source connection region 43 , and the conductivity of the second sub-region 2 is greater than the conductivity of the drain connection region 45 .
  • the oxygen element content of the second sub-region 2 is less than the conductivity of the source connection region 43 , and the oxygen element content of the second sub-region 2 is less than the oxygen element content of the drain connection region 45 .
  • the thickness of the first sub-region 1 can be a first conductor material.
  • the first conductor material is obtained by performing a conductive treatment on the first metal oxide film.
  • the material of the second sub-region 2 can be a second conductor material.
  • the second conductor material includes: a stacked first sub-conductor material and a second sub-conductor material.
  • the first sub-conductor material is obtained by subjecting the first metal oxide film to conductive treatment twice.
  • the second sub-conductor material is obtained by subjecting the first metal oxide film to conductive treatment.
  • the two metal oxide films are obtained by performing two conduction treatments.
  • the second metal oxide film is disposed on the side of the first metal oxide film away from the substrate 10 .
  • the oxygen element hardness of the second metal oxide film is smaller than that of the first metal oxide film. The hardness of the film. In this way, the signal transmission capability can be enhanced, the current output capability of the thin film transistor can be improved, and the electrical performance of the thin film transistor can be improved.
  • the material of the first sub-region 1 and the third The material of the sub-region 3 can be a first conductor material, which is obtained by performing a conductive treatment on the first metal oxide film.
  • the material of the second sub-region 2 can be a third conductor material.
  • the conductor material is obtained by conducting conductive treatment on the first metal oxide film twice. In this way, the signal transmission capability can be enhanced, the current output capability of the thin film transistor can be improved, and the electrical performance of the thin film transistor can be improved.
  • the thickness of the second metal oxide layer in the second sub-region is smaller than the thickness of the first metal oxide layer in the second sub-region.
  • the thickness of the second sub-conductor material in the second sub-region is smaller than the thickness of the first sub-conductor material.
  • the first metal oxide film and the second metal oxide film may include, but are not limited to, an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten and indium and Oxides of zinc, oxides containing titanium and indium, oxides containing titanium and indium and tin, oxides containing indium and zinc, oxides containing silicon and indium and tin, oxides containing indium and gallium and zinc and other metal oxides.
  • both the first metal oxide film and the second metal oxide film may be formed using indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • both the first metal oxide film and the second metal oxide film can be formed using indium tin zinc oxide (ITZO).
  • ITZO indium tin zinc oxide
  • the width of the second sub-region may be smaller than the width of the first sub-region; or, the width of the second sub-region may be smaller than the width of the third sub-region.
  • the source electrode 62 at least partially covers the second sub-region 2 of the source transition region 42 ; or the drain electrode 63 at least partially covers the second sub-region 2 of the drain transition region 44 . In this way, the over-engraving phenomenon in the first sub-region 1 due to process errors can be avoided.
  • the second sub-region 2 of the source transition region 42 may include: a first portion (not labeled in the figure) covered by the source electrode 62 and a portion not covered by the source electrode 62
  • the second part (not labeled in the figure) the width of the first part is smaller than the width of the second part;
  • the second sub-region 2 of the drain transition region 44 includes: a third part covered by the drain electrode 63 and a third part not covered by the drain electrode 63 Cover the fourth part, the width of the third part being less than the width of the fourth part.
  • the active layer 40 may further include: a first region 46 located on a side of the source connection region 43 away from the channel region 41 and a first region 46 located on a side of the drain connection region 45 away from the channel.
  • the second region 47 on one side of the track region 41; wherein the width of the second sub-region 2 of the source transition region 52 is smaller than the width of the first region 46, or the width of the second sub-region 2 of the drain transition region 44 is smaller than the width of the second region 47.
  • the width of area 46 is
  • the width may refer to the dimensional features along the first direction D1, the first direction D1 intersects the second direction D2, for example, the first direction D1 is perpendicular to the second direction D2, and the second direction D2 may refer to the dimension perpendicular to The direction of the plane of the thin film transistor or the thickness direction of the thin film transistor.
  • the source electrode 62 is disposed in the first sub-region 1 of the source transition region 42 of the active layer 40 and is connected to the active layer through the first via K1
  • the drain electrode 63 is connected to the first sub-region 1 of the drain transition region 44 of the active layer 40 and is connected to the drain connection region 45 of the active layer 40 through the second via hole K2. In this way, it is beneficial to improve the electrical characteristics of the thin film transistor.
  • the boundary of the orthographic projection of the active layer 40 on the substrate 10 is located within the boundary of the orthographic projection of the blocking layer 20 on the substrate 10 .
  • the shielding layer 20 may include: a first shielding layer 201 and a second shielding layer 202 arranged at intervals, an orthographic projection of the active layer 40 on the substrate 10 The boundary is located within the boundary range of the orthographic projection of the first shielding layer 201 on the substrate, and the source electrode 62 is connected to the second shielding layer 202 through the third via hole K3.
  • the second shielding layer 202 may be configured to transmit gate signals, so that a thin film transistor with a dual-gate structure may be formed, that is, the thin film transistor may include a lower transistor and an upper transistor of the same channel.
  • the threshold voltage of the lower transistor is less negatively biased than that of the upper transistor.
  • the negative bias degree reduces the overall negative bias degree of the thin film transistor, which can ensure the stability of the thin film transistor and the uniformity of the electrical characteristics of the transistor.
  • the first shielding layer 201 may be configured to shield the thin film transistor from light, thereby reducing the intensity of light irradiating the thin film transistor and reducing the leakage current, thereby reducing the impact of light on the characteristics of the thin film transistor.
  • the shielding layer may be made of any one or more of metal materials such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo). It can be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo). It can be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • the embodiment of the present disclosure does not limit this.
  • the second sub-region 2 is formed by a first conductorization process and a second conductorization process, and the first sub-region 2 1 is formed by a first conductorization process, the third sub-region 3 is formed by a second conductorization process, and the channel region 41 is formed during a self-aligned second conductorization process.
  • the conductivity of the second sub-region 2 can be improved, which is beneficial to improving the electrical characteristics of the pixel driving circuit.
  • the channel region is formed during the self-aligned second conductorization process, the alignment accuracy between the gate electrode and the underlying channel region can be improved, and the electrical characteristics of the thin film transistor can be improved.
  • the thin film transistor in the exemplary embodiment of the present disclosure can be applied in a display substrate with a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED). ) or quantum dot light-emitting diode display (QDLED) and other display substrates.
  • a pixel driving circuit such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED). ) or quantum dot light-emitting diode display (QDLED) and other display substrates.
  • QLED quantum dot display
  • Micro LED or Mini LED micro LED or Mini LED
  • QDLED quantum dot light-emitting diode display
  • the following is an exemplary description through the preparation process of a thin film transistor.
  • the "patterning process" mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” mentioned in this disclosure means that A and B are formed simultaneously through the same patterning process, and the “thickness” of the film layer is the size of the film layer in the direction perpendicular to the thin film transistor.
  • “the orthographic projection of B is within the range of the orthographic projection of A” or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the orthographic projection of A. within the bounds of A, or the bounds of the orthographic projection of A overlap with the bounds of the orthographic projection of B.
  • the preparation process of the thin film transistor may include the following operations:
  • forming the shielding layer pattern may include: sequentially depositing a first metal film on the substrate 10 , patterning the first metal film through a patterning process, and forming the shielding layer 20 pattern on the substrate 10 .
  • the first metal film is patterned through a halftone patterning process.
  • the photoresist pattern may include unexposed areas. and a fully exposed area.
  • the unexposed area includes the location of the first shielding layer 201 and the second shielding layer 202 patterns.
  • the photoresist in the unexposed area has a first thickness.
  • the photoresist in the fully exposed area is completely removed.
  • On the substrate 10 forms the shielding layer 20 pattern.
  • the thickness of the first metal film may be approximately 100 nm (nanometer) to 1000 nm.
  • the embodiment of the present disclosure does not limit this.
  • forming the active layer pattern may include: sequentially depositing a first insulating film, a first metal oxide film 81 and For the second metal oxide film 82, the first metal oxide film 81 and the second metal oxide film 82 are patterned through a halftone patterning process to form a buffer layer 30 covering the pattern of the shielding layer 20, and to form Active layer 40 pattern on buffer layer 30 .
  • patterning the first metal oxide film 81 and the second metal oxide film 82 through a halftone patterning process may include: first The metal oxide film 82 is coated with a layer of photoresist, and a halftone mask is used to expose the photoresist. After development, a photoresist pattern is formed.
  • the photoresist pattern includes unexposed areas and partially exposed areas. area and the fully exposed area.
  • the unexposed area includes the positions of the channel area 41, the source transition area 42, the drain transition area 44, the source connection area 43 and the drain connection area 45 in the active layer 40.
  • the photoresist in the unexposed area has First thickness.
  • the partially exposed region includes the location of the second sub-region 2 in the source transition region 42 and the second sub-region 2 in the drain transition region 44.
  • the photoresist in the partially exposed region has a second thickness, and the second thickness is smaller than the first thickness.
  • the other areas are fully exposed areas, and the photoresist in the fully exposed areas is completely removed, exposing the surface of the second metal oxide film 82 .
  • a first etching process is used to remove the first metal oxide film 81 and the second metal oxide film 82 in the fully exposed area.
  • an ashing process is used to remove the photoresist in the partially exposed area, so that the surface of the second metal oxide film 82 is exposed in the partially exposed area.
  • a second etching process is used to remove the second metal oxide film 82 in the partially exposed area, exposing the first metal oxide film 81 in the partially exposed area.
  • the remaining photoresist is peeled off to form an active layer 40 pattern on the substrate.
  • the channel region 41 in the active layer 40 , the first sub-region 1 and the third sub-region 3 in the source transition region 42 , the first sub-region 1 and the third sub-region 3 in the drain transition region 44 , and the source connection A metal oxide film is formed in the region 43 and the drain connection region 45, and a double-layer metal oxide film is formed in the second sub-region 2 in the source transition region 42 and the second sub-region 2 in the drain transition region 44.
  • the second sub-region 2 and the drain transition region in the source transition region 42 can be increased.
  • the etching resistance of the location where the second sub-region 2 is located in the region 44 so that the metal oxide in the second sub-region 2 in the source transition region 42 and the second sub-region 2 in the drain transition region 44 can be avoided in subsequent processes.
  • the membrane is etched through, thereby increasing conductivity.
  • the deposition process of the second metal oxide film 82 is different from the deposition process of the first metal oxide film 81 .
  • the oxygen element content of the second metal oxide film 82 is greater than the oxygen element content of the first metal oxide film 81
  • the power of the second metal oxide film 82 is less than the power of the first metal oxide film 81 . In this way, there can be an obvious film quality difference between the second metal oxide film 82 and the first metal oxide film 81.
  • the hardness of the first metal oxide film 81 is greater than the hardness of the second metal oxide film 82, so that , on the one hand, by performing the second etching process for an appropriate time, the second metal oxide film 82 above the first metal oxide film 81 can be etched away; on the other hand, the first metal oxide film 81 can be added
  • the etching resistance is high enough to avoid partial loss of the first metal oxide film 81 .
  • power refers to the sputtering power used in the deposition process when depositing a metal oxide film.
  • the oxygen content of the second metal oxide film may be approximately 30% to 50%, and the oxygen content of the first metal oxide film may be approximately 20% to 30%.
  • the embodiment of the present disclosure does not limit this.
  • the power of the second metal oxide film may be approximately 4 kw to 6 kw, and the power of the first metal oxide film may be approximately 8 kw to 14 kw.
  • the embodiment of the present disclosure does not limit this.
  • the first metal oxide film and the second metal oxide film may include, but are not limited to, an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten and indium and Oxides of zinc, oxides containing titanium and indium, oxides containing titanium and indium and tin, oxides containing indium and zinc, oxides containing silicon and indium and tin, oxides containing indium and gallium and zinc and other metal oxides.
  • both the first metal oxide film and the second metal oxide film may be formed using indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • both the first metal oxide film and the second metal oxide film can be formed using indium tin zinc oxide (ITZO).
  • ITZO indium tin zinc oxide
  • the thickness of the first metal oxide film and the thickness of the second metal oxide film may be approximately 20 nm to 200 nm.
  • the embodiment of the present disclosure does not limit this.
  • the thickness of the first insulating film may be approximately 200 nm to 1000 nm.
  • the embodiment of the present disclosure does not limit this.
  • forming a pattern of the gate insulation (GI) layer 50 may include: sequentially depositing a second insulating film on the substrate 10 on which the foregoing pattern is formed, and using a halftone patterning process.
  • the second insulating film is patterned to form a gate insulating (GI) layer 50 pattern and a plurality of via hole patterns opened on the gate insulating (GI) layer 50 .
  • the plurality of via hole patterns include at least a first via hole K1 and a second via hole K1 . Via hole K2, third via hole K3, fourth via hole K4 and fifth via hole K5.
  • patterning the second insulating film through a halftone patterning process may include: first coating a layer of photoresist on the second insulating film, using a halftone patterning process.
  • the mask exposes the photoresist, and develops it to form a photoresist pattern.
  • the photoresist pattern includes an unexposed area, a partially exposed area, and a fully exposed area.
  • the fully exposed area includes the location of the third via K3 pattern, and the partially exposed area includes the location of the third via K3 pattern.
  • the area includes the locations of the first via hole K1, the second via hole K2, the fourth via hole K4 and the fifth via hole K5.
  • the other areas are unexposed areas.
  • the photoresist in the unexposed area has a first thickness and is partially exposed.
  • the photoresist in the region has a second thickness, and the second thickness is less than the first thickness.
  • a first etching process is used to remove the second insulating film and the first insulating layer in the fully exposed area to form a third via K3 pattern, so that the third via K3 exposes the second shielding layer 202 for subsequent formation.
  • the source electrode 62 may be connected to the second shielding layer 202 through the third via hole K3.
  • an ashing process is used to remove the photoresist in the partially exposed area, so that the second insulating film is exposed in the partially exposed area.
  • a second etching process is used to remove the second insulating film in the partially exposed area, forming a pattern of first via hole K1, second via hole K2, fourth via hole K4, and fifth via hole K5, so that the first via hole K1, the second via hole K2, the fourth via hole K4 and the fifth via hole K5 expose the active layer 40 for subsequent conductive processing for the second time.
  • the remaining photoresist is peeled off to form a gate insulation (GI) layer 50 pattern and a plurality of via hole patterns opened on the gate insulation (GI) layer 50 .
  • GI gate insulation
  • the plurality of via hole patterns include at least a first via hole K1, a second via hole K2, a third via hole K3, a fourth via hole K4, and a fifth via hole K5.
  • the first via K1 is located at the location of the source connection region 43 in the active layer 40 and exposes the surface of the source connection region 43 in the active layer 40 .
  • the first via K1 is configured to enable the source of the subsequently formed thin film transistor.
  • the electrode 62 is connected to the source connection area 43 .
  • the second via hole K2 is located at the location of the drain connection region 45 in the active layer 40, exposing the surface of the drain connection region 45 in the active layer 40.
  • the second via hole K2 is configured to prevent the leakage current of the subsequently formed thin film transistor.
  • Pole 63 is connected to drain connection area 45 .
  • the third via K3 is located at the location of the second shielding layer 202 in the shielding layer 20 , exposing the surface of the second shielding layer 202 in the shielding layer 20 .
  • the third via K3 is configured as a source of a subsequently formed thin film transistor.
  • the electrode 62 is connected to the second shielding layer 202 of the shielding layer 20 .
  • the fourth via K4 is located at the location of the first sub-region 1 and the second sub-region 2 in the source transition region 42 in the active layer 40 , exposing the first sub-region 1 and the second sub-region 2 in the source transition region 42 in the active layer 40
  • the surface of the second sub-region 2 is for subsequent conductive processing.
  • the fifth via K5 is located at the location of the first sub-region 1 and the second sub-region 2 in the drain transition region 44 in the active layer 40 , exposing the first sub-region 1 and the second sub-region 2 in the drain transition region 44 in the active layer 40
  • the surface of the second sub-region 2 is for subsequent conductive processing.
  • a gate insulation (GI) layer 50 located where the active layer 40 is located covers a partial area of the active layer 40 .
  • the thickness of the second insulating film may be approximately 100 nm to 500 nm.
  • the embodiment of the present disclosure does not limit this.
  • a first conductorization process is performed.
  • the first conductorization process may include: performing a first conductorization process on the partial area of the active layer 40 that is not covered by the gate insulation (GI) layer 50 on the substrate on which the foregoing pattern is formed, that is, on the source transition area.
  • the active layer where the first sub-region 1 of 42, the first sub-region 1 of the drain transition region 44, the source connection region 43 and the drain connection region 45 are located undergoes a first conductorization process to form a source transition region of the active layer.
  • the second sub-region 2 is subjected to a conductorization process to form the second sub-region 2 after primary conductivity.
  • forming the conductive layer pattern may include: depositing a second metal film on the substrate on which the foregoing pattern is formed. Coat a layer of photoresist on the second metal film, form a photoresist pattern through masking, exposure and development, and use the first etching process to etch the second metal film to form a conductive layer pattern, leaving the conductive layer of photoresist.
  • the conductive layer pattern may include at least gate electrode 61, source electrode 62, and drain electrode 63 patterns.
  • the source electrode 62 is connected to the source connection region 43 of the active layer 40 that has undergone conductive processing through the first via hole K1 , and the first end of the source electrode 62 is placed on In the first sub-region 1 of the source transition region 42 where the source layer 40 undergoes conductive treatment, the second end of the source electrode 62 is connected to the second shielding layer 202 through the third via hole K3.
  • the drain electrode 63 is connected to the conductorized drain connection region 45 of the active layer 40 through the second via hole K2 , and the first end of the source electrode 62 is placed on The source layer 40 is conductorized on the first subregion 1 of the drain transition region 44 .
  • the thickness of the second metal film may be approximately 100 nm to 1000 nm.
  • the embodiment of the present disclosure does not limit this.
  • the second etching process may include: using the conductive layer pattern and the photoresist on the remaining conductive layer as a mask, self-aligning through the second etching process.
  • the gate insulation (GI) layer 50 is etched downward to remove the gate insulation (GI) layer 50 covering the third sub-region 3 of the source transition region 42 and the third sub-region 3 of the drain transition region 44 of the active layer.
  • the boundary of the orthographic projection of the gate electrode 61 on the substrate 10 is located within the boundary of the orthographic projection of the gate insulating (GI) layer 50 on the substrate, and the channel of the active layer
  • the boundary of the orthographic projection of the region 41 on the substrate 10 is located within the boundary of the orthographic projection of the gate insulating (GI) layer 50 on the substrate.
  • the second conductorization process may include: a gate insulation (GI) layer 50 and a conductive layer pattern disposed on the gate insulation (GI) layer 50 (For example, the conductive layer pattern may at least include gate electrode 61, source electrode 62 and drain electrode 63 patterns), and the photoresist remaining on the conductive layer is used as a mask, and the gate insulation (GI) layer in the active layer 40 is not Another part of the area covered by 50 is conductive, that is, the channel region 41 of the unconducted active layer 40, the third sub-region 3 of the source transition region 42 of the unconducted active layer 40 and the unconducted The position of the third sub-region 3 of the drain transition region 44 is conductive treated to form the channel region 41 of the active layer 40, the third sub-region 3 of the source transition region 42 of the active layer 40 and the drain transition region 44.
  • GI gate insulation
  • the conductive layer pattern may at least include gate electrode 61, source electrode 62 and drain electrode 63 patterns
  • the photoresist remaining on the conductive layer is used
  • the third sub-region 3; and the second sub-region 2 of the source transition region 42 after the primary conductorization and the second sub-region 2 of the drain transition region 44 after the primary conductivity are both conductorized to form two The second subregion 2 of the source transition region 42 after secondary conductivity and the second subregion 2 of the drain transition region 44 after secondary conductivity. Peel off remaining photoresist.
  • the second conductorization process uses the gate insulating (GI) layer 50, the conductive layer pattern, and the photoresist remaining on the conductive layer as a mask, it is a self-aligned conductorization process, so the final formation
  • the channel width of is substantially the same as the width of the gate electrode 61. In this way, the alignment accuracy between the gate electrode 61 and the underlying channel region can be improved, and the electrical characteristics of the thin film transistor can be greatly improved.
  • the active layer undergoes two conductorization processes, so that the active layer forms five regions: a channel region 41, a source transition region 42 located on both sides of the channel region 41, and a drain transition region 44. , a source connection region 43 located on a side of the source transition region 42 away from the channel region 41 , and a drain connection region 45 located on a side of the drain transition region 44 away from the channel region 41 .
  • the orthographic boundary of the channel region 41 on the substrate substantially overlaps the orthographic boundary of the gate electrode 61 on the substrate.
  • the area of the first conductorization process and the area of the second conductorization process have an overlapping area, that is, the second sub-region 2 location. Since there are thicker metal oxide films in the second sub-region 2 in the source transition region 42 and the second sub-region 2 in the drain transition region 44 in the active layer 40 , the second sub-region 2 in the source transition region 42 can be increased. and the etching resistance of the second sub-region 2 in the drain transition region 44, thereby avoiding the metal oxide film in the second sub-region 2 in the source transition region 42 and the second sub-region 2 in the drain transition region 44. Etched through, thereby improving conductivity.
  • the second sub-region 2 in the source transition region 42 and the second sub-region 2 in the drain transition region 44 of the active layer 40 undergo conductive processing twice, the The second sub-region 2 in the source transition region 42 and the drain transition region 44 in the active layer 40 have lower resistance and stronger conductivity, and the conductivity of the second sub-region 2 is greater than that of the first sub-region 1
  • the conductivity of the second sub-region 2 is greater than the conductivity of the third sub-region 3 . In this way, it is beneficial to improve the electrical characteristics of the thin film transistor.
  • the second sub-region 2 in the source transition region 42 and the second sub-region 2 in the drain transition region 44 of the active layer 40 undergo conductive processing twice, so that the conductive processing is performed twice.
  • the second sub-region 2 in the source transition region 42 and the second sub-region 2 in the drain transition region 44 of the active layer 40 are subjected to two helium (He) plasma treatments, resulting in a further reduction in the oxygen element content in the film layer. Therefore, the third The oxygen element content of the second sub-region 2 is less than the oxygen element content of the first sub-region 1, and the oxygen element content of the second sub-region 2 is less than the oxygen element content of the third sub-region 3. In this way, it is beneficial to improve the electrical characteristics of the thin film transistor.
  • the source transition region 4 in the active layer 40 undergo conductive processing twice, the source transition region 4 in the active layer 40
  • the connection region 43 and the drain connection region 45 have only undergone the first conductorization process. Therefore, the conductivity of the second sub-region 2 is greater than that of the source connection region 43, and the conductivity of the second sub-region 2 is greater than that of the drain connection region 45. conductivity.
  • the oxygen element content of the second sub-region 2 is less than the oxygen element content of the source connection region 43 , and the oxygen element content of the second sub-region 2 is less than the oxygen element content of the drain connection region 45 .
  • the gate insulation (GI) layer 50 is etched twice, and the over-etching of the etching process will etch away the source transition in the active layer 40
  • the thickness of oxide layer 81 may become thinner or even completely missing.
  • the thickness of the first metal oxide layer 82 in the second sub-region 2 may be a second conductor material.
  • the second conductor material includes: a stacked first sub-conductor material and a second sub-conductor material. The conductor material is obtained by subjecting the first metal oxide film to conductive treatment twice, and the second sub-conductor material is obtained by subjecting the second metal oxide film to conductive treatment twice, so that the thickness of the second sub-region 2 is greater than the channel.
  • the thickness of the region 41 (for example, k can be about 1 to 1.5); and after step 7, when the second metal oxide layer 81 in the second sub-region 2 is completely missing, the material of the second sub-region 2 can be
  • the third conductor material is obtained by conducting conductive treatment on the first metal oxide film twice, so that the thickness of the second sub-region 2 is less than or equal to the thickness of the channel region 41 (for example, k may be approximately 0.8 to 1).
  • the loss of the second sub-region can be avoided in the final thin film transistor, thereby enhancing the signal transmission capability, improving the current output capability of the thin film transistor, and improving the electrical performance of the thin film transistor.
  • the thickness of the second sub-region 2 in the source transition region 42 and the drain transition region 44 in the finally formed active layer 40 may be k times the thickness of the channel region 41 , and k may be about 0.8 to 1.5. In this way, as shown in FIG. 13 , defects in the second sub-region 2 are avoided, thereby improving the conductivity of the source transition region 42 and the drain transition region 44 , thereby improving the current output capability of the thin film transistor.
  • forming the passivation layer pattern may include: depositing a third insulating film on the substrate on which the foregoing pattern is formed to form a passivation layer 70 pattern covering the foregoing structure.
  • the thickness of the third insulating film may be approximately 200 nm to 1000 nm.
  • the embodiment of the present disclosure does not limit this.
  • the shielding layer and the conductive layer can be made of metal materials, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) or More kinds, or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • metal materials such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) or More kinds, or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb)
  • AlNd aluminum-neodymium alloy
  • MoNb molybdenum-niobium alloy
  • the buffer layer, gate insulating layer and passivation layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON). , can be single layer, multi-layer or composite layer.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • SiON silicon oxynitride
  • the embodiment of the present disclosure does not limit this.
  • the substrate may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate may include, but is not limited to, materials such as glass or quartz.
  • the flexible substrate may include, but is not limited to, materials such as polyimide (PI) or polyethylene terephthalate (PET).
  • PI polyimide
  • PET polyethylene terephthalate
  • the flexible substrate may be a single-layer structure, or may be an inorganic material layer and a flexible material layer. composed of laminated structures.
  • the embodiment of the present disclosure does not limit this.
  • Exemplary embodiments of the present disclosure also provide a method of manufacturing a thin film transistor.
  • the thin film transistor is the thin film transistor in one or more exemplary embodiments described above.
  • a method of manufacturing the thin film transistor may include:
  • Step S1 Form an occlusion layer, a buffer layer and an active layer on the substrate in sequence;
  • Step S2 Form a gate insulating layer and a conductive layer on the active layer in sequence.
  • the active layer forms a channel region, a source transition region and a drain transition region located on both sides of the channel region, and a source transition region located on both sides of the channel region.
  • the source connection region on the side of the region away from the channel region, and the drain connection region on the side of the drain transition region away from the channel region; the conductive layer may include: a gate electrode, a source electrode and a drain electrode; the source connection region and the source electrode connection, the drain connection region is connected to the drain electrode; both the source transition region and the drain transition region may include: a first sub-region, a second sub-region and a third sub-region connected in sequence, the first sub-region is located far away from the second sub-region On one side of the channel region, the third sub-region is located on the side of the second sub-region close to the channel region.
  • the thickness of the first sub-region and the thickness of the third sub-region are both equal to the thickness of the channel region.
  • the second sub-region is The thickness of the region is k times the thickness of the channel region, k may be about 0.8 to 1.5.
  • step S1 may include:
  • Step S11 Form a shielding layer and a buffer layer on the substrate in sequence
  • Step S12 Form two layers of metal oxide films on the buffer layer, pattern the two layers of metal oxide films to form an active layer, the two layers of metal oxide films may include: a stacked first metal oxide film and a second metal oxide film, the oxygen element content of the second metal oxide film is greater than the oxygen element content of the first metal oxide film, and the power of the second metal oxide film is less than the power of the first metal oxide film.
  • step S2 may include:
  • Step S21 Form a gate insulating layer on the active layer
  • Step S22 Perform a first conductorization process on the active layer not covered by the gate insulating layer to form the first sub-region of the source transition region, the first sub-region of the drain transition region, the source connection region and the drain region of the active layer. connection area;
  • Step S23 Form a conductive layer on the gate insulating layer
  • Step S24 Use a self-aligned etching method to remove the gate insulating layer of the source transition region and the gate insulating layer of the drain transition region to expose the third sub-region of the unconducted drain transition region and the unconducted source transition.
  • Step S25 Perform a second conductorization process on the active layer not covered by the gate insulating layer to form the channel region of the active layer, the second sub-region and the third sub-region of the source transition region, and the drain transition region. Second sub-area and third sub-area.
  • An embodiment of the present disclosure provides a display substrate, which may include the thin film transistor in one or more of the above embodiments.
  • the display substrate may include: a driving circuit layer provided on the substrate, a light-emitting structure layer provided on a side of the driving circuit layer away from the substrate, and a light-emitting structure layer provided on the side of the driving circuit layer away from the substrate.
  • the display substrate may include other film layers, such as a touch structure layer.
  • the embodiment of the present disclosure does not limit this.
  • the driving circuit layer of each sub-pixel may include: a plurality of transistors and a storage capacitor constituting the pixel driving circuit, and at least one of the plurality of transistors may be the thin film in one or more of the above embodiments.
  • transistor the pixel driving circuit can adopt a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the embodiment of the present disclosure does not limit this.
  • the light-emitting structure layer may include: an anode, a pixel definition layer, an organic light-emitting layer, and a cathode.
  • the anode is connected to the drain electrode of the driving transistor through a via hole.
  • the organic light-emitting layer is connected to the anode.
  • the cathode is connected to the organic light-emitting layer.
  • the layers are connected, and the organic light-emitting layer emits light of corresponding colors driven by the anode and cathode.
  • the packaging structure layer may include a stacked first packaging layer, a second packaging layer, and a third packaging layer.
  • the first packaging layer and the third packaging layer may be made of inorganic materials
  • the second packaging layer may be made of organic materials. It is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.
  • the embodiment of the present disclosure does not limit this.
  • the organic light-emitting layer may include: an light-emitting layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer (EBL) , hole blocking layer (HBL), electron transport layer (ETL) and electron injection layer (EIL).
  • EML light-emitting layer
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer and electron injection layer of all sub-pixels may be connected to Together with the common layer, the light-emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.
  • the embodiment of the present disclosure does not limit this.
  • the display substrate in the exemplary embodiment of the present disclosure may include, but is not limited to, an OLED display substrate, a QLED display substrate, a light emitting diode display (Micro LED or Mini LED) or a quantum dot light emitting diode (QDLED). ) display substrate, etc.
  • the embodiment of the present disclosure does not limit this.
  • the display substrate in the embodiment of the present disclosure may also include other necessary components and structures, such as gate lines, data lines, pixel electrodes or common electrodes and other components. Those skilled in the art can design and supplement accordingly according to the type of the display substrate, which will not be described again here.
  • the above description of the display substrate embodiment is similar to the above description of the thin film transistor embodiment, and has similar beneficial effects as the thin film transistor embodiment.
  • those skilled in the art should refer to the description of the embodiments of the thin film transistor of the present disclosure for understanding, and will not be described again here.
  • An embodiment of the present disclosure also provides a display device, which may include the display substrate in one or more of the above embodiments.
  • the display device may include, but is not limited to, an OLED display device, a QLED display device, a light emitting diode (Micro LED or Mini LED) display device, or a quantum dot light emitting diode (QDLED) display device, etc. having pixels.
  • Display device driving circuit For example, assuming that the display device adopts an OLED display device, the display device may be a 48-inch television (TV). Here, the embodiment of the present disclosure does not limit this.
  • the display device may include, but is not limited to, any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator.
  • the embodiment of the present disclosure does not limit the type of the display device.
  • Other essential components of the display device are understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used to limit the present disclosure.
  • the above description of the display device embodiment is similar to the description of the above thin film transistor and display substrate embodiments, and has similar beneficial effects as the thin film transistor and display substrate embodiments.
  • those skilled in the art should refer to the descriptions of the embodiments of the thin film transistors and display substrates of the present disclosure for understanding, and will not be described again here.

Abstract

一种薄膜晶体管及其制备方法、显示基板、显示装置，该薄膜晶体管，包括：基底以及在基底上叠设的遮挡层、缓冲层、有源层、栅绝缘层和导电层；其中，导电层包括：栅电极、源电极和漏电极；有源层包括：沟道区域、位于沟道区域两侧的源过渡区域和漏过渡区域、位于源过渡区域的远离沟道区域一侧的源连接区域、以及位于漏过渡区域的远离沟道区域一侧的漏连接区域；源过渡区域和漏过渡区域均包括：依次连接的第一子区、第二子区和第三子区，第一子区位于第二子区的远离沟道区域的一侧，第三子区位于第二子区的靠近沟道区域的一侧，第二子区的厚度为沟道区域的厚度的k倍，k为0.8至1.5。

Description

薄膜晶体管及其制备方法、显示基板、显示装置 技术领域
本公开实施例涉及但不限于显示技术领域，尤其涉及一种薄膜晶体管及其制备方法、显示基板、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，TFT)进行信号控制的显示装置已成为目前显示领域的主流产品。TFT是目前显示装置中的主要开关元件，TFT的电学特性直接关系到显示装置的显示效果。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开实施例提供了一种薄膜晶体管，包括：基底以及在基底上叠设的遮挡层、缓冲层、有源层、栅绝缘层和导电层；其中，
所述导电层包括：栅电极、源电极和漏电极；
所述有源层包括：沟道区域、位于所述沟道区域两侧的源过渡区域和漏过渡区域、位于所述源过渡区域的远离所述沟道区域一侧的源连接区域、以及位于所述漏过渡区域的远离所述沟道区域一侧的漏连接区域；
所述源连接区域与所述源电极连接，所述漏连接区域与所述漏电极连接；
所述源过渡区域和所述漏过渡区域均包括：依次连接的第一子区、第二子区和第三子区，所述第一子区位于所述第二子区的远离所述沟道区域的一侧，所述第三子区位于所述第二子区的靠近所述沟道区域的一侧，所述第二 子区的厚度为所述沟道区域的厚度的k倍，k为0.8至1.5。
第二方面，本公开实施例还提供了一种显示基板，包括：上述实施例中所述的薄膜晶体管。
第三方面，本公开实施例还提供了一种显示装置，包括：上述实施例中所述的显示基板。
第四方面，本公开实施例还提供了一种薄膜晶体管的制备方法，包括：
在基底上依次形成遮挡层、缓冲层和有源层；
在有源层上依次形成栅绝缘层和导电层，通过两次导体化处理使所述有源层形成沟道区域、位于所述沟道区域两侧的源过渡区域和漏过渡区域、位于所述源过渡区域的远离所述沟道区域一侧的源连接区域、以及位于所述漏过渡区域的远离所述沟道区域一侧的漏连接区域；所述导电层包括：栅电极、源电极和漏电极；所述源连接区域与所述源电极连接，所述漏连接区域与所述漏电极连接；所述源过渡区域和所述漏过渡区域均包括：依次连接的第一子区、第二子区和第三子区，所述第一子区位于所述第二子区的远离所述沟道区域的一侧，所述第三子区位于所述第二子区的靠近所述沟道区域的一侧，所述第一子区的厚度和所述第三子区的厚度均与所述沟道区域的厚度相等，所述第二子区的厚度为所述沟道区域的厚度的k倍，k为0.8至1.5。
本公开的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本公开而了解。本公开的其他优点可通过在说明书以及附图中所描述的方案来实现和获得。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中每个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1A为一些技术中第一次导体化处理后的示意图；
图1B为一些技术中形成导电层图案后的示意图；
图1C为一些技术中第二次导体化处理后的示意图；
图2为本公开示例性实施例中的薄膜晶体管的一种结构示意图；
图3为本公开示例性实施例中的薄膜晶体管的另一种结构示意图；
图4为本公开示例性实施例中的薄膜晶体管的又一种结构示意图；
图5为本公开示例性实施例中形成遮挡层图案后的示意图；
图6为本公开示例性实施例中沉积第二金属氧化物薄膜的示意图；
图7为本公开示例性实施例中的对第一金属氧化物薄膜和第二金属氧化物薄膜第一次刻蚀工艺后的示意图；
图8为本公开示例性实施例中的形成有源层图案后的示意图；
图9为本公开示例性实施例中的形成栅绝缘层图案以及第一次导体化处理后的示意图；
图10为本公开示例性实施例中形成导电层图案后的示意图；
图11为本公开示例性实施例中对栅绝缘层进行第二次刻蚀后的示意图；
图12为本公开示例性实施例中第二次导体化处理以及形成钝化层图案后的示意图；
图13为本公开示例性实施例中第二次导体化处理后的示意图。
具体实施方式
本文描述了多个实施例，但是该描述是示例性的，而不是限制性的，在本文所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在示例性实施方式中进行了讨论，但是所公开的特征的许多其它组合方式是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
在描述具有代表性的实施例时，说明书可能已经将方法或过程呈现为特定的步骤序列。然而，在该方法或过程不依赖于本文步骤的特定顺序的程度 上，该方法或过程不应限于的特定顺序的步骤。如本领域普通技术人员将理解的，其它的步骤顺序是可能的。因此，说明书中阐述的步骤的特定顺序不应被解释为对权利要求的限制。此外，针对该方法或过程的权利要求不应限于按照所写顺序执行它们的步骤，本领域技术人员可以容易地理解，这些顺序可以变化，并且仍然保持在本公开实施例的精神和范围内。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如，沟道的宽长比、各个膜层的厚度和间距等，可以根据实际需要进行调整。例如，在附图中，有时为了明确起见，夸大表示了每个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中每个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
在本公开示例性实施例中，“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本公开示例性实施例中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述每个构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本公开示例性实施例中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本公开示例性实施例中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”例如可以是电极或布线，或者是晶体管等开关元件，或者是电阻器、电感器 或电容器等其它功能元件等。
在本公开示例性实施例中，晶体管是指至少包括栅电极(栅极或控制极)、漏电极(漏电极端子、漏区域或漏极)以及源电极(源电极端子、源区域或源极)这三个端子的元件。晶体管在漏电极与源电极之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本公开示例性实施例中，为了区分晶体管除栅电极(栅极或控制极)之外的两极，直接描述了其中一极为第一极，另一极为第二极，其中，第一极可以为漏电极且第二极可以为源电极，或者，第一极可以为源电极且第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时可以互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本公开示例性实施例中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
在本公开示例性实施例中，“约”是指不严格限定界限，允许工艺和测量误差范围内的数值。
随着显示技术的快速发展，薄膜晶体管技术由非晶硅(a-Si)薄膜晶体管发展到氧化物(Oxide)薄膜晶体管。氧化物薄膜晶体管的有源层采用氧化物有源层(Oxide)，氧化物有源层的载流子迁移率是非晶硅有源层的20至30倍，具有迁移率大、开态电流高、开关特性更优、均匀性更好的特点，可以大大提高薄膜晶体管的特性，提高像素的响应速度，实现更快的刷新率，可以适用于需要快速响应和较大电流的应用。
氧化物薄膜晶体管包括两种类型，分别是底栅型薄膜晶体管和顶栅型薄膜晶体管，其中，底栅型薄膜晶体管的结构特点是：源电极和漏电极分别覆盖在氧化物有源层的两侧，源电极与漏电极之间形成沟道(channel)区域；顶栅型薄膜晶体管的结构特点是：源电极和漏电极分别通过过孔与金属氧化物有源层连接。由于顶栅型薄膜晶体管具有短沟道的特点，开态电流(Ion)得以有效提升，因而可以显著提升显示效果，有效降低功耗。由于顶栅型薄膜晶体管中栅电极与源漏电极之间交叠面积小，产生的寄生电容较小，具有较小的电路延迟和较高的开关速度，因而发生栅极与漏极短路(GDS)等不良的可能性较低。
图1A为一些技术中第一次导体化后的示意图，图1B为一些技术中形成导电层图案后的示意图，图1C为一些技术中第二次导体化后的示意图。其中，图1A至图1C中以氧化物有源层采用IGZO为例，在图1A和图1B中，氧化物有源层中的第一区域101为未被导体化的IGZO，氧化物有源层中的第二区域102为导体化的IGZO(通过第一次导体化处理形成)；在图1C中，氧化物有源层中的第一区域101为导体化的IGZO(通过第二次导体化处理形成)，氧化物有源层中的空白区域103为被损伤的IGZO，氧化物有源层中的第一子区为导体化的IGZO(通过两次导体化处理形成)，氧化物有源层中的第二子区为导体化的IGZO(通过第一次导体化处理形成)。此外，图1C中是以箭头表示电流流向为例进行示意的。
如图1A至图1C所示，在一些采用5Mask工艺制备的显示产品中，，由于制备TFT的过程中通常采用一道Mask对栅绝缘层(GI)与缓冲层(Buffer)进行刻蚀(Etch)工艺，使得GI整体刻蚀时间较长，而且在栅电极(Gate)61与氧化物有源层(如，IGZO)的搭接区域，氧化物有源层会进行两次干刻工艺和两次导体化处理。因此，如图1C所示，容易导致金属氧化物有源层会出现部分缺失。
此外，如图1C所示，在GI整面刻蚀过程中，由于存在光刻(Photoresist，PR)胶保护，使得栅电极(Gate)边缘区域仅可以保留约0.7微米的导体化的IGZO，而电流主要通过该部分IGZO流出。因此，由于氧化物有源层出现部分缺失可以导致导通通道很短，使得电流流过能力限制明显，从而，导 致薄膜晶体管的电流输出效率降低，薄膜晶体管的电学特性变差。进而，当该薄膜晶体管应用到显示产品时，会影响显示品质。
本公开实施例提供一种薄膜晶体管。该薄膜晶体管可以包括：基底以及在基底上叠设的遮挡层、缓冲层、有源层、栅绝缘层和导电层；其中，
导电层可以包括：栅电极、源电极和漏电极；
有源层可以包括：沟道区域、位于沟道区域两侧的源过渡区域和漏过渡区域、位于源过渡区域的远离沟道区域一侧的源连接区域、以及位于漏过渡区域的远离沟道区域一侧的漏连接区域；
源连接区域与源电极连接，漏连接区域与漏电极连接；
源过渡区域和漏过渡区域均可以包括：依次连接的第一子区、第二子区和第三子区，第一子区位于第二子区的远离沟道区域的一侧，第三子区位于第二子区的靠近沟道区域的一侧，第二子区的厚度可以为沟道区域的厚度的k倍，k可以为0.8至1.5。
例如，k可以包括但不限于为0.8、0.85、0.9、0.95、1、1.5、1.2、1.25、1.3、1.35、1.4、1.45或者1.5等。这里，本公开实施例对此不作限定。
其中，膜层的厚度可以是指膜层在垂直于薄膜晶体管的平面的方向上的尺寸特征。例如，有源层的沟道区域的厚度可以是指有源层的沟道区域在垂直于薄膜晶体管的平面的方向上的尺寸特征，有源层的源过渡区域中的第二子区的厚度可以是指有源层的源过渡区域中的第二子区在垂直于薄膜晶体管的平面的方向上的尺寸特征，有源层的漏过渡区域中的第二子区的厚度可以是指有源层的漏过渡区域中的第二子区在垂直于薄膜晶体管的平面的方向上的尺寸特征。
图2为本公开示例性实施例中的薄膜晶体管的一种结构示意图，图3为本公开示例性实施例中的薄膜晶体管的另一种结构示意图，图4为本公开示例性实施例中的薄膜晶体管的又一种结构示意图。其中，图2至图4中均是以第二子区的厚度大于沟道区域的厚度为例进行示意的。
在一种示例性实施例中，如图2至图4所示，本公开示例性实施例提供的薄膜晶体管可以包括：基底10、设置在基底10上的遮挡(Shield，SHL) 层20、设置在遮挡层20的远离基底10一侧的缓冲(Buffer)层30、设置缓冲层30的远离基底10一侧的有源(Active，ACT)层40，设置在有源层40的远离基底10一侧的栅绝缘(GI)层50、设置在栅绝缘层50的远离基底10一侧的导电层、以及设置在导电层的远离基底10一侧的钝化层70。其中，导电层可以包括：栅电极61、源电极62和漏电极63。有源层40可以包括：沟道区域41、位于沟道区域41两侧的源过渡区域42和漏过渡区域44、位于源过渡区域42的远离沟道区域41一侧的源连接区域43、以及位于漏过渡区域44的远离沟道区域41一侧的漏连接区域45；源连接区域43与源电极62连接，漏连接区域45与漏电极63连接；源过渡区域42和漏过渡区域44均可以包括：依次连接的第一子区1、第二子区2和第三子区3，第一子区1位于第二子区2的远离沟道区域41的一侧，第三子区3位于第二子区2的靠近沟道区域41的一侧，第二子区2的厚度可以为沟道区域41的厚度的k倍，k可以约为0.8至1.5。如此，由于薄膜晶体管中有源层40中的源过渡区域42和漏过渡区域44中的第二子区2的厚度为沟道区域41的厚度的k倍，且k可以约为0.8至1.5，避免了第二子区2发生缺失，从而，可以提高源过渡区域42和漏过渡区域44的导电能力，进而，可以提升薄膜晶体管的电流输出能力。
这里，在制备薄膜晶体管的过程中，有源层中的源过渡区域42和漏过渡区域44中的第二子区2为有源层中受到双次刻蚀和双次导体化的区域。
在一种示例性实施例中，k可以设置为1至1.5，例如，k可以约为1、1.5、1.2、1.25、1.3、1.35、1.4、1.45或者1.5等。如此，可以更为有效地防止由于两次导体化导致的薄膜晶体管不良。
在一种示例性实施例中，如图2和图3所示，第一子区1的厚度和第三子区3的厚度均可以与沟道区域41的厚度相等。
在一种示例性实施例中，第一子区1的厚度可以约为20nm至200nm，第二子区2的厚度可以为16nm至300nm，第三子区3的厚度可以约为20nm至200nm，沟道区域41的厚度可以约为20nm至200nm。这里，本公开实施例对此不作限定。
在一种示例性实施例中，栅电极61、源电极62和漏电极63同材料同层 设置。如此，可以减少图案化工艺次数，缩短工艺时间，降低工艺成本。这里，“同层设置”可以是指两种(或两种以上)结构通过同一次图案化工艺得以图案化而形成的结构，它们的材料可以相同或不同。例如，形成同层设置的多种结构的前驱体的材料是相同的，最终形成的材料可以相同或不同。
在一种示例性实施例中，第二子区2的导电率大于第一子区1的导电率，且第二子区2的导电率大于第三子区3的导电率。如此，有利于提高薄膜晶体管的电学特性。
在一种示例性实施例中，第二子区2的氧元素含量小于第一子区1的氧元素含量，且第二子区2的氧元素含量小于第三子区3的氧元素含量。如此，有利于提高薄膜晶体管的电学特性。
在一种示例性实施例中，第二子区2的导电率大于源连接区域43的导电率，且第二子区2的导电率大于漏连接区域45的导电率。
在一种示例性实施例中，第二子区2的氧元素含量小于源连接区域43的导电率，且第二子区2的氧元素含量小于漏连接区域45的氧元素含量。
在一种示例性实施例中，如图2所示，以第二子区2的厚度大于沟道区域41的厚度(例如，k可以约为1至1.5)为例，第一子区1的材料和第三子区3的材料均可以为第一导体材料，第一导体材料为对第一金属氧化物膜进行一次导体化处理得到，第二子区2的材料可以为第二导体材料，第二导体材料包括：叠设的第一子导体材料和第二子导体材料，第一子导体材料为对第一金属氧化物膜进行两次导体化处理得到，第二子导体材料为对第二金属氧化物膜进行两次导体化处理得到，第二金属氧化物膜设置于第一金属氧化物膜的远离基底10的一侧，第二金属氧化物膜的氧元素硬度小于第一金属氧化物膜的硬度。如此，可以加强信号传输能力，提高薄膜晶体管的电流输出能力，提升薄膜晶体管的电学性能。
在一种示例性实施例中，当第二子区2的厚度小于或等于沟道区域41的厚度(例如，k可以约为0.8至1)为例，第一子区1的材料和第三子区3的材料均可以为第一导体材料，所述第一导体材料为对第一金属氧化物膜进行一次导体化处理得到，第二子区2的材料可以为第三导体材料，第三导体材料为对第一金属氧化物膜进行两次导体化处理得到。如此，可以加强信号 传输能力，提高薄膜晶体管的电流输出能力，提升薄膜晶体管的电学性能。
在一种示例性实施例中，第二子区中的第二金属氧化物层的厚度小于第二子区中的第一金属氧化物层的厚度。例如，第二子区中的第二子导体材料的厚度小于第一子导体材料的厚度。
在一种示例性实施例中，第一金属氧化物膜和第二金属氧化物膜可以包括但不限于采用：包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物、包含铟和镓和锌的氧化物等金属氧化物。例如，第一金属氧化物膜和第二金属氧化物膜均可以采用铟镓锌氧化物(IGZO)形成。例如，第一金属氧化物膜和第二金属氧化物膜均可以采用铟锡锌氧化物(ITZO)形成。这里，本公开实施例对此不做限定。
在一种示例性实施例中，第二子区的宽度可以小于第一子区的宽度；或者，第二子区的宽度可以小于第三子区的宽度。
在一种示例性实施例中，如图4所示，源电极62至少部分覆盖源过渡区域42的第二子区2；或者，漏电极63至少部分覆盖漏过渡区域44的第二子区2。如此，可以避免由于工艺误差导致第一子区1出现过刻现象。
在一种示例性实施例中，如图4所示，源过渡区域42的第二子区2可以包括：被源电极62覆盖的第一部分(图中未标示)和未被源电极62覆盖的第二部分(图中未标示)，第一部分的宽度小于第二部分的宽度；或者，漏过渡区域44的第二子区2包括：被漏电极63覆盖的第三部分和未被漏电极63覆盖的第四部分，第三部分的宽度小于第四部分的宽度。
在一种示例性实施例中，如图4所示，有源层40还可以包括：位于源连接区域43的远离沟道区域41一侧的第一区域46以及位于漏连接区域45的远离沟道区域41一侧的第二区域47；其中，源过渡区域52的第二子区2的宽度小于第一区域46的宽度，或者，漏过渡区域44的第二子区2的宽度小于第二区域46的宽度。
这里，宽度可以是指沿着第一方向D1上的尺寸特征，第一方向D1与第二方向D2交叉，例如，第一方向D1与第二方向D2垂直，第二方向D2可以是指垂直于薄膜晶体管平面的方向或者薄膜晶体管的厚度方向。
在一种示例性实施例中，如图2和图4所示，源电极62搭设在有源层40的源过渡区域42的第一子区1，且通过第一过孔K1与有源层40的源连接区域43连接；以及，漏电极63搭设在有源层40的漏过渡区域44的第一子区1，且通过第二过孔K2与有源层40的漏连接区域45连接。如此，有利于提高薄膜晶体管的电学特性。
在一种示例性实施例中，如图2和图3所示，有源层40在基底10上的正投影的边界位于遮挡层20在基底10上的正投影的边界范围内。
在一种示例性实施例中，如图2和图3所示，遮挡层20可以包括：间隔设置的第一遮挡层201和第二遮挡层202，有源层40在基底10上的正投影的边界位于第一遮挡层201在基底上的正投影的边界范围内，源电极62通过第三过孔K3与第二遮挡层202连接。例如，第二遮挡层202可以被配置为进行栅极信号的传输，如此，可以形成双栅结构的薄膜晶体管，即薄膜晶体管可以包括同沟道的下晶体管和上晶体管。由于下晶体管的栅极(第二遮挡层202)的信号电压值小于上晶体管的栅极(栅电极61)的信号电压值，因而，下晶体管的阈值电压负偏程度小于上晶体管的的阈值电压负偏程度，降低了薄膜晶体管整体的负偏程度，可以保证薄膜晶体管的稳定性，保证晶体管电学特性的均一性。例如，第一遮挡层201可以被配置为对薄膜晶体管进行遮光处理，如此，可以降低照射到薄膜晶体管上的光强度，降低漏电流，从而，可以减少光照对薄膜晶体管特性的影响。
在一种示例性实施例中，遮挡层可以采用银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)等金属材料中的任意一种或更多种，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。这里，本公开实施例对此不做限定。
在一种示例性实施例中，针对有源层40的源过渡区域42和漏过渡区域44，第二子区2通过第一次导体化处理和第二次导体化处理形成，第一子区1通过第一次导体化处理形成，第三子区3通过第二次导体化处理形成，沟道区域41在自对准的第二次导体化处理过程中形成。如此，由于第二子区2是经过两次导体化处理形成的，因此，可以提高第二子区2的导电能力，有利于提高像素驱动电路的电学特性。而且，由于沟道区域是在自对准的第二次导体化处理过程中形成的，因此，可以提升栅电极与下方沟道区域之间的 对位精度，可以提升薄膜晶体管的电学特性。
在一种示例性实施例中，本公开示例性实施例中的薄膜晶体管可以应用于具有像素驱动电路的显示基板中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等显示基板。这里，本公开实施例对此不做限定。
下面通过薄膜晶体管的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于薄膜晶体管方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在一种示例性实施例中，以图2所示薄膜晶体管的结构为例，如图5至图12所示，薄膜晶体管的制备过程可以包括如下操作：
(1)形成遮挡层图案。
在一种示例性实施例中，形成遮挡层图案可以包括：在基底10上依次沉积第一金属薄膜，通过图案化工艺对第一金属薄膜进行构图，在基底10上形成遮挡层20图案。
在一种示例性实施例中，如图5所示，以遮挡层20可以包括：第一遮挡层201和第二遮挡层202为例，通过半色调的图案化工艺对第一金属薄膜进 行构图，可以包括：先在第一金属薄膜上涂覆一层光刻胶，采用掩膜板(Mask)对光刻胶进行曝光，显影后形成光刻胶图案，光刻胶图案可以包括未曝光区域和完全曝光区域，未曝光区域包括第一遮挡层201和第二遮挡层202图案所在位置，未曝光区域的光刻胶具有第一厚度，完全曝光区域的光刻胶被完全去除，在基底上10形成遮挡层20图案。
在一种示例性实施例中，第一金属薄膜的厚度可以约为100nm(纳米)至1000nm。这里，本公开实施例对此不作限定。
(2)形成有源层图案。
在一种示例性实施例中，如图6至图8所示，形成有源层图案可以包括：在形成前述图案的基底10上，依次沉积第一绝缘薄膜、第一金属氧化物薄膜81和第二金属氧化物薄膜82，通过半色调的图案化工艺对第一金属氧化物薄膜81和第二金属氧化物薄膜82进行构图，形成覆盖遮挡层20图案的缓冲(Buffer)层30，以及形成在缓冲(Buffer)层30上的有源层40图案。
在一种示例性实施例中，如图6至图8所示，通过半色调的图案化工艺对第一金属氧化物薄膜81和第二金属氧化物薄膜82进行构图，可以包括：先在第二金属氧化物薄膜82涂覆一层光刻胶，采用半色调掩膜板(Halftone Mask)对光刻胶进行曝光，显影后形成光刻胶图案，光刻胶图案包括未曝光区域、部分曝光区域和完全曝光区域，未曝光区域包括有源层40中沟道区域41、源过渡区域42、漏过渡区域44、源连接区域43以及漏连接区域45所在位置，未曝光区域的光刻胶具有第一厚度。部分曝光区域包括源过渡区域42中第二子区2和漏过渡区域44中第二子区2所在位置，部分曝光区域的光刻胶具有第二厚度，第二厚度小于第一厚度。其它区域为完全曝光区域，完全曝光区域的光刻胶被完全去除，暴露出第二金属氧化物薄膜82的表面。随后，采用第一次刻蚀工艺去除完全曝光区域的第一金属氧化物薄膜81和第二金属氧化物薄膜82。随后，采用灰化工艺去除部分曝光区域的光刻胶，使部分曝光区域暴露出第二金属氧化物薄膜82的表面。随后，采用第二次刻蚀工艺去除部分曝光区域的第二金属氧化物薄膜82，暴露出部分曝光区域的第一金属氧化物薄膜81。最后，剥离剩余的光刻胶，在基底上形成有源层40图案。如此，可以在有源层40中沟道区域41、源过渡区域42中第一子区1和第三 子区3、漏过渡区域44中第一子区1和第三子区3、源连接区域43以及漏连接区域45所在位置形成一层金属氧化物膜，而在源过渡区域42中第二子区2和漏过渡区域44中第二子区2所在位置形成双层金属氧化物膜。这样，由于源过渡区域42中第二子区2和漏过渡区域44中第二子区2所在位置存在较厚的金属氧化物膜，可以增加源过渡区域42中第二子区2和漏过渡区域44中第二子区2所在位置的耐刻蚀能力，从而，可以在后续工艺中避免源过渡区域42中第二子区2和漏过渡区域44中第二子区2中的金属氧化物膜被刻蚀穿，从而，可以提高导电能力。
在一种示例性实施例中，第二金属氧化物膜82的沉积工艺与第一金属氧化物膜81的沉积工艺不同。例如，第二金属氧化物膜82的氧元素含量大于第一金属氧化物膜81的氧元素含量，且第二金属氧化物膜82的功率小于第一金属氧化物膜81的功率。如此，可以使得第二金属氧化物薄膜82与第一金属氧化物薄膜81存在明显膜质差，相对来说，第一金属氧化物薄膜81的硬度大于第二金属氧化物膜82的硬度，从而，一方面，进行适当时间的第二次刻蚀工艺，可以将第一金属氧化物薄膜81上方的第二金属氧化物薄膜82刻蚀掉，另一方面，可以增加第一金属氧化物薄膜81的耐刻蚀度，避免第一金属氧化物薄膜81出现部分缺失。这里，功率是指沉积金属氧化物膜时，沉积工艺所采用的溅射功率。
在一种示例性实施例中，第二金属氧化物膜的氧元素含量可以约为30％至50％，第一金属氧化物膜的氧元素含量可以约为20％至30％。这里，本公开实施例对此不作限定。
在一种示例性实施例中，第二金属氧化物膜的功率可以约为4kw(千瓦)至6kw，第一金属氧化物膜的功率可以约为8kw至14kw。这里，本公开实施例对此不作限定。
在一种示例性实施例中，第一金属氧化物膜和第二金属氧化物膜可以包括但不限于采用：包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物、包含铟和镓和锌的氧化物等金属氧化物。例如，第一金属氧化物膜和第二金属氧化物膜均可以采用铟镓锌氧化 物(IGZO)形成。例如，第一金属氧化物膜和第二金属氧化物膜均可以采用铟锡锌氧化物(ITZO)形成。这里，本公开实施例对此不做限定。
在一种示例性实施例中，形成有源层图案后，第一金属氧化物薄膜的厚度和第二金属氧化物薄膜的厚度可以约为20nm至200nm。这里，本公开实施例对此不作限定。
在一种示例性实施例中，第一绝缘薄膜的厚度可以约为200nm至1000nm。这里，本公开实施例对此不作限定。
(3)形成栅绝缘(GI)层图案。
在一种示例性实施例中，如图9所示，形成栅绝缘(GI)层50图案可以包括：在形成前述图案的基底10上，依次沉积第二绝缘薄膜，通过半色调的图案化工艺对第二绝缘薄膜进行构图，形成栅绝缘(GI)层50图案以及开设在栅绝缘(GI)层50上的多个过孔图案，多个过孔图案至少包括第一过孔K1、第二过孔K2、第三过孔K3、第四过孔K4和第五过孔K5。
在一种示例性实施例中，如图9所示，通过半色调的图案化工艺对第二绝缘薄膜进行构图可以包括：先在第二绝缘薄膜上涂覆一层光刻胶，采用半色调掩膜板对光刻胶进行曝光，显影后形成光刻胶图案，光刻胶图案包括未曝光区域、部分曝光区域和完全曝光区域，完全曝光区域包括第三过孔K3图案所在位置，部分曝光区域包括第一过孔K1、第二过孔K2、第四过孔K4和第五过孔K5图案所在位置，其它区域为未曝光区域，未曝光区域的光刻胶具有第一厚度，部分曝光区域的光刻胶具有第二厚度，第二厚度小于第一厚度。随后，采用第一次刻蚀工艺去除完全曝光区域的第二绝缘薄膜和第一绝缘层，形成第三过孔K3图案，使得第三过孔K3暴露出第二遮挡层202，以便后续形成的源电极62可以通过第三过孔K3与第二遮挡层202连接。随后，采用灰化工艺去除部分曝光区域的光刻胶，使部分曝光区域暴露出第二绝缘薄膜。随后，采用第二次刻蚀工艺去除部分曝光区域的第二绝缘薄膜，形成第一过孔K1、第二过孔K2、第四过孔K4和第五过孔K5图案，使得第一过孔K1、第二过孔K2、第四过孔K4和第五过孔K5暴露出有源层40，以便后续进行第二次导体化处理。最后，剥离剩余的光刻胶，形成栅绝缘(GI)层50图案以及开设在栅绝缘(GI)层50上的多个过孔图案。
在一种示例性实施例中，多个过孔图案至少包括第一过孔K1、第二过孔K2、第三过孔K3、第四过孔K4和第五过孔K5。第一过孔K1位于有源层40中的源连接区域43所在位置，暴露出有源层40中的源连接区域43的表面，第一过孔K1被配置为使后续形成的薄膜晶体管的源电极62与源连接区域43连接。第二过孔K2位于有源层40中的漏连接区域45所在位置，暴露出有源层40中的漏连接区域45的表面，第二过孔K2被配置为使后续形成的薄膜晶体管的漏电极63与漏连接区域45连接。第三过孔K3位于遮挡层20中的第二遮挡层202所在位置，暴露出遮挡层20中的第二遮挡层202的表面，第三过孔K3被配置为使后续形成的薄膜晶体管的源电极62与遮挡层20中的第二遮挡层202连接。第四过孔K4位于有源层40中的源过渡区域42中第一子区1和第二子区2所在位置，暴露出有源层40中的源过渡区域42中第一子区1和第二子区2的表面，以便后续进行导体化处理。第五过孔K5位于有源层40中的漏过渡区域44中第一子区1和第二子区2所在位置，暴露出有源层40中的漏过渡区域44中第一子区1和第二子区2的表面，以便后续进行导体化处理。
在一种示例性实施例中，位于有源层40所在位置的栅绝缘(GI)层50覆盖有源层40的部分区域。
在一种示例性实施例中，第二绝缘薄膜的厚度可以约为100nm至500nm。这里，本公开实施例对此不作限定。
(4)第一次导体化处理。
在一种示例性实施例中，如图9所示，在形成开设在栅绝缘(GI)层50上的多个过孔图案之后，进行第一次导体化处理。第一次导体化处理可以包括：在形成前述图案的基底上，对有源层40中未被栅绝缘(GI)层50覆盖的部分区域进行第一次导体化处理，即：对源过渡区域42的第一子区1、漏过渡区域44的第一子区1、源连接区域43和漏连接区域45所在位置的有源层进行第一次导体化处理，形成有源层的源过渡区域42的第一子区1、漏过渡区域44的第一子区1、源连接区域43和漏连接区域45；以及对有源层的源过渡区域42的第二子区2、漏过渡区域44的第二子区2进行导体化处理，形成一次导体化后的第二子区2。
(5)形成导电层图案。
在一种示例性实施例中，如图10所示，形成导电层图案可以包括：在形成有前述图案的基底上，沉积第二金属薄膜。在第二金属薄膜上涂覆一层光刻胶，通过掩膜、曝光和显影形成光刻胶图案，利用第一次刻蚀工艺刻蚀第二金属薄膜，形成导电层图案，保留导电层上的光刻胶。导电层图案至少可以包括栅电极61、源电极62和漏电极63图案。
在一种示例性实施例中，如图10所示，源电极62通过第一过孔K1与有源层40经过导体化处理的源连接区域43连接，源电极62的第一端搭设在有源层40经过导体化处理的源过渡区域42的第一子区1上，源电极62的第二端通过第三过孔K3与第二遮挡层202连接。
在一种示例性实施例中，如图10所示，漏电极63通过第二过孔K2与有源层40经过导体化处理的漏连接区域45连接，源电极62的第一端搭设在有源层40经过导体化处理的漏过渡区域44的第一子区1上。
在一种示例性实施例中，第二金属薄膜的厚度可以约为100nm至1000nm。这里，本公开实施例对此不作限定。
(6)第二次刻蚀处理。
在一种示例性实施例中，如图11所示，第二次刻蚀处理可以包括：以导电层图案和保留导电层上的光刻胶为掩膜，通过第二次刻蚀工艺自对准向下刻蚀栅绝缘(GI)层50，去除有源层的源过渡区域42的第三子区3和漏过渡区域44的第三子区3覆盖的栅绝缘(GI)层50。
在一种示例性实施例中，如图11所示，栅电极61在基底10上正投影的边界位于栅绝缘(GI)层50在基底上正投影的边界范围内，有源层的沟道区域41在基底10上正投影的边界位于栅绝缘(GI)层50在基底上正投影的边界范围内。
(7)第二次导体化处理。
在一种示例性实施例中，如图11和图12所示，第二次导体化处理可以包括：以栅绝缘(GI)层50、设置在栅绝缘(GI)层50上的导电层图案(如导电层图案至少可以包括栅电极61、源电极62和漏电极63图案)、以及保 留在导电层上的光刻胶为掩膜，对有源层40中未被栅绝缘(GI)层50覆盖的另一部分区域进行导体化处理，即：对未导体化的有源层40的沟道区域41、未导体化的有源层40的源过渡区域42的第三子区3和未导体化的漏过渡区域44的第三子区3所在位置进行导体化处理，形成有源层40的沟道区域41、有源层40的源过渡区域42的第三子区3和漏过渡区域44的第三子区3；以及对一次导体化后的源过渡区域42的第二子区2和一次导体化后的漏过渡区域44的第二子区2所在位置均进行导体化处理，形成二次导体化后的源过渡区域42的第二子区2和二次导体化后的漏过渡区域44的第二子区2。剥离剩余的光刻胶。
这里，由于第二次导体化处理是利用栅绝缘(GI)层50、导电层图案以及保留在导电层上的光刻胶作为掩膜，是一种自对准导体化处理工艺，因而最终形成的沟道宽度与栅电极61的宽度基本上相同。如此，可以提升栅电极61与下方沟道区域之间的对位精度，极大地提升薄膜晶体管的电学特性。
在一种示例性实施例中，有源层经过两次导体化处理，使得有源层形成五个区域：沟道区域41、位于沟道区域41两侧的源过渡区域42和漏过渡区域44、位于源过渡区域42的远离沟道区域41一侧的源连接区域43、以及位于漏过渡区域44的远离沟道区域41一侧的漏连接区域45。其中，沟道区域41在基底上正投影的边界与栅电极61在基底上正投影的边界基本上重叠。
在一种示例性实施例中，由于采用两次导体化处理和两次刻蚀处理，第一次导体化处理的区域与第二次导体化处理的区域有重叠区域，即第二子区2所在位置。由于有源层40中源过渡区域42中第二子区2和漏过渡区域44中第二子区2所在位置存在较厚的金属氧化物膜，可以增加源过渡区域42中第二子区2和漏过渡区域44中第二子区2所在位置的耐刻蚀能力，从而，可以避免源过渡区域42中第二子区2和漏过渡区域44中第二子区2中的金属氧化物膜被刻蚀穿，从而，可以提高导电能力。
在一种示例性实施例中，由于有源层40中源过渡区域42中第二子区2和漏过渡区域44中第二子区2经过两次导体化处理，经过两次导体化处理的有源层40中源过渡区域42中第二子区2和漏过渡区域44中第二子区2的电阻更低，导电能力更强，第二子区2的导电率大于第一子区1的导电率，且 第二子区2的导电率大于第三子区3的导电率。如此，有利于提高薄膜晶体管的电学特性。
在一种示例性实施例中，由于有源层40中源过渡区域42中第二子区2和漏过渡区域44中第二子区2经过两次导体化处理，使得经过两次导体化处理的有源层40中源过渡区域42中第二子区2和漏过渡区域44中第二子区2受到两次氦(He)等离子处理，导致膜层内氧元素含量进一步降低，因而，第二子区2的氧元素含量小于第一子区1的氧元素含量，且第二子区2的氧元素含量小于第三子区3的氧元素含量。如此，有利于提高薄膜晶体管的电学特性。
在一种示例性实施例中，由于有源层40中源过渡区域42中第二子区2和漏过渡区域44中第二子区2经过两次导体化处理，而有源层40中源连接区域43和漏连接区域45只经过第一次导体化处理，因而，第二子区2的导电率大于源连接区域43的导电率，且第二子区2的导电率大于漏连接区域45的导电率。第二子区2的氧元素含量小于源连接区域43的氧元素含量，且第二子区2的氧元素含量小于漏连接区域45的氧元素含量。
在一种示例性实施例中，两次导体化处理过程中，对栅绝缘(GI)层50进行了两次刻蚀处理，刻蚀过程的过刻会刻蚀掉有源层40中源过渡区域42中第二子区2和漏过渡区域44中第二子区2的部分厚度，因此，相较于步骤2形成有源层图案，步骤7之后，第二子区2中的第二金属氧化物层81的厚度会变薄，甚至会完全缺失。所以，步骤7之后，当第二子区2中的第二金属氧化物层81仅变薄时，例如，第二子区2中的第二金属氧化物层81的厚度小于第二子区2中的第一金属氧化物层82的厚度，第二子区2的材料可以为第二导体材料，第二导体材料包括：叠设的第一子导体材料和第二子导体材料，第一子导体材料为对第一金属氧化物膜进行两次导体化处理得到，第二子导体材料为对第二金属氧化物膜进行两次导体化处理得到，使得第二子区2的厚度大于沟道区域41的厚度(例如，k可以约为1至1.5)；而步骤7之后，当第二子区2中的第二金属氧化物层81发生完全缺失时，第二子区2的材料可以为第三导体材料，第三导体材料为对第一金属氧化物膜进行两次导体化处理得到，使得第二子区2的厚度小于或等于沟道区域41的厚度(例 如，k可以约为0.8至1)。如此，由于在形成有源层图案时，通过步骤2在第二子区2中形成了两层不同的金属氧化物膜，使得第二子区2的厚度较厚，那么，在经过双次刻蚀工艺和双次导体化处理后，在最终形成的薄膜晶体管中可以避免第二子区发生缺失，从而，可以加强信号传输能力，提高薄膜晶体管的电流输出能力，提升薄膜晶体管的电学性能。
在一种示例性实施例中，由于步骤2使得有源层40中源过渡区域42中第二子区2和漏过渡区域44中第二子区2所在位置存在较厚的金属氧化物膜，因此，最终形成的有源层40中的源过渡区域42和漏过渡区域44中的第二子区2的厚度可以为沟道区域41的厚度的k倍，且k可以约为0.8至1.5。如此，如图13所示，避免了第二子区2发生缺失，从而，可以提高源过渡区域42和漏过渡区域44的导电能力，进而，可以提升薄膜晶体管的电流输出能力。
(8)形成钝化(Passivation，Pas)层图案。
在一种示例性实施例中，如图12所示，形成钝化层图案可以包括：在形成有前述图案的基底上，沉积第三绝缘薄膜，形成覆盖前述结构的钝化层70图案。
在一种示例性实施例中，第三绝缘薄膜的厚度可以约为200nm至1000nm。这里，本公开实施例对此不做限定。
在一种示例性实施例中，遮挡层和导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。这里，本公开实施例对此不做限定。
在一种示例性实施例中，缓冲层、栅绝缘层和钝化层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。这里，本公开实施例对此不做限定。
在一种示例性实施例中，基底可以是柔性基底，或者可以是刚性基底。例如，刚性基底可以包括但不限于玻璃或者石英等材料。例如，柔性基底可以包括但不限于采用聚酰亚胺(PI)或者聚对苯二甲酸乙二酯(PET)等材 料，柔性基底可以是单层结构，或者可以是无机材料层和柔性材料层构成的叠层结构。这里，本公开实施例对此不做限定。
本公开示例性实施例还提供了一种薄膜晶体管的制备方法。该薄膜晶体管为上述一个或多个示例性实施例中的薄膜晶体管。
在一种示例性实施例中，该薄膜晶体管的制备方法可以包括：
步骤S1：在基底上依次形成遮挡层、缓冲层和有源层；
步骤S2：在有源层上依次形成栅绝缘层和导电层，通过两次导体化处理使有源层形成沟道区域、位于沟道区域两侧的源过渡区域和漏过渡区域、位于源过渡区域的远离沟道区域一侧的源连接区域、以及位于漏过渡区域的远离沟道区域一侧的漏连接区域；导电层可以包括：栅电极、源电极和漏电极；源连接区域与源电极连接，漏连接区域与漏电极连接；源过渡区域和漏过渡区域均可以包括：依次连接的第一子区、第二子区和第三子区，第一子区位于第二子区的远离沟道区域的一侧，第三子区位于第二子区的靠近沟道区域的一侧，第一子区的厚度和第三子区的厚度均与沟道区域的厚度相等，第二子区的厚度为沟道区域的厚度的k倍，k可以约为0.8至1.5。
在一种示例性实施例中，步骤S1可以包括：
步骤S11：在基底上依次形成遮挡层和缓冲层；
步骤S12：在缓冲层上形成两层金属氧化物膜，对两层金属氧化物膜进行图案化处理，形成有源层，两层金属氧化物膜可以包括：叠设的第一金属氧化物膜和第二金属氧化物膜，第二金属氧化物膜的氧元素含量大于第一金属氧化物膜的氧元素含量，且第二金属氧化物膜的功率小于第一金属氧化物膜的功率。
在一种示例性实施例中，步骤S2可以包括：
步骤S21：在有源层上形成栅绝缘层；
步骤S22：对未被栅绝缘层覆盖的有源层进行第一次导体化处理，形成有源层的源过渡区域的第一子区、漏过渡区域的第一子区、源连接区域和漏连接区域；
步骤S23：在栅绝缘层上形成导电层；
步骤S24：使用自对准刻蚀方式，去除源过渡区域的栅绝缘层和漏过渡区域的栅绝缘层，以暴露出未导体化的漏过渡区域的第三子区和未导体化的源过渡区域的第三子区；
步骤S25：对未被栅绝缘层覆盖的有源层进行第二次导体化处理，形成有源层的沟道区域、源过渡区域的第二子区和第三子区、以及漏过渡区域的第二子区和第三子区。
有关薄膜晶体管的制备过程，已在之前的薄膜晶体管实施例中详细说明，对于本公开薄膜晶体管的制备方法实施例中未披露的技术细节，本领域的技术人员请参照本公开薄膜晶体管实施例中的描述而理解，这里不再赘述。
本公开实施例提供一种显示基板，该显示基板可以包括：上述一个或多个实施例中的薄膜晶体管。
在一种示例性实施例中，在垂直于显示基板的平面上，显示基板可以包括：设置在基底上的驱动电路层、设置在驱动电路层远离基底一侧的发光结构层以及设置在发光结构层远离基底一侧的封装结构层。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等。这里，本公开实施例对此不做限定。
在一种示例性实施例中，每个子像素的驱动电路层可以包括：构成像素驱动电路的多个晶体管和存储电容，多个晶体管中的至少一个可以为上述一个或多个实施例中的薄膜晶体管。例如，像素驱动电路可以采用3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构等。这里，本公开实施例对此不做限定。
在一种示例性实施例中，发光结构层可以包括：阳极、像素定义层、有机发光层和阴极，阳极通过过孔与驱动晶体管的漏电极连接，有机发光层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用 有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。这里，本公开实施例对此不做限定。
在一种示例性实施例中，有机发光层可以包括：发光层(EML)以及如下任意一层或多层：空穴注入层HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在一种示例性实施例中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一层或多层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的。这里，本公开实施例对此不做限定。
在一种示例性实施例中，本公开示例性实施例中的显示基板可以包括但不限于为OLED显示基板、QLED显示基板、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管(QDLED)显示基板等。这里，本公开实施例对此不做限定。
此外，本公开实施例中的显示基板除了可以包括上述所列出的结构以外，还可以包括其它必要的组成和结构，例如，栅线、数据线、像素电极或者公共电极等部件。本领域技术人员可根据该显示基板的种类进行相应地设计和补充，在此不再赘述。
以上显示基板实施例的描述，与上述薄膜晶体管实施例的描述是类似的，具有同薄膜晶体管实施例相似的有益效果。对于本公开显示基板实施例中未披露的技术细节，本领域的技术人员请参照本公开薄膜晶体管实施例中的描述而理解，这里不再赘述。
本公开实施例还提供一种显示装置，该显示装置可以包括：上述一个或多个实施例中的显示基板。
在一种示例性实施例中，该显示装置可以包括但不限于为OLED显示装置、QLED显示装置、发光二极管(Micro LED或Mini LED)显示装置或量子点发光二极管(QDLED)显示装置等具有像素驱动电路的显示装置。例如，以显示装置采用OLED显示装置为例，显示装置可以为48英寸(inch)的电视机(TV)。这里，本公开实施例对此不做限定。
在一种示例性实施例中，该显示装置可以包括但不限于为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或者导航仪等任何具有显示功能的产品或部件。这里，本公开实施例对显示装置的类型不做限定。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
以上显示装置实施例的描述，与上述薄膜晶体管、显示基板实施例的描述是类似的，具有同薄膜晶体管、显示基板实施例相似的有益效果。对于本公开显示装置实施例中未披露的技术细节，本领域的技术人员请参照本公开薄膜晶体管、显示基板实施例中的描述而理解，这里不再赘述。
虽然本公开所揭露的实施方式如上，但上述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种薄膜晶体管，包括：基底以及在基底上叠设的遮挡层、缓冲层、有源层、栅绝缘层和导电层；其中，
    所述导电层包括：栅电极、源电极和漏电极；
    所述有源层包括：沟道区域、位于所述沟道区域两侧的源过渡区域和漏过渡区域、位于所述源过渡区域的远离所述沟道区域一侧的源连接区域、以及位于所述漏过渡区域的远离所述沟道区域一侧的漏连接区域；
    所述源连接区域与所述源电极连接，所述漏连接区域与所述漏电极连接；
    所述源过渡区域和所述漏过渡区域均包括：依次连接的第一子区、第二子区和第三子区，所述第一子区位于所述第二子区的远离所述沟道区域的一侧，所述第三子区位于所述第二子区的靠近所述沟道区域的一侧，所述第二子区的厚度为所述沟道区域的厚度的k倍，k为0.8至1.5。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述第一子区的厚度和所述第三子区的厚度均与所述沟道区域的厚度相等。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述第二子区的导电率大于所述第一子区的导电率，且所述第二子区的导电率大于所述第三子区的导电率。
  4. 根据权利要求1所述的薄膜晶体管，其中，所述第二子区的氧元素含量小于所述第一子区的氧元素含量，且所述第二子区的氧元素含量小于所述第三子区的氧元素含量。
  5. 根据权利要求1至4任一项所述的薄膜晶体管，其中，所述第二子区的导电率大于所述源连接区域的导电率，且所述第二子区的导电率大于所述漏连接区域的导电率。
  6. 根据权利要求1至4任一项所述的薄膜晶体管，其中，所述第二子区的氧元素含量小于所述源连接区域的导电率，且所述第二子区的氧元素含量小于所述漏连接区域的氧元素含量。
  7. 根据权利要求1至4任一项所述的薄膜晶体管，其中，所述第一子区的材料和所述第三子区的材料均为第一导体材料，所述第一导体材料为对第 一金属氧化物膜进行一次导体化处理得到，所述第二子区的材料包括：第二导体材料或者第三导体材料，第二导体材料包括：叠设的第一子导体材料和第二子导体材料，第一子导体材料为对第一金属氧化物膜进行两次导体化处理得到，第二子导体材料为对第二金属氧化物膜进行两次导体化处理得到，第三导体材料为对第一金属氧化物膜进行两次导体化处理得到，所述第二金属氧化物膜的硬度小于所述第一金属氧化物膜的硬度。
  8. 根据权利要求7所述的薄膜晶体管，其中，所述第二子区中的第二金属氧化物层的厚度小于所述第二子区中的第一金属氧化物层的厚度。
  9. 根据权利要求7所述的薄膜晶体管，其中，所述第一金属氧化物膜和所述第二金属氧化物膜均采用铟镓锌氧化物IGZO形成。
  10. 根据权利要求1至4任一项所述的薄膜晶体管，其中，所述第二子区的宽度小于所述第一子区的宽度；或者，所述第二子区的宽度小于所述第三子区的宽度。
  11. 根据权利要求1至4任一项所述的薄膜晶体管，其中，所述源电极至少部分覆盖所述源过渡区域的第二子区；或者，所述漏电极至少部分覆盖所述漏过渡区域的第二子区。
  12. 根据权利要求11所述的薄膜晶体管，其中，所述源过渡区域的第二子区包括：被所述源电极覆盖的第一部分和未被所述源电极覆盖的第二部分，第一部分的宽度小于第二部分的宽度；或者，所述漏过渡区域的第二子区包括：被所述漏电极覆盖的第三部分和未被所述漏电极覆盖的第四部分，第三部分的宽度小于第四部分的宽度。
  13. 根据权利要求11所述的薄膜晶体管，其中，所述有源层还包括：位于所述源连接区域的远离所述沟道区域一侧的第一区域以及位于所述漏连接区域的远离所述沟道区域一侧的第二区域；所述源过渡区域的第二子区的宽度小于所述第一区域的宽度，或者，所述漏过渡区域的第二子区的宽度小于所述第二区域的宽度。
  14. 根据权利要求1至4任一项所述的薄膜晶体管，其中，所述源电极搭设在所述源过渡区域的第一子区，且通过第一过孔与所述源连接区域连接；以及，所述漏电极搭设在所述漏过渡区域的第一子区，且通过第二过孔与所 述漏连接区域连接。
  15. 根据权利要求14所述的薄膜晶体管，其中，所述遮挡层包括：间隔设置的第一遮挡层和第二遮挡层，所述有源层在基底上的正投影的边界位于所述第一遮挡层在基底上的正投影的边界范围内，所述源电极通过第三过孔与所述第二遮挡层连接。
  16. 根据权利要求1至4任一项所述的薄膜晶体管，其中，所述第二子区通过第一次导体化处理和第二次导体化处理形成，所述第一子区通过第一次导体化处理形成，所述第三子区通过第二次导体化处理形成，所述沟道区域在自对准的第二次导体化处理过程中形成。
  17. 一种显示基板，包括：如权利要求1至16任一所述的薄膜晶体管。
  18. 一种显示装置，包括：如权利要求17所述的显示基板。
  19. 一种薄膜晶体管的制备方法，包括：
    在基底上依次形成遮挡层、缓冲层和有源层；
    在有源层上依次形成栅绝缘层和导电层，通过两次导体化处理使所述有源层形成沟道区域、位于所述沟道区域两侧的源过渡区域和漏过渡区域、位于所述源过渡区域的远离所述沟道区域一侧的源连接区域、以及位于所述漏过渡区域的远离所述沟道区域一侧的漏连接区域；所述导电层包括：栅电极、源电极和漏电极；所述源连接区域与所述源电极连接，所述漏连接区域与所述漏电极连接；所述源过渡区域和所述漏过渡区域均包括：依次连接的第一子区、第二子区和第三子区，所述第一子区位于所述第二子区的远离所述沟道区域的一侧，所述第三子区位于所述第二子区的靠近所述沟道区域的一侧，所述第一子区的厚度和所述第三子区的厚度均与所述沟道区域的厚度相等，所述第二子区的厚度为所述沟道区域的厚度的k倍，k为0.8至1.5。
  20. 根据权利要求19所述的制备方法，其中，所述在基底上依次形成遮挡层、缓冲层和有源层，包括：
    在基底上依次形成遮挡层和缓冲层；
    在缓冲层上形成两层金属氧化物膜，对两层金属氧化物膜进行图案化处理，形成所述有源层，所述两层金属氧化物膜包括：叠设的第一金属氧化物 膜和第二金属氧化物膜，所述第二金属氧化物膜的氧元素含量大于所述第一金属氧化物膜的氧元素含量，且所述第二金属氧化物膜的功率小于所述第一金属氧化物膜的功率。
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