WO2015000247A1 - 阵列基板、阵列基板的制备方法以及显示装置 - Google Patents

阵列基板、阵列基板的制备方法以及显示装置 Download PDF

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Publication number
WO2015000247A1
WO2015000247A1 PCT/CN2013/087253 CN2013087253W WO2015000247A1 WO 2015000247 A1 WO2015000247 A1 WO 2015000247A1 CN 2013087253 W CN2013087253 W CN 2013087253W WO 2015000247 A1 WO2015000247 A1 WO 2015000247A1
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Prior art keywords
gate
layer
line
electrode
source
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PCT/CN2013/087253
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English (en)
French (fr)
Inventor
成军
宁策
孙宏达
杨维
王珂
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京东方科技集团股份有限公司
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Publication of WO2015000247A1 publication Critical patent/WO2015000247A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Definitions

  • Array substrate method for preparing array substrate, and display device
  • the present invention belongs to the field of display technologies, and in particular, to an array substrate, a preparation method, and a display device. Background technique
  • flat panel display devices have replaced cumbersome CRT (Cathode Ray Tube) display devices in people's daily lives.
  • CRT Cathode Ray Tube
  • Currently, commonly used flat panel display devices include LCD (Liquid Crystal Display), PDP (Plasma Display Panel), and OLED (Organic Light-Emitting Diode) display devices.
  • the 0LED display device has many advantages such as self-illumination, fast response angle, and the like, and can be used for various applications such as flexible display, transparent display, and 3D display.
  • each pixel in the LCD and Active Matrix Organic Light Emission Display (AMOLED) display device is composed of a thin film transistor (TFT) integrated in the array substrate. ) to drive, thus achieving image display.
  • TFT thin film transistor
  • Each thin film transistor can independently control one pixel without causing crosstalk to other pixels.
  • the thin-film transistor is the key to realize the display of LCD and 0LED display devices, which is directly related to the development direction of high-performance display devices.
  • the thin film transistor mainly includes a gate electrode, a gate insulating layer, an active layer, a source and a drain.
  • the active layer is usually formed using a silicon-containing material or a metal oxide semiconductor material.
  • a thin film transistor using a metal oxide semiconductor material as an active layer has good on-state current and switching characteristics, high mobility, good uniformity, no need to add a compensation circuit, and has both a mask quantity and a ease of fabrication.
  • metal oxide semiconductor materials exhibit good semiconductor properties when they have a high oxygen content, and have a low resistivity when they have a low oxygen content, so they can be used as transparent electrodes, which are sufficient for fast response and large Current applications such as high frequency, high resolution, medium to large size LCDs and 0 LEDs In the display device.
  • the metal oxide semiconductor material forming the active layer is simple in fabrication process, and can be sprayed or the like, has good matching with the existing LCD production line, is easy to be transformed, does not require additional equipment, and has a cost advantage.
  • a typical structure of a thin film transistor in which an active layer is formed by using a metal oxide semiconductor material in the prior art is: a gate 2a is disposed on the substrate 1, and a gate insulating layer 3 is disposed on the gate 2a.
  • An active layer 4 ie, a metal oxide semiconductor layer
  • an etch stop layer 5 is disposed on the active layer 4
  • a source 6a and a drain 6b are disposed on the etch stop layer 5
  • a passivation layer 7 is disposed on the source 6a and the drain 6b
  • a pixel electrode 8 i.e., an IT0 transparent electrode layer
  • the thin film transistor of the above structure is prepared by: depositing a gate metal material on the substrate 1, forming a gate electrode 2a by a first patterning process; depositing a gate insulating layer 3 on the gate electrode 2a, in the gate insulating layer 3
  • the active layer 4 is deposited thereon, the trench region and the source and drain contact regions are formed by a second patterning process; an etch barrier film is deposited on the active layer 4, and an etch barrier layer is formed by a third patterning process 5; depositing a metal material on the etch barrier layer 5, forming a source electrode 6a and a drain electrode 6b by a fourth patterning process; depositing a passivation layer film on the source electrode 6a and the drain electrode 6b, and forming a fifth patterning process
  • the passivation layer 7 and the via holes in the passivation layer 7; the IT0 transparent electrode material is deposited on the passivation layer 7, and the pixel electrode 8 is formed by the sixth patterning process, and the pixel electrode 8 is connected to the
  • the technical problem to be solved by the present invention is to provide an array substrate, a method for preparing an array substrate, and a display device, which are prepared by using only four patterning processes, and are provided for the above-mentioned deficiencies in the prior art.
  • the line and the data line are formed by the same metal layer forming the gate, which simplifies the preparation process of the array substrate.
  • the present invention provides an array substrate including a substrate and a plurality of gate lines and a plurality of data lines disposed on the substrate, the gate lines are disposed to intersect with the data lines, and the substrate is divided a plurality of pixel regions, each of the pixel regions is provided with a thin film transistor, the thin film transistor including a gate, a source and a drain, and the gate and the gate
  • the gate line is electrically connected, the source is electrically connected to the data line, wherein the gate, the gate line is disposed in the same layer as the data line, and the data line is crossed with the gate line
  • the area of the disconnection is disconnected, and the disconnected data lines are electrically connected by a number-number connection line different from the data line.
  • a pixel electrode is further disposed in the pixel region, wherein the number-number connection line, the source, and the drain are disposed in the same layer as the pixel electrode, and the number-number connection line is disposed on The area corresponding to the disconnected area of the data line is connected to the disconnected data line.
  • the array substrate further includes a gate insulating layer disposed between the gate and the source and the drain; the active layer and the active layer a gate is disposed opposite to each other and located at a side of the gate insulating layer away from the gate; the source and the drain are disposed adjacent to the active layer at a position corresponding to both ends of the active layer The position is partially overlapped with the gate in the forward projection direction.
  • the array substrate further includes an etch barrier layer, the gate line, the gate line and the data line are disposed on the substrate in the same layer; the gate insulating layer is disposed on the substrate a gate, the gate line and the data line, and completely covering the gate, the gate line and the data line, the gate insulating layer being opened in a region corresponding to the data line a first connection line via and a first source-to-number connection line via;
  • the active layer is disposed on the gate insulating layer corresponding to the gate, and completely covers an area corresponding to the gate;
  • the etch barrier layer is disposed above the active layer, and the etch barrier layer has a source via hole at a position corresponding to one end of the active layer, and the etch barrier layer is a drain via is formed at a position corresponding to the other end of the active layer, and the etch barrier has a second connection line via and a second source-number connection in a region corresponding to the data line.
  • Line through hole
  • the digital-number connection line, the source, the drain and the pixel electrode are disposed in the same layer above the etch barrier layer, and the source is embedded in the source via hole to be Contacting the active layer, the source is embedded in the first source-number connection line via and the second source-number connection line via to electrically connect with the data line, and the digital-number connection line passes Embed
  • the first connection line via and the second connection via are electrically connected to the plurality of disconnected data lines; the drain is embedded in the drain via to contact the active layer, The drain is electrically connected to the pixel electrode.
  • a preferred structure is that the array substrate further includes a passivation layer.
  • the active layer is disposed on the substrate
  • the gate insulating layer is disposed above the active layer, and opposite ends of the active layer in a direction parallel to the gate line are not covered by the gate insulating layer;
  • the gate, the gate line and the data line are disposed in the same layer above the gate insulating layer, and an area of the gate in a right projection direction is smaller than an area of the active layer; a layer disposed over the gate, the gate line and the data line, and completely covering the gate, the gate line and the data line, the passivation layer being active a source via is formed at a position corresponding to an end of the layer not covered by the gate insulating layer, the passivation layer being at a position corresponding to the other end of the active layer not covered by the gate insulating layer a drain via is disposed at the opening, and the passivation layer is provided with a connection line via and a source-number connection line via in a region corresponding to the data line;
  • the digital-number connection line, the source, the drain and the pixel electrode are disposed in the same layer above the passivation layer, and the source is embedded in the source via hole to Contacting the source layer, the source is embedded in the source-number connection line via to electrically connect with the data line, and the number-number connection line is electrically connected by disconnecting the plurality of data lines by embedding the connection line via
  • the drain is embedded in the drain via to be in contact with the active layer, and the drain is electrically connected to the pixel electrode.
  • the gate, the gate line and the data line are made of the same material and formed in the same patterning process.
  • the gate, the gate line and the data line are each formed of at least one of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-niobium alloy, titanium, chromium and copper;
  • the gate line and the data line are a single layer structure or a multilayer composite stacked structure, and the gate, the gate line and the data line have a thickness ranging from 100 to 3000 nm.
  • the number-number connection line, the source, the drain, and the pixel electrode are at least one of indium gallium zinc oxide, indium zinc oxide, indium tin oxide, and indium gallium tin oxide. form;
  • the active layer is formed of a metal oxide semiconductor material;
  • the gate insulating layer is a single layer structure or a multilayer composite laminated structure, and the gate insulating layer is made of silicon oxide, silicon nitride, germanium oxide, silicon nitrogen. Forming at least one of an oxide and an aluminum oxide;
  • the etch barrier layer and the passivation layer are a single layer structure or a multilayer composite laminate structure, and are formed of at least one of silicon oxide, silicon nitride, hafnium oxide, and aluminum oxide.
  • a display device comprising the above array substrate.
  • a method for fabricating an array substrate comprising the steps of forming a plurality of gate lines and a plurality of data lines on a substrate to divide the substrate into a plurality of pixel regions, further comprising forming a thin film transistor in each of the pixel regions Step, the thin film transistor includes a gate, a source and a drain, the gate is electrically connected to the gate line, and the source is electrically connected to the data line.
  • the same composition is used a process of forming the gate, the gate line and the data line in a same layer, disconnecting the data line in a region crossing the gate line, and forming the broken data line through A digital-to-number connection line at a different layer is electrically connected to the data line.
  • a preferred method specifically includes the following steps:
  • Step S1 forming a pattern including a gate, a gate line, and a data line on the substrate by using a patterning process, the data line being disconnected in a region crossing the gate line;
  • Step S2 using a patterning process, forming a pattern including a gate insulating layer on the substrate on which the step S1 is completed, and forming a pattern including an active layer above the gate insulating layer corresponding to the gate.
  • the gate insulating layer completely covers the gate, the gate line and the data line, and the active layer completely covers an area corresponding to the gate;
  • Step S3 forming a pattern including an etch barrier layer on the substrate completing step S2 by using a patterning process
  • Step S4 using a patterning process, a pattern including a plurality of connection lines, a source, a drain, and a pixel electrode is formed on the substrate on which the step S3 is completed.
  • step S2 the gate insulating layer is formed with a first connection line via and a first source-number connection via in a region corresponding to the data line; in step S3: the etching The barrier layer forms a source via hole at a position corresponding to one end of the active layer, The etch barrier layer is formed with a second connection line via and a second source-number connection via in a region corresponding to the data line; in step S4: the source is embedded in the source a hole thus contacting the active layer, the source being embedded in the first source-number connection line via and the second source-number connection line via to electrically connect to the data line, the number a plurality of connecting lines are electrically connected by disconnecting the plurality of the data lines by embedding the first connecting line via holes and the second connecting line via holes;
  • step S3 the etch barrier layer is formed with a drain via at a position corresponding to the other end opposite to the end of the active layer to which the source is connected; in step S4: the drain embedding device The drain via is in contact with the active layer, and the drain is electrically connected to the pixel electrode.
  • a preferred method specifically includes the following steps:
  • Step S1 forming a pattern including an active layer on the substrate by using a patterning process, and forming a pattern including a gate insulating layer over the active layer, the active layer being parallel to the gate line The opposite ends are not covered by the gate insulating layer;
  • Step S2 forming a pattern including a gate electrode, a gate line, and a data line on the substrate completing the step S1 by using a patterning process, the data line being disconnected in a region crossing the gate line, The area of the gate in the orthogonal projection direction is smaller than the area of the active layer;
  • Step S3 forming a pattern including the passivation layer on the substrate completing step S2 by using a patterning process;
  • Step S4 using a patterning process, a pattern including a plurality of connection lines, a source, a drain, and a pixel electrode is formed on the substrate on which the step S3 is completed.
  • the passivation layer forms a source via at a position corresponding to an end of the active layer not covered by the gate insulating layer, and the passivation layer is a connection line via hole and a source-number connection line via hole are formed in a region corresponding to the data line;
  • the source is embedded in the source via hole to be in contact with the active layer, a source is embedded in the source-number connection line via hole to be electrically connected to the data line, and the number-number connection line is electrically connected by inserting the connection line via hole so that the plurality of disconnected data lines are electrically connected;
  • step S3 the passivation layer is formed at a position corresponding to the other end of the opposite end to which the source layer is connected to the active layer without being covered by the gate insulating layer.
  • a drain via in step S4: the drain is embedded in the drain via to be in contact with the active layer, and the drain is electrically connected to the pixel electrode.
  • the beneficial effects of the present invention are as follows:
  • the active layer is formed by using a metal oxide semiconductor material, and the entire array substrate can be prepared only by using four patterning processes, and the gate lines and the data lines are formed by gate electrodes.
  • the formation of the same layer of metal layer simplifies the preparation process of the array substrate, greatly improving the productivity and saving the cost.
  • FIG. 1 is a cross-sectional view of an array substrate in the prior art
  • 2-1 and 2-2 are schematic structural diagrams of an array substrate according to Embodiment 1 of the present invention.
  • Figure 2-1 is a plan view of the array substrate
  • Figure 2-2 is a cross-sectional view taken along line D-D of Figure 2-1;
  • 3-1 to 3-8 are schematic views showing a preparation flow of an array substrate in Embodiment 1 of the present invention.
  • Figure 3-1 is a plan view of forming a pattern including a gate, a gate line, and a data line for the first patterning process;
  • Figure 3-2 is a cross-sectional view taken along line A-A of Figure 3-1;
  • 3-3 is a plan view showing a pattern including a gate insulating layer and an active layer in a second patterning process
  • Figure 3-4 is a cross-sectional view taken along line B-B of Figure 3-3;
  • Figure 3-5 is a plan view showing a pattern including an etch barrier layer in a third patterning process; and Figure 3-6 is a cross-sectional view taken along line C-C shown in Figures 3-5;
  • 3-7 are plan views showing a pattern including a number-number connection line, a source, a drain, and a pixel electrode in a fourth patterning process;
  • Figure 3-8 is a cross-sectional view taken along line D-D of Figure 3-7;
  • FIG. 4-1, 4-2 are schematic structural views of an array substrate according to Embodiment 2 of the present invention; wherein - FIG. 4-1 is a plan view of the array substrate; Figure 4-2 is a cross-sectional view taken along line DD of Figure 4-1;
  • 5-1 to 5-8 are schematic views showing a preparation flow of an array substrate in Embodiment 2 of the present invention.
  • Figure 5-1 is a plan view of the first patterning process including the active layer and the gate insulating layer;
  • Figure 5-2 is a cross-sectional view taken along line A-A of Figure 5-1;
  • Figure 5-3 is a plan view showing a pattern including a gate, a gate line, and a data line in a second patterning process
  • Figure 5-4 is a cross-sectional view taken along line B-B of Figure 5-3;
  • FIG. 5-5 are plan views showing a pattern including a passivation layer in a third patterning process; and FIG. 5-6 is a cross-sectional view taken along line C-C shown in FIG. 5-5;
  • 5-7 are plan views showing a pattern including a number-number connection line, a source, a drain, and a pixel electrode in a fourth patterning process;
  • Figure 5-8 is a cross-sectional view taken along line D-D of Figure 5-7;
  • Figures 6-1 and 6-2 are schematic views corresponding to the steps of patterning using a photoresist mask in Figures 5-1 and 5-2;
  • An array substrate includes a substrate and a plurality of gate lines and a plurality of data lines disposed on the substrate, wherein the gate lines are disposed to intersect with the data lines and divide the substrate into a plurality of images a thin film transistor is disposed in each of the pixel regions, the thin film transistor includes a gate, a source and a drain, the gate is electrically connected to the gate line, the source and the data line The electrical connection, wherein the gate, the gate line and the data line are disposed in the same layer, the data line is disconnected in a region crossing the gate line, and the disconnected data line is electrically connected through the digital-number connection line different from the data line.
  • a display device comprising the above array substrate.
  • a method for fabricating an array substrate comprising the steps of forming a plurality of gate lines and a plurality of data lines on a substrate to divide the substrate into a plurality of pixel regions, further comprising forming a thin film transistor in each of the pixel regions Step, the thin film transistor includes a gate, a source and a drain, the gate is electrically connected to the gate line, and the source is electrically connected to the data line.
  • the same composition is used a process of forming the gate, the gate line and the data line in a same layer, disconnecting the data line in a region crossing the gate line, and forming the broken data line through A digital-to-number connection line at a different layer is electrically connected to the data line.
  • the array substrate includes a plurality of layers stacked on the substrate 1 in sequence, respectively: a gate 2a, a data line 2c, and a gate line 2b disposed in the same layer; a gate insulating layer 3; an active layer 4; an etch barrier layer 5; and a source 6a, a drain 6b, a pixel electrode 8, and a number-number connection line 9 disposed in the same layer.
  • the gate 2a is electrically connected to the gate line 2b
  • the data line 2c is electrically connected to the source 6a
  • the gate line 2b is disposed to intersect the data line 2c and divide the substrate 1 into a plurality of pixel regions.
  • the data line 2c is disconnected in the area intersecting the gate line 2b, and the broken data line 2c is electrically connected through the number-number connection line 9 of a different layer of the data line 2c; the number-number connection line 9 It is provided in a region corresponding to the disconnection region of the data line 2c, and is connected to the disconnected data line 2c.
  • the gate insulating layer 3 is disposed between the gate 2a and the source 6a and the drain 6b; the active layer 4 is disposed opposite to the gate 2a, and is located on a side of the gate insulating layer 3 away from the gate 2a; 6a and the drain 6b are disposed adjacent to the active layer 4 at positions corresponding to both ends of the active layer 4, and partially overlap the gate 2a in the orthogonal projection direction.
  • the structure of the array substrate is as follows:
  • the gate 2a, the gate line 2b and the data line 2c are disposed on the substrate 1 in the same layer;
  • the gate insulating layer 3 is disposed above the gate 2a, the gate line 2b, and the data line 2c, and completely covers the gate 2a, the gate line 2b, and the data line 2c.
  • the gate insulating layer 3 is provided with a first connection line via 71c in a region corresponding to the data line 2c (corresponding to the second connection line via 72c in FIG. 2-1, not specifically shown in FIG. 2-2) and The first source-number connection line via 71d (corresponding to the second source-number connection line via 72d in Figure 2-1, not specifically shown in Figure 2-2);
  • the active layer 4 is disposed on the gate insulating layer 3 corresponding to the gate 2a and completely covers the region corresponding to the gate 2a;
  • the etch stop layer 5 is disposed above the active layer 4, and the etch stop layer 5 defines a source via hole 7a at a position corresponding to one end of the active layer 4, and the etch stop layer 5 is in the active layer 4
  • the other end of the other end is provided with a drain via 7b, and the etch barrier 5 is provided with a second connection line via 72c and a second source-number connection line via 72d in a region corresponding to the data line 2c;
  • the digital-to-number connection line 9, the source 6a, the drain 6b and the pixel electrode 8 are disposed in the same layer above the etch barrier layer 5, and the source 6b is embedded in the source via 7a and in contact with the active layer 4, the source 6a
  • the first source-number connection line via 71d and the second source-number connection line via 72d are embedded as a source-to-number connection line for electrically connecting to the data line 2c, and the number-number connection line 9 is embedded by the first The connection line via 71c and the second connection line via 72c electrically connect the disconnected plurality of data lines 2c; the drain 6b is embedded in the drain via 7b and is in contact with the active layer 4, and the drain 6b and the pixel electrode 8 Electrical connection.
  • the gate 2a, the gate line 2b and the data line 2c are both molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (A1), aluminum-niobium alloy (AlNd), titanium (Ti), chromium (Cr).
  • Mo molybdenum
  • MoNb molybdenum-niobium alloy
  • AlNd aluminum-niobium alloy
  • Ti titanium
  • Cr chromium
  • the gate 2a, the gate line 2b and the data line 2c are single or multi-layer composite laminated structures, gate 2a, the gate line 2b and the data line 2c have a thickness ranging from 100 mm to 3000 nm.
  • the source 6a, the drain 6b, the pixel electrode 8, and the number-number connection line 9 are made of indium gallium zinc oxide (IGZ0), indium zinc oxide (IZ0), indium tin oxide (IT0), indium gallium tin oxide, indium gallium zinc oxide. At least one material in (ITZ0) is formed.
  • the source 6a, the drain 6b, the pixel electrode 8, and the number-number connection line 9 may be selected from indium tin oxide, indium gallium zinc oxide, It is formed of a transparent conductive material such as indium zinc oxide or indium gallium zinc oxide.
  • the active layer 4 is formed of a metal oxide semiconductor material, and is made of a material containing an element such as indium (In), gallium (Ga), zinc (Zn), oxygen (0), tin (Sn), etc., which must contain oxygen.
  • the element and the other two or more elements such as at least one of indium gallium zinc oxide (IGZ0), indium zinc oxide (IZ0), indium tin oxide (InSnO), and indium gallium tin oxide (InGaSnO).
  • the gate insulating layer 3 is a single layer or a multilayer composite laminated structure, and the gate insulating layer 3 is made of silicon oxide (SiOx), silicon nitride (SiNx), tantalum oxide (HfOx), silicon oxynitride (SiON), aluminum. At least one material of the oxide (AlOx) is formed.
  • the etch barrier layer 5 is a single layer or a multilayer composite laminated structure, and at least one of silicon oxide (SiOx), silicon nitride (SiNx), tantalum oxide (SiON), and aluminum oxide (AlOx) is used. form.
  • the method for fabricating the above array substrate includes the steps of forming a plurality of gate lines and a plurality of data lines on the substrate to divide the substrate into a plurality of pixel regions, and further comprising the step of forming a thin film transistor in each of the pixel regions,
  • the thin film transistor includes a gate, a source and a drain, the gate is electrically connected to the gate line, and the source is electrically connected to the data line.
  • the gate, the gate line and the data line are used in the same patterning process Formed in the same layer, the data lines are disconnected in the region crossing the gate lines, and the broken data lines are electrically connected to the data lines through the number-number connection lines formed in the different layers.
  • the patterning process may include only a photolithography step, or may include a photolithography step and an etching step, and may also include printing, inkjet, and the like for forming a predetermined pattern.
  • the photolithography process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like, including a molding process, an exposure process, a development process, and the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present invention.
  • the method includes the following steps:
  • Step S1 A pattern including a gate electrode, a gate line, and a data line is formed on the substrate by one patterning process, and the data line is disconnected in a region crossing the gate line.
  • an electrode metal film is formed on the substrate 1, and a pattern including the gate electrode 2a, the gate line 2b, and the data line 2c is formed by one patterning process, and the data line 2c is formed. It is broken in the area crossing the gate line 2b. As can be seen from this step, the grid The pole 2a, the gate line 2b, and the data line 2c are formed using the same layer of electrode metal film.
  • an electrode metal film is formed on the substrate 1 by deposition, sputtering or thermal evaporation.
  • a pattern including the gate electrode 2a, the gate line 2b, and the data line 2c is formed in the non-pixel region of the array substrate, and a common electrode line 2d is formed.
  • the common electrode line 2d is left to be electrically connected to the common electrode after forming a common electrode in the subsequent processing, and will not be described in detail herein.
  • the cross-sectional view 3-2 is a cross-sectional view taken along the line A-A in the plan view 3-1.
  • the cross-sectional view 3-2 is slightly different from the plan view 3-1, and the following cross-sectional views are the same as the respective plan views.
  • Step S2 using a patterning process, forming a pattern including a gate insulating layer on the substrate on which the step S1 is completed, and forming a pattern including the active layer above the gate insulating layer corresponding to the gate.
  • a gate insulating film (FGI Deposition) is formed on the substrate 1 on which the step S1 is completed, that is, at the gate 2a, the gate line 2b, and the data line 2c.
  • a gate insulating film is formed on top of the gate; then an active layer film is formed over the gate insulating film.
  • a pattern including the gate insulating layer 3 and the active layer 4 is simultaneously formed by a patterning process, and the gate insulating layer 3 is formed with a first connection line via 71c and a first source-number connection line in a region corresponding to the data line 2c. Hole 71 d.
  • the gate insulating film is formed by plasma enhanced chemical vapor deposition (PECVD), and the active layer film is formed by deposition, sputtering or thermal evaporation.
  • PECVD plasma enhanced chemical vapor deposition
  • the active layer film is formed by deposition, sputtering or thermal evaporation.
  • the gate insulating layer 3 is generally formed of a transparent material (silicon oxide, silicon nitride, tantalum oxide, silicon oxynitride, aluminum oxide), the observation of the plan view is not hindered, so in FIG.
  • the schematic diagram of the gate insulating layer 3 is omitted in FIG. 3, and only the positions of the connection line vias and the source-number connection line vias opened therein are shown correspondingly; at the same time, in order to facilitate understanding of the structure of each layer in the pixel region and the layers
  • the positional relationship between the two, the layers in the plan 3-3 are set to have a certain transparency, and the following plan views are the same.
  • Step S3 using one patterning process, forming on the substrate on which step S2 is completed, including Etching the pattern of the barrier layer.
  • an etch barrier film is formed on the substrate on which step S2 is completed, and a pattern including the etch barrier layer 5 is formed by one patterning process.
  • the etch barrier layer 5 forms a source via hole 7a at a position corresponding to one end of the active layer 4, and the etch barrier layer 5 is formed with a drain via hole 7b at a position corresponding to the other end of the active layer 4.
  • the etch barrier layer 5 is formed with a second connection line via 72c and a second source-number connection line via 72d in a region corresponding to the data line 2c.
  • an etch barrier film is formed by deposition, sputtering, thermal evaporation or by special PECVD.
  • the etch barrier film is characterized in that the film layer has a low hydrogen content and has excellent surface characteristics.
  • Step S4 A pattern including a number-number connection line, a source, a drain, and a pixel electrode is formed on the substrate on which the step S3 is completed by using one patterning process.
  • a transparent electrode metal film is formed on the substrate 1 which is completed in step S3, and one end of the active layer 4 is formed on the etching barrier layer 5 by a patterning process.
  • a source 6a is formed at a corresponding position
  • a drain 6b is formed at a position corresponding to the other end of the active layer 4
  • a number-number connection line 9 is formed in a region corresponding to the data line 2c, and at the same time, near the drain
  • a pixel electrode 8 is formed on one side of 6b, and the pixel electrode 8 is electrically connected to the drain electrode 6b.
  • the source 6a is embedded in the source via 7a to be in contact with the active layer 4, and the source 6a is embedded in the first source-number connection via 71d (corresponding to the second source-number connection line in FIG. 3-7)
  • the lower side of the hole 72d) and the second source-number connection line via 72d are electrically connected to the data line 2c, and the number-number connection line 9 is embedded in the first connection line via 71c (corresponding to the second connection in FIGS.
  • the lower side of the line via 72c) and the second connection line via 72c electrically connect the disconnected plurality of data lines 2c; the drain 6b is embedded in the drain via 7b to be in contact with the active layer 4, and the drain 6b and the pixel
  • the electrodes 8 are electrically connected.
  • the electrode metal film is formed by deposition, sputtering or thermal evaporation, and the thickness of the electrode metal film ranges from 20 to 150 nm.
  • the electrode metal film in this embodiment is a metal oxide semiconductor, and specifically: indium gallium zinc oxide (IGZ0), indium zinc oxide (IZ0), indium tin oxide (IT0), indium gallium tin oxide (InGaSnO) Forming at least one material, for example: using indium tin oxide (IT0) material as the electrode metal
  • IGZ0 indium gallium zinc oxide
  • IZ0 indium zinc oxide
  • IT0 indium gallium tin oxide
  • InGaSnO indium gallium tin oxide
  • the amorphous transparent electrode metal thin film is formed by a step of forming a film by sputtering, and then crystallized by annealing.
  • the active layer forming the thin film transistor uses a metal oxide semiconductor material, the electron mobility between the source and the drain is increased, so that
  • the transparent electrode metal film forming the pixel electrode also forms a number-number connection line for connecting the disconnected data lines, and the number-number connection line passes through the first connection line opened in the gate insulating layer.
  • the vias and the second connection vias in the etch barrier layer allow the disconnected plurality of data lines to be connected into a complete data line.
  • the number-number connection line 9 is not limited as long as the disconnected data lines 2c can be electrically connected to each other, and the width of the log-number connection line 9 is not limited;
  • the positional relationship between the data line 2c and the second connection line via 72c is such that the width of the number-number connection line 9 is slightly smaller than the width of the data line 2c in FIGS. 3-7.
  • the width of the number-number connection line 9 is usually designed not to be smaller than the width of the data line 2c to ensure good continuity between the data lines 2c.
  • the array substrate can be formed by using six patterning processes and the preparation method thereof.
  • the array substrate of the embodiment can be prepared by only four patterning processes. Simplifies the process flow and saves preparation time.
  • Embodiment 1 Also provided based on Embodiment 1 is a display device including the above array substrate.
  • the display device can be: LCD panel, electronic paper, 0LED panel, mobile phone, tablet, TV, display, laptop, digital photo frame, navigator, etc. Any product or component with display function.
  • the thin film transistor in the array substrate is a top gate type structure.
  • the structure of the array substrate in this embodiment is specifically as follows:
  • the active layer 4 is disposed on the substrate 1;
  • the gate insulating layer 3 is disposed above the active layer 4, and opposite ends of the active layer 4 in the direction parallel to the gate line 2b are not covered by the gate insulating layer 3;
  • the gate 2a and the gate line 2b are disposed on the same layer as the data line 2c above the gate insulating layer 3, And the area of the gate 2a in the orthogonal projection direction is smaller than the area of the active layer 4;
  • the passivation layer 7 is disposed above the gate 2a, the gate line 2b, and the data line 2c, and completely covers the gate 2a, the gate line 2b, and the data line 2c.
  • the passivation layer 7 is provided with a source via hole 7a at a position corresponding to an end of the active layer 4 not covered by the gate insulating layer 3, and the passivation layer 7 is additionally covered with the active layer without the gate insulating layer 3.
  • a drain via 7b is formed at a position corresponding to one end, and a pass line 7c and a source-number connection line via 7d are opened in a region corresponding to the data line 2c;
  • the number-number connection line 9, the source 6a, the drain 6b and the pixel electrode 8 are disposed in the same layer above the passivation layer 7, the source 6a is embedded in the source via 7a to be in contact with the active layer 4, and the source 6a is embedded.
  • the source-number connection line via 7d serves as a source-to-number connection line to be electrically connected to the data line 2c, and the number-number connection line 9 electrically connects the disconnected plurality of data lines 2c by embedding the connection line via hole 7c; 6b is embedded in the drain via 7b to be in contact with the active layer 4, and the drain 6b is electrically connected to the pixel electrode 8.
  • the method for preparing the above array substrate specifically includes the following steps:
  • Step S1 forming a pattern including an active layer on the substrate by using one patterning process, and forming a pattern including a gate insulating layer over the active layer, the opposite ends of the active layer in a direction parallel to the gate line Covered by a gate insulating layer.
  • an active layer film is formed on the substrate 1 by using a metal oxide semiconductor material, and the metal oxide semiconductor material includes indium gallium zinc oxide (IGZ0) and indium oxide. (In203), zinc oxide (ZnO) or indium tin zinc oxide (ITZ0).
  • IGZ0 indium gallium zinc oxide
  • In203 indium oxide
  • ZnO zinc oxide
  • ITZ0 indium tin zinc oxide
  • an active layer film and a gate insulating film are sequentially formed on the substrate 1.
  • a pattern including the active layer 4 and the gate insulating layer 3 is formed by the first patterning process.
  • the opposite ends of the active layer 4 in the direction parallel to the gate line 2b are not covered by the gate insulating layer 3 to facilitate contact of the active layer 4 with the source 6a and the drain 6b in the subsequent process.
  • Step S11 depositing a metal oxide semiconductor film having a thickness ranging from 30 to 50 nm by magnetron sputtering (the active layer film 40 in FIG. 6-1), and then using PECVD Forming a gate insulating film having a thickness ranging from 200 to 400 nm (such as the gate insulating film 30 in FIG. 6_1);
  • Step S12 coating a photoresist on the gate insulating film 30, and exposing and developing the photoresist by using a gray tone mask or a halftone mask to completely remove part of the photoresist, and also partially removing the photoresist. Retaining a portion of the photoresist (the specific fully removed portion and the partially retained portion are determined by the pattern of the active layer and the gate insulating layer) to form a photoresist mask 41, as shown in FIG. 6-1; Under the protection of the mold 41, a partial pattern including the gate insulating layer 3 is formed by the first dry etching process, and a pattern including the active layer 4 is formed by wet etching.
  • Step S13 etching and developing the photoresist by ashing, removing a portion of the remaining photoresist, forming a photoresist mask 41 having a modified protection range as shown in FIG. 6-2, and then passing The second dry etching process forms a complete pattern including the gate insulating layer 3.
  • Step S2 using a patterning process, forming a pattern including a gate electrode, a gate line, and a data line on the substrate on which the step S1 is completed, the data line being disconnected in a region crossing the gate line, and the gate electrode in the orthogonal projection direction
  • the area is smaller than the area of the active layer.
  • an electrode metal film having a thickness ranging from 200 to 300 nm is deposited by magnetron sputtering, and a gate pattern 2a and a gate line are formed by a second patterning process. 2b and data line 2c graphics.
  • the electrode metal is preferably copper (Cu), and a material such as aluminum (Al) or molybdenum ( Mo ) may also be preferable.
  • Step S3 A pattern including a passivation layer is formed on the substrate on which the step S2 is completed by using one patterning process.
  • a passivation film is formed by deposition, sputtering or thermal evaporation.
  • a passivation layer film having a thickness ranging from 200 to 400 nm can be deposited by PECVD, and then a pattern including the passivation layer 7 is formed.
  • the passivation layer 7 forms a source via hole 7a at a position corresponding to an end of the active layer 4 not covered by the gate insulating layer 3, and the passivation layer 7 is covered with the active layer 4 without the gate insulating layer 3.
  • the other end of the other end is formed with a drain via 7b; the passivation layer 7 is formed with a via via 7c and a source-to-number via via 7d in a region corresponding to the data line 2c.
  • the passivation layer 7 is a single layer or a multilayer composite laminated structure, using silicon. At least one of an oxide (SiOx), a silicon nitride (SiNx), a tantalum oxide (SiON), and an aluminum oxide (AlOx) is formed.
  • SiOx oxide
  • SiNx silicon nitride
  • SiON tantalum oxide
  • AlOx aluminum oxide
  • the passivation layer 7 is generally formed of a transparent material (silicon oxide, silicon nitride, tantalum oxide, silicon oxynitride, aluminum oxide), the observation of the plan view is not hindered, and therefore, in FIG. 5 -
  • the schematic diagram of the passivation layer 7 is omitted in the schematic diagram of FIG. 5, and only the positions of the source via, the drain via, the data line via, and the source-number via are opened correspondingly; and, for ease of understanding
  • the structure of each layer in the pixel region and the positional relationship between the layers, the layers in the plan view 5-5 are set to have a certain transparency, and the following plan views are the same.
  • Step S4 A pattern including a number-number connection line, a source, a drain, and a pixel electrode is formed on the substrate on which the step S3 is completed by using one patterning process.
  • a transparent electrode metal film having a thickness ranging from 30 to 200 nm is deposited by magnetron sputtering, and a fourth patterning process is used to form a digital-number connection line.
  • the source 6a is embedded in the source via 7a to be in contact with the active layer 4, the source 6a is embedded in the source-number connection via 7d to be electrically connected to the data line 2c, and the digital-to-number connection 9 is embedded through the connection line.
  • the hole 7c electrically connects the disconnected plurality of data lines 2c; the drain 6b is embedded in the drain via 7b to be in contact with the active layer 4, and the drain 6b is electrically connected to the pixel electrode 8.
  • a TN (Twi sted Neraati c) mode, a VA (Vertical Alignment) mode liquid crystal display device can be easily formed, and an OLED display device can be formed.
  • a transparent electrode metal film is formed under the transparent pixel electrode to form a common electrode, that is, ADS (ADvanced).
  • ADS Advanced super-dimensional field conversion technology
  • the ADS mode is: a multi-dimensional electric field is formed by an electric field generated by the edge of the slit electrode in the same plane and an electric field generated between the slit electrode layer and the plate electrode layer, so that all the orientations between the slit electrodes and the electrode directly inside the liquid crystal cell are obtained.
  • Liquid crystal molecules can produce rotation, which improves the efficiency of liquid crystal molecules. Rate and increase the light transmission efficiency.
  • the pixel electrode may be in the shape of a plate or a slit.
  • the common electrode may be in the shape of a slit or a plate, as long as the electrode at the upper side is slit-shaped.
  • the electrode below is a plate shape.
  • Advanced super-dimensional field conversion technology can improve the picture quality of LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no push mura.
  • the active layer is formed of a metal oxide semiconductor material, and the entire array substrate can be prepared by using only four patterning processes, and the gate lines and the data lines are formed by the same layer of metal layers forming the gate electrodes.
  • the preparation process of the array substrate is simplified, the productivity is greatly improved, and the cost is saved.

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Abstract

一种阵列基板、阵列基板的制备方法以及显示装置。阵列基板包括，基板（1）和设置在基板上的多条栅线（2b）和多条数据线（2c），栅线和数据线交叉设置且将基板划分为多个像素区域，每个像素区域内设置有薄膜晶体管（30），薄膜晶体管包括栅极（2a）、源极（6a）和漏极（6b），栅极与栅线电连接，源极与数据线电连接，其中，栅极、栅线和数据线同层设置，数据线在与栅线交叉的区域中断开，断开的数据线通过与数据线不同层的数-数连接线（9）电连接。有源层（4）采用金属氧化物半导体材料形成，栅线与数据线由形成栅极的同层金属层形成，整个阵列基板仅需采用四次构图工序即可制备完成，简化了制备过程，提高了产能，节约了成本。

Description

阵列基板、 阵列基板的制备方法以及显示装置 技术领域
本发明属于显示技术领域， 具体涉及一种阵列基板、 制备方法 以及显示装置。 背景技术
随着科学技术的发展， 平板显示装置已取代笨重的 CRT (Cathode Ray Tube，阴极射线管）显示装置日益深入人们的日常生活 中。 目前， 常用的平板显示装置包括 LCD ( Liquid Crystal Display: 液晶显示装置） 、 PDP ( Plasma Display Panel : 等离子显示装置） 和 OLED ( Organic Light-Emitting Diode : 有机发光二极管） 显示 装置。 尤其是 0LED显示装置， 与 LCD相比， 具有自发光、 响应速度 快宽视角等诸多优点， 可用于柔性显示、 透明显示， 3D 显示等多种 应用。
在成像过程中， LCD 和有源矩阵驱动式 OLED ( Active Matrix Organic Light Emission Display, 简称 AMOLED) 显示装置中的每 一像素点都由集成在阵列基板中的薄膜晶体管 （Thin Fi lm Transistor: 简称 TFT)来驱动， 从而实现图像显示。 每个薄膜晶体 管可独立控制一个像素点，而不会对其他像素点造成串扰。薄膜晶体 管作为发光控制开关， 是实现 LCD和 0LED显示装置显示的关键， 直 接关系到高性能显示装置的发展方向。
薄膜晶体管主要包括栅极、 栅绝缘层、 有源层、 源极和漏极。 目前， 有源层通常采用含硅材料或金属氧化物半导体材料形成。
采用金属氧化物半导体材料作为有源层的薄膜晶体管具有较好 的开态电流和开关特性， 且迁移率高， 均匀性好， 不需要增加补偿电 路，在掩模数量和制作简易度上均有优势；金属氧化物半导体材料具 有高氧含量时能表现出很好的半导体特性，具有较低氧含量时具有较 低的电阻率， 因此可作为透明电极使用，足以用于需要快速响应和较 大电流的应用，如应用于高频、高分辨率、中大尺寸的 LCD以及 0LED 显示装置中。同时，金属氧化物半导体材料形成有源层的制作工艺简 单， 采用溅射等方法即可， 与现有的 LCD产线匹配性好， 容易转型， 不需增加额外的设备， 具有成本优势。
但是， 采用金属氧化物半导体材料作为有源层， 薄膜晶体管的 制备过程一般需采用六次以上的构图工序， 产能较低。 如图 1所示， 现有技术中采用金属氧化物半导体材料形成有源层的薄膜晶体管的 一种典型结构为： 在基板 1上设置栅极 2a， 在栅极 2a上设置栅绝缘 层 3， 在栅绝缘层 3上设置有源层 4 (即金属氧化物半导体层） ， 在 有源层 4上设置刻蚀阻挡层 5， 在刻蚀阻挡层 5上设置源极 6a和漏 极 6b，在源极 6a和漏极 6b上设置钝化层 7，在钝化层 7上设置像素 电极 8 (即 IT0透明电极层） 。
相应的， 上述结构的薄膜晶体管的制备方法为： 在基板 1 上沉 积栅极金属材料， 采用第一次构图工序形成栅极 2a; 在栅极 2a上沉 积栅绝缘层 3， 在栅绝缘层 3上沉积有源层 4， 采用第二次构图工序 形成沟槽区和源极、漏极接触区；在有源层 4上沉积刻蚀阻挡层薄膜， 采用第三次构图工序形成刻蚀阻挡层 5 ;在刻蚀阻挡层 5上沉积金属 材料， 采用第四次构图工序形成源极 6a和漏极 6b; 在源极 6a和漏 极 6b上沉积钝化层薄膜， 采用第五次构图工序形成钝化层 7以及钝 化层 7中的过孔；在钝化层 7上沉积 IT0透明电极材料，采用第六次 构图工序形成像素电极 8， 像素电极 8通过过孔与漏极 6b连接。 发明内容
本发明所要解决的技术问题是针对现有技术中存在的上述不 足， 提供一种阵列基板、 阵列基板的制备方法以及显示装置， 该阵列 基板仅需采用四次构图工序即可制备完成，且栅线与数据线由形成栅 极的同层金属层形成， 简化了阵列基板的制备过程。
基于上述目的， 本发明提供了一种阵列基板， 包括基板以及设 置于所述基板上的多条栅线和多条数据线，所述栅线与所述数据线交 叉设置且将所述基板划分为多个像素区域，每个所述像素区域内设置 有薄膜晶体管， 所述薄膜晶体管包括栅极、源极和漏极， 所述栅极与 所述栅线电连接， 所述源极与所述数据线电连接， 其中， 所述栅极、 所述栅线与所述数据线同层设置，所述数据线在与所述栅线交叉的区 域中断开， 断开的所述数据线通过与所述数据线不同层的数-数连接 线电连接。
优选的是， 所述像素区域内还设置有像素电极， 所述数-数连接 线、 所述源极、 所述漏极与所述像素电极同层设置， 所述数-数连接 线设置于与所述数据线的断开区域对应的区域中、且与断开的所述数 据线连接。
优选的是， 所述阵列基板还包括栅绝缘层和有源层， 所述栅绝 缘层设置于所述栅极与所述源极和所述漏极之间；所述有源层与所述 栅极正对设置，且位于所述栅绝缘层远离所述栅极的一侧；所述源极 与所述漏极紧邻所述有源层设置在与所述有源层的两端对应的位置 处、 且与所述栅极在正投影方向上部分重叠。
一种优选的结构是， 所述阵列基板还包括刻蚀阻挡层， 所述栅极、 所述栅线与所述数据线同层设置于所述基板上； 所述栅绝缘层设置于所述栅极、所述栅线与所述数据线的上方， 且完全覆盖所述栅极、所述栅线与所述数据线，所述栅绝缘层在与所 述数据线对应的区域中开设有第一连接线过孔和第一源 -数连接线过 孔；
所述有源层设置于所述栅绝缘层对应着所述栅极的上方， 且完 全覆盖所述栅极对应着的区域；
所述刻蚀阻挡层设置于所述有源层的上方， 所述刻蚀阻挡层在 与所述有源层的一端对应的位置处开设有源极过孔，所述刻蚀阻挡层 在与所述有源层的另一端对应的位置处开设有漏极过孔，所述刻蚀阻 挡层在与所述数据线对应的区域中开设有第二连接线过孔和第二源- 数连接线过孔；
所述数 -数连接线、 所述源极、 所述漏极与所述像素电极同层设 置于所述刻蚀阻挡层的上方，所述源极嵌入所述源极过孔从而与所述 有源层接触，所述源极嵌入所述第一源 -数连接线过孔和所述第二源- 数连接线过孔从而与所述数据线电连接， 所述数 -数连接线通过嵌入 所述第一连接线过孔和所述第二连接线过孔使得断开的多条所述数 据线电连接；所述漏极嵌入所述漏极过孔从而与所述有源层接触，所 述漏极与所述像素电极电连接。
一种优选的结构是， 所述阵列基板还包括钝化层，
所述有源层设置于所述基板上；
所述栅绝缘层设置于所述有源层的上方， 且所述有源层与所述 栅线平行方向上的相对两端未被所述栅绝缘层覆盖；
所述栅极、 所述栅线与所述数据线同层设置于所述栅绝缘层的 上方， 且所述栅极在正投影方向上的面积小于所述有源层的面积； 所述钝化层设置于所述栅极、 所述栅线与所述数据线的上方， 且完全覆盖所述栅极、所述栅线与所述数据线，所述钝化层在与所述 有源层未被所述栅绝缘层覆盖的一端相对应的位置处开设有源极过 孔，所述钝化层在与所述有源层未被所述栅绝缘层覆盖的另一端相对 应的位置处开设有漏极过孔，所述钝化层在与所述数据线对应的区域 中开设有连接线过孔和源-数连接线过孔；
所述数 -数连接线、 所述源极、 所述漏极与所述像素电极同层设 置于所述钝化层的上方，所述源极嵌入所述源极过孔从而与所述有源 层接触， 所述源极嵌入源-数连接线过孔从而与所述数据线电连接， 所述数 -数连接线通过嵌入连接线过孔使得断开的多条所述数据线电 连接；所述漏极嵌入所述漏极过孔从而与所述有源层接触，所述漏极 与所述像素电极电连接。
优选的是， 所述栅极、 所述栅线和所述数据线采用相同的材料、 且在同一构图工序中形成。
进一步优选的是， 所述栅极、 所述栅线和所述数据线均采用钼、 钼铌合金、 铝、 铝钕合金、 钛、 铬和铜中的至少一种材料形成； 所述 栅极、所述栅线和所述数据线为单层结构或多层复合叠层结构，所述 栅极、 所述栅线和所述数据线的厚度范围为 100-3000nm。
优选的是， 所述数 -数连接线、 所述源极、 所述漏极和所述像素 电极采用氧化铟镓锌、氧化铟锌、氧化铟锡、氧化铟镓锡中的至少一 种材料形成； 所述有源层采用金属氧化物半导体材料形成； 所述栅绝缘层为单层结构或多层复合叠层结构， 所述栅绝缘层 采用硅氧化物、硅氮化物、 铪氧化物、硅氮氧化物、 铝氧化物中的至 少一种材料形成；
所述刻蚀阻挡层和所述钝化层为单层结构或多层复合叠层结 构， 采用硅氧化物、硅氮化物、 铪氧化物、 铝氧化物中的至少一种材 料形成。
一种显示装置， 包括上述的阵列基板。
一种阵列基板的制备方法， 包括在基板上形成多条栅线和多条 数据线以将所述基板划分为多个像素区域的步骤，还包括在每个所述 像素区域内形成薄膜晶体管的步骤，所述薄膜晶体管包括栅极、源极 和漏极，所述栅极与所述栅线电连接，所述源极与所述数据线电连接， 在所述制备方法中，采用同一构图工序将所述栅极、所述栅线与所述 数据线形成在同层， 使所述数据线在与所述栅线交叉的区域中断开， 并将断开的所述数据线通过形成在不同层的数-数连接线与所述数据 线电连接。
一种优选方法具体包括如下步骤：
步骤 S 1 : 采用一次构图工序， 在基板上形成包括栅极、 栅线和 数据线的图形， 所述数据线在与所述栅线交叉的区域中断开；
步骤 S2 :采用一次构图工序，在完成步骤 S 1的所述基板上形成 包括栅绝缘层的图形，以及在所述栅绝缘层对应着所述栅极的上方形 成包括有源层的图形，所述栅绝缘层完全覆盖所述栅极、所述栅线和 所述数据线， 所述有源层完全覆盖所述栅极对应着的区域；
步骤 S3 :采用一次构图工序，在完成步骤 S2的所述基板上形成 包括刻蚀阻挡层的图形；
步骤 S4:采用一次构图工序，在完成步骤 S3的所述基板上形成 包括数 -数连接线、 源极、 漏极和像素电极的图形。
优选的是， 在步骤 S2中： 所述栅绝缘层在与数据线对应的区域 中形成有第一连接线过孔和第一源-数连接线过孔；在步骤 S3中：所 述刻蚀阻挡层在与所述有源层的一端对应的位置处形成有源极过孔， 所述刻蚀阻挡层在与所述数据线对应的区域中形成有第二连接线过 孔和第二源-数连接线过孔；在步骤 S4中：所述源极嵌入所述源极过 孔从而与所述有源层接触， 所述源极嵌入所述第一源-数连接线过孔 和所述第二源-数连接线过孔从而与所述数据线电连接，所述数 -数连 接线通过嵌入第一连接线过孔和第二连接线过孔使得断开的多条所 述数据线电连接；
在步骤 S3中： 所述刻蚀阻挡层在与所述有源层连接了源极的一 端相对的另一端对应的位置处形成有漏极过孔； 在步骤 S4中： 所述 漏极嵌入所述漏极过孔从而与所述有源层接触，所述漏极与所述像素 电极电连接。
一种优选方法具体包括如下步骤：
步骤 S 1 :采用一次构图工序，在基板上形成包括有源层的图形， 以及在所述有源层的上方形成包括栅绝缘层的图形，所述有源层与所 述栅线平行方向上的相对两端未被所述栅绝缘层覆盖；
步骤 S2 :采用一次构图工序，在完成步骤 S 1的所述基板上形成 包括栅极、栅线和数据线的图形，所述数据线在与所述栅线交叉的区 域中断开， 所述栅极在正投影方向上的面积小于所述有源层的面积； 步骤 S3 :采用一次构图工序，在完成步骤 S2的所述基板上形成 包括钝化层的图形；
步骤 S4:采用一次构图工序，在完成步骤 S3的所述基板上形成 包括数 -数连接线、 源极、 漏极和像素电极的图形。
优选的是， 在步骤 S3中： 所述钝化层在与所述有源层未被所述 栅绝缘层覆盖的一端相对应的位置处形成有源极过孔，所述钝化层在 与所述数据线对应的区域中形成有连接线过孔和源-数连接线过孔； 在步骤 S4中： 所述源极嵌入所述源极过孔从而与所述有源层接触， 所述源极嵌入所述源-数连接线过孔从而与所述数据线电连接， 所述 数-数连接线通过嵌入连接线过孔使得断开的多条所述数据线电连 接；
在步骤 S3中： 所述钝化层在与所述有源层未被所述栅绝缘层覆 盖的两端当中连接了源极的一端相对的另一端对应的位置处形成有 漏极过孔； 在步骤 S4中： 所述漏极嵌入所述漏极过孔从而与所述有 源层接触， 所述漏极与所述像素电极电连接。
本发明的有益效果是： 本发明的阵列基板中， 有源层采用金属 氧化物半导体材料形成，整个阵列基板仅需采用四次构图工序即可制 备完成，且栅线与数据线由形成栅极的同层金属层形成，简化了阵列 基板的制备过程， 极大地提高了产能， 节约了成本。 附图说明
图 1为现有技术中阵列基板的剖视图；
图 2-1、 2-2为本发明实施例 1中阵列基板的结构示意图； 其中，
图 2-1为阵列基板的平面图；
图 2-2为沿图 2-1所示的 D-D线的剖视图；
图 3-1至 3-8为本发明实施例 1中阵列基板的制备流程的示意 图；
其中- 图 3-1 为第一次构图工序形成包括栅极、 栅线和数据线的图形 的平面图；
图 3-2为沿图 3-1所示的 A-A线的剖视图；
图 3-3为第二次构图工序形成包括栅绝缘层、 有源层的图形的 平面图；
图 3-4为沿图 3-3所示的 B-B线的剖视图；
图 3-5为第三次构图工序形成包括刻蚀阻挡层的图形的平面图； 图 3-6为沿图 3-5所示的 C-C线的剖视图；
图 3-7为第四次构图工序形成包括数 -数连接线、 源极、 漏极和 像素电极的图形的平面图；
图 3-8为沿图 3-7所示的 D-D线的剖视图；
图 4-1、 4-2为本发明实施例 2中阵列基板的结构示意图； 其中- 图 4-1为阵列基板的平面图； 图 4-2为沿图 4-1所示的 D-D线的剖视图；
图 5-1至 5-8为本发明实施例 2中阵列基板的制备流程的示意 图；
其中- 图 5-1为第一次构图工序形成包括有源层、栅绝缘层的平面图； 图 5-2为沿图 5-1所示的 A-A线的剖视图；
图 5-3为第二次构图工序形成包括栅极、 栅线和数据线的图形 的平面图；
图 5-4为沿图 5-3所示的 B-B线向的剖视图；
图 5-5为第三次构图工序形成包括钝化层的图形的平面图； 图 5-6为沿图 5-5所示的 C-C线的剖视图；
图 5-7为第四次构图工序形成包括数 -数连接线、 源极、 漏极和 像素电极的图形的平面图；
图 5-8为沿图 5-7所示的 D-D线的剖视图；
图 6-1、 6-2为对应着图 5-1、 5-2中采用光刻胶掩模进行构图 工序的示意图；
附图标记： 1 _基板； 2a_栅极； 2b-栅线； 2c-数据线； 2d-公 共电极线； 3—栅绝缘层； 30-栅绝缘层薄膜； 4-有源层； 40-有源层 薄膜； 41-光刻胶掩模； 5-刻蚀阻挡层； 6a_源极； 6b-漏极； 7—钝 化层； 7a-源极过孔； 7b-漏极过孔； 7c-连接线过孔； 71c-第一连接 线过孔； 72c-第二连接线过孔； 7d-源-数连接线过孔； 71d-第一源- 数连接线过孔； 72d-第二源-数连接线过孔； 8—像素电极； 9一数- 数连接线。 具体实施方式
为使本领域技术人员更好地理解本发明的技术方案， 下面结合 附图和具体实施方式对本发明阵列基板、制备方法以及显示装置作进 一步详细描述。
一种阵列基板， 包括基板以及设置于基板上的多条栅线和多条 数据线，所述栅线与所述数据线交叉设置且将所述基板划分为多个像 素区域，每个所述像素区域内设置有薄膜晶体管，所述薄膜晶体管包 括栅极、源极和漏极， 所述栅极与所述栅线电连接， 所述源极与所述 数据线电连接， 其中， 栅极、 栅线与数据线同层设置， 数据线在与栅 线交叉的区域中断开， 断开的数据线通过与数据线不同层的数 -数连 接线电连接。
一种包括上述阵列基板的显示装置。
一种阵列基板的制备方法， 包括在基板上形成多条栅线和多条 数据线以将所述基板划分为多个像素区域的步骤，还包括在每个所述 像素区域内形成薄膜晶体管的步骤，所述薄膜晶体管包括栅极、源极 和漏极，所述栅极与所述栅线电连接，所述源极与所述数据线电连接， 在所述制备方法中，采用同一构图工序将所述栅极、所述栅线与所述 数据线形成在同层， 使所述数据线在与所述栅线交叉的区域中断开， 并将断开的所述数据线通过形成在不同层的数-数连接线与所述数据 线电连接。 实施例 1 :
如图 2-1和图 2-2所示， 阵列基板包括依次层叠设置于基板 1 上的多层结构， 分别为： 同层设置的栅极 2a、 数据线 2c、 栅线 2b; 栅绝缘层 3 ; 有源层 4; 刻蚀阻挡层 5 ; 以及同层设置的源极 6a、 漏 极 6b、 像素电极 8和数-数连接线 9。 其中， 栅极 2a与栅线 2b电连 接，数据线 2c与源极 6a电连接，栅线 2b与数据线 2c交叉设置且将 基板 1划分为多个像素区域。
在本实施例中， 数据线 2c在与栅线 2b交叉的区域中断开， 断 开的数据线 2c通过与数据线 2c不同层的数-数连接线 9电连接；数- 数连接线 9设置于与数据线 2c的断开区域对应的区域中、 且与断开 的数据线 2c连接。 另外， 栅绝缘层 3设置于栅极 2a与源极 6a和漏 极 6b之间；有源层 4与栅极 2a正对设置，且位于栅绝缘层 3远离栅 极 2a的一侧； 源极 6a与漏极 6b紧邻有源层 4设置在与有源层 4的 两端对应的位置处、 且与栅极 2a在正投影方向上部分重叠。
具体的， 如图 2-1和图 2-2所示， 阵列基板的结构如下： 栅极 2a、 栅线 2b和数据线 2c同层设置于基板 1上；
栅绝缘层 3设置于栅极 2a、 栅线 2b和数据线 2c的上方， 且完 全覆盖栅极 2a、 栅线 2b和数据线 2c。 栅绝缘层 3在与数据线 2c对 应的区域中开设有第一连接线过孔 71 c (对应着图 2-1中第二连接线 过孔 72c下方， 图 2-2中未具体标示） 和第一源-数连接线过孔 71d (对应着图 2-1中第二源-数连接线过孔 72d下方， 图 2-2中未具体 标示） ；
有源层 4设置于栅绝缘层 3对应着栅极 2a的上方， 且完全覆盖 栅极 2a对应着的区域；
刻蚀阻挡层 5设置于有源层 4的上方， 刻蚀阻挡层 5在与有源 层 4的一端对应的位置处开设有源极过孔 7a， 刻蚀阻挡层 5在与有 源层 4的另一端对应的位置处开设有漏极过孔 7b， 刻蚀阻挡层 5在 与数据线 2c对应的区域中开设有第二连接线过孔 72c和第二源 -数连 接线过孔 72d;
数-数连接线 9、 源极 6a、 漏极 6b与像素电极 8同层设置于刻 蚀阻挡层 5的上方，源极 6b嵌入源极过孔 7a且与有源层 4接触，源 极 6a嵌入第一源-数连接线过孔 71 d和第二源-数连接线过孔 72d来 作为用于与数据线 2c电连接的源 -数连接线， 数-数连接线 9通过嵌 入第一连接线过孔 71 c和第二连接线过孔 72c使得断开的多条数据线 2c电连接； 漏极 6b嵌入漏极过孔 7b且与有源层 4接触， 漏极 6b与 像素电极 8电连接。
优选的是， 栅极 2a、 栅线 2b和数据线 2c均采用钼 （Mo ) 、 钼 铌合金（MoNb ) 、 铝 （A1 ) 、 铝钕合金（AlNd) 、 钛（Ti ) 、 铬（Cr ) 和铜（Cu )中的至少一种材料形成，优选为钼、铝或含钼、铝的合金； 栅极 2a、栅线 2b和数据线 2c为单层或多层复合叠层结构，栅极 2a、 栅线 2b和数据线 2c的厚度范围为 100_3000nm。
源极 6a、 漏极 6b、 像素电极 8和数-数连接线 9采用氧化铟镓 锌 （IGZ0) 、 氧化铟锌 （IZ0) 、 氧化铟锡 （IT0) 、 氧化铟镓锡、 铟 镓氧化锌 （ITZ0 ) 中的至少一种材料形成。 在本实施例中， 源极 6a、 漏极 6b、像素电极 8和数-数连接线 9可选择氧化铟锡、氧化铟镓锌、 氧化铟锌、 铟镓氧化锌等透明导电材料形成。
有源层 4采用金属氧化物半导体材料形成，包括由包含铟（ In)、 镓 （Ga) 、 锌 （Zn) 、 氧 （0) 、 锡 （Sn) 等元素的材料制成， 其中 必须包含氧元素和其他两种或两种以上的元素， 如氧化铟镓锌 ( IGZ0)、氧化铟锌（ IZ0)、氧化铟锡（ InSnO)、氧化铟镓锡（ InGaSnO) 中的至少一种材料。
栅绝缘层 3为单层或多层复合叠层结构， 栅绝缘层 3采用硅氧 化物 （SiOx) 、 硅氮化物 （SiNx) 、 铪氧化物 （HfOx ) 、 硅氮氧化物 ( SiON) 、 铝氧化物 （AlOx) 中的至少一种材料形成。
刻蚀阻挡层 5 为单层或多层复合叠层结构， 采用硅氧化物 ( SiOx )、 硅氮化物（SiNx )、 铪氧化物（SiON)、 铝氧化物（AlOx) 中的至少一种材料形成。
相应的， 上述阵列基板的制备方法， 包括在基板上形成多条栅 线和多条数据线以将基板划分为多个像素区域的步骤，还包括在每个 像素区域内形成薄膜晶体管的步骤，薄膜晶体管包括栅极、源极和漏 极， 栅极与栅线电连接， 源极与数据线电连接， 在该阵列基板的制备 方法中， 采用同一构图工序将栅极、栅线与数据线形成在同层， 使数 据线在与栅线交叉的区域中断开，并将断开的数据线通过形成在不同 层的数-数连接线与数据线电连接。
在具体阐述之前， 应该理解的是， 本发明中， 构图工序， 可只 包括光刻步骤，或者可以包括光刻步骤以及刻蚀步骤， 同时还可以包 括打印、喷墨等其他用于形成预定图形的步骤；光刻工序是指包括成 模、 曝光、 显影等加工过程的利用光刻胶、掩模板、 曝光机等形成图 形的加工工序。 可根据本发明中所形成的结构选择相应的构图工序。
具体的， 该方法包括如下步骤：
步骤 S1 : 采用一次构图工序， 在基板上形成包括栅极、 栅线和 数据线的图形， 数据线在与栅线交叉的区域中断开。
在该步骤中， 如图 3-1、 图 3-2所示， 在基板 1上形成电极金属 膜， 采用一次构图工序形成包括栅极 2a、 栅线 2b和数据线 2c的图 形， 数据线 2c在与栅线 2b交叉的区域中断开。从该步骤中可知， 栅 极 2a、 栅线 2b、 数据线 2c是采用同一层电极金属膜形成的。
其中， 采用沉积、 溅射或热蒸发的方法在基板 1上形成电极金 属薄膜。
进一步的， 在阵列基板的非像素区域， 形成包括栅极 2a、 栅线 2b与数据线 2c的图形的同时，还形成有公共电极线 2d。该公共电极 线 2d留待后续加工过程中形成公共电极后用于与公共电极电连接， 这里不再详述。
其中， 剖视图 3-2为沿着平面图 3-1中 A-A线的剖视图。 这里， 为能更突出地示意本实施例中阵列基板在制备过程中的剖面结构，剖 视图 3-2与平面图 3-1的比例设置稍有不同，以下各剖视图与各平面 图与此同。
步骤 S2 :采用一次构图工序，在完成步骤 S 1的基板上形成包括 栅绝缘层的图形，以及在栅绝缘层对应着栅极的上方形成包括有源层 的图形。
在该步骤中， 如图 3-3、 图 3-4所示， 在完成步骤 S 1的基板 1 上形成栅绝缘层薄膜 （FGI Deposition) ， 即在栅极 2a、 栅线 2b和 数据线 2c的上方形成栅绝缘层薄膜； 然后在栅绝缘层薄膜的上方形 成有源层薄膜 （Act ive Deposition) 。 采用一次构图工序同时形成 包括栅绝缘层 3和有源层 4的图形， 栅绝缘层 3在与数据线 2c对应 的区域中形成有第一连接线过孔 71c和第一源-数连接线过孔 71 d。
其中， 采用等离子体增强化学气相沉积法 （Plasma Enhanced Chemi cal Vapor Deposit ion: 简称 PECVD) 形成栅绝缘层薄膜， 采 用沉积、 溅射或热蒸发等方法形成有源层薄膜。
这里， 由于栅绝缘层 3—般采用透明材料 （硅氧化物、 硅氮化 物、 铪氧化物、 硅氮氧化物、 铝氧化物）形成， 对平面图的观察不会 造成阻碍， 因此在图 3-3的平面示意图中略去栅绝缘层 3的示意，只 相应示出其中开设的连接线过孔和源-数连接线过孔的位置； 同时， 为便于了解像素区域中各层结构以及各层之间的位置关系， 平面图 3-3中的各层设置为具有一定透明度， 以下各平面图与此同。
步骤 S3 :采用一次构图工序，在完成步骤 S2的基板上形成包括 刻蚀阻挡层的图形。
在该步骤中， 如图 3-5、 图 3-6所示， 在完成步骤 S2的基板上 形成刻蚀阻挡层薄膜，采用一次构图工序形成包括刻蚀阻挡层 5的图 形。刻蚀阻挡层 5在与有源层 4的一端对应的位置处形成有源极过孔 7a,刻蚀阻挡层 5在与有源层 4的另一端对应的位置处形成有漏极过 孔 7b，刻蚀阻挡层 5在与数据线 2c对应的区域中形成有第二连接线 过孔 72c和第二源-数连接线过孔 72d。
其中， 采用沉积、 溅射、 热蒸发或用特殊的 PECVD等方法形成 刻蚀阻挡层薄膜。 蚀刻阻挡层薄膜的特点是膜层含有较低的氢含量、 并且有很好的表面特性。
步骤 S4:采用一次构图工序，在完成步骤 S3的基板上形成包括 数 -数连接线、 源极、 漏极和像素电极的图形。
在该步骤中， 如图 3-7、 图 3-8所示， 在完成步骤 S3的基板 1 上形成透明电极金属薄膜，采用一次构图工序在刻蚀阻挡层 5上与有 源层 4的一端对应的位置处形成源极 6a， 在与有源层 4的另一端对 应的位置处形成漏极 6b， 在与数据线 2c对应的区域中形成数 -数连 接线 9， 同时， 在靠近漏极 6b 的一侧形成像素电极 8， 像素电极 8 与漏极 6b电连接。
其中： 源极 6a嵌入源极过孔 7a从而与有源层 4接触， 源极 6a 嵌入第一源-数连接线过孔 71d (在图 3-7中对应着第二源-数连接线 过孔 72d的下方）和第二源-数连接线过孔 72d从而与数据线 2c电连 接， 数-数连接线 9嵌入第一连接线过孔 71c (在图 3-7中对应着第 二连接线过孔 72c的下方）和第二连接线过孔 72c使得断开的多条数 据线 2c电连接； 漏极 6b嵌入漏极过孔 7b从而与有源层 4接触， 并 且漏极 6b与像素电极 8电连接。
其中， 采用沉积、 溅射或热蒸发的方法形成电极金属薄膜， 电 极金属薄膜的厚度范围为 20-150nm。 本实施例中的电极金属薄膜采 用金属氧化物半导体， 具体的可以是： 氧化铟镓锌（IGZ0) 、 氧化铟 锌 （IZ0) 、 氧化铟锡 （IT0) 、 氧化铟镓锡 （InGaSnO) 中的至少一 种材料形成， 例如： 采用氧化铟锡 （IT0) 材料作为电极金属， 并采 用溅射成膜的步骤形成非晶态的透明电极金属薄膜，再通过退火使之 晶化。本实施例中， 由于形成薄膜晶体管的有源层采用了金属氧化物 半导体材料，使得源极与漏极之间的电子迁移率增加， 因此能获得较 好的源极与漏极之间的电子迁移率。
在本实施例中， 形成像素电极的透明电极金属薄膜还同时形成 了用于连接断开的数据线的数 -数连接线，数-数连接线通过在栅绝缘 层中开设的第一连接线过孔以及在刻蚀阻挡层中开设的第二连接线 过孔， 使得断开的多段数据线得以连接成完整的数据线。
这里应该理解的是，数-数连接线 9只要能使得断开的数据线 2c 之间互相电连接即可， 对数-数连接线 9的宽度不做限定； 同时， 为 了较好地示出数据线 2c与第二连接线过孔 72c的位置关系，在图 3-7 中数-数连接线 9的宽度略小于数据线 2c的宽度。但是，在实际生产 中，数-数连接线 9的宽度通常设计为不小于数据线 2c的宽度， 以保 证数据线 2c之间良好的导通性。
相比现有技术中采用金属氧化物半导体作为有源层时需采用六 次构图工序才能形成的阵列基板及其制备方法，本实施例的阵列基板 只需四次构图工序即可完成制备，大大简化了工序流程，节省了制备 时间。
基于实施例 1还提供了一种显示装置， 包括上述的阵列基板。 显示装置可以为： 液晶面板、 电子纸、 0LED面板、 手机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功 能的产品或部件。 实施例 2 :
在本实施例中， 阵列基板中的薄膜晶体管为顶栅型结构。
如图 4-1和图 4-2所示， 本实施例中阵列基板的结构具体如下： 有源层 4设置于基板 1上；
栅绝缘层 3设置于有源层 4的上方， 且有源层 4与栅线 2b平行 方向上的相对两端未被栅绝缘层 3覆盖；
栅极 2a、 栅线 2b与数据线 2c同层设置于栅绝缘层 3的上方， 且栅极 2a在正投影方向上的面积小于有源层 4的面积；
钝化层 7设置于栅极 2a、 栅线 2b与数据线 2c的上方， 且完全 覆盖栅极 2a、栅线 2b与数据线 2c。钝化层 7在与有源层 4未被栅绝 缘层 3覆盖的一端相对应的位置处开设有源极过孔 7a， 钝化层 7在 与有源层未被栅绝缘层 3 覆盖的另一端对应的位置处开设有漏极过 孔 7b， 钝化层 7在与数据线 2c对应的区域中开设有连接线过孔 7c 和源-数连接线过孔 7d;
数-数连接线 9、 源极 6a、 漏极 6b与像素电极 8同层设置于钝 化层 7的上方，源极 6a嵌入源极过孔 7a从而与有源层 4接触，源极 6a嵌入源-数连接线过孔 7d来作为源-数连接线从而与数据线 2c电 连接，数-数连接线 9通过嵌入连接线过孔 7c使得断开的多条数据线 2c电连接； 漏极 6b嵌入漏极过孔 7b从而与有源层 4接触， 并且漏 极 6b与像素电极 8电连接。
相应的， 如图 5-1至 5-8所示， 上述阵列基板的制备方法具体 包括如下步骤：
步骤 S 1 :采用一次构图工序，在基板上形成包括有源层的图形， 以及在有源层的上方形成包括栅绝缘层的图形，有源层与栅线平行的 方向上相对的两端未被栅绝缘层覆盖。
在该步骤中， 如图 5-1、 图 5-2所示， 采用金属氧化物半导体材 料在基板 1上方形成有源层薄膜，金属氧化物半导体材料包括氧化铟 镓锌（IGZ0)、氧化铟（In203 )、氧化锌（ZnO)或氧化铟锡锌（ITZ0) 等。
在本实施例中， 在基板 1上先后形成有源层薄膜和栅绝缘层薄 膜。采用第一次构图工序形成包括有源层 4和栅绝缘层 3的图形。其 中， 有源层 4与栅线 2b平行的方向上相对的两端未被栅绝缘层 3覆 盖， 以便于后续工序中有源层 4与源极 6a和漏极 6b的接触。
作为一种示例， 如图 6-1、 图 6-2所示， 该步骤更具体的步骤如 下：
步骤 S 11 :利用磁控溅射方式沉积厚度范围为 30-50nm的金属氧 化物半导体薄膜 （如图 6-1 中的有源层薄膜 40 ) ， 然后利用 PECVD 方式沉积厚度范围为 200-400nm的栅绝缘层薄膜（如图 6_1中的栅绝 缘层薄膜 30 ) ；
步骤 S 12 : 在栅绝缘层薄膜 30上方涂覆一层光刻胶， 并采用灰 色调掩模板或半色调掩模板对光刻胶进行曝光和显影处理，完全去除 部分光刻胶， 同时还部分保留部分光刻胶（具体的完全去除部分和部 分保留部分由有源层和栅绝缘层的图形决定） ， 形成光刻胶掩模 41， 如图 6-1所示； 然后在光刻胶掩模 41的保护下， 通过第一次干刻处 理形成包括栅绝缘层 3的部分图形，并通过湿刻处理形成包括有源层 4的图形。
步骤 S 13 : 通过灰化处理， 继续对光刻胶进行曝光、 显影， 去除 部分保留的光刻胶，形成如图 6-2所示的改变了保护范围的光刻胶掩 模 41， 然后通过第二次干刻处理形成包括栅绝缘层 3的完整图形。
步骤 S2 :采用一次构图工序，在完成步骤 S 1的基板上形成包括 栅极、栅线和数据线的图形， 数据线在与栅线交叉的区域中断开， 栅 极在正投影方向上的面积小于有源层的面积。
在该步骤中， 如图 5-3、 图 5-4所示， 利用磁控溅射方式沉积厚 度范围为 200-300nm的电极金属薄膜，采用第二次构图工序形成包括 栅极 2a、 栅线 2b和数据线 2c的图形。
在本实施例中，电极金属优选铜（Cu)，同时还可以优选铝（Al )， 钼 （Mo) 等材料。
步骤 S3 :采用一次构图工序，在完成步骤 S2的基板上形成包括 钝化层的图形。
在该步骤中， 如图 5-5、 图 5-6所示， 采用沉积、 溅射或热蒸发 的方法形成钝化层薄膜。具体的，可利用 PECVD方式沉积厚度范围为 200-400nm的钝化层薄膜， 然后形成包括钝化层 7的图形。 其中， 钝 化层 7在与有源层 4未被栅绝缘层 3覆盖的一端对应的位置处形成有 源极过孔 7a， 钝化层 7在与有源层 4未被栅绝缘层 3覆盖的另一端 对应的位置处形成有漏极过孔 7b;钝化层 7在与数据线 2c对应的区 域中形成有连接线过孔 7c和源-数连接线过孔 7d。
在本实施例中， 钝化层 7为单层或多层复合叠层结构， 采用硅 氧化物 （SiOx ) 、 硅氮化物 （SiNx ) 、 铪氧化物 （SiON) 、 铝氧化物 ( AlOx ) 中的至少一种材料形成。
这里， 由于钝化层 7—般采用透明材料（硅氧化物、 硅氮化物、 铪氧化物、硅氮氧化物、 铝氧化物）形成， 对平面图的观察不会造成 阻碍， 因此在图 5-5的平面示意图中略去钝化层 7的示意，只相应示 出其中开设的源极过孔、 漏极过孔、 数据线过孔和源-数连接线过孔 的位置； 同时，为便于了解像素区域中各层结构以及各层之间的位置 关系，平面图 5-5中的各层设置为具有一定透明度， 以下各平面图与 此同。
步骤 S4:采用一次构图工序，在完成步骤 S3的基板上形成包括 数 -数连接线、 源极、 漏极和像素电极的图形。
在该步骤中， 如图 5-7、 图 5-8所示， 利用磁控溅射方式沉积厚 度范围为 30-200nm的透明电极金属薄膜， 采用第四次构图工序形成 包括数-数连接线 9、 源极 6a、 漏极 6b和像素电极 8的图形。
其中， 源极 6a嵌入源极过孔 7a从而与有源层 4接触， 源极 6a 嵌入源-数连接线过孔 7d从而与数据线 2c 电连接， 数-数连接线 9 通过嵌入连接线过孔 7c使得断开的多条数据线 2c电连接； 漏极 6b 嵌入漏极过孔 7b从而与有源层 4接触， 并且漏极 6b与像素电极 8 电连接。 采用本发明中的阵列基板， 可很方便地形成 TN ( Twi sted Neraati c , 扭曲向列） 模式、 VA ( Vertical Al ignment , 垂直取向） 模式的液晶显示装置， 还可以形成 0LED显示装置。
同时， 作为一种变型， 本领域的技术人员很容易想到， 在本发 明阵列基板的基础上，在透明的像素电极的下方或上方，加入透明的 电极金属薄膜形成公共电极， 也即 ADS ( ADvanced Super Dimension Switch, 高级超维场转换技术）模式等其他模式。其中， ADS模式为： 通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状 电极层间产生的电场形成多维电场，使液晶盒内狭缝电极间、电极正 上方所有取向液晶分子都能够产生旋转，从而提高了液晶分子工作效 率并增大了透光效率。 同样应该理解是， 变型的阵列基板中， 像素电 极可以为板状也可以为狭缝状，相应的，公共电极可以为狭缝状也可 以为板状，只要保证处于上方的电极为狭缝状、处于下方的电极为板 状即可。高级超维场转换技术可以提高 LCD产品的画面品质，具有高 分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低色差、 无挤压水 波紋 （push Mura) 等优点。 本发明的阵列基板中， 有源层采用金属氧化物半导体材料形成， 整个阵列基板仅需采用四次构图工序即可制备完成，且栅线与数据线 由形成栅极的同层金属层形成，简化了阵列基板的制备过程，极大地 提高了产能， 节约了成本。 可以理解的是， 以上实施方式仅仅是为了说明本发明的原理而 采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的 普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做 出各种变型和改进， 这些变型和改进也视为本发明的保护范围。

Claims

权利要求
1. 一种阵列基板， 包括基板以及设置于所述基板上的多条栅线 和多条数据线，所述栅线与所述数据线交叉设置且将所述基板划分为 多个像素区域，每个所述像素区域内设置有薄膜晶体管，所述薄膜晶 体管包括栅极、源极和漏极， 所述栅极与所述栅线电连接， 所述源极 与所述数据线电连接， 所述阵列基板的特征在于， 所述栅极、所述栅 线与所述数据线同层设置，所述数据线在与所述栅线交叉的区域中断 开， 断开的所述数据线通过与所述数据线不同层的数-数连接线电连 接。
2. 根据权利要求 1所述的阵列基板， 其特征在于， 所述像素区 域内还设置有像素电极， 所述数 -数连接线、 所述源极、 所述漏极与 所述像素电极同层设置， 所述数-数连接线设置于与所述数据线的断 开区域对应的区域中、 且与断开的所述数据线连接。
3. 根据权利要求 2所述的阵列基板， 其特征在于， 所述阵列基 板还包括栅绝缘层和有源层，所述栅绝缘层设置于所述栅极与所述源 极和所述漏极之间；所述有源层与所述栅极正对设置，且位于所述栅 绝缘层远离所述栅极的一侧；所述源极与所述漏极紧邻所述有源层设 置在与所述有源层的两端对应的位置处、且与所述栅极在正投影方向 上部分重叠。
4. 根据权利要求 3所述的阵列基板， 其特征在于， 所述阵列基 板还包括刻蚀阻挡层，
所述栅极、 所述栅线与所述数据线同层设置于所述基板上； 所述栅绝缘层设置于所述栅极、所述栅线与所述数据线的上方， 且完全覆盖所述栅极、所述栅线与所述数据线，所述栅绝缘层在与所 述数据线对应的区域中开设有第一连接线过孔和第一源 -数连接线过 孔； 所述有源层设置于所述栅绝缘层对应着所述栅极的上方， 且完 全覆盖所述栅极对应着的区域；
所述刻蚀阻挡层设置于所述有源层的上方， 所述刻蚀阻挡层在 与所述有源层的一端对应的位置处开设有源极过孔，所述刻蚀阻挡层 在与所述有源层的另一端对应的位置处开设有漏极过孔，所述刻蚀阻 挡层在与所述数据线对应的区域中开设有第二连接线过孔和第二源- 数连接线过孔；
所述数 -数连接线、 所述源极、 所述漏极与所述像素电极同层设 置于所述刻蚀阻挡层的上方，所述源极嵌入所述源极过孔从而与所述 有源层接触，所述源极嵌入所述第一源 -数连接线过孔和所述第二源- 数连接线过孔从而与所述数据线电连接， 所述数 -数连接线通过嵌入 所述第一连接线过孔和所述第二连接线过孔使得断开的多条所述数 据线电连接；所述漏极嵌入所述漏极过孔从而与所述有源层接触，并 且所述漏极与所述像素电极电连接。
5. 根据权利要求 2所述的阵列基板， 其特征在于， 所述阵列基 板还包括有源层， 栅绝缘层和钝化层，
所述有源层设置于所述基板上；
所述栅绝缘层设置于所述有源层的上方， 且所述有源层与所述 栅线平行方向上的相对两端未被所述栅绝缘层覆盖；
所述栅极、 所述栅线与所述数据线同层设置于所述栅绝缘层的 上方， 且所述栅极在正投影方向上的面积小于所述有源层的面积； 所述钝化层设置于所述栅极、 所述栅线与所述数据线的上方， 且完全覆盖所述栅极、所述栅线与所述数据线，所述钝化层在与所述 有源层未被所述栅绝缘层覆盖的一端相对应的位置处开设有源极过 孔，所述钝化层在与所述有源层未被所述栅绝缘层覆盖的另一端相对 应的位置处开设有漏极过孔，所述钝化层在与所述数据线对应的区域 中开设有连接线过孔和源-数连接线过孔；
所述数 -数连接线、 所述源极、 所述漏极与所述像素电极同层设 置于所述钝化层的上方，所述源极嵌入所述源极过孔从而与所述有源 层接触， 所述源极嵌入源-数连接线过孔从而与所述数据线电连接， 所述数 -数连接线通过嵌入连接线过孔使得断开的多条所述数据线电 连接；所述漏极嵌入所述漏极过孔从而与所述有源层接触，并且所述 漏极与所述像素电极电连接。
6. 根据权利要求 1-5中任一项所述的阵列基板， 其特征在于， 所述栅极、所述栅线和所述数据线采用相同的材料、且在同一构图工 序中形成。
7. 根据权利要求 6所述的阵列基板， 其特征在于， 所述栅极、 所述栅线和所述数据线均采用钼、 钼铌合金、 铝、 铝钕合金、 钛、 铬 和铜中的至少一种材料形成；所述栅极、所述栅线和所述数据线为单 层结构或多层复合叠层结构，所述栅极、所述栅线和所述数据线的厚 度范围为 100-3000nm。
8. 根据权利要求 1一 5中任一项所述的阵列基板， 其特征在于， 所述数 -数连接线、 所述源极、 所述漏极和所述像素电极采用氧化铟 镓锌、 氧化铟锌、 氧化铟锡、 氧化铟镓锡中的至少一种材料形成。
9. 根据权利要求 3— 5中任一项所述的阵列基板， 其特征在于， 所述有源层采用金属氧化物半导体材料形成。
10. 根据权利要求 3— 5中任一项所述的阵列基板，其特征在于， 所述栅绝缘层为单层结构或多层复合叠层结构，所述栅绝缘层采用硅 氧化物、 硅氮化物、 铪氧化物、硅氮氧化物、 铝氧化物中的至少一种 材料形成。
11 . 根据权利要求 4所述的阵列基板， 其特征在于， 所述刻蚀 阻挡层为单层结构或多层复合叠层结构， 采用硅氧化物、 硅氮化物、 铪氧化物、 铝氧化物中的至少一种材料形成。
12. 根据权利要求 5所述的阵列基板， 其特征在于， 所述钝化 层为单层结构或多层复合叠层结构， 采用硅氧化物、硅氮化物、铪氧 化物、 铝氧化物中的至少一种材料形成。
13. 一种显示装置， 其特征在于， 包括权利要求 1-12任一项所 述的阵列基板。
14. 一种阵列基板的制备方法， 包括在基板上形成多条栅线和 多条数据线以将所述基板划分为多个像素区域的步骤，还包括在每个 所述像素区域内形成薄膜晶体管的步骤， 所述薄膜晶体管包括栅极、 源极和漏极，所述栅极与所述栅线电连接，所述源极与所述数据线电 连接， 所述制备方法的特征在于， 采用同一构图工序将所述栅极、所 述栅线与所述数据线形成在同层，使所述数据线在与所述栅线交叉的 区域中断开， 并将断开的所述数据线通过形成在不同层的数-数连接 线与所述数据线电连接。
15. 根据权利要求 14所述的制备方法， 其特征在于， 该方法具 体包括如下步骤：
步骤 S 1 : 采用一次构图工序， 在基板上形成包括栅极、 栅线和 数据线的图形， 所述数据线在与所述栅线交叉的区域中断开；
步骤 S2 :采用一次构图工序，在完成步骤 S 1的所述基板上形成 包括栅绝缘层的图形，以及在所述栅绝缘层对应着所述栅极的上方形 成包括有源层的图形，所述栅绝缘层完全覆盖所述栅极、所述栅线和 所述数据线， 所述有源层完全覆盖所述栅极对应着的区域；
步骤 S3 :采用一次构图工序，在完成步骤 S2的所述基板上形成 包括刻蚀阻挡层的图形；
步骤 S4:采用一次构图工序，在完成步骤 S3的所述基板上形成 包括数 -数连接线、 源极、 漏极和像素电极的图形。
16. 根据权利要求 15所述的制备方法， 其特征在于， 在步骤 S2 中：所述栅绝缘层在与数据线对应的区域中形成有第一连接线过孔和 第一源-数连接线过孔；在步骤 S3中：所述刻蚀阻挡层在与所述有源 层的一端对应的位置处形成有源极过孔，所述刻蚀阻挡层在与所述数 据线对应的区域中形成有第二连接线过孔和第二源-数连接线过孔； 在步骤 S4中： 所述源极嵌入所述源极过孔从而与所述有源层接触， 所述源极嵌入所述第一源-数连接线过孔和所述第二源 -数连接线过 孔从而与所述数据线电连接， 所述数-数连接线通过嵌入第一连接线 过孔和第二连接线过孔使得断开的多条所述数据线电连接；
在步骤 S3中： 所述刻蚀阻挡层在与所述有源层连接了源极的一 端相对的另一端对应的位置处形成有漏极过孔； 在步骤 S4中： 所述 漏极嵌入所述漏极过孔从而与所述有源层接触，所述漏极与所述像素 电极电连接。
17. 根据权利要求 14所述的制备方法， 其特征在于， 该方法具 体包括如下步骤：
步骤 S 1 :采用一次构图工序，在基板上形成包括有源层的图形， 以及在所述有源层的上方形成包括栅绝缘层的图形，所述有源层与所 述栅线平行方向上的相对两端未被所述栅绝缘层覆盖；
步骤 S2 :采用一次构图工序，在完成步骤 S 1的所述基板上形成 包括栅极、栅线和数据线的图形，所述数据线在与所述栅线交叉的区 域中断开， 所述栅极在正投影方向上的面积小于所述有源层的面积； 步骤 S3 :采用一次构图工序，在完成步骤 S2的所述基板上形成 包括钝化层的图形；
步骤 S4:采用一次构图工序，在完成步骤 S3的所述基板上形成 包括数 -数连接线、 源极、 漏极和像素电极的图形。
18. 根据权利要求 17所述的制备方法， 其特征在于， 在步骤 S3 中：所述钝化层在与所述有源层未被所述栅绝缘层覆盖的一端相对应 的位置处形成有源极过孔，所述钝化层在与所述数据线对应的区域中 形成有连接线过孔和源-数连接线过孔；在步骤 S4中：所述源极嵌入 所述源极过孔从而与所述有源层接触， 所述源极嵌入所述源-数连接 线过孔从而与所述数据线电连接， 所述数 -数连接线通过嵌入连接线 过孔使得断开的多条所述数据线电连接；
在步骤 S3中： 所述钝化层在与所述有源层未被所述栅绝缘层覆 盖的两端当中连接了源极的一端相对的另一端对应的位置处形成有 漏极过孔； 在步骤 S4中： 所述漏极嵌入所述漏极过孔从而与所述有 源层接触， 并且所述漏极与所述像素电极电连接。
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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367248A (zh) * 2013-07-01 2013-10-23 京东方科技集团股份有限公司 阵列基板、制备方法以及显示装置
CN103681696A (zh) 2013-12-24 2014-03-26 京东方科技集团股份有限公司 一种电极引出结构、阵列基板以及显示装置
CN103985714B (zh) * 2013-12-31 2017-02-01 上海天马微电子有限公司 阵列基板及其制造方法
CN103943636A (zh) * 2014-04-04 2014-07-23 深圳莱宝高科技股份有限公司 一种薄膜晶体管阵列基板及其制作方法
CN104064601B (zh) * 2014-06-30 2017-12-26 上海天马微电子有限公司 Tft、tft阵列基板及其制造方法、显示面板、显示装置
CN104157613B (zh) 2014-07-31 2017-03-08 京东方科技集团股份有限公司 一种阵列基板的制备方法
CN104393020B (zh) 2014-11-21 2017-07-04 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN105977205B (zh) * 2016-05-10 2019-10-15 京东方科技集团股份有限公司 薄膜晶体管、阵列基板的制备方法、阵列基板及显示装置
CN105977266A (zh) * 2016-07-18 2016-09-28 深圳市华星光电技术有限公司 Tft基板及其制作方法
CN109698204B (zh) * 2017-10-24 2021-09-07 元太科技工业股份有限公司 驱动基板及显示装置
TWI659254B (zh) 2017-10-24 2019-05-11 元太科技工業股份有限公司 驅動基板及顯示裝置
CN110148601B (zh) * 2019-05-31 2022-12-20 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置
CN112654917B (zh) * 2019-07-26 2023-10-13 京东方科技集团股份有限公司 显示基板、显示装置、显示基板的制作方法及驱动方法
CN111403423B (zh) * 2020-03-27 2023-04-14 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板和显示装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080018821A1 (en) * 2004-11-12 2008-01-24 Park Yong I Liquid crystal display device and method of fabricating the same
CN103022149A (zh) * 2012-12-14 2013-04-03 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及制造方法和显示器件
CN103367248A (zh) * 2013-07-01 2013-10-23 京东方科技集团股份有限公司 阵列基板、制备方法以及显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100194679B1 (ko) * 1996-05-21 1999-07-01 윤종용 박막 트랜지스터 및 그 제조 방법
KR101013625B1 (ko) * 2003-12-23 2011-02-10 엘지디스플레이 주식회사 액정표시소자 및 그 제조방법
KR20070002933A (ko) * 2005-06-30 2007-01-05 엘지.필립스 엘시디 주식회사 폴리 박막 트랜지스터 기판 및 그 제조 방법
CN203503657U (zh) * 2013-07-01 2014-03-26 京东方科技集团股份有限公司 阵列基板以及显示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080018821A1 (en) * 2004-11-12 2008-01-24 Park Yong I Liquid crystal display device and method of fabricating the same
CN103022149A (zh) * 2012-12-14 2013-04-03 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及制造方法和显示器件
CN103367248A (zh) * 2013-07-01 2013-10-23 京东方科技集团股份有限公司 阵列基板、制备方法以及显示装置

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