WO2014187113A1 - 阵列基板及制备方法、显示装置 - Google Patents

阵列基板及制备方法、显示装置 Download PDF

Info

Publication number
WO2014187113A1
WO2014187113A1 PCT/CN2013/089144 CN2013089144W WO2014187113A1 WO 2014187113 A1 WO2014187113 A1 WO 2014187113A1 CN 2013089144 W CN2013089144 W CN 2013089144W WO 2014187113 A1 WO2014187113 A1 WO 2014187113A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
substrate
drain
pixel electrode
array substrate
Prior art date
Application number
PCT/CN2013/089144
Other languages
English (en)
French (fr)
Inventor
徐向阳
金玟秀
王凯
Original Assignee
合肥京东方光电科技有限公司
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 合肥京东方光电科技有限公司, 京东方科技集团股份有限公司 filed Critical 合肥京东方光电科技有限公司
Priority to US14/355,463 priority Critical patent/US20150214253A1/en
Publication of WO2014187113A1 publication Critical patent/WO2014187113A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the pixel electrode is mainly charged by a switch of a thin film transistor (TFT) provided on the array substrate, thereby realizing liquid crystal deflection.
  • TFT thin film transistor
  • other types of display panels such as electroluminescent display panels
  • thin film transistors are also required to drive the pixels for display.
  • the parasitic capacitance C gd between the gate and the drain of the TFT, the parasitic capacitance C gd pulls down the pixel voltage at the moment when the TFT is turned on, thereby causing an increase in power consumption of the array substrate, so that the picture quality is also improved. affected. Summary of the invention
  • Embodiments of the present invention provide an array substrate, a preparation method, and a display device, which can reduce parasitic capacitance between a gate and a drain, thereby reducing power consumption of the array substrate and improving picture display quality.
  • an embodiment of the present invention provides an array substrate, including: a substrate substrate; a patterned gate metal layer, a gate insulating layer, a patterned semiconductor active layer, a source/drain metal layer, and a pixel electrode; And the organic transparent insulating layer is disposed between the patterned gate metal layer and the pixel electrode.
  • an embodiment of the present invention provides a display device, including: the above array substrate; and a color filter substrate, and the array substrate pair.
  • an embodiment of the present invention provides a method for fabricating an array substrate, including: preparing a substrate; forming a patterned gate metal layer, a gate insulating layer, and a patterned semiconductor active layer on the substrate; a source/drain metal layer, and a pixel electrode, further comprising: forming an organic transparent insulating layer between the patterned gate metal layer and the pixel electrode, the patterned gate metal layer including a gate and a gate line
  • the patterned source/drain metal layer includes a source and a drain.
  • FIG. 1 is a schematic diagram of a process for preparing an array substrate according to Embodiment 1 of the present invention
  • FIG. 8 to FIG. 9 are schematic diagrams showing a process for preparing an array substrate according to Embodiment 2 of the present invention
  • FIG. 10 to FIG. 12 are schematic diagrams showing the process of fabricating another array substrate according to Embodiment 3 of the present invention. detailed description
  • Embodiments of the present invention provide a method of fabricating an array substrate, the method comprising: forming a patterned gate metal layer, a gate insulating layer, a patterned semiconductor active layer, a source/drain metal layer, and The pixel electrode further includes: forming an organic transparent insulating layer between the patterned gate metal layer and the pixel electrode.
  • the patterned source/drain metal layer includes a source and a drain
  • the patterned gate metal layer includes a gate and a gate line
  • the material of the organic transparent insulating layer may be a photoresist (PR) material, and the material of the organic transparent insulating layer may be a high transmittance organic transparent insulating material, so as to avoid the influence of the organic transparent insulating layer.
  • PR photoresist
  • the organic transparent insulating layer has a thickness of 2000A to 5000A.
  • C parallel plate capacitance
  • ⁇ is the dielectric constant
  • S is the parallel plate d
  • the area, d is the spacing of the parallel plates. It can be seen from the formula that the size of the capacitor is proportional to the area of overlap of the parallel plates, proportional to the dielectric constant of the medium, and inversely proportional to the spacing of the parallel plates. It can be seen that when the embodiment of the present invention forms an organic transparent insulating layer between the gate metal layer and the pixel electrode, The distance between the gate electrode and the pixel electrode is connected to the drain electrode, thereby reducing the parasitic capacitance c gd between the gate and the drain, thereby reducing the power consumption of the array substrate and improving the picture. Display quality.
  • the organic transparent insulating layer is formed under the patterned source/drain metal layer, that is, when the organic transparent insulating layer is formed first to form the patterned source/drain metal layer, due to process limitations ⁇ / RTI> may affect the formation of the source/drain metal layer pattern, and thus, exemplarily, the organic transparent insulating layer is formed between the patterned source/drain metal layer and the pixel electrode; A via that exposes the drain is connected to the drain.
  • the pixel electrode is connected to the drain through the via hole exposing the drain.
  • the patterned source/drain metal layer including the drain is formed first, and then formed. Patterning the other layers on the source/drain metal layer, and then forming a pixel electrode, and forming a via hole exposing the drain electrode for other layers on the source/drain metal layer, so that the pixel electrode formed later passes the exposed drain A via is connected to the drain.
  • an oxide semiconductor has been widely used in the field of liquid crystal display because of its high electron mobility and good uniformity. Therefore, when the semiconductor active layer is an oxide semiconductor active layer, The method further includes: forming an etch stop layer on a side of the semiconductor active layer opposite the substrate substrate.
  • the material of the oxide semiconductor active layer may be: ZnO, InZnO, ZnSnO, GalnZnO or ZrlnZnO.
  • an embodiment of the present invention forms an etch barrier, for example, over the active layer of the oxide semiconductor.
  • the layer is used to avoid affecting the active layer of the oxide semiconductor when etching the metal layer on the active layer of the oxide semiconductor in a subsequent process, and also avoiding oxygen or water exposed to the outside of the active layer of the oxide semiconductor The reaction in turn leads to a change in the characteristics of the thin film transistor.
  • an etch stop layer is formed on a side of the semiconductor active layer opposite to the base substrate, specifically, the oxide semiconductor is formed first.
  • the active layer is formed to form the etch stop layer, and the rest of the cases are analogous and will not be described in detail.
  • Embodiment 1 provides a method for preparing an array substrate, including the following steps:
  • the patterned gate metal layer includes a gate electrode l1 and a gate line (Fig. Not shown in the), and the gate line lead l lb.
  • a thickness can be prepared on the base substrate 10 using a magnetron sputtering method.
  • the metal material can usually be a metal such as molybdenum, aluminum, an aluminum-nickel alloy, a molybdenum-tungsten alloy, chromium, or copper, or a combination of films of the above materials. Then, using a mask to perform a patterning process such as exposure, development, etching, and peeling, forming a gate electrode 1 la, a gate line (marked in the drawing), and a gate line l ib on a certain region of the substrate. The patterned gate metal layer.
  • film refers to a film formed by depositing or other processes on a substrate. If the “film” does not require a patterning process throughout the manufacturing process, the “film” may also be referred to as a “layer”; if the “film” still requires a patterning process throughout the manufacturing process, it is referred to as "before the patterning process”. The film " is called a "layer” after the patterning process.
  • the patterning process generally comprises: coating a photoresist on the film, exposing the photoresist by using a mask, removing the photoresist to be removed by using a developing solution, and etching away the uncovered photoresist. The film portion is finally stripped of the remaining photoresist.
  • step S101 is completed to form a gate insulating layer 12 as shown in FIG.
  • the thickness of the substrate can be continuously deposited on the substrate by chemical vapor deposition.
  • the material of the insulating film is usually silicon nitride, and silicon oxide, silicon oxynitride or the like can also be used.
  • An oxide semiconductor thin film is formed on the substrate of the step S102, and the oxide semiconductor active layer 13 as shown in FIG. 3 is formed by a patterning process.
  • an oxide semiconductor thin film having a thickness of 50 ⁇ 80 ⁇ may be deposited on the substrate by chemical vapor deposition.
  • the material of the active layer of the oxide semiconductor may be ZnO, InZnO, ZnSnO, GalnZnO or ZrlnZnO.
  • the oxide semiconductor active layer 13 is formed on a certain region of the substrate by a patterning process such as exposure, development, etching, and lift-off using a mask.
  • step S104 Form an inorganic thin film on the substrate on which step S103 is completed, and pass through a patterning process.
  • the etch stop layer 14 as shown in FIG. 4 is formed.
  • the etch barrier layer includes a first via hole 14a and a second via hole 14b exposing the oxide semiconductor active layer 13, and a third via hole 14c exposing the gate line lead ib.
  • an inorganic thin film having a thickness of 500 A to 2000 A may be deposited on the substrate, and the material of the inorganic thin film may be, for example, SiOx. Then, an etch stop layer 14 is formed on a certain area of the substrate by a masking process such as exposure, development, etching, and peeling using a mask.
  • the gate insulating layer 12 is further formed over the gate line lead ib, and the third via hole
  • the gate via layer 12 is also etched out of the via hole exposing the gate line lead ib while etching the third via hole 14c.
  • a metal thin film is formed on the substrate on which step S104 is completed, and a patterned source/drain metal layer as shown in FIG. 5 is formed by one patterning process.
  • the patterned source/drain metal layer includes: a source 15a contacting the oxide semiconductor active layer 13 through the first via 14a, and the oxide via the second via 14b The drain electrode 15b that the semiconductor active layer 13 contacts, the metal pattern 15c electrically connected to the gate line lead 1 ib through the third via hole 14c, and the data line 15d and the data line lead 15e.
  • a metal thin film having a thickness of 1000 A to 6000 A can be prepared on a substrate by a magnetron sputtering method. Then, the patterned source/drain metal layer is formed on the substrate by a patterning process such as exposure, development, etching, and lift-off using a mask.
  • step S105 Form an organic transparent insulating film on the substrate on which step S105 is completed, and form an organic transparent insulating layer 16 as shown in FIG. 6 by one patterning process; wherein the organic transparent insulating layer 16 includes a portion exposing the drain 15b.
  • step S105 Form an organic transparent insulating film on the substrate on which step S105 is completed, and form an organic transparent insulating layer 16 as shown in FIG. 6 by one patterning process; wherein the organic transparent insulating layer 16 includes a portion exposing the drain 15b.
  • Four vias 16a are examples of vias 16a.
  • the organic transparent insulating layer 16 further includes a via hole exposing the metal pattern 15c and the data line lead 15e.
  • an organic transparent insulating film having a thickness of 2000 A to 5000 A may be deposited on the substrate, and then the organic transparent insulating layer is formed on the substrate by a masking process such as exposure, development, etching, and peeling. 16.
  • step S107 Form a transparent conductive film on the substrate on which step S106 is completed, and pass a patterning work.
  • the art process forms the pixel electrode 17 as shown in FIG. 7; wherein the pixel electrode 17 is connected to the drain 15b through the fourth via hole 16a.
  • a transparent conductive film having a thickness of between 100A and 1000A may be deposited on the substrate by chemical vapor deposition.
  • the transparent conductive film may be made of ITO (Indium Tin Oxides). Or ⁇ (Indium Zinc Oxide).
  • the pixel electrode 17 is formed on a certain area of the substrate by a patterning process such as exposure, development, etching, and peeling using a mask.
  • the first embodiment of the present invention is only a method for preparing an array substrate.
  • the embodiment of the present invention is not limited thereto, and may be another method for preparing an array substrate, for example, a top gate array substrate may also be included.
  • the organic transparent insulating layer may be formed only between the source/drain metal layer and the pixel electrode.
  • the distance between the gate electrode and the pixel electrode is correspondingly increased, and the formula of the capacitor is known.
  • the parasitic capacitance between the gate and the pixel electrode can be reduced, and since the pixel electrode is connected to the drain, the purpose of reducing the parasitic capacitance C gd between the gate and the drain can be achieved, thereby reducing the array substrate. Power consumption improves picture display quality.
  • the array substrate provided by the embodiment of the invention is suitable for the production of an advanced super-dimensional field conversion technology type liquid crystal display device.
  • the advanced super-dimensional field conversion technology its core technical characteristics are described as:
  • the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer form a multi-dimensional electric field, so that the inside of the liquid crystal cell All the aligned liquid crystal molecules between the slit electrodes and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, push mura, etc. advantage.
  • the method according to the first embodiment of the present invention further includes: forming a passivation layer and a common electrode on the base substrate, wherein the pixel electrode and the common electrode are respectively Formed on both sides of the passivation layer; wherein the pixel electrode is connected to the drain through a via hole exposing the drain.
  • the pixel electrode is formed between the passivation layer and the organic transparent insulating layer, and the common electrode is formed on a side of the passivation layer opposite to the substrate substrate; or The common electrode is formed between the passivation layer and the organic transparent insulating layer, and the pixel electrode Formed on a side of the passivation layer opposite to the substrate of the substrate.
  • This embodiment provides a method for preparing an array substrate, and the steps in the first embodiment are
  • the method further includes the following steps:
  • the passivation layer includes a via hole exposing the metal pattern 15c and the data line lead 15e.
  • a passivation layer film having a thickness of from 2000A to 4000A may be applied over the entire substrate, and the material of the passivation layer film is usually silicon nitride or a transparent organic resin material.
  • the passivation layer 18 is then formed on the substrate by a patterning process such as exposure, development, etching, and lift-off using a mask.
  • a transparent conductive film is formed on the substrate on which step S201 is completed, and a common electrode 19 as shown in FIG. 9 is formed by one patterning process.
  • a retention pattern connected to the metal pattern 15c and the data line lead 15e is also formed.
  • the wiring density of the common electrode can be increased, and parasitic capacitance between the common electrode and the data line can be avoided.
  • the advanced super-dimensional field conversion technology can improve the picture quality of the TFT-LCD product, and has high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, There is no advantage such as squeeze Mura; on the other hand, since an organic transparent insulating layer is added between the source/drain metal layer and the pixel electrode, the parasitic capacitance C between the gate and the drain can be reduced.
  • the purpose of gd is to reduce the power consumption of the array substrate and improve the display quality of the screen.
  • the embodiment provides a method for preparing an array substrate.
  • the method includes the steps S101-S106 of the first embodiment, and further includes the following steps:
  • a transparent conductive film is formed on the substrate on which the above step S106 is completed, and the common electrode 19 shown in FIG. 10 is formed by one patterning process.
  • 5302 forming a passivation layer film on the substrate on which step S301 is completed, and forming a passivation layer 18 as shown in FIG. 11 by one patterning process; wherein the passivation layer 18 includes a fifth pass exposing the drain 15b. Hole 18a.
  • the passivation layer 18 further includes a via hole exposing the metal pattern 15c and the data line lead 15e.
  • a transparent conductive film is formed on the substrate on which step S302 is completed, and a pixel electrode 17 as shown in FIG. 12 is formed by one patterning process, and the pixel electrode 17 passes through the fourth via hole 16a and the fifth via hole. 18a is connected to the drain 15b.
  • a retention pattern in the same layer as the first electrode 17 is formed, the retention pattern passing through the via hole exposing the metal pattern 15c and the data line lead 15e The metal pattern and the data line lead are electrically connected.
  • the method for fabricating the array substrate provided by the third embodiment of the present invention differs from the second embodiment in the order in which the pixel electrode and the common electrode are formed. It can be seen that whether the pixel electrode is formed first or the common electrode is formed first, as long as an organic transparent insulating layer is formed between the pixel electrode layer and the source/drain metal layer, the parasitic capacitance C gd between the gate and the drain can be reduced. Thereby, the power consumption of the array substrate can be reduced, thereby improving the picture display quality.
  • an embodiment of the present invention further provides an array substrate.
  • the array substrate includes: a substrate substrate 10; a patterned gate metal layer, a gate insulating layer 12, and a patterning
  • the semiconductor active layer 13, the source/drain metal layer, and the pixel electrode are disposed on the base substrate, wherein the organic transparent insulating layer 16 is disposed between the patterned gate metal layer and the pixel electrode 17.
  • the patterned gate metal layer includes a gate electrode 11a, and further includes a gate line, a gate line lead 1 ib, and the like; the patterned source/drain metal layer includes a source 15a and a drain 15b, and further includes a data line 15d. , data line lead 15e, etc.
  • the material of the organic transparent insulating layer may be a photoresist (PR) material, and the material of the organic transparent insulating layer may be a high transmittance organic transparent insulating material, so as to avoid the influence of the organic transparent insulating layer.
  • PR photoresist
  • the organic transparent insulating layer may have a thickness of 2000A to 5000A.
  • parallel plate capacitance C ie C oc
  • S is the parallel plate
  • the area, d is the spacing of the parallel plates.
  • the size of the capacitor is proportional to the area of overlap of the parallel plates, proportional to the dielectric constant of the medium, and inversely proportional to the spacing of the parallel plates. Therefore, when the organic transparent insulating layer is disposed between the gate metal layer and the pixel electrode, the distance between the gate electrode and the pixel electrode is increased, and the pixel electrode is connected to the drain electrode. Therefore, the purpose of reducing the parasitic capacitance C gd between the gate and the drain can be achieved, thereby reducing the power consumption of the array substrate and improving the picture display quality.
  • the source may be due to process limitations.
  • the formation of the drain metal layer pattern affects, and thus, exemplarily, the organic transparent insulating layer 16 is disposed between the source/drain metal layer and the pixel electrode 17; the pixel electrode 17 is disposed at the drain 15b The upper via is connected to the drain 15b.
  • the array substrate further includes an etch barrier layer 14 disposed on a side of the semiconductor active layer opposite to the substrate substrate.
  • the material of the oxide semiconductor active layer may be: ZnO, InZnO, ZnSnO, GalnZnO or ZrlnZnO.
  • the embodiment of the present invention is on the substrate of the oxide semiconductor active layer 13
  • An etch stop layer 14 is formed on the opposite side of the substrate for avoiding the influence of the metal layer on the active layer of the oxide semiconductor in the subsequent process, and also avoiding the active of the oxide semiconductor.
  • the layer is exposed to oxygen or water in the air to cause changes in the characteristics of the thin film transistor.
  • the array substrate provided by the embodiment of the invention can be applied to an advanced super-dimensional field conversion technology type display device, so that the display device has high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, No squeezing water ripples and other advantages.
  • the array substrate further includes: a passivation layer 18 and a common electrode 19 , and the pixel electrode 17 and the common electrode 19 are respectively disposed on the passivation layer 18 .
  • Both sides of the pixel electrode 17 are connected to the drain electrode 15b through a via hole provided above the drain electrode 15b.
  • the pixel electrode 17 is disposed between the passivation layer 18 and the organic transparent insulating layer 16
  • the common electrode 19 is disposed on the passivation layer 18 .
  • the common electrode 19 is disposed between the passivation layer 18 and the organic transparent insulating layer 16, and the pixel electrode 17 is disposed on the blunt The side of the layer opposite the substrate.
  • Embodiments of the present invention provide an array substrate, including: a patterned gate metal layer, a gate insulating layer, a patterned semiconductor active layer, a source/drain metal layer, and a pixel electrode disposed on a substrate; Including an organic transparent insulating layer disposed between the gate metal layer and the pixel electrode; due to the addition of an organic transparent insulating layer between the source/drain metal layer and the pixel electrode layer, between the gate and the pixel electrode The distance is also increased correspondingly, and since the pixel electrode is connected to the drain, the purpose of reducing the parasitic capacitance c gd between the gate and the drain can be achieved, thereby reducing the power consumption of the array substrate and thereby improving the picture. Display quality.
  • the embodiment of the invention further provides a display device comprising a color filter substrate and an array substrate behind the box, wherein the array substrate may be an array substrate of any of the above.
  • the display device may be a product or component having any display function such as a liquid crystal display, a liquid crystal television, a digital camera, a mobile phone, a tablet computer or the like.

Abstract

提供一种阵列基板及制备方法、显示装置，涉及显示技术领域，用于显示装置的制造，可降低栅极与漏极之间的寄生电容，从而降低阵列基板的功耗，进而提高画面显示品质。该阵列基板包括：设置在衬底基板（10）上图案化了的栅金属层（11a、11b）、半导体有源层（13）、源漏金属层（15a、15b、15c、15d、15e）以及像素电极（17），还包括设置在所述栅金属层（11a、11b）与所述像素电极（17）之间的有机透明绝缘层（16）。

Description

阵列基板及制备方法、 显示装置 技术领域
本发明的实施例涉及一种阵列基板及制备方法、 显示装置。 背景技术
随着薄膜晶体管液晶显示器 （TFT-LCD , Thin Film Transistor-Liquid Crystal Display ) 的不断发展， 画面质量越来越受到重视。
对于目前的液晶显示器， 主要靠设置在阵列基板上的薄膜晶体管（ TFT ) 的开关对像素电极充电， 从而实现液晶偏转。 对于其他类型的显示面板， 如 电致发光显示面板， 也需要薄膜晶体管驱动像素进行显示。 然而， 由于 TFT 的栅极和漏极之间存在寄生电容 Cgd,使得在 TFT导通瞬间，该寄生电容 Cgd 会将像素电压拉低， 从而导致阵列基板的功耗增加， 使得画面质量也受到影 响。 发明内容
本发明的实施例提供一种阵列基板及制备方法、 显示装置， 可降低栅极 与漏极之间的寄生电容， 从而降低阵列基板的功耗， 提高画面显示品质。
一方面， 本发明的实施例提供一种阵列基板， 包括： 衬底基板； 图案化 的栅金属层、 栅绝缘层、 图案化的半导体有源层、 源漏金属层、 以及像素电 极， 设置在所述衬底基板上； 以及有机透明绝缘层， 设置在所述图案化的栅 金属层与所述像素电极之间。
另一方面， 本发明的实施例提供一种显示装置， 包括： 上述的阵列基板； 以及彩膜基板， 与所述阵列基板对盒。
再一方面， 本发明的实施例提供一种阵列基板的制备方法， 包括： 制备 衬底基板； 在衬底基板上形成图案化的栅金属层、 栅极绝缘层、 图案化的半 导体有源层、 源漏金属层、 以及像素电极， 其中还包括： 在所述图案化的栅 金属层与所述像素电极之间形成有机透明绝缘层， 所述图案化的栅金属层包 括栅极和栅线， 所述图案化的源漏金属层包括源极和漏极。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1〜图 7为本发明实施例一提供的一种制备阵列基板的过程示意图； 图 8〜图 9为本发明实施例二提供的一种制备阵列基板的过程示意图； 以及
图 10〜图 12为本发明实施例三提供的另一种阵列基板的制备方法的过 程示意图。 具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而 不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有做 出创造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例提供了一种阵列基板的制备方法， 该方法包括： 在衬底基 板上形成图案化的栅金属层、 栅极绝缘层、 图案化的半导体有源层、 源漏金 属层、 以及像素电极； 进一步还包括： 在所述图案化的栅金属层与所述像素 电极之间形成有机透明绝缘层。
其中， 在本发明实施例中， 所述图案化的源漏金属层包括源极和漏极， 所述图案化的栅金属层包括栅极和栅线。
所述有机透明绝缘层的材料可以为一种光刻胶（PR )材料， 这里所述有 机透明绝缘层的材料可以为高透过率有机透明绝缘材料， 这样可以避免所述 有机透明绝缘层影响显示面板的透过率。
示例性地， 所述有机透明绝缘层的厚度为 2000A ~5000A。 根据平行板电容 C的公式， 即 C oC 其中 ε为介电系数， S为平行板 d
的面积， d 为平行板的间距。 由公式可知， 电容大小与平行板的重叠面积成 正比， 与介质的介电系数成正比， 与平行板的间距成反比。 由此可知， 当本 发明实施例在栅金属层与所述像素电极之间形成有机透明绝缘层时， 增加了 栅极与像素电极之间的距离， 又由于像素电极与所述漏极相连， 因而可实现 降低栅极与漏极之间的寄生电容 cgd的目的， 进而可降低阵列基板功耗， 提 高画面显示品质。
考虑到当所述有机透明绝缘层形成在所述图案化的源漏金属层下方时， 即， 先形成所述有机透明绝缘层再形成所述图案化的源漏金属层时， 由于工 艺的限制， 可能会对源漏金属层图案的形成造成影响， 因此， 示例性地， 在 所述图案化的源漏金属层与所述像素电极之间形成所述有机透明绝缘层； 所 述像素电极通过暴露漏极的过孔与所述漏极相连。
此处需要说明的是， 所述像素电极通过暴露漏极的过孔与所述漏极相连 是指， 在本发明实施例中先形成包括漏极的图案化的源漏金属层， 再形成位 于图案化的源漏金属层上的其他层， 然后形成像素电极， 对于位于源漏金属 层上的其他层需形成露出所述漏极的过孔， 以使后形成的像素电极通过露出 所述漏极的过孔与所述漏极相连。
示例性地， 氧化物半导体由于其具有电子迁移率高、 均一性好等特点， 已被广泛应用于液晶显示领域， 因此， 当所述半导体有源层为氧化物半导体 有源层时， 所述方法还包括： 在所述半导体有源层的与所述衬底基板相反的 一侧形成刻蚀阻挡层。
其中， 所述氧化物半导体有源层的材料可以为： ZnO、 InZnO、 ZnSnO、 GalnZnO或 ZrlnZnO等。
由于氧化物半导体有源层， 其材料暴露在外容易与空气中的氧气或水反 应从而导致薄膜晶体管特性发生变化， 因此， 本发明实施例例如在所述氧化 物半导体有源层上方形成刻蚀阻挡层， 用于避免在后续工艺中刻蚀氧化物半 导体有源层上的金属层时对氧化物半导体有源层造成影响， 也可避免氧化物 半导体有源层暴露在外与空气中的氧气或水反应进而导致薄膜晶体管特性的 变化。
此处需要说明的是， 在本发明的实施例中， 在所述半导体有源层的与所 述衬底基板相反的一侧形成刻蚀阻挡层， 具体是指， 先形成所述氧化物半导 体有源层， 再形成所述刻蚀阻挡层， 其余情况依次类推， 不再详述。
下面将提供一具体实施例， 以详细描述上述的阵列基板的制作过程。 实施例一 本实施例提供了一种阵列基板的制备方法， 包括如下步骤：
5101、 在衬底基板 10上制作金属薄膜， 通过一次构图工艺处理形成如 图 1所示的图案化的栅金属层； 其中所述图案化的栅金属层包括栅极 l la、 栅线（图中未标出） 、 以及栅线引线 l lb。
示例性地， 可以使用磁控溅射方法， 在衬底基板 10上制备一层厚度在
2000A~5000A的金属薄膜。 金属材料通常可以采用钼、 铝、 铝镍合金、 钼钨 合金、 铬、 或铜等金属， 也可以使用上述几种材料薄膜的组合结构。 然后， 用掩模板通过曝光、 显影、 刻蚀、 剥离等构图工艺处理， 在衬底基板的一定 区域上形成包括栅极 l la、 栅线（图中为标出） 、 以及栅线引线 l ib的图案 化的栅金属层。
此处需要说明的是， "薄膜" 是指将某一种材料在衬底基板上利用沉积 或其他工艺制作出的一层薄膜。 若在整个制作过程当中该 "薄膜" 无需构图 工艺， 则该 "薄膜" 还可以称为 "层" ； 若在整个制作过程当中该 "薄膜" 还需构图工艺， 则在构图工艺前称为 "薄膜" ， 构图工艺后称为 "层" 。
其中， 构图工艺通常包括： 在薄膜上涂光刻胶， 利用掩模板对所述光刻 胶进行曝光， 再利用显影液将需要去除的光刻胶去除掉， 再刻蚀掉未覆盖光 刻胶的薄膜部分， 最后将剩下的光刻胶剥离。
5102、 在完成步骤 S101的基板上制作绝缘薄膜， 形成如图 2所示的栅 绝缘层 12。
示例性地， 可以利用化学气相沉积法在衬底基板上连续沉积厚度为
2000A~5000A的绝缘薄膜， 绝缘薄膜的材料通常是氮化硅， 也可以使用氧化 硅和氮氧化硅等。
5103、 在完成步骤 S102 的衬底基板上制作氧化物半导体薄膜， 通过一 次构图工艺处理形成如图 3所示的氧化物半导体有源层 13。
示例性地， 可以利用化学气相沉积法在基板上沉积厚度为 50θΑ~80θΑ 的氧化物半导体薄膜， 通常氧化物半导体有源层的材料可以采用 ZnO、 InZnO、 ZnSnO、 GalnZnO或 ZrlnZnO等。 然后， 用掩模板通过曝光、 显影、 刻蚀、 剥离等构图工艺处理， 在基板的一定区域上形成所述氧化物半导体有 源层 13。
S104、 在完成步骤 S103 的基板上制作无机薄膜， 通过一次构图工艺处 理形成如图 4所示的刻蚀阻挡层 14。
其中，所述刻蚀阻挡层包括露出所述氧化物半导体有源层 13的第一过孔 14a和第二过孔 14b, 以及露出所述栅线引线 l ib的第三过孔 14c。
示例性地， 可以在基板上沉积厚度为 500A~2000A的无机薄膜， 该无机 薄膜的材料例如可以为 SiOx。 然后， 用掩模板通过曝光、 显影、 刻蚀、 剥离 等构图工艺处理， 在基板的一定区域上形成刻蚀阻挡层 14。
这样， 可以避免在后续工艺中刻蚀氧化物半导体有源层上的金属层时对 氧化物半导体有源层造成影响， 也可避免氧化物半导体有源层暴露在外与空 气中的氧气或水反应进而导致薄膜晶体管特性发生变化。
此处， 由于在所述栅线引线 l ib上方还形成有栅绝缘层 12, 且第三过孔
14c露出栅线引线 l ib, 因此，这里在刻蚀出第三过孔 14c的同时也将栅绝缘 层 12刻蚀出露出栅线引线 l ib的过孔。
5105、 在完成步骤 S104的基板上制作金属薄膜， 通过一次构图工艺处 理形成如图 5所示的图案化的源漏金属层。
其中， 所述图案化的源漏金属层包括： 通过所述第一过孔 14a与所述氧 化物半导体有源层 13接触的源极 15a,通过所述第二过孔 14b与所述氧化物 半导体有源层 13接触的漏极 15b,通过所述第三过孔 14c与所述栅线引线 l ib 电连接的金属图案 15c, 以及数据线 15d, 数据线引线 15e。
示例性地， 可以使用磁控溅射方法， 在基板上制备一层厚度在 1000A~6000A的金属薄膜。 然后， 用掩模板通过曝光、 显影、 刻蚀、 剥离等 构图工艺处理， 在基板上形成图案化的所述源漏金属层。
5106、 在完成步骤 S105 的基板上制作有机透明绝缘薄膜， 通过一次构 图工艺处理形成如图 6所示的有机透明绝缘层 16;其中所述有机透明绝缘层 16包括露出所述漏极 15b的第四过孔 16a。
此外，所述有机透明绝缘层 16还包括露出所述金属图案 15c和所述数据 线引线 15e的过孔。
具体的，可以在基板上沉积一层厚度在 2000A~5000A的有机透明绝缘薄 膜， 然后， 用掩模板通过曝光、 显影、 刻蚀、 剥离等构图工艺处理， 在基板 上形成所述有机透明绝缘层 16。
S107、 在完成步骤 S106的基板上制作透明导电薄膜， 通过一次构图工 艺处理形成如图 7所示的像素电极 17; 其中所述像素电极 17通过所述第四 过孔 16a与所述漏极 15b相连。
示例性地， 可以使用化学气相沉积法， 在基板上沉积一层厚度在 100A 至 1000A之间的透明导电薄膜， 通常所述透明导电薄膜的材料可以采用 ITO ( Indium Tin Oxides ,铟锡氧化物）或 ΙΖΟ ( Indium Zinc Oxide,铟辞氧化物）。 然后， 用掩模板通过曝光、 显影、 刻蚀、 剥离等构图工艺处理， 在基板的一 定区域上形成所述像素电极 17。
需要说明的是， 本发明实施例一仅是其中一种阵列基板的制备方法， 本 发明实施例并不限于此， 也可以是阵列基板的其他的制备方法， 例如还可以 包括顶栅型阵列基板的制备方法，不管是哪种制备方法，在本发明实施例中， 只需在所述源漏金属层与所述像素电极之间形成所述有机透明绝缘层即可。
在本发明实施例中， 由于在源漏金属层与所述像素电极之间增加了有机 透明绝缘层， 使得栅极与像素电极之间的距离也相应的增加了， 由电容的公 式可知， 这样便可降低栅极与像素电极之间的寄生电容， 又由于像素电极与 所述漏极相连， 因而可实现降低栅极与漏极之间的寄生电容 Cgd的目的， 进 而降低了阵列基板的功耗， 提高了画面显示品质。
本发明实施例提供的阵列基板适用于高级超维场转换技术型液晶显示装 置的生产。 其中， 高级超维场转换技术， 其核心技术特性描述为： 通过同一 平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电 场形成多维电场， 使液晶盒内狭缝电极间、 电极正上方所有取向液晶分子都 能够产生旋转， 从而提高了液晶工作效率并增大了透光效率。 高级超维场转 换技术可以提高 TFT-LCD产品的画面品质， 具有高分辨率、 高透过率、 低 功耗、 宽视角、 高开口率、 低色差、 无挤压水波纹（push Mura )等优点。
示例性地， 对于高级超维场转换技术型液晶显示装置， 根据本发明实施 例一的方法还包括： 在衬底基板上形成钝化层以及公共电极， 所述像素电极 和所述公共电极分别形成于所述钝化层两侧； 其中， 所述像素电极通过暴露 所述漏极的过孔与所述漏极连接。
进一步可选的， 所述像素电极形成于所述钝化层与所述有机透明绝缘层 之间，所述公共电极形成于所述钝化层的与所述衬底基板相反的一侧；或者， 所述公共电极形成于所述钝化层与所述有机透明绝缘层之间， 所述像素电极 形成于所述钝化层的与所述村底基板相反的一侧。
下面将提供两个具体实施例， 以详细描述上述的适用于高级超维场转换 技术型液晶显示装置的阵列基板的制作过程。
实施例二
本实施例提供了一种阵列基板的制备方法， 在上述实施例一的步骤
S101-S107的基础上， 所述方法还包括如下步骤：
S201、 在完成上述步骤 S107的基板上制作钝化层薄膜， 通过一次构图 工艺处理形成如图 8所示的钝化层 18。
其中， 所述钝化层包括露出所述金属图案 15c和所述数据线引线 15e的 过孔。
示例性地，可以在整个基板上涂覆一层厚度在 2000A到 4000A的钝化层 薄膜， 所述钝化层薄膜的材料通常是氮化硅或透明的有机树脂材料。 然后用 掩模板通过曝光、 显影、 刻蚀、 剥离等构图工艺处理， 在基板上形成所述钝 化层 18。
S202、 在完成步骤 S201 的基板上制作透明导电薄膜， 通过一次构图工 艺处理形成如图 9所示的公共电极 19。
此外，在形成所述公共电极 19时，还形成与所述金属图案 15c和所述数 据线引线 15e连接的保留图案。
此处， 由于有机透明绝缘层 16的存在， 可以提高公共电极的布线密度， 而避免公共电极与数据线之间产生寄生电容。
在本发明实施例中， 一方面， 高级超维场转换技术可以提高 TFT-LCD 产品的画面品质， 具有高分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低色差、 无挤压水波纹（push Mura )等优点； 另一方面， 由于在源漏金属层 与所述像素电极之间增加了有机透明绝缘层， 可实现降低栅极与漏极之间的 寄生电容 Cgd的目的， 进而降低了阵列基板的功耗， 提高了画面显示品质。
实施例三
本实施例提供了一种阵列基板的制备方法， 该方法包括上述实施例一的 步骤 S101-S106的基础上， 还包括如下步骤：
S301、 在完成上述步骤 S106的基板上制作透明导电薄膜， 通过一次构 图工艺处理形成如图 10所示的公共电极 19。 5302、 在完成步骤 S301 的基板上制作钝化层薄膜， 通过一次构图工艺 处理形成如图 11所示的钝化层 18;其中所述钝化层 18包括露出所述漏极 15b 的第五过孔 18a。
此外， 所述钝化层 18还包括露出所述金属图案 15c和所述数据线引线 15e的过孔。
5303、 在完成步骤 S302 的基板上制作透明导电薄膜， 通过一次构图工 艺处理形成如图 12所示的像素电极 17,所述像素电极 17通过所述第四过孔 16a和所述第五过孔 18a与所述漏极 15b连接。
此外， 在形成所述像素电极 17的同时， 还形成与所述第一电极 17同层 的保留图案， 该保留图案通过露出所述金属图案 15c和所述数据线引线 15e 的过孔与所述金属图案和所述数据线引线电连接。
通过上述的描述可知， 本发明实施例三提供的阵列基板的制备方法与实 施例二的不同在于， 像素电极和公共电极的形成顺序。 由此可知， 不管是先 形成像素电极还是先形成公共电极， 只要在像素电极层和源漏金属层之间形 成有机透明绝缘层， 便可降低栅极与漏极之间的寄生电容 Cgd, 从而可降低 阵列基板的功耗， 进而提高了画面显示品质。
另外， 本发明实施例还提供了一种阵列基板， 参考图 8、 图 11和图 12 所示， 该阵列基板包括： 衬底基板 10; 图案化的栅金属层、 栅绝缘层 12、 图 案化的半导体有源层 13、 源漏金属层， 以及像素电极， 设置在所述衬底基板 上， 其中有机透明绝缘层 16设置在所述图案化的栅金属层与所述像素电极 17之间。
其中， 所述图案化的栅金属层包括栅极 11a,还包括栅线、栅线引线 l ib 等； 所述图案化的源漏金属层包括源极 15a和漏极 15b, 还包括数据线 15d、 数据线引线 15e等。
所述有机透明绝缘层的材料可以为一种光刻胶（PR )材料， 这里所述有 机透明绝缘层的材料可为高透过率有机透明绝缘材料， 这样可以避免所述有 机透明绝缘层影响显示面板的透过率。
示例性地， 所述有机透明绝缘层的厚度可以为 2000A ~5000A。 根据平行板电容 C的公式， 即 C oc ， 其中 为介电系数， S为平行板 的面积， d为平行板的间距。 由公式可知， 电容大小与平行板的重叠面积成 正比， 与介质的介电系数成正比， 与平行板的间距成反比。 由此可知， 当本 发明实施例在栅金属层与所述像素电极之间设置有机透明绝缘层时， 增加了 栅极与像素电极之间的距离， 又由于像素电极与所述漏极相连， 因而可实现 降低栅极与漏极之间的寄生电容 Cgd的目的， 进而可降低阵列基板功耗， 提 高画面显示品质。
考虑到当所述有机透明绝缘层 16形成在所述源漏金属层下方时， 即，先 形成所述有机透明绝缘层再形成所述源漏金属层时， 由于工艺的限制， 可能 会对源漏金属层图案的形成造成影响， 因此， 示例性地， 所述有机透明绝缘 层 16设置于所述源漏金属层与所述像素电极 17之间；所述像素电极 17通过 设置在漏极 15b上方的过孔与所述漏极 15b连接。
示例性地， 氧化物半导体由于其具有电子迁移率高、 均一性好等特点， 已被广泛应用于液晶显示领域， 因此， 如图 8、 图 11和图 12所示， 当所述 半导体有源层 13为氧化物半导体有源层时，所述阵列基板还包括：设置在所 述半导体有源层的与所述衬底基板相反的一侧的刻蚀阻挡层 14。
其中， 所述氧化物半导体有源层的材料可以为： ZnO、 InZnO、 ZnSnO、 GalnZnO或 ZrlnZnO等。
由于氧化物半导体有源层 13,其材料暴露在外容易与空气中的氧气或水 反应从而导致薄膜晶体管特性发生变化， 因此， 本发明实施例在所述氧化物 半导体有源层 13的与衬底基板相反的一侧形成刻蚀阻挡层 14, 用于避免在 后续工艺中刻蚀氧化物半导体有源层上的金属层时对氧化物半导体有源层造 成影响， 也可避免氧化物半导体有源层暴露在外与空气中的氧气或水反应进 而导致薄膜晶体管特性的变化。
本发明实施例提供的阵列基板可适用于高级超维场转换技术型显示装 置， 从而使得该显示装置具有高分辨率、 高透过率、 低功耗、 宽视角、 高开 口率、 低色差、 无挤压水波纹等优点。
因此， 示例性地， 如图 11和图 12所示， 所述阵列基板还包括： 钝化层 18以及公共电极 19,所述像素电极 17和所述公共电极 19分设于所述钝化层 18的两侧； 所述像素电极 17通过设置在所述漏极 15b上方的过孔与所述漏 极 15b连接。 进一步可选的， 如图 11所示， 所述像素电极 17设置于所述钝化层 18 与所述有机透明绝缘层 16之间 ,所述公共电极 19设置于所述钝化层 18的与 衬底基板相反的一侧； 或者， 如图 12所示， 所述公共电极 19设置于所述钝 化层 18与所述有机透明绝缘层 16之间，所述像素电极 17设置于所述钝化层 的与衬底基板相反的一侧。
本发明实施例提供了一种阵列基板， 包括： 设置在衬底基板上的图案化 了的栅金属层、 栅绝缘层、 图案化的半导体有源层、 源漏金属层、 以及像素 电极， 还包括设置在所述栅金属层与所述像素电极之间的有机透明绝缘层； 由于在源漏金属层与所述像素电极层之间增加了有机透明绝缘层， 使得栅极 与像素电极之间的距离也相应的增加了， 又由于像素电极与所述漏极相连， 因而可实现降低栅极与漏极之间的寄生电容 cgd的目的， 从而可降低阵列基 板的功耗， 进而提高画面显示品质。
本发明实施例还提供一种显示装置，包括对盒后的彩膜基板和阵列基板， 其中， 所述阵列基板可以是上述的任一种的阵列基板。 所述显示装置可以为 液晶显示器、 液晶电视、 数码相机、 手机、 平板电脑等具有任何显示功能的 产品或者部件。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护 范围应以所述权利要求的保护范围为准。

Claims

权利要求书
1、 一种阵列基板， 包括：
衬底基板；
图案化的栅金属层、 栅绝缘层、 图案化的半导体有源层、 源漏金属层、 以及像素电极， 设置在所述衬底基板上； 以及，
有机透明绝缘层， 设置在所述图案化的栅金属层与所述像素电极之间。
2、根据权利要求 1所述的阵列基板，其中所述图案化的栅金属层包括栅 极和栅线， 所述图案化的源漏金属层包括源极和漏极。
3、根据权利要求 2所述的阵列基板，其中所述有机透明绝缘层设置于所 述图案化的源漏金属层与所述像素电极之间，
所述像素电极通过暴露所述漏极的过孔与所述漏极连接。
4、根据权利要求 2或 3所述的阵列基板，其中所述阵列基板还包括钝化 层以及公共电极， 所述像素电极和所述公共电极分设于所述钝化层的两侧； 所述像素电极通过暴露所述漏极的过孔与所述漏极连接。
5、根据权利要求 4所述的阵列基板，其中所述像素电极设置于所述钝化 层与所述有机透明绝缘层之间， 所述公共电极设置于所述钝化层的与所述衬 底基板相反的一侧； 或者，
所述公共电极设置于所述钝化层与所述有机透明绝缘层之间， 所述像素 电极设置于所述钝化层的与所述衬底基板相反的一侧。
6、 根据权利要求 2或 3所述的阵列基板， 还包括： 刻蚀阻挡层， 形成在 所述半导体有源层的与所述衬底基板相反的一侧， 所述半导体有源层为氧化 物半导体有源层。
7、根据权利要求 2或 3所述的阵列基板，其中所述有机透明绝缘层的厚 度为 2000A ~5000A。
8、根据权利要求 6所述的阵列基板，其中所述氧化物半导体有源层的材 料为： ZnO、 InZnO、 ZnSnO、 GalnZnO或 ZrInZnO。
9、根据权利要求 2或 3所述的衬底基板，其中所述阵列基板为顶栅型阵 列基板或底栅型阵列基板。
10、 一种显示装置， 包括： 阵列基板， 如权利要求 1-3中任一项所述； 以及
彩膜基板， 与所述阵列基板对盒。
11、 一种阵列基板的制备方法， 包括：
制备衬底基板；
在衬底基板上形成图案化的栅金属层、 栅极绝缘层、 图案化的半导体有 源层、 源漏金属层、 以及像素电极，
其中还包括： 在所述图案化的栅金属层与所述像素电极之间形成有机透 明绝缘层，
所述图案化的栅金属层包括栅极和栅线， 所述图案化的源漏金属层包括 源极和漏极。
12、根据权利要求 11所述的方法，其中所述在所述图案化的栅金属层与 所述像素电极之间形成有机透明绝缘层包括： 在所述图案化的源漏金属层与 所述像素电极之间形成所述有机透明绝缘层； 所述像素电极通过暴露所述漏 极的过孔与所述漏极相连。
13、 根据权利要求 11或 12所述的方法， 所述方法还包括： 在所述衬底 基板上形成钝化层以及公共电极， 所述像素电极和所述公共电极分别形成于 所述钝化层两侧； 其中， 所述像素电极通过暴露所述漏极的过孔与所述漏极 连接。
14、根据权利要求 13所述的方法，其中所述像素电极形成于所述钝化层 与所述有机透明绝缘层之间， 所述公共电极形成于所述钝化层的与所述衬底 基板相反的一侧； 或者，
所述公共电极形成于所述钝化层与所述有机透明绝缘层之间， 所述像素 电极形成于所述钝化层的与所述衬底基板相反的一侧。
15、 根据权利要求 11或 12所述的方法， 其中所述方法还包括： 在所述 半导体有源层的与所述衬底基板相反的一侧形成刻蚀阻挡层， 其中， 所述半 导体有源层为氧化物半导体有源层。
16、 根据权利要求 11或 12所述的方法， 其中所述有机透明绝缘层的厚 度为 2000A ~5000A。
17、 根据权利要求 11或 12所述的方法， 其中所述阵列基板是顶栅型阵 列基板或底栅型阵列基板。
18、根据权利要求 15所述方法，其中所述氧化物半导体有源层的材料为： ZnO、 InZnO、 ZnSnO、 GalnZnO或 ZrInZnO。
19、根据权利要求 15所述的方法，其中在所述阵列基板是底栅型阵列基 板的情况下， 所述在所述衬底基板上形成图案化的栅金属层、 栅极绝缘层、 图案化的半导体有源层、 源漏金属层、 以及像素电极包括：
在所述衬底基板上制作金属薄膜， 通过一次构图工艺形成所述图案化的 栅金属层；
在完成上述步骤的衬底基板上制作绝缘薄膜， 形成所述栅绝缘层； 在完成上述步骤的衬底基板上制作氧化物半导体薄膜， 通过一次构图工 艺形成所述图案化的半导体有源层；
在完成上述步骤的衬底基板上制作无机薄膜， 通过一次构图工艺形成所 述刻蚀阻挡层， 其中所述刻蚀阻挡层包括暴露所述漏极的过孔；
在完成上述步骤的衬底基板上制作金属薄膜， 通过一次构图工艺形成所 述图案化的源漏金属层；
在完成上述步骤的衬底基板上制作有机透明绝缘薄膜， 通过一次构图工 艺形成所述有机透明绝缘层， 其中所述有机透明绝缘层包括露出所述漏极的 过孔；
在完成上述步骤的衬底基板上制作透明导电薄膜， 通过一次构图工艺形 成所述像素电极， 其中所述像素电极通过露出所述漏极的过孔与所述漏极相 连。
20、 根据权利要求 19所述的方法， 还包括：
在完成上述步骤的衬底基板上形成钝化层；
在所述钝化层上形成公共电极。
PCT/CN2013/089144 2013-05-23 2013-12-11 阵列基板及制备方法、显示装置 WO2014187113A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/355,463 US20150214253A1 (en) 2013-05-23 2013-12-11 Array substrate, manufacturing method thereof and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310195242.6 2013-05-23
CN2013101952426A CN103325792A (zh) 2013-05-23 2013-05-23 一种阵列基板及制备方法、显示装置

Publications (1)

Publication Number Publication Date
WO2014187113A1 true WO2014187113A1 (zh) 2014-11-27

Family

ID=49194450

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/089144 WO2014187113A1 (zh) 2013-05-23 2013-12-11 阵列基板及制备方法、显示装置

Country Status (3)

Country Link
US (1) US20150214253A1 (zh)
CN (1) CN103325792A (zh)
WO (1) WO2014187113A1 (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103325792A (zh) * 2013-05-23 2013-09-25 合肥京东方光电科技有限公司 一种阵列基板及制备方法、显示装置
CN103489876B (zh) 2013-09-27 2016-07-06 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN103730475B (zh) 2013-12-26 2016-08-31 京东方科技集团股份有限公司 一种阵列基板及其制造方法、显示装置
KR102132445B1 (ko) * 2013-12-31 2020-07-09 엘지디스플레이 주식회사 액정 디스플레이 패널 및 이의 제조 방법
CN104037126A (zh) * 2014-05-16 2014-09-10 京东方科技集团股份有限公司 一种阵列基板的制备方法、阵列基板和显示装置
CN104966721B (zh) * 2015-07-15 2018-10-02 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板和显示装置
CN105487285B (zh) * 2016-02-01 2018-09-14 深圳市华星光电技术有限公司 阵列基板及阵列基板的制备方法
CN105826249B (zh) 2016-04-11 2019-08-06 京东方科技集团股份有限公司 金属层制作方法、功能基板及其制作方法、以及显示装置
CN106483726B (zh) * 2016-12-21 2023-07-25 昆山龙腾光电股份有限公司 薄膜晶体管阵列基板及制作方法和液晶显示面板
WO2020143024A1 (zh) * 2019-01-11 2020-07-16 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板
CN110459475A (zh) * 2019-07-23 2019-11-15 南京中电熊猫平板显示科技有限公司 一种薄膜晶体管及其制造方法
CN110600483A (zh) * 2019-08-30 2019-12-20 南京中电熊猫平板显示科技有限公司 一种阵列基板及其制造方法
CN111048532B (zh) * 2020-01-03 2022-09-27 深圳市华星光电半导体显示技术有限公司 阵列基板、其制作方法及显示面板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080157080A1 (en) * 2006-07-17 2008-07-03 Unidym, Inc. Transparent and Conductive Nanostructure-Film Pixel Electrode and Method of Making the Same
CN102645808A (zh) * 2012-04-20 2012-08-22 京东方科技集团股份有限公司 一种阵列基板的制造方法、阵列基板及显示装置
CN103325792A (zh) * 2013-05-23 2013-09-25 合肥京东方光电科技有限公司 一种阵列基板及制备方法、显示装置

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5032883A (en) * 1987-09-09 1991-07-16 Casio Computer Co., Ltd. Thin film transistor and method of manufacturing the same
CN100424575C (zh) * 1995-08-11 2008-10-08 夏普株式会社 透射型液晶显示器件
DE19712233C2 (de) * 1996-03-26 2003-12-11 Lg Philips Lcd Co Flüssigkristallanzeige und Herstellungsverfahren dafür
JP3340353B2 (ja) * 1996-08-20 2002-11-05 松下電器産業株式会社 液晶画像表示装置の製造方法と液晶画像表示装置
US6011274A (en) * 1997-10-20 2000-01-04 Ois Optical Imaging Systems, Inc. X-ray imager or LCD with bus lines overlapped by pixel electrodes and dual insulating layers therebetween
TW583492B (en) * 2003-04-17 2004-04-11 Hannstar Display Corp Manufacturing method for LCD panel with high aspect ratio
US7298084B2 (en) * 2004-11-02 2007-11-20 3M Innovative Properties Company Methods and displays utilizing integrated zinc oxide row and column drivers in conjunction with organic light emitting diodes
KR20070059559A (ko) * 2005-12-07 2007-06-12 삼성전자주식회사 표시 장치 및 그 제조 방법
CN101393363B (zh) * 2007-09-21 2010-06-09 北京京东方光电科技有限公司 Ffs型tft-lcd阵列基板结构及其制造方法
JP2009079166A (ja) * 2007-09-27 2009-04-16 Fujifilm Corp 中空粒子、その製造方法および感熱転写受像シート
KR101286544B1 (ko) * 2008-07-11 2013-07-17 엘지디스플레이 주식회사 액정표시장치 및 그 제조방법
KR101540341B1 (ko) * 2008-10-17 2015-07-30 삼성전자주식회사 패널 구조체, 패널 구조체를 포함하는 표시장치 및 이들의 제조방법
CN101847641B (zh) * 2009-03-27 2011-12-28 京东方科技集团股份有限公司 阵列基板及其制造方法和宽视角液晶显示器
CN102023430B (zh) * 2009-09-17 2012-02-29 京东方科技集团股份有限公司 Ffs型tft-lcd阵列基板及其制造方法
KR20130011856A (ko) * 2011-07-22 2013-01-30 삼성디스플레이 주식회사 표시기판 및 그 제조방법
KR101841770B1 (ko) * 2011-09-02 2018-03-26 엘지디스플레이 주식회사 산화물 박막 트랜지스터를 구비한 평판 표시장치 및 그의 제조방법
KR101894328B1 (ko) * 2011-10-06 2018-09-03 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 그 제조 방법
CN102651371A (zh) * 2012-04-06 2012-08-29 北京京东方光电科技有限公司 阵列基板及其制作方法和显示装置
WO2014054569A1 (ja) * 2012-10-03 2014-04-10 シャープ株式会社 半導体装置及び表示装置
CN102981335A (zh) * 2012-11-15 2013-03-20 京东方科技集团股份有限公司 像素单元结构、阵列基板和显示装置
KR102022396B1 (ko) * 2013-02-20 2019-09-19 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080157080A1 (en) * 2006-07-17 2008-07-03 Unidym, Inc. Transparent and Conductive Nanostructure-Film Pixel Electrode and Method of Making the Same
CN102645808A (zh) * 2012-04-20 2012-08-22 京东方科技集团股份有限公司 一种阵列基板的制造方法、阵列基板及显示装置
CN103325792A (zh) * 2013-05-23 2013-09-25 合肥京东方光电科技有限公司 一种阵列基板及制备方法、显示装置

Also Published As

Publication number Publication date
US20150214253A1 (en) 2015-07-30
CN103325792A (zh) 2013-09-25

Similar Documents

Publication Publication Date Title
WO2014187113A1 (zh) 阵列基板及制备方法、显示装置
US9929277B2 (en) Thin film transistor and fabrication method thereof, array substrate and display
WO2017166341A1 (zh) Tft基板的制作方法及制得的tft基板
KR101900170B1 (ko) 어레이 기판의 제조 방법, 어레이 기판 및 디스플레이 디바이스
US9711544B2 (en) Thin film transistor and manufacturing method thereof, array substrate and manufacturing method thereof, display device
US9613986B2 (en) Array substrate and its manufacturing method, display device
US10651204B2 (en) Array substrate, its manufacturing method and display device
US8895334B2 (en) Thin film transistor array substrate and method for manufacturing the same and electronic device
WO2015081652A1 (zh) 阵列基板及其制作方法、显示装置
US11087985B2 (en) Manufacturing method of TFT array substrate
WO2013155830A1 (zh) 阵列基板的制造方法、阵列基板及显示装置
WO2015043268A1 (zh) 阵列基板及其制备方法、和显示装置
CN110148601B (zh) 一种阵列基板、其制作方法及显示装置
US20160148954A1 (en) Manufacturing method of array substrate, array substrate and display device
WO2015043069A1 (zh) 阵列基板及其制备方法、显示装置
WO2015043282A1 (zh) 阵列基板及其制造方法和显示装置
WO2015027632A1 (zh) 一种阵列基板、显示装置及阵列基板的制造方法
US10254609B2 (en) Array substrate including pixel electrode and drain electrode in direct contact to each other, and method of manufacturing the same, display panel, and display device
WO2015192595A1 (zh) 阵列基板及其制备方法、显示装置
WO2014180111A1 (zh) 阵列基板及其制备方法、显示装置
CN108873526B (zh) 阵列基板及其制造方法、显示装置
WO2017028493A1 (zh) 薄膜晶体管及其制作方法、显示器件
WO2015010404A1 (zh) 薄膜晶体管及其制作方法、阵列基板及显示装置
WO2015021720A1 (zh) 一种阵列基板及其制备方法及显示装置
WO2014117444A1 (zh) 阵列基板及其制作方法、显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14355463

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13885042

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13885042

Country of ref document: EP

Kind code of ref document: A1