WO2020143024A1 - 阵列基板及其制作方法、显示面板 - Google Patents

阵列基板及其制作方法、显示面板 Download PDF

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Publication number
WO2020143024A1
WO2020143024A1 PCT/CN2019/071347 CN2019071347W WO2020143024A1 WO 2020143024 A1 WO2020143024 A1 WO 2020143024A1 CN 2019071347 W CN2019071347 W CN 2019071347W WO 2020143024 A1 WO2020143024 A1 WO 2020143024A1
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Prior art keywords
insulating layer
array substrate
gate
electrode
layer
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PCT/CN2019/071347
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English (en)
French (fr)
Inventor
李栋
李小龙
李良坚
田宏伟
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/071347 priority Critical patent/WO2020143024A1/zh
Priority to US16/643,233 priority patent/US20210217781A1/en
Priority to CN201980000058.7A priority patent/CN111684602B/zh
Publication of WO2020143024A1 publication Critical patent/WO2020143024A1/zh
Priority to US18/116,689 priority patent/US20230207578A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the embodiments of the present disclosure relate to an array substrate, a manufacturing method thereof, and a display panel.
  • OLED display panels have the characteristics of self-luminescence, high contrast, low energy consumption, wide viewing angle, fast response speed, can be used in flexible panels, wide use temperature range, simple manufacturing, etc. Prospects.
  • flexible display devices with foldable performance are gradually favored by people. For example, in order to realize the narrow border or even borderless display of the display device, the non-display area of the display device may be bent; or for the convenience of carrying, the display device may also be bent. How to optimize the manufacturing process of the display panel is a problem concerned in the field.
  • an array substrate including a display pixel area for providing pixel units arranged in an array
  • the array substrate further includes: a base substrate, a first insulating layer, and disposed on the base substrate And the first insulating layer is provided with a groove, the groove is provided in the display pixel area; the second insulating layer is provided on the first insulating layer, and the second insulating layer Filled into the groove; the first conductive pattern layer is disposed on the second insulating layer.
  • the second insulating layer is an organic insulating layer.
  • the groove exposes the base substrate.
  • the first conductive pattern layer includes a gate line for the display pixel area or a portion of the gate line.
  • the groove includes a first portion that is parallel to the gate line or overlaps the gate line in a direction perpendicular to the base substrate.
  • the pixel unit includes a first transistor including a first gate, the first gate is on a side of the second insulating layer close to the base substrate, and The first via hole in the second insulating layer is electrically connected to the gate line.
  • the array substrate further includes a gate connection electrode, the gate connection electrode is located between the second insulating layer and the first conductive pattern layer, and the first gate is connected through the gate The electrode is electrically connected to the gate line.
  • the first transistor further includes a first source electrode and a first drain electrode, the first source electrode and the first drain electrode are provided in the same layer and with the same material as the gate connection electrode.
  • the array substrate further includes a data line for the display pixel area, the data line is provided in the same layer and with the same material as the first source electrode and the first drain electrode;
  • the groove further includes a second portion that is parallel to the data line or overlaps the data line in a direction perpendicular to the base substrate.
  • the pixel unit further includes a second transistor including a second gate connected to the first source or the first drain of the first transistor .
  • the groove is distributed around the second gate.
  • the groove further includes a third portion, the third portion is parallel to the second gate and correspondingly disposed; in the length direction of the third groove, the third portion Is longer than the second gate.
  • the second transistor includes a second source and a second drain, and the second source and the second drain are located in the second in a direction perpendicular to the base substrate Between the insulating layer and the first conductive pattern layer.
  • the array substrate further includes a third insulating layer, and the third insulating layer is located between the second source electrode and the second drain electrode in a direction perpendicular to the base substrate Between the first conductive pattern layers.
  • the array substrate further includes a fourth insulating layer and a pixel electrode stacked on the first conductive pattern layer, and the second source or second drain is insulated by the fourth The second via in the layer is electrically connected to the pixel electrode.
  • the first conductive pattern layer further includes a driving connection electrode, and the second source electrode or the second drain electrode is connected to the pixel electrode through the driving connection electrode.
  • the array substrate further includes a first capacitor electrode, and the first capacitor electrode is disposed on the first insulating layer and the second insulating layer in a direction perpendicular to the base substrate between.
  • the array substrate further includes a second capacitor electrode, the second capacitor electrode is disposed in the same layer as the first gate, and directly faces the first capacitor electrode to form a capacitor.
  • Some embodiments of the present disclosure also provide a display panel, including the above array substrate.
  • Some embodiments of the present disclosure also provide a manufacturing method of an array substrate, the array substrate includes a display pixel area for providing pixel units arranged in an array, the manufacturing method includes providing a substrate substrate; A first insulating layer is formed on the substrate, and a groove is formed on the first insulating layer, the groove is formed in the display pixel area; a second insulating layer is formed on the first insulating layer, and the A second insulating layer is also filled into the groove; a first conductive pattern layer is formed on the second insulating layer.
  • the first insulating layer is an organic insulating layer.
  • forming the first conductive pattern layer includes forming a gate line for the display pixel area or forming a portion of the gate line.
  • FIG. 1 is a schematic plan view of an array substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a partially enlarged schematic view of an array substrate provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional view of FIG. 2 along section line A-A';
  • FIG. 4 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 5 is a flowchart of a method for manufacturing an array substrate provided by an embodiment of the present disclosure.
  • a flexible electronic device includes a flexible substrate and various circuit structures and electronic devices prepared on the flexible substrate. According to needs, some parts of the flexible electronic device (such as the display area, the pad area, etc.) can be folded and fixed, or bent during use to adjust the positional relationship between different parts (such as a multi-screen mobile phone). Due to the bending stress, the layer structure on the base substrate is prone to break and fall off, thereby causing the risk of a bad device structure.
  • Some embodiments of the present disclosure provide an array substrate including a base substrate and a display pixel area, the display pixel area is used to provide pixel units arranged in an array, and includes: a first insulating layer, a second insulating layer, and a first A conductive pattern layer, wherein a first insulating layer is provided on the base substrate, and a groove is provided in the first insulating layer; a second insulating layer is provided on the first insulating layer, and the second insulating layer It is also filled into the groove; the first conductive pattern layer is disposed on the second insulating layer.
  • the second insulating layer and the first insulating layer can be added Contact area, which releases the internal stress that is likely to cause fracture in the second insulating layer during the bending of the array substrate, and makes the strain under the stress mainly occur in the groove area (strain absorption area); If the array substrate is bent, if a crack is generated in the stacked structure of the array, the groove can also block the propagation of the crack.
  • the arrangement of the above-mentioned embodiments of the present disclosure can reduce or eliminate the risk of the second insulating layer and the structure thereon (such as the first guide pattern layer) falling off during the bending of the array substrate, and improve the display pixel area of the array substrate
  • the impact resistance and bending resistance of the device improve the performance and yield of the product.
  • the groove structure refers to a structure provided according to needs, which is different from the uneven surface structure that cannot be avoided in the conventional manufacturing method, and is also different from the via structure that functions as a connection.
  • FIG. 1 is a schematic plan view of an array substrate provided by some embodiments of the present disclosure.
  • the array substrate 200 includes a display pixel area 210 for providing a plurality of pixel units 201 arranged in an array.
  • the array substrate further includes a plurality of gate lines 71 extending in the first direction D1, and a plurality of data lines 61 extending in the second direction D2.
  • the plurality of gate lines and the data lines cross each other to define a plurality of pixel areas, a plurality of The pixel units 201 are distributed in a plurality of pixel areas one-to-one.
  • the array substrate may further include a data driving circuit 6 and a gate driving circuit 7, the data driving circuit is used to provide a data signal to the pixel unit 201; the gate driving circuit is used to provide a scanning signal to the pixel unit 201;
  • the array substrate may also include other circuits or devices to further provide other various control signals.
  • the data driving circuit and the gate driving circuit are respectively connected to the pixel unit 201 through the data line 61 and the gate line 71, and each pixel unit 201 is connected to the gate line 71, the data line 61, etc. to receive corresponding electrical signals to emit light to realize Show operation.
  • the array substrate may be an organic light emitting diode (OLED) array substrate or an array substrate used for liquid crystal display.
  • OLED organic light emitting diode
  • the embodiments of the present disclosure will be specifically described below by taking the array substrate as an organic light emitting diode array substrate as an example, but the embodiments of the present disclosure do not limit this.
  • each pixel unit 201 includes a light-emitting element (ie, OLED) and a pixel circuit that drives the light-emitting element to emit light.
  • the pixel circuit may include a conventional 2T1C pixel circuit, that is, it includes two transistors and a capacitor, one of the two transistors is a switching transistor, and the other is a driving transistor.
  • the pixel circuit may also be a pixel circuit of another structure, such as a 3T1C based on the aforementioned 2T1C pixel or a pixel circuit that further includes a compensation function, a reset function, and the like, which are not limited in the embodiments of the present disclosure.
  • FIG. 2 is a partially enlarged schematic view of a layout of a pixel unit in an array substrate of a specific example of an embodiment
  • FIG. 3 is a schematic cross-sectional view of FIG. 2 along section line A-A'.
  • FIG. 2 only illustrates the semiconductor layer 240, the gate layer 250, and the groove area in the array substrate, and schematically illustrates the gate line 71 and the data line 61.
  • FIG. 3 only shows the pixel unit.
  • the first transistor 110 is a switching transistor, which mainly functions as a switch, and controls the transmission of data signals under the control of the gate line 71;
  • the second transistor 120 is a driving transistor, which mainly functions as a cathode or anode of the light-emitting element
  • the pixel electrode provides driving current.
  • the array substrate 200 includes a base substrate 211, and a first insulating layer 212, a second insulating layer 214, and a first conductive pattern layer 213 that are sequentially stacked on the base substrate 211.
  • a groove 220 is provided in the first insulating layer 212, the groove 220 is disposed in the pixel display area 210, and the second insulating layer 214 is also filled into the groove 220; for example, further, the second insulating layer 214 may be It has a flat surface and plays a role in flattening.
  • the second insulating layer 214 is an organic insulating layer.
  • the organic insulating material has better flexibility than the inorganic insulating material, so that the impact resistance and bending resistance of the array substrate 200 can be further improved.
  • the material of the second insulating layer 214 is at least one of polymethyl methacrylate, polycarbonate, polystyrene, epoxy resin, polyimide, and polyethylene.
  • the first insulating layer 212 may be an organic insulating material, such as resin material such as polyimide; or an inorganic insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride or metal oxide insulation material.
  • organic insulating material such as resin material such as polyimide
  • inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride or metal oxide insulation material.
  • the material of the first conductive pattern layer 213 may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and combinations of the above metals
  • the resulting alloy material or conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc.
  • the groove 220 may be provided in the first insulating layer 212 without any via hole.
  • the embodiment of the present disclosure does not limit the setting area of the groove 220, that is, it does not affect the formation of the device structure.
  • the groove 220 may extend downward until the base substrate 211 is exposed, that is, the surface of the base substrate 211 is exposed through the groove 220.
  • the present disclosure does not limit the planar shape of the groove 200 in the direction parallel to the base substrate 211, including circular, triangular, rectangular, elliptical, T-shaped, strip-shaped, broken-line, or other The shape defined by the device structure.
  • the length direction of the groove 220 is parallel to the bending axis (not shown) of the array substrate 200, so that when the array substrate 200 is bent along the bending axis, the bending resistance of the array substrate 200 can be improved.
  • the groove 220 is distributed around the second transistor 120 relative to the plane where the base substrate is located.
  • the groove 220 is distributed around the second gate 121 of the second transistor 120, that is, at least part of the groove 220 is distributed around the second gate 121.
  • the groove 220 is disposed on at least two sides of the second gate 121, for example, on a base substrate, the extending direction of the groove 220 and the extending direction of the second gate 121 are parallel to each other.
  • the second transistor 120 is used as the driving transistor of the pixel unit.
  • the driving transistor occupies a larger area in the pixel unit, and its performance is more important than the switching transistor for the display effect. As a result, it is also important to maintain the stability of its performance.
  • the above configuration can effectively protect the second transistor 120 from damage due to external forces or bending.
  • at least a part of the groove 220 may also be disposed between the first transistor 110 and the second transistor 120, for example, the first The source layer 112 and the second active layer 122 of the second transistor 120; or the groove 220 is provided between the first gate 111 of the first transistor 110 and the second gate 121 of the second transistor 120.
  • the first conductive pattern layer 213 includes the gate line 71 or a portion of the gate line 71 for displaying the pixel area 210.
  • the gate line 71 is disposed on the side of the second insulating layer 214 away from the base substrate 211, so that the arrangement of the groove 220 is not restricted by the gate line 71, whereby the installation position of the groove 220 can be more flexible and the installation area can be Bigger.
  • the first insulating layer 212 and the second insulating layer 214 are sequentially stacked between the base substrate 211 and the first conductive layer 213, and can be laid out according to a specific array substrate structure, and is not limited to a specific insulating layer structure.
  • the second insulating layer 214 is the organic insulating layer closest to the base substrate 211.
  • this arrangement can make the insulating materials corresponding to the positions of the groove 220 in the direction perpendicular to the base substrate 211 all organic insulating materials, and thus can be better The impact resistance and bending resistance of the array substrate 200 are improved.
  • the groove 220 includes a first portion 221 that is parallel to the gate line 71 (as shown in FIG. 2) or overlaps the gate line 71 in a direction perpendicular to the base substrate 211.
  • the length direction of the first portion 221 is parallel to the extending direction of the gate line.
  • the extension of the pattern in the present disclosure is not limited to extending along a straight line, but may also extend along a curved line, such as a serpentine extension.
  • the gate layer 250 includes the first gate 111 of the first transistor 110.
  • the gate layer 250 further includes the second gate 121 of the second transistor 120.
  • the semiconductor layer 240 is located on the side of the gate layer 250 close to the base substrate 211 and includes the first active layer 112 of the first transistor 110 and the second active layer 122 of the second transistor 120.
  • the groove 220 further includes a third portion 223, which is parallel to and corresponding to the second gate 121 of the second transistor.
  • the length direction of the third groove 223 i.e. In one direction D1
  • the third portion 223 of the groove is set to have a length in the first direction D1 greater than that of the second gate 121
  • the length, which is greater than the length of the channel region of the second transistor 120, can effectively protect the channel region.
  • different parts of the groove 220 may have different depths, and may be flexibly designed according to actual available space, which is not limited in the embodiments of the present disclosure.
  • the groove 220 may form a chevron shape around the second gate 121. Due to the presence of the semiconductor layer 240, the groove 220 may have a shallow depth at the position overlapping the semiconductor layer 240 (relative to the base substrate), for example, the groove 220 penetrates the surface of the semiconductor layer 240 in the longitudinal direction, which can avoid The semiconductor layer 240 causes damage.
  • the above description of the groove mainly uses the second transistor as an example.
  • the space in the substrate allows, a similar arrangement can be made for each transistor in each pixel, for example, the gate around each transistor is correspondingly arranged There are the above grooves.
  • the gate layer 250 is on the side of the second insulating layer 214 close to the base substrate 211.
  • the first gate 111 of the first transistor 110 is electrically connected to the gate line 71 through the first via 241 in the second insulating layer 214.
  • the gate layer 250 may also be located between the first insulating layer 212 and the second insulating layer 214, for example, the first insulating layer 212 serves as the first A gate insulating layer of a transistor 110 and a second transistor 120.
  • the embodiments of the present disclosure do not limit this.
  • the material of the gate layer 250 may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and a combination of the above metals Alloy materials; or conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc.
  • the materials of the semiconductor layer 240 include, but are not limited to, silicon-based materials (amorphous silicon a-Si, polysilicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (hexathiophene, Polythiophene, etc.).
  • silicon-based materials amorphous silicon a-Si, polysilicon p-Si, etc.
  • metal oxide semiconductors IGZO, ZnO, AZO, IZTO, etc.
  • organic materials hexathiophene, Polythiophene, etc.
  • the first transistor 110 and the second transistor 120 are both top-gate structures. In other embodiments, the first transistor 110 and the second transistor 120 may also be bottom-gate structures.
  • the first transistor 110 has a top-gate structure
  • the second transistor 120 has a bottom-gate structure.
  • the top-gate transistor has a smaller parasitic capacitance and can have a faster turn-on speed; the bottom-gate transistor has a larger on-state current and electrical stability, and thus has a stronger driving capability.
  • the first transistor 110 and the second transistor 120 are thin film transistors. The embodiments of the present disclosure do not limit the specific structures and types of the first transistor 110 and the second transistor 120.
  • the first transistor 110 includes a first source 113 and a first drain 114.
  • the first source 113 or the first drain 114 is electrically connected to the second gate 121 of the second transistor 120.
  • the first source 113, the first drain 114, and the data line 61 are provided in the same layer and have the same material, and thus can be obtained through the same patterning process.
  • the first source 113 or the first drain 114 is electrically connected to the data line 61 to receive a data signal for emitting light.
  • the electrode of the first source 113 and the first drain 114 that is not electrically connected to the second gate 121 of the second transistor 120 is electrically connected to the data line 61.
  • the groove 220 may further include a second portion 222 that is parallel to the data line 61 or overlaps the data line in a direction perpendicular to the base substrate 211.
  • the length direction of the second portion 222 is parallel to the extending direction of the data line 61 (see FIG. 2).
  • the array substrate 200 further includes a gate connection electrode 72, and the gate connection electrode 72 is located between the gate layer 250 and the first conductive pattern layer 213 for connecting the first gate 111 and the gate line 71.
  • the gate connection electrode 72 is located between the gate layer 250 and the first conductive pattern layer 213 for connecting the first gate 111 and the gate line 71. If the depth of the via hole is too large, the conductive material filled in the via hole may wrinkle or break (especially in a bent state), resulting in excessive contact resistance or poor contact.
  • the first grid electrode is connected by providing a grid connection electrode 111 and the gate line 71 can prevent the depth of the continuous via hole directly connecting the first gate 111 and the gate line 71 from being too deep, which helps to improve the yield and bending resistance of the array substrate.
  • the gate connection electrode 72 may be provided in the same layer and with the same material as any conductive layer between the gate layer 250 and the first conductive pattern layer 213, and thus may be obtained through the same patterning process.
  • the gate connection electrode 72 is located between the second insulating layer 214 and the first conductive pattern layer 213; for example, the array substrate further includes a third insulating layer 216 disposed between the gate connection electrode 72 and the first conductive pattern layer 213.
  • the gate connection electrode 72 is electrically connected to the first gate 111 through the first via 241 in the second insulating layer 214, and is electrically connected to the gate line 71 through the second via 261 in the third insulating layer 216, thereby The gate line 71 is electrically connected to the first gate 111.
  • the gate connection electrode 72 and the first source electrode 113 and the first drain electrode 114 of the first transistor 110 are provided in the same layer and have the same material, and thus can be obtained through the same patterning process.
  • the third insulating layer 216 is located between the second source electrode 123 and the second drain electrode 124 and the first conductive pattern layer 213.
  • the second transistor 120 further includes a second source 123 and a second drain 124.
  • the second source electrode 123 and the second drain electrode 124 are located between the second insulating layer 214 and the first conductive pattern layer 213.
  • the second source electrode 123 and the second drain electrode 124 are disposed in the same layer and with the same material as the first source electrode 113 and the first drain electrode 114, and thus can be obtained through the same patterning process.
  • the light emitting element 300 includes a first electrode 301, a light emitting layer 302, and a second electrode 303.
  • the first electrode 301 is a pixel electrode
  • the second electrode 303 is a common electrode.
  • One of the first electrode 301 and the second electrode 303 is an anode, and the other is a cathode.
  • the light emitting element 300 may include at least one of a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, etc. in addition to the light emitting layer 302.
  • the second source 123 or the second drain 124 of the second transistor 120 is electrically connected to the first electrode 301 (pixel electrode) of the light emitting element 300.
  • the light emitting element 300 is located on the side of the first conductive pattern layer 213 away from the base substrate 211.
  • the array substrate 200 further includes a fourth insulating layer 218 on the first conductive pattern layer 213, the light emitting element 300 is formed on the fourth insulating layer 218, and the second source electrode 123 or the second drain electrode 124 of the second transistor 120
  • the first electrode 301 of the light emitting element 300 is electrically connected through the third via 281 in the fourth insulating layer 218.
  • the array substrate 200 further includes a driving connection electrode 230, which is located between the second source 123 (or the second drain 124) of the second transistor 120 and the pixel electrode of the light emitting element 300, and is connected to the second transistor The second source electrode 123 (or the second drain electrode 124) of 120 and the pixel electrode of the light emitting element 300.
  • the driving connection electrode 230 has the effect of reducing the via depth similar to the gate connection electrode 72, and can also increase the pixel distribution density of the array substrate 200 and reduce the resistance between the second transistor 120 and the pixel electrode.
  • the driving connection electrode 230 and the groove 220 overlap in a direction perpendicular to the base substrate 221.
  • the driving connection electrode 230 and the gate line 71 are provided in the same layer and have the same material, which can be obtained through the same patterning process, that is, the first conductive pattern layer 213 further includes the driving connection electrode 230.
  • the driving connection electrode 230 is electrically connected to the second source 123 or the second drain 124 of the second transistor 120 through the fourth via 264 in the third insulating layer 216, and is connected to the first light emitting element 300 through the third via 281
  • An electrode 301 is electrically connected.
  • the light emitting element 300 may have a top emission, bottom emission, or double-sided emission structure.
  • the light-emitting element 300 has a top-emission structure
  • the first electrode 301 has reflectivity
  • the second electrode 303 has transmissivity or translucency.
  • the first electrode 301 is a transparent conductive oxide material such as indium tin oxide (ITO).
  • the first electrode 301 is a high work function material to serve as an anode, such as an ITO/Ag/ITO stacked structure
  • the second electrode 303 is a low work function material to serve as a cathode, such as a semi-transmissive metal or metal alloy
  • the material is, for example, Ag/Mg alloy material.
  • the third insulating layer 216 and the fourth insulating layer 218 are planarization layers.
  • the third insulating layer 216 and the fourth insulating layer 218 are both organic materials, such as resins such as polyimide (PI).
  • the array substrate 200 further includes a storage capacitor Cst, for example, for storing data signals during the operation of the pixel circuit.
  • the arrangement and connection of the storage capacitor can be adjusted according to the specific pixel circuit structure.
  • the first capacitor electrode 411 of the storage capacitor is disposed between the first insulating layer 212 and the second insulating layer 214;
  • the first gate 111 of the first transistor 110 is provided in the same layer and with the same material, and thus can be obtained through the same patterning process, and the first capacitor electrode 411 and the second capacitor electrode 412 are directly opposite to constitute the storage capacitor Cst.
  • At least a part of the groove 220 is disposed between the second transistor 120 and the storage capacitor Cst.
  • the array substrate 200 further includes a pixel defining layer 215 disposed on the first electrode 301 of the light-emitting element 300 to isolate the light-emitting layer of the adjacent light-emitting element, thereby preventing cross color in the display operation.
  • the pixel defining layer 215 forms an opening at a position corresponding to the first electrode 301 to at least partially expose the first electrode 301, and the light emitting layer 302 is formed in the opening.
  • the second electrode 303 is formed on the light emitting layer 302 and the pixel defining layer.
  • the pixel defining layer 215 is an organic material such as resin or an inorganic material such as silicon oxide.
  • the array substrate 200 further includes a spacer layer 217 disposed on the pixel defining layer 215.
  • the spacer layer 217 is used to support the evaporation mask when the organic light-emitting layer 302 is formed by evaporation, so as to isolate the pixel defining layer 215 from the evaporation mask to protect the pixel defining layer 215; the spacer layer 217 can also serve to further isolate adjacent organic light-emitting layers.
  • the spacer layer 217 generally includes a plurality of spacers (Spacer) separated by spaces. The shape of the spacers is generally rectangular parallelepiped, columnar, spherical, hemispherical or not limited thereto.
  • the array substrate 200 further includes a protective layer 219 disposed on the second electrode 303.
  • the protective layer 219 is, for example, an inorganic protective layer or an organic protective layer, or a stack of an inorganic protective layer and an organic protective layer.
  • the protective layer 219 may further include a reducing material and/or a hygroscopic material to avoid the adverse effect of oxygen/water vapor on the light emitting element 300.
  • the array substrate 200 further includes a gate insulating layer 207 disposed between the gate layer 250 and the semiconductor layer 240.
  • the material of the gate insulating layer 207 is silicon oxide, silicon nitride, or silicon oxynitride.
  • the groove 220 also penetrates the gate insulating layer 207 to expose the base substrate 211.
  • the array substrate 200 further includes a buffer layer (not shown) disposed between the base substrate 211 and the semiconductor layer 240.
  • the buffer layer is used to make the surface of the base substrate 211 flatter, and can also prevent harmful impurities in the base substrate 211 from entering the pixel circuit.
  • the groove 220 may expose the buffer layer without passing through the buffer layer to expose the base substrate.
  • the array substrate 200 is a flexible array substrate.
  • the base substrate 211 is an organic flexible material, such as polyimide (PI), polyethylene terephthalate (PET), polycarbonate, polyethylene, polyacrylate, polyetherimide Amine, polyethersulfone, etc.
  • some embodiments of the present disclosure also provide a display panel 20 including the above-mentioned array substrate 200.
  • the display panel is an OLED display panel, accordingly the array substrate included is an OLED array substrate, and the light emitting element included in the pixel unit is OLED.
  • the display panel further includes an encapsulation layer 501 and a cover plate 502 disposed on the array substrate 200.
  • the encapsulation layer 501 is configured to seal the light emitting element 300 to prevent external moisture and oxygen from flowing to the light emitting element and the pixel circuit. Penetration causes damage to the device.
  • the encapsulation layer 501 includes an organic thin film or a structure including alternately stacked organic thin films and inorganic thin films.
  • a water absorbing layer (not shown) may be disposed between the encapsulation layer 501 and the array substrate 200, and configured to absorb water vapor or sol remaining in the light-emitting element 300 during the previous manufacturing process.
  • the cover 502 is, for example, a glass cover.
  • the cover plate 502 and the encapsulation layer 501 may be an integrated structure.
  • the display panel 20 is a liquid crystal display panel, and the display panel 20 further includes a color filter substrate opposite to the array substrate and a liquid crystal layer disposed between the array substrate and the color filter substrate.
  • the display device may be, for example, a liquid crystal display device, an OLED display device or electronic paper, a digital photo frame, a smart bracelet, a smart watch, a mobile phone, a tablet computer, a display, a notebook computer, a navigator, and other products or components with any display function.
  • Some embodiments of the present disclosure also provide a method of manufacturing an array substrate including a display pixel area for providing pixel units arranged in an array.
  • the manufacturing method includes: providing a base substrate; forming a first insulating layer on the base substrate, and forming a groove on the first insulating layer, the groove being formed in the display pixel area; A second insulating layer is formed on the first insulating layer, and the second insulating layer is also filled into the groove; a first conductive pattern layer is formed on the second insulating layer.
  • FIG. 5 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure.
  • the manufacturing method of the array substrate provided by the embodiments of the present disclosure will be exemplarily described below with reference to FIGS. 1, 3, and 5.
  • the manufacturing method for forming the array substrate includes at least step S51 to step S53.
  • Step S51 providing a base substrate, forming a first insulating layer on the base substrate, and forming a groove on the first insulating layer, the groove being formed in the display pixel area;
  • Step S52 forming a second insulating layer on the first insulating layer, and the second insulating layer is also filled into the groove;
  • Step S53 forming a first conductive pattern layer on the second insulating layer.
  • a base substrate 211 is first provided, and then a first insulating layer 212 is formed on the base substrate 211 and a groove 220 is formed in the first insulating layer 212.
  • the semiconductor layer 240, the gate insulating layer 207, and the gate layer 250 are sequentially formed on the base substrate 211 before the first insulating layer 212 is formed.
  • the base substrate 211 is an organic flexible material, such as polyimide (PI), polyethylene terephthalate (PET), polycarbonate, polyethylene, polyacrylate, polyetherimide , Polyethersulfone, etc.
  • PI polyimide
  • PET polyethylene terephthalate
  • PC polycarbonate
  • polyethylene polyethylene
  • polyacrylate polyetherimide
  • Polyethersulfone etc.
  • forming the gate layer includes forming a first conductive layer and performing a patterning process on the conductive layer to form the gate 111 of the first transistor 110 and the second gate 121 of the second transistor 120.
  • the material of the first conductive layer is a metal material, such as copper, aluminum, magnesium, molybdenum, chromium, and alloys of the above metals.
  • forming the groove 220 includes etching the first insulating layer 212.
  • the groove 220 does not overlap with the semiconductor layer 240 and the gate layer 250 in a direction perpendicular to the base substrate 211.
  • the groove 220 also penetrates the gate insulating layer 207 to expose the base substrate 211.
  • the first insulating layer 212 may be an organic insulating material such as polyimide and other resin materials; it may also be an inorganic insulating material such as silicon oxide, silicon nitride or silicon oxynitride or metal oxide insulation material.
  • conventional physical vapor deposition for example, forming a conductive layer
  • chemical vapor deposition process for example, forming an insulating layer
  • spin coating process for example, forming an organic layer
  • photolithography process for example, the patterning process.
  • the material of the second insulating layer 212 is an organic insulating material, such as polymethyl methacrylate, polycarbonate, polystyrene, epoxy resin, polyimide, or polyethylene. At least one.
  • the formation method of the second insulating layer 212 includes spin coating or inkjet printing.
  • the forming method of the second insulating layer 212 further includes curing.
  • the organic insulating material has better flexibility than the inorganic insulating material, so that the impact resistance and bending resistance of the array substrate 200 can be further improved.
  • step S52 further includes etching the second insulating layer 214 to form the first via hole 241 and the source and drain contact holes of the first transistor 110 and the second transistor 120.
  • the first via 241 also penetrates the first insulating layer 212 to expose at least part of the gate layer 250.
  • the source-drain contact hole also penetrates the first insulating layer 212 and the gate insulating layer 207 to respectively expose at least part of the semiconductor layer 240.
  • this step further includes forming a second conductive layer and a third insulating layer 216 in sequence on the second insulating layer 214 before forming the first conductive pattern layer 213.
  • a patterning process is performed on the second conductive layer to form the first source 113 and the first drain 114 of the first transistor 110, and the second source 123 and the second drain 124 of the second transistor 120.
  • the second conductive layer is subjected to a patterning process to form a gate connection electrode 72 and a data line 61.
  • the gate connection electrode 72 is electrically connected to the first gate 111 through the first via 241.
  • the first source 113 and the first drain 114 of the first transistor 110 are in electrical contact with the first active layer 112 through the source-drain contact hole, respectively, and the second source 123 and the second drain of the second transistor 120 124 respectively make electrical connection with the second active layer 122 through the source-drain contact holes.
  • step S53 further includes performing a patterning process on the third insulating layer 216 to form a second via 261 and a fourth via 262.
  • the second via 261 exposes at least a portion of the gate connection electrode 72; the fourth via 262 exposes at least a portion of the second source 123 or the second drain 124 of the second transistor 120.
  • forming the first conductive pattern layer 213 includes forming a third conductive layer and performing a patterning process on the third conductive layer to form the gate line 71 and the driving connection electrode 230.
  • the gate line 71 is electrically connected to the gate connection electrode 72 via the second via 261.
  • the driving connection electrode 230 is electrically connected to the second source 123 or the second drain 124 of the second transistor 120 through the fourth via 262.
  • the manufacturing method of the array substrate further includes forming a light-emitting element 300 on the first conductive pattern layer 213, and forming the light-emitting element 300 includes sequentially forming a first electrode 301, a light-emitting layer 302, and a second electrode 303.
  • the driving connection electrode 230 is electrically connected.
  • the manufacturing method of the array substrate further includes forming a fourth insulating layer 218, a pixel defining layer 215, a spacer layer 217, and a protective layer 219. I won't repeat them here.
  • the material of the conductive layer may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and a combination of the above metals Alloy materials; or conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc.
  • gold Au
  • silver Au
  • Cu copper
  • Al aluminum
  • Mo molybdenum
  • Mo magnesium
  • W tungsten
  • conductive metal oxide materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc.

Abstract

一种阵列基板及其制作方法，该阵列基板(200)包括用于提供阵列排布的像素单元(201)的显示像素区(210)，所述阵列基板(200)还包括：衬底基板(211)、第一绝缘层(212)、第二绝缘层(214)和第一导电图案层(213)。第一绝缘层(212)设置于衬底基板(211)上，且第一绝缘层(211)中设置有凹槽(220)，该凹槽(220)设置于该显示像素区(210)；第二绝缘层(214)设置在第一绝缘层(211)上，且第二绝缘层(214)还填充入凹槽(220)中；第一导电图案层(213)设置在第二绝缘层(214)上。该阵列基板(200)通过设置该凹槽(220)可以具有更好的抗冲击性能和耐弯折性能。

Description

阵列基板及其制作方法、显示面板 技术领域
本公开实施例涉及一种阵列基板及其制作方法、显示面板。
背景技术
在显示领域，有机发光二极管(OLED)显示面板具有自发光、对比度高、能耗低、视角广、响应速度快、可用于挠曲性面板、使用温度范围广、制造简单等特点，具有广阔的发展前景。随着柔性电子技术的发展，具有可折叠性能的柔性显示装置逐渐受到人们的青睐。例如，为了实现显示装置的窄边框甚至无边框显示，可以对显示装置的非显示区进行弯折处理；或者为了便于携带，也可以对显示装置进行弯曲处理。如何优化显示面板的制作工艺是本领域关注的问题。
发明内容
本公开的一些实施例提供一种阵列基板，包括用于提供阵列排布的像素单元的显示像素区，所述阵列基板还包括：衬底基板，第一绝缘层，设置于所述衬底基板上，且所述第一绝缘层中设置有凹槽，所述凹槽设置于所述显示像素区；第二绝缘层，设置在所述第一绝缘层上，且所述第二绝缘层还填充入所述凹槽中；第一导电图案层，设置在所述第二绝缘层上。
在至少一个示例中，所述第二绝缘层为有机绝缘层。
在至少一个示例中，所述凹槽暴露所述衬底基板。
在至少一个示例中，所述第一导电图案层包括用于所述显示像素区的栅线或所述栅线的部分。
在至少一个示例中，所述凹槽包括第一部分，所述凹槽的第一部分平行于所述栅线或与所述栅线在垂直于所述衬底基板的方向上重叠。
在至少一个示例中，所述像素单元包括第一晶体管，所述第一晶体管包括第一栅极，所述第一栅极在所述第二绝缘层靠近所述衬底基板的一侧，且通过所述第二绝缘层中的第一过孔与所述栅线电连接。
在至少一个示例中，所述阵列基板还包括栅连接电极，所述栅连接电极位于所述第二绝缘层与所述第一导电图案层之间，所述第一栅极通过所述栅连接电极与所述栅线电连接。
在至少一个示例中，所述第一晶体管还包括第一源极和第一漏极，所述第一源极和所述第一漏极与所述栅连接电极同层设置且材料相同。
在至少一个示例中，所述阵列基板还包括用于所述显示像素区的数据线，所述数据线与所述第一源极及所述第一漏极同层设置且材料相同；所述凹槽还包括第二部分，所述凹槽的第二部分与所述数据线平行或在垂直于所述衬底基板的方向与所述数据线重叠。
在至少一个示例中，所述像素单元还包括第二晶体管，所述第二晶体管包括第二栅极，所述第二栅极与所述第一晶体管的第一源极或第一漏极连接。
在至少一个示例中，所述凹槽围绕所述第二栅极分布。
在至少一个示例中，所述凹槽还包括第三部分，所述第三部分与所述第二栅极平行且对应设置；在所述第三凹槽的长度方向上，所述第三部分的长度大于所述第二栅极的长度。
在至少一个示例中，所述第二晶体管包括第二源极和第二漏极，在垂直于所述衬底基板的方向上，所述第二源极和第二漏极位于所述第二绝缘层与所述第一导电图案层之间。
在至少一个示例中，所述阵列基板还包括第三绝缘层，在垂直于所述衬底基板的方向上，所述第三绝缘层位于所述第二源极和第二漏极与所述第一导电图案层之间。
在至少一个示例中，所述阵列基板还包括层叠设置于所述第一导电图案层之上的第四绝缘层和像素电极，所述第二源极或第二漏极通过所述第四绝缘层中的第二过孔与所述像素电极电连接。
在至少一个示例中，所述第一导电图案层还包括驱动连接电极，所述第二源极或第二漏极通过所述驱动连接电极与所述像素电极连接。
在至少一个示例中，所述阵列基板还包括第一电容电极，在垂直于所述衬底基板的方向上，所述第一电容电极设置于所述第一绝缘层和所述第二绝缘层之间。
在至少一个示例中，所述阵列基板还包括第二电容电极，所述第二电容电极与所述第一栅极同层设置且与所述第一电容电极正对形成电容。
本公开的一些实施例还提供一种显示面板，包括上述阵列基板。
本公开的一些实施例还提供一种阵列基板的制作方法，所述阵列基板包括用于提供阵列排布的像素单元的显示像素区，所述制作方法包括提供衬底基板；在所述衬底基板上形成第一绝缘层，并在所述第一绝缘层上形成凹槽，所述凹槽形成于所述显示像素区；在所述第一绝缘层上形成第二绝缘层，且所述第二绝缘层还填充入所述凹槽中；在所述第二绝缘层上形成第一导电图案层。
在至少一个示例中，所述第一绝缘层为有机绝缘层。
在至少一个示例中，形成所述第一导电图案层包括：形成用于所述显示像素区的栅线或形成所述栅线的部分。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1是本公开一实施例提供的一种阵列基板的平面示意图；
图2是本公开一实施例提供的阵列基板的局部放大示意图；
图3是图2沿剖面线A-A’的剖面示意图；
图4是本公开一实施例提供的一种显示面板的示意图；
图5是本公开一实施例提供的一种阵列基板的制作方法的流程图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造 性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
用于显示装置的阵列基板或具有该显示装置的电子装置在外界应力作用下容易发生损伤。另外，随着技术的发展以及消费者的需求的变化，厂商将推出具有可折叠显示屏的柔性电子装置。例如，柔性电子装置包括柔性基板以及在该柔性基板上制备的各种电路结构以及电子器件等。根据需要，柔性电子装置的一些部分(例如显示区、焊盘区等)可被折叠并固定，或者在使用过程中根据需要弯折以调整不同部分之间的位置关系(例如多屏手机)。由于弯折应力，衬底基板上的层结构容易发生断裂而脱落，从而引发器件结构发生不良的风险。
本公开的一些实施例提供一种阵列基板，包括衬底基板和显示像素区，所述显示像素区用于提供阵列排布的像素单元，且包括：第一绝缘层、第二绝缘层和第一导电图案层，其中，第一绝缘层设置于所述衬底基板上，且第一绝缘层中设置有凹槽；第二绝缘层设置在所述第一绝缘层上，且第二绝缘层还填充入凹槽中；第一导电图案层设置在所述第二绝缘层上。
本公开的一些实施例，通过在阵列基板的显示像素区中的第一绝缘层中设置凹槽，并使得第二绝缘层填充入该凹槽中，可以增加第二绝缘层与第一绝缘层的接触面积，从而释放了在阵列基板被弯曲的过程中发生在第二绝缘层中易于导致断裂的内应力，并使得应力作用下的应变主要发生在该凹槽区域(应变吸收区)；此外，如果在阵列基板被弯曲的 过程中，如果在阵列的叠层结构中产生裂纹，该凹槽还可以阻隔裂纹的延展。因此，本公开上述实施例的这种设置可以减少或者消除该第二绝缘层以及其上结构(如第一导图案层)在阵列基板弯曲过程中的脱落风险，提高了阵列基板显示像素区的器件的抗冲击性能和耐弯折性能，从而提高了产品的性能和良率。
需要说明的是，该凹槽结构是指根据需要而设置的结构，区别于常规的制作方法中无法避免而出现的表面不平整结构，也区别于起连接作用的过孔结构。
图1为本公开一些实施例提供的一种阵列基板的平面示意图。如图所示，阵列基板200包括显示像素区210，显示像素区210用于提供阵列排布的多个像素单元201。该阵列基板还包括沿第一方向D1延伸的多条栅线71、沿第二方向D2延伸的多条数据线61，该多条栅线和数据线彼此交叉定义出多个像素区，多个像素单元201一一对应分布于多个像素区内。
例如，该阵列基板还可以包括数据驱动电路6和栅极驱动电路7，该数据驱动电路用于为像素单元201提供数据信号；该栅极驱动电路用于为像素单元201提供扫描信号；此外，该阵列基板还可以包括其他电路或器件以进一步用于提供其他各种控制信号。该数据驱动电路和栅极驱动电路分别通过数据线61和栅线71与像素单元201连接，每个像素单元201与栅线71、数据线61等连接以接收相应的电信号以进行发光，实现显示操作。
例如，该阵列基板可以是有机发光二极管(OLED)阵列基板，也可以是用于液晶显示的阵列基板。以下以该阵列基板为有机发光二极管阵列基板为例对本公开的实施例进行具体描述，但本公开实施例对此不作限制。
例如，每个像素单元201包括发光元件(即OLED)以及驱动该发光元件发光的像素电路。例如，该像素电路可以包括常规的2T1C像素电路，即包括两个晶体管和一个电容，该两个晶体管一个为开关晶体管，另一个为驱动晶体管。又例如，该像素电路还可以为其他结构的像素电路，例如基于前述2T1C像素的3T1C或进一步包括补偿功能、复位功 能等的像素电路等，本公开的实施例对此不作限制。
图2是一个实施例的具体示例的阵列基板中一个像素单元的布图的部分放大示意图；图3为图2沿剖面线A-A’的剖面示意图。为了清楚起见，图2仅示意出了阵列基板中的半导体层240、栅极层250以及凹槽区域，并示意性地示意出栅线71和数据线61，图3中仅示出了像素单元中的发光元件300、第一晶体管110和第二晶体管120。例如，第一晶体管110为开关晶体管，主要起开关作用，在栅线71的控制下控制数据信号的传输；第二晶体管120为驱动晶体管，主要起驱动作用，为作为发光元件的阴极或阳极的像素电极提供驱动电流。
需要说明的是，本公开的实施例对第一晶体管和第二晶体管以及发光元件之间的具体连接方式不作限制。
请一并参照图2和图3，阵列基板200包括衬底基板211、以及依次层叠设置于衬底基板211上的第一绝缘层212、第二绝缘层214和第一导电图案层213。第一绝缘层212中设置有凹槽220，该凹槽220设置于该像素显示区210，且第二绝缘层214还填充入该凹槽220中；例如，更进一步，第二绝缘层214可以具有平坦表面，起到平坦化的作用。
例如，第二绝缘层214为有机绝缘层。有机绝缘材料相对于无机绝缘材料具有更好的柔韧性，因而可以更进一步提高阵列基板200的抗冲击性能和耐弯折性能。
例如，第二绝缘层214的材料为聚甲基丙烯酸甲酯、聚碳酸酯、聚苯乙烯、环氧树脂、聚酰亚胺、聚乙烯中的至少一种。
例如，第一绝缘层212可以是有机绝缘材料，如聚酰亚胺等树脂材料；也可以是无机绝缘材料，如硅的氧化物、硅的氮化物或硅的氮氧化物或金属氧化物绝缘材料。
例如，第一导电图案层213的材料可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料；或者导电金属氧化物材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。
例如，该凹槽220可以设置于该第一绝缘层212中任何没有设置过孔。本公开实施例对于凹槽220的设置区域不作限制，也即不影响器件 结构的形成即可。例如，在至少一个实施例中，凹槽220可以向下延伸直至暴露出衬底基板211，即衬底基板211的表面通过凹槽220暴露。
例如，本公开对该凹槽200在在平行于衬底基板211的方向上的平面形状不作限制，包括圆形、三角形、矩形、椭圆形、T形、条状、折线状，或者其它由周边器件结构所限定的形状。例如，该凹槽220的长度方向与阵列基板200的弯折轴(未示出)平行，从而当阵列基板200沿着该弯折轴弯折时，可以提高阵列基板200的耐弯折性能。
在至少一个实施例中，例如，如图2所示，相对于衬底基板所在的平面，凹槽220的至少一部分环绕第二晶体管120分布。例如，凹槽220环绕第二晶体管120的第二栅极121分布，也即所述第二栅极121的四周都分布有该凹槽220的至少部分。例如，凹槽220设置于第二栅极121的至少两侧，例如在衬底基板上，凹槽220的延伸方向与第二栅极121的延伸方向彼此平行。在本实施例中，第二晶体管120作为像素单元的驱动晶体管，通常而言，驱动晶体管在像素单元中所占的面积较大，而且其性能相比于开关晶体管对于显示效果有更为重要的影响，因此保持其性能的稳定也较为重要，上述设置可以有效保护第二晶体管120在外力作用或弯折下不易受损。例如，如图2所示，相对于衬底基板所在的平面，凹槽220的至少一部分还可以设置在第一晶体管110和第二晶体管120之间，例如设置在第一晶体管110的第一有源层112和第二晶体管120的第二有源层122之间；或者凹槽220设置在第一晶体管110的第一栅极111和第二晶体管120的第二栅极121之间。
例如，第一导电图案层213包括用于显示像素区210的栅线71或栅线71的部分。将栅线71设置在第二绝缘层214远离衬底基板211的一侧，因而使得凹槽220的设置不受栅线71的限制，由此凹槽220的设置位置可以更加灵活以及设置面积可以更大。
第一绝缘层212和第二绝缘层214依次层叠设置于衬底基板211与该第一导电层213之间，可以根据具体的阵列基板结构进行布局，而并不限定于特定的绝缘层结构。
例如，该第二绝缘层214为最靠近该衬底基板211的有机绝缘层。在凹槽220暴露衬底基板211的情形下，这种设置可以使得在垂直于衬 底基板211的方向上、对应于凹槽220的位置的绝缘材料均为有机绝缘材料，因而可以更好地提高阵列基板200的抗冲击性能和耐弯折性能。
例如，凹槽220包括第一部分221，该第一部分221平行于栅线71(如图2)或与栅线71在垂直于衬底基板211的方向上重叠。例如，该第一部分221的长度方向与栅线的延伸方向平行。需要说明的是，本公开中图案的延伸不限于沿直线延伸，还可以沿曲线延伸，如蛇形延伸。
例如，栅极层250包括第一晶体管110的第一栅极111。
例如，栅极层250还包括第二晶体管120的第二栅极121。
例如，半导体层240位于栅极层250靠近衬底基板211的一侧，包括第一晶体管110的第一有源层112和第二晶体管120的第二有源层122。
例如，如图2所示，该凹槽220还包括第三部分223，第三部分223与第二晶体管的第二栅极121平行且对应设置，在第三凹槽223的长度方向(即第一方向D1)上，该第三部分223的长度大于与该第二栅极121的长度，从而对作为像素驱动晶体管的第二晶体管120形成有效保护。例如，由于半导体层240中被栅极覆盖的区域通常作为晶体管的沟道区，因此，将该凹槽的第三部分223设置为在第一方向D1上的长度大于该第二栅极121的长度，也即大于该第二晶体管120的沟道区长度，可以有效保护该沟道区。
例如，凹槽220的不同部分可以具有不同的深度，可以根据实际可用空间灵活设计，本公开实施例对此不作限制。
在一些示例中，例如，凹槽220可以围绕第二栅极121形成口字状。由于半导体层240的存在，凹槽220可以在与半导体层240重叠(相对于衬底基板)的位置的深度较浅，例如凹槽220在纵向上贯穿至半导体层240的表面，这样可以避免对半导体层240造成损伤。
以上对凹槽的描述主要以第二晶体管为示例，在基板中空间允许的情形下，可以对每个像素中的每个晶体管作类似的设置，例如，每个晶体管的栅极周围都对应设置有上述凹槽。
例如，栅极层250在第二绝缘层214靠近衬底基板211的一侧。
例如，第一晶体管110的第一栅极111通过第二绝缘层214中的第 一过孔241与栅线71电连接。
例如，在垂直于衬底基板的方向(参见图3中的方向D)上，栅极层250也可以位于第一绝缘层212和第二绝缘层214之间，例如第一绝缘层212充当第一晶体管110和第二晶体管120的栅极绝缘层。本公开的实施例对此不作限制。
例如，栅极层250的材料可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料；或者导电金属氧化物材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。
例如，半导体层240的材料包括但不限于硅基材料(非晶硅a-Si、多晶硅p-Si等)、金属氧化物半导体(IGZO、ZnO、AZO、IZTO等)以及有机物材料(六噻吩，聚噻吩等)。
在本公开的一些实施例中，第一晶体管110和第二晶体管120均为顶栅型结构，在其它一些实施例中，第一晶体管110和第二晶体管120也可以是底栅结构。例如，第一晶体管110为顶栅结构，第二晶体管120为底栅结构。顶栅型结构的晶体管具有较小的寄生电容从而能具有更快的开启速度；底栅型结构的晶体管具有较大的开态电流和电学稳定性能，从而具有更强的驱动能力。例如，第一晶体管110和第二晶体管120为薄膜晶体管。本公开实施例对于第一晶体管110和第二晶体管120的具体结构和类型不作限制。
例如，第一晶体管110包括第一源极113和第一漏极114。例如，第一源极113或第一漏极114与第二晶体管120的第二栅极121电连接。
例如，第一源极113、第一漏极114与数据线61同层设置且材料相同，由此可以通过同一构图工艺得到。例如，第一源极113或第一漏极114与数据线61电连接以接收用于发光的数据信号。例如，第一源极113和第一漏极114中不与第二晶体管120的第二栅极121电连接的电极与数据线61电连接。
例如，凹槽220还可以包括第二部分222，第二部分222与数据线61平行或在垂直于衬底基板211的方向上与数据线重叠。例如，第二部分222的长度方向与数据线61的延伸方向平行(如图2)。
例如，阵列基板200还包括栅连接电极72，栅连接电极72位于栅极层250与第一导电图案层213之间，用于连接第一栅极111和栅线71。由于过孔深度过大容易使得填充入过孔中的导电材料产生褶皱或发生断裂(尤其是在弯折状态下)而导致接触电阻过大或接触不良，通过设置栅连接电极连接第一栅极111和栅线71，可以避免直接连接第一栅极111和栅线71的连续过孔的深度过深，有助于提高阵列基板的良率和耐弯折性能。
例如，栅连接电极72可以与栅极层250与第一导电图案层213之间的任一导电层同层设置且材料相同，由此可以通过同一构图工艺得到。
例如，栅连接电极72位于第二绝缘层214与第一导电图案层213之间；例如，阵列基板还包括设置于栅连接电极72与第一导电图案层213之间的第三绝缘层216。例如，栅连接电极72通过第二绝缘层214中的第一过孔241与第一栅极111电连接，并通过第三绝缘层216中的第二过孔261与栅线71电连接，从而使得栅线71与第一栅极111电连接。
例如，栅连接电极72与第一晶体管110的第一源极113、第一漏极114同层设置且材料相同，由此可以通过同一构图工艺得到。例如，在垂直于衬底基板的方向上，第三绝缘层216位于第二源极123和第二漏极124以及第一导电图案层213之间。
例如，第二晶体管120还包括第二源极123和第二漏极124。例如，第二源极123和第二漏极124位于第二绝缘层214与第一导电图案层213之间。例如，第二源极123和第二漏极124与第一源极113、第一漏极114同层设置且材料相同，由此可以通过同一构图工艺得到。
例如，发光元件300包括第一电极301、发光层302和第二电极303。这里第一电极301为像素电极，而第二电极303为公共电极。第一电极301和第二电极303之一为阳极，另一个为阴极。例如，在至少一个示例中，发光元件300除了发光层302之外还可以包括空穴注入层、空穴传输层、电子注入层、电子传输层等至少之一。
例如，第二晶体管120的第二源极123或第二漏极124与发光元件 300的第一电极301(像素电极)电连接。
例如，发光元件300位于第一导电图案层213远离衬底基板211的一侧。例如，阵列基板200还包括位于第一导电图案层213上的第四绝缘层218，发光元件300形成于第四绝缘层218上，第二晶体管120的第二源极123或第二漏极124与发光元件300的第一电极301通过第四绝缘层218中的第三过孔281电连接。
例如，阵列基板200还包括驱动连接电极230，驱动连接电极230位于第二晶体管120的第二源极123(或第二漏极124)与发光元件300的像素电极之间，并连接第二晶体管120的第二源极123(或第二漏极124)与发光元件300的像素电极。该驱动连接电极230除了具有类似于栅连接电极72的降低过孔深度的效果，还可以提高阵列基板200的像素分布密度并降低第二晶体管120与像素电极之间的电阻。
例如，如图3所示，驱动连接电极230与凹槽220在垂直于衬底基板221的方向重叠。
例如，如图2所示，驱动连接电极230与栅线71同层设置且材料相同，由此可以通过同一构图工艺得到，也即第一导电图案层213还包括驱动连接电极230。驱动连接电极230通过第三绝缘层216中的第四过孔264与第二晶体管120的第二源极123或第二漏极124电连接，并通过第三过孔281与发光元件300的第一电极301电连接。
例如，发光元件300可以为顶发射、底发射或双面发射结构。例如，发光元件300为顶发射结构，第一电极301具有反射性而第二电极303具有透射性或半透射性，例如第一电极301为氧化铟锡(ITO)等透明导电氧化物材料。例如，第一电极301为高功函数的材料以充当阳极，例如为ITO/Ag/ITO叠层结构；第二电极303为低功函数的材料以充当阴极，例如为半透射的金属或金属合金材料，例如为Ag/Mg合金材料。
例如，该第三绝缘层216和第四绝缘层218为平坦化层。例如，该第三绝缘层216和第四绝缘层218均为有机材料，例如为聚酰亚胺(PI)等树脂。
例如，该阵列基板200还包括存储电容Cst，例如用于在像素电路的工作过程中存储数据信号。该存储电容的设置方式和连接方式可以根 据具体的像素电路结构进行调整。例如，如图3所示，在垂直于衬底基板的方向上，该存储电容的第一电容电极411设置于第一绝缘层212和第二绝缘层214之间；第二电容电极412例如与第一晶体管110的第一栅极111同层设置且材料相同，由此可以通过同一构图工艺得到，第一电容电极411和第二电容电极412正对设置构成该存储电容Cst。
例如，相对于衬底基板所在的平面，凹槽220的至少一部分设置于第二晶体管120和存储电容Cst之间。
例如，阵列基板200还包括设置于发光元件300的第一电极301上的像素界定层215，用于隔离相邻的发光元件的发光层，从而在显示操作中防止串色。像素界定层215在对应于第一电极301的位置形成开口以至少部分暴露出第一电极301，在该开口中形成发光层302。在发光层302以及像素界定层上形成第二电极303。例如，该像素界定层215为树脂等有机材料或氧化硅等无机材料。
例如，阵列基板200还包括设置于像素界定层215上的隔垫层217。例如，隔垫层217用于在蒸镀形成有机发光层302时支撑蒸镀掩膜板，从而将像素界定层215与蒸镀掩膜板进行隔离以对像素界定层215形成保护；隔垫层217还可以起到进一步隔离相邻有机发光层的作用。隔垫层217通常包括由间隔的多个隔垫物(Spacer)，隔垫物的形状通常为长方体、柱状、球状、半球状或不限于此。
例如，阵列基板200还包括设置于该第二电极303之上的保护层219。保护层219例如为无机保护层或有机保护层，或无机保护层和有机保护层的叠层。此外，保护层219中还可以包括还原性材料和/或吸湿性材料，以避免氧/水汽对发光元件300的不利影响。
例如，阵列基板200还包括设置于栅极层250与半导体层240之间的栅极绝缘层207。
例如，栅极绝缘层207的材料为硅的氧化物、硅的氮化物或硅的氮氧化物。
例如，在至少一个实施例中，凹槽220还贯穿栅极绝缘层207以暴露衬底基板211。
例如，在垂直于衬底基板的方向上，阵列基板200还包括设置于衬 底基板211与半导体层240之间的缓冲层(未示出)。该缓冲层用于使的衬底基板211的表面更为平整，还可以防止衬底基板211中的有害杂质进入像素电路。例如，该凹槽220可暴露该缓冲层而不再穿过该缓冲层以暴露衬底基板。
例如，该阵列基板200为柔性阵列基板。例如，该衬底基板211为有机柔性材料，例如聚酰亚胺(PI)、聚乙烯对苯二甲酸乙二醇酯(PET)、聚碳酸酯、聚乙烯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜等。
如图4所示，本公开的一些实施例还提供一种显示面板20，该显示面板20包括上述阵列基板200。例如，该显示面板为OLED显示面板，相应地其包括的阵列基板为OLED阵列基板，像素单元包括的发光元件为OLED。例如，该显示面板还包括设置于阵列基板200上的封装层501和盖板502，该封装层501配置为对发光元件300进行密封以防止外界的湿气和氧向该发光元件及像素电路的渗透而造成对器件的损坏。例如，封装层501包括有机薄膜或者包括有机薄膜及无机薄膜交替层叠的结构。例如，该封装层501与阵列基板200之间还可以设置吸水层(未示出)，配置为吸收发光元件300在前期制作工艺中残余的水汽或者溶胶。盖板502例如为玻璃盖板。例如，盖板502和封装层501可以为一体的结构。
在另一个示例中，显示面板20为液晶显示面板，该显示面板20还包括与该阵列基板对置的彩膜基板以及设置于该阵列基板与彩膜基板之间的液晶层。
本公开的一些实施例还提供一种显示装置，包括上述阵列基板或显示面板。该显示装置例如可以为液晶显示装置、OLED显示装置或电子纸、数码相框、智能手环、智能手表、手机、平板电脑、显示器、笔记本电脑、导航仪等具有任何显示功能的产品或者部件。
本公开的一些实施例还提供一种阵列基板的制造方法，所述阵列基板包括用于提供阵列排布的像素单元的显示像素区。所述制作方法包括：提供衬底基板；在所述衬底基板上形成第一绝缘层，并在所述第一绝缘层上形成凹槽，所述凹槽形成于所述显示像素区；在所述第一绝缘层上形成第二绝缘层，且所述第二绝缘层还填充入所述凹槽中；在所述 第二绝缘层上形成第一导电图案层。
图5为本公开一实施例提供的阵列基板的制作方法的流程图。以下将结合图1、图3和图5对本公开实施例提供的阵列基板的制作方法进行示例性说明，形成该阵列基板的制作方法至少包括步骤S51至步骤S53。
步骤S51：提供衬底基板，并在所述衬底基板上形成第一绝缘层，并在所述第一绝缘层上形成凹槽，所述凹槽形成于所述显示像素区；
步骤S52：在所述第一绝缘层上形成第二绝缘层，且所述第二绝缘层还填充入所述凹槽中；以及
步骤S53：在所述第二绝缘层上形成第一导电图案层。
在步骤S51的一个示例中，先提供衬底基板211，然后在衬底基板211上形成第一绝缘层212并在第一绝缘层212中形成凹槽220。例如，在形成第一绝缘层212之前在衬底基板211上依次形成半导体层240、栅极绝缘层207以及栅极层250。
例如，衬底基板211为有机柔性材料，例如聚酰亚胺(PI)、聚乙烯对苯二甲酸乙二醇酯(PET)、聚碳酸酯、聚乙烯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜等。
例如，形成栅极层包括形成第一导电层并对该导电层进行构图工艺形成第一晶体管110的栅极111和第二晶体管120的第二栅极121。
例如，该第一导电层的材料为金属材料，例如为铜、铝、镁、钼、铬以及上述金属的合金等。
例如，形成凹槽220包括对第一绝缘层212进行刻蚀。
例如，凹槽220与半导体层240及栅极层250在垂直于衬底基板211的方向上均不重叠。
例如，凹槽220还贯穿栅极绝缘层207以暴露衬底基板211。
例如，第一绝缘层212可以是有机绝缘材料，如聚酰亚胺等树脂材料；也可以是无机绝缘材料，如硅的氧化物、硅的氮化物或硅的氮氧化物或者金属氧化物绝缘材料。
例如，在形成过程中可以采用常规的例如溅射工艺的物理气相沉积(例如形成导电层)、化学气相淀积工艺(例如形成绝缘层)、旋涂工 艺(例如形成有机层)、光刻工艺(例如进行构图工艺)等。
在步骤S52的一个示例中，第二绝缘层212的材料为有机绝缘材料，例如为聚甲基丙烯酸甲酯、聚碳酸酯、聚苯乙烯、环氧树脂、聚酰亚胺、聚乙烯中的至少一种。例如，第二绝缘层212的形成方法包括旋涂或喷墨打印。例如，第二绝缘层212的形成方法还包括固化。
有机绝缘材料相对于无机绝缘材料具有更好的柔韧性，因而可以更进一步提高阵列基板200的抗冲击性能和耐弯折性能。
例如，步骤S52还包括对第二绝缘层214进行刻蚀以形成第一过孔241以及第一晶体管110和第二晶体管120的源漏极接触孔。该第一过孔241还贯穿第一绝缘层212以暴露出栅极层250的至少部分。该源漏极接触孔还贯穿第一绝缘层212以及栅极绝缘层207以分别暴露出半导体层240的至少部分。
在步骤S53的一个示例中，该步骤还包括在形成第一导电图案层213之前在第二绝缘层214上依次形成第二导电层以及第三绝缘层216。例如，对该第二导电层进行构图工艺形成第一晶体管110的第一源极113和第一漏极114、第二晶体管120的第二源极123和第二漏极124。例如，对该第二导电层进行构图工艺还形成栅连接电极72和数据线61，栅连接电极72经第一过孔241并与第一栅极111电连接。第一晶体管110的第一源极113和第一漏极114分别经源漏极接触孔与第一有源层112接触形成电连接，第二晶体管120的第二源极123和第二漏极124分别经源漏极接触孔与第二有源层122接触形成电连接。
例如，步骤S53还包括对第三绝缘层216进行构图工艺形成第二过孔261和第四过孔262。第二过孔261暴露出栅连接电极72的至少部分；第四过孔262暴露出第二晶体管120的第二源极123或第二漏极124的至少部分。
例如，形成第一导电图案层213包括形成第三导电层并对该第三导电层进行构图工艺形成栅线71及驱动连接电极230。栅线71经第二过孔261与栅连接电极72电连接。驱动连接电极230经第四过孔262与第二晶体管120的第二源极123或第二漏极124电连接。
例如，该阵列基板的制作方法还包括在第一导电图案层213上形成 发光元件300，形成发光元件300包括依次形成第一电极301、发光层302和第二电极303，该第一电极301与驱动连接电极230电连接。
例如，该阵列基板的制作方法还包括形成第四绝缘层218、像素界定层215、隔垫层217和保护层219。此处不再赘述。
例如，上述导电层的材料可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料；或者导电金属氧化物材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (20)

  1. 一种阵列基板，包括显示像素区，所述显示像素区用于提供阵列排布的像素单元，所述阵列基板还包括：
    衬底基板，
    第一绝缘层，设置于所述衬底基板上，且所述第一绝缘层中设置有凹槽，所述凹槽设置于所述显示像素区；
    第二绝缘层，设置在所述第一绝缘层上，且所述第二绝缘层还填充入所述凹槽中；
    第一导电图案层，设置在所述第二绝缘层上。
  2. 如权利要求1所述的阵列基板，其中，所述第二绝缘层为有机绝缘层。
  3. 如权利要求1或2所述的阵列基板，其中，所述凹槽暴露所述衬底基板。
  4. 如权利要求1-3任一所述的阵列基板，其中，所述第一导电图案层包括用于所述显示像素区的栅线或所述栅线的部分。
  5. 如权利要求4所述的阵列基板，所述凹槽包括第一部分，其中，所述凹槽的第一部分平行于所述栅线或与所述栅线在垂直于所述衬底基板的方向上重叠。
  6. 如权利要求4或5所述的阵列基板，所述像素单元包括第一晶体管，所述第一晶体管包括第一栅极，所述第一栅极在所述第二绝缘层靠近所述衬底基板的一侧，且通过所述第二绝缘层中的第一过孔与所述栅线电连接；
    所述阵列基板还包括栅连接电极，其中，所述栅连接电极位于所述第二绝缘层与所述第一导电图案层之间，所述第一栅极通过所述栅连接电极与所述栅线电连接。
  7. 如权利要求6所述的阵列基板，其中，所述第一晶体管还包括第一源极和第一漏极，所述阵列基板还包括用于所述显示像素区的数据线，
    所述第一源极和所述第一漏极及所述数据线与所述栅连接电极同层设置且材料相同。
  8. 如权利要求7所述的阵列基板，
    所述凹槽还包括第二部分，所述凹槽的第二部分与所述数据线平行或在垂直于所述衬底基板的方向与所述数据线重叠。
  9. 如权利要求8所述的阵列基板，其中，所述像素单元还包括第二晶体管，
    所述第二晶体管包括第二栅极，所述第二栅极与所述第一晶体管的第一源极或第一漏极连接。
  10. 如权利要求9所述的阵列基板，其中，所述凹槽围绕所述第二栅极分布。
  11. 如权利要求9或10所述的阵列基板，其中，所述凹槽还包括第三部分，所述第三部分与所述第二栅极平行且对应设置；
    在所述第三凹槽的长度方向上，所述第三部分的长度大于所述第二栅极的长度。
  12. 如权利要求9-11任一所述的阵列基板，所述第二晶体管包括第二源极和第二漏极，所述阵列基板还包括第三绝缘层；
    其中，在垂直于所述衬底基板的方向上，所述第二源极和第二漏极位于所述第二绝缘层与所述第一导电图案层之间；在垂直于所述衬底基板的方向上，所述第三绝缘层位于所述第二源极和第二漏极与所述第一导电图案层之间。
  13. 如权利要求12所述的阵列基板，还包括层叠设置于所述第一导电图案层之上的第四绝缘层和像素电极，
    其中，所述第二源极或第二漏极通过所述第四绝缘层中的第二过孔与所述像素电极电连接。
  14. 如权利要求11-13任一所述的阵列基板，其中，所述第一导电图案层还包括驱动连接电极，
    所述第二源极或第二漏极通过所述驱动连接电极与所述像素电极连接。
  15. 如权利要求6-14任一所述的阵列基板，还包括第一电容电极，其中，在垂直于所述衬底基板的方向上，所述第一电容电极设置于所述第一绝缘层和所述第二绝缘层之间。
  16. 如权利要求15所述的阵列基板，还包括第二电容电极，其中，所述第二电容电极与所述第一栅极同层设置且与所述第一电容电极正对形成电容。
  17. 一种显示面板，包括如权利要求1-16任一所述的阵列基板。
  18. 一种阵列基板的制作方法，所述阵列基板包括用于提供阵列排布的像素单元的显示像素区，
    其中，所述制作方法包括：
    提供衬底基板，
    在所述衬底基板上形成第一绝缘层，并在所述第一绝缘层上形成凹槽，所述凹槽形成于所述显示像素区中；
    在所述第一绝缘层上形成第二绝缘层，且所述第二绝缘层还填充入所述凹槽中；
    在所述第二绝缘层上形成第一导电图案层。
  19. 如权利要求18所述的制作方法，其中，所述第一绝缘层为有机绝缘层。
  20. 如权利要求18或19所述的制作方法，其中，形成所述第一导电图案层包括：形成用于所述显示像素区的栅线或形成所述栅线的部分。
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