WO2014180111A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

Info

Publication number
WO2014180111A1
WO2014180111A1 PCT/CN2013/087156 CN2013087156W WO2014180111A1 WO 2014180111 A1 WO2014180111 A1 WO 2014180111A1 CN 2013087156 W CN2013087156 W CN 2013087156W WO 2014180111 A1 WO2014180111 A1 WO 2014180111A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
array substrate
spacer
passivation layer
switch unit
Prior art date
Application number
PCT/CN2013/087156
Other languages
English (en)
French (fr)
Inventor
张家祥
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/386,592 priority Critical patent/US9740053B2/en
Publication of WO2014180111A1 publication Critical patent/WO2014180111A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the spacers are all located on opposite substrates.
  • a spacer having a predetermined height is formed by applying a layer of an organic resin layer on the opposite substrate and then performing a photolithography process. After the array substrate and the opposite substrate are paired with the cartridge, the end of the spacer is in contact with the array substrate, and the contact position is at the highest position of the array substrate.
  • the spacer slides down to a lower position, and it is difficult to return to the original position, thereby causing the array substrate to be misaligned, thereby causing light leakage.
  • inventions of the present invention provide an array substrate.
  • the array substrate includes: a substrate, and a switch unit disposed on the substrate.
  • the array substrate further includes: a passivation layer disposed on the substrate; and a spacer disposed on the passivation layer. The spacer corresponds to the switch unit.
  • the passivation layer and the spacer are made of an organic resin material.
  • the passivation layer and the spacer are integrally formed.
  • the switching unit is a thin film transistor.
  • the thin film transistor is of a bottom gate type or a top gate type.
  • the array substrate further includes a common electrode.
  • the passivation layer covers the switching unit.
  • embodiments of the present invention provide a display device including the above array substrate.
  • an embodiment of the present invention provides a method of fabricating an array substrate, the method comprising: forming a switching unit on a substrate. The method further includes: forming a passivation layer on the substrate and forming a spacer corresponding to the switch unit.
  • the passivation layer and the spacer are made of an organic resin material.
  • the method comprises: forming a film made of a positive or negative organic resin material on a substrate; exposing the film by using a gray tone mask or a halftone mask, and developing the film to cover the substrate a passivation layer and the spacer corresponding to the switch unit.
  • the switching unit is a thin film transistor.
  • the thin film transistor is of a bottom gate type or a top gate type.
  • the method further includes: forming a common electrode on the substrate.
  • the passivation layer is formed to cover the switching unit.
  • FIG. 7 is a schematic diagram of a process for fabricating an array substrate according to a first embodiment of the present invention
  • FIG. 8 is a schematic structural view of an array substrate according to Embodiment 2 of the present invention
  • FIG. 9 is a schematic structural diagram of another array substrate according to Embodiment 2 of the present invention. detailed description
  • This embodiment provides a method of fabricating an array substrate, the method comprising forming a switching unit on a substrate.
  • the method also includes forming a passivation layer on the substrate and forming a spacer corresponding to the switching unit.
  • the switching unit may be a thin film transistor (Thin Film Transistor). And may include: a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode.
  • Thin Film Transistor Thin Film Transistor
  • the spacer corresponding to the switch unit means that the spacer is located above the switch unit as seen from the direction of the vertical array substrate.
  • This embodiment provides a method of fabricating an array substrate, the method comprising forming a switching unit, a passivation layer, and a spacer corresponding to the switching unit on the substrate.
  • the spacer not only serves to maintain the thickness of the case, but also has the effect of maintaining the uniformity of the thickness of the display panel behind the case. However, when the array is reversed from the opposite substrate, the uniformity of the thickness of the display panel is affected. In the embodiment, since the spacer is formed on the array substrate, the thickness of the box can be made more uniform, thereby improving the display effect.
  • the passivation layer covers the switching unit.
  • the passivation layer and the spacer are made of an organic resin material and integrally formed.
  • the organic resin material has a good dielectric constant, it can be used as a material for preparing a passivation layer.
  • the method comprises: forming a film made of a positive or negative organic resin material on a substrate; exposing the film by using a gray tone mask or a halftone mask, and developing the passivation of the cover substrate after development a layer and the spacer corresponding to the switch unit.
  • the passivation layer and the spacer are formed by one patterning process, which can reduce the number of patterning processes and simplify the process flow, thereby saving cost.
  • the method for preparing the array substrate provided in this embodiment may include the following steps.
  • a metal thin film is formed on the substrate 10, and a gate electrode 201 as shown in FIG. 1 is formed by one patterning process.
  • gate lines and gate line leads can also be formed in this step.
  • a magnetron sputtering method can be used to prepare a layer of thickness 1000A on a glass substrate.
  • 7000A metal film The metal material can usually be a metal such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a combination of the above-mentioned materials.
  • the metal thin film is patterned by exposure, development, etching, peeling, or the like using a mask to form a gate electrode 201, a gate line, and a gate line on the substrate.
  • a gate insulating layer 202 as shown in FIG. 2 is formed on the substrate on which step S101 is completed.
  • a gate insulating layer 202 as shown in FIG. 2 is formed.
  • an insulating layer film having a thickness of 1000 A to 6000 A may be deposited on the substrate by chemical vapor deposition, and the material of the insulating layer film is usually silicon nitride.
  • the gate insulating layer 202 may also be formed using silicon oxide, silicon oxynitride or the like.
  • step S102 On the substrate on which step S102 is completed, an active layer film is formed, and the active layer 203 shown in FIG. 3 is formed by one patterning process.
  • a metal oxide semiconductor thin film having a thickness of 1000 A to 6000 A may be deposited on the substrate by chemical vapor deposition, and then the metal oxide semiconductor thin film may be patterned by exposure, development, etching, peeling, or the like using a mask.
  • the active layer 203 is formed on a substrate.
  • step S103 On the substrate on which step S103 is completed, a metal thin film is formed, and a source electrode 204a and a drain electrode 204b as shown in FIG. 4 are formed by one patterning process.
  • data lines and data line leads can also be formed in this step.
  • a metal film having a thickness of between 1000A and 7000A may be deposited on the substrate, and then the metal film is patterned by exposure, development, etching, peeling, etc. using a mask to form the source electrode on the substrate.
  • a gate electrode 201 includes a gate electrode 201, a gate insulating layer 202, an active layer 203, and a source electrode 204a and a drain electrode 204b.
  • the switch unit 20 prepared in the above steps S101-S104 is a bottom gate type structure.
  • the embodiment is not limited thereto, and the switch unit 20 may also be a top gate type structure.
  • a transparent conductive film is formed on the substrate on which step S104 is completed, and a pixel electrode 205 as shown in FIG. 5 is formed by one patterning process, and the pixel electrode 205 is electrically connected to the drain electrode 204b.
  • a transparent conductive film having a thickness of between 100 A and 1000 A may be deposited on the entire substrate by chemical vapor deposition.
  • the transparent conductive film may be an ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) film. Then, the transparent conductive film is patterned by exposure, development, etching, peeling, etc. using a mask, The pixel electrode 205 is formed on a substrate.
  • an organic resin film 34 is formed on the substrate on which step S105 is completed.
  • a 3.5-4.2 ⁇ m thick organic resin film can be applied to the substrate according to product design requirements.
  • a 4.0 ⁇ m thick positive organic resin film 34 may be coated on the substrate.
  • the passivation layer 30 and the spacer are formed as shown in FIG.
  • the object 40, and the spacer 40 corresponds to the switch unit 20.
  • the gray tone mask 50 is used to selectively expose and develop the photoresist by a grating effect to make the intensity of light transmitted through different regions during exposure different.
  • the gray tone mask 50 includes an opaque portion 501, a translucent portion 502, and the opaque portion 501 corresponds to the spacer 40 to be formed, and the light transmittance of the translucent portion 502 may be blunt depending on the formation.
  • the thickness of the layer 30 depends on the thickness of the layer 30.
  • the height of the spacer 40 is about 3.5 ⁇ m, and the thickness of the passivation layer 30 is about 0.6 ⁇ m. Therefore, the light transmittance of the translucent portion 502 of the gray tunable mask 50 can be set to about 85% (3.5/4.1), so that after exposure and development, passivation with a thickness of about 0.6 ⁇ can be formed.
  • a halftone mask can also be used in this step.
  • the principle of the halftone mask is similar to that of the gray mask 50, and will not be described herein.
  • the produced organic resin film 34 may be a negative organic resin, in which case the gray tunable mask 50 includes a transparent portion and a translucent portion, and the transparent portion and the portion to be formed Corresponding to the spacer 40, the light transmittance of the translucent portion 502 may be determined according to the thickness of the passivation layer 30 to be formed, and details are not described herein again.
  • the array substrate provided in this embodiment can be applied to a liquid crystal display device of a type such as an advanced super-dimensional field conversion type or a planar conversion type.
  • a multi-dimensional electric field is formed by an electric field generated by the edge of the slit electrode in the same plane and an electric field generated between the slit electrode layer and the plate electrode layer, so that the slit electrode is in the liquid crystal cell All of the aligned liquid crystal molecules directly above the electrode can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field-conversion array substrate improves the picture quality of TFT-LCD products with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no squeeze water ripple (push Mura) ) Etc.
  • the method further includes:
  • a transparent conductive film is formed on the substrate on which step S107 is completed, and the common electrode 60 shown in Fig. 9 is formed by one patterning process.
  • the passivation layer and the spacer are simultaneously formed of the same material.
  • the embodiment is not limited thereto, and the passivation layer and the spacer may be formed of different materials, and the passivation layer and the spacer may be formed separately by different patterning processes.
  • the passivation layer and the spacer are formed of an organic resin material.
  • the embodiment is not limited thereto, and the passivation layer and the spacer may be formed of other materials that can be patterned.
  • the passivation layer and the spacer are in direct contact.
  • the embodiment is not limited thereto, and another layer may be interposed between the passivation layer and the spacer so that the passivation layer and the spacer are not in direct contact.
  • the method for preparing the array substrate is not limited to the above-mentioned preparation methods, and may include other methods, and only needs to form a switching unit, a passivation layer, and a corresponding switch unit on the substrate.
  • the spacer can be used, and will not be described here.
  • the embodiment provides a method for preparing an array substrate, the method comprising: forming a thin film transistor switching unit including a gate electrode, a gate insulating layer, an active layer, and a source electrode and a floor electrode on the substrate, the pixel electrode, and the passivation a layer, a spacer corresponding to the switch unit, and a common electrode.
  • forming the spacer on the array substrate can avoid the problem of positional displacement of the spacer and the array substrate, thereby preventing light leakage caused by the deviation of the opposite substrate and the array substrate from the cassette, and can also make The thickness of the display panel behind the box is more uniform, thereby improving the display effect.
  • advanced super-dimensional field-converting array substrates have the advantages of high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no squeezing water ripple.
  • the array substrate includes a substrate 10 and a switch unit 20 disposed on the substrate.
  • the array substrate further includes: a passivation layer 30 disposed on the substrate; and a spacer 40 disposed on the passivation layer, and the spacer 40 corresponds to the switch unit 20.
  • the switching unit 20 is a thin film transistor and includes a gate electrode 201, a gate insulating layer 202, an active layer 203, and a source electrode 204a and a drain electrode 204b.
  • the spacer 40 corresponds to the switch unit 20" as described herein means that the spacer 40 is located above the switch unit 20 as seen from the direction of the vertical array substrate.
  • the embodiment provides an array substrate comprising a switching unit 20 disposed on the substrate, a passivation layer 30, and a spacer 40 disposed on the passivation layer corresponding to the switching unit.
  • the spacers 40 are disposed on the array substrate, which can avoid the problem of the positional displacement of the spacers and the array substrate, thereby preventing light leakage caused by the deviation of the opposite substrate and the array substrate from the cassette, and can also make the pair
  • the thickness of the display panel behind the box is more uniform, thereby improving the display effect.
  • the material of the passivation layer 30 and the spacer 40 may be an organic resin material. Since the organic resin material has a good dielectric constant, it can be used as a material for preparing a passivation layer.
  • the passivation layer 30 and the spacer 40 can be formed by one patterning process, which can reduce the number of patterning processes and simplify Process flow, which saves costs.
  • the array substrate may further include a common electrode.
  • An embodiment of the present invention provides an array substrate including a switch unit 20 disposed on a substrate, a passivation layer 30, a spacer 40 disposed on the passivation layer corresponding to the switch unit, and a common electrode 60.
  • the spacers 40 are disposed on the array substrate, which can avoid the problem of the positional displacement of the spacers and the array substrate, thereby preventing the light leakage problem caused by the deviation of the opposite substrate and the array substrate from the cassette, and also The thickness of the display panel after the box can be made more uniform, thereby improving the display effect.
  • the advanced super-dimensional field-converting array substrate has the advantages of high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no squeezing water ripple.
  • the embodiment of the invention further provides a display device comprising any one of the above array substrates.
  • the display device may be a product or component having any display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer, or the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Nonlinear Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Ceramic Engineering (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种阵列基板及其制备方法、显示装置，阵列基板包括：基板（10），设置在基板上的开关单元（20）。阵列基板还包括：设置在基板（10）上的钝化层（30）以及设置在钝化层（30）上的隔垫物（40）。隔垫物（40）与开关单元（20）对应。

Description

阵列基板及其制备方法、 显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制备方法、 显示装置。 背景技术
在薄膜晶体管液晶显示器（ Thin Film Transistor-Liquid Crystal Display, 简称 TFT-LCD )中， 为了形成液晶旋光所需的液晶盒厚， 隔垫物是必不可少 的。
目前， 隔垫物都是位于对置基板上。 通过在对置基板上涂覆一层有机树 脂层， 再通过光刻工艺形成具有预定高度的隔垫物。 在阵列基板和对置基板 对盒后， 隔垫物的端部与阵列基板接触， 并且接触位置处于阵列基板的最高 位置。 当阵列基板受到挤压或者沖压时， 隔垫物会顺势滑落到较低位置， 并 J 艮难恢复到原有位置， 因此会导致阵列基板错位， 从而引发漏光。 发明内容
一方面， 本发明的实施例提供了一种阵列基板。 该阵列基板包括： 基板、 设置在基板上的开关单元。 所述阵列基板还包括： 设置在基板上的钝化层以 及设置在所述钝化层上的隔垫物。 所述隔垫物与所述开关单元对应。
例如， 所述钝化层和所述隔垫物的材质为有机树脂材料。
例如， 所述钝化层和所述隔垫物一体形成。
例如， 所述开关单元为薄膜晶体管。
例如， 所述薄膜晶体管为底栅型或顶栅型。
例如， 所述阵列基板还包括公共电极。
例如， 所述钝化层覆盖所述开关单元。
另一方面， 本发明的实施例提供了一种显示装置， 该显示装置包括上述 的阵列基板。
再一方面， 本发明的实施例提供了一种阵列基板的制备方法， 该方法包 括： 在基板上形成开关单元。 该方法还包括： 在基板上形成钝化层以及形成 与所述开关单元对应的隔垫物。
例如， 所述钝化层和所述隔垫物的材质为有机树脂材料。 包括： 在基板上形成由正性或负性有机树脂材料制成的薄膜； 采用灰色调掩 膜板或半色调掩膜板对所述薄膜进行曝光， 经显影后形成覆盖所述基板的所 述钝化层以及与所述开关单元对应的所述隔垫物。
例如， 所述开关单元为薄膜晶体管。
例如， 所述薄膜晶体管为底栅型或顶栅型。
例如， 所述方法还包括： 在基板上形成公共电极。
例如， 所述钝化层形成为覆盖所述开关单元。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实 施例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面 描述中的附图仅仅是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动的前提下， 还可以根据这些附图获得其他的附图。
图 1-图 7为本发明实施例一提供的阵列基板的制备方法的过程示意图； 图 8为本发明实施例二提供的阵列基板的结构示意图；
图 9为本发明实施例二提供的另一种阵列基板的结构示意图。 具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而 不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有做 出创造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。
实施例一
本实施例提供了一种阵列基板的制备方法， 该方法包括在基板上形成开 关单元。 该方法还包括： 在基板上形成钝化层， 以及形成与所述开关单元对 应的隔垫物。
例如，所述开关单元可以为薄膜晶体管（ Thin Film Transistor,筒称 TFT ), 并可以包括： 栅电极、 栅绝缘层、 有源层、 源电极和漏电极等。
需要说明的是， 这里所描述的 "与所述开关单元对应的所述隔垫物" 是 指， 从垂直阵列基板的方向看过去， 所述隔垫物位于所述开关单元的上方。
本实施例提供了一种阵列基板的制备方法， 该方法包括在基板上形成开 关单元、 钝化层、 以及与所述开关单元对应的隔垫物。 通过在阵列基板上形 成所述隔垫物， 可以避免隔垫物与阵列基板位置偏移的问题， 从而防止了由 于对置基板和阵列基板对盒偏差导致的漏光现象。
隔垫物不仅起到保持盒厚的作用， 还具有保持对盒后的显示面板厚度均 一性的作用。 但是当阵列 反和对置基板对盒出现偏差时， 会影响显示面板 厚度的均一性。 本实施例中由于在阵列基板上形成所述隔垫物， 可使对盒的 厚度更加均一， 进而改善显示效果。
例如， 所述钝化层覆盖所述开关单元。
优选的， 所述钝化层和所述隔垫物的材质可以为有机树脂材料并一体形 成。
由于有机树脂材料具有良好的介电常数， 因此其可以作为制备钝化层的 材料。 包括： 在基板上形成由正性或负性有机树脂材料制成的薄膜； 采用灰色调掩 膜板或半色调掩膜板对所述薄膜进行曝光 , 经显影后形成覆盖基板的所述钝 化层以及与所述开关单元对应的所述隔垫物。
所述钝化层和所述隔垫物通过一次构图工艺形成，可减少构图工艺次数， 简化工艺流程， 从而节约了成本。
例如， 本实施例提供的阵列基板的制备方法可以包括如下步骤。
S101、 在基板 10上制作金属薄膜， 通过一次构图工艺形成如图 1所示 的栅电极 201。
当然， 在该步骤中还可以形成栅线、 以及栅线引线。
需要说明的是， 本发明所有附图是阵列基板的筒略的示意图， 只为清楚 描述本发明的实施例， 而与本发明实施例无关的阵列基板的其他部分在附图 中并未体现或只体现部分。
例如， 可以使用磁控溅射方法， 在玻璃基板上制备一层厚度在 1000A至 7000A的金属薄膜。 金属材料通常可以采用钼、 铝、 铝镍合金、 钼钨合金、 铬、 或铜等金属， 也可以使用上述几种材料薄膜的组合结构。 然后用掩膜板 通过曝光、 显影、 刻蚀、 剥离等对金属薄膜进行构图工艺， 在基板上形成栅 电极 201、 栅线、 以及栅线引线。
S102、 在完成步骤 S101的基板上， 形成如图 2所示的栅绝缘层 202。 例如，可以利用化学气相沉积法在基板上沉积厚度为 1000A至 6000A的 绝缘层薄膜， 所述绝缘层薄膜的材料通常是氮化硅。 也可以使用氧化硅和氮 氧化硅等， 形成所述栅绝缘层 202。
5103、 在完成步骤 S102 的基板上， 制作有源层薄膜， 通过一次构图工 艺形成如图 3所示的有源层 203。
例如， 可以利用化学气相沉积法在基板之上沉积厚度为 1000A至 6000A 的金属氧化物半导体薄膜， 然后用掩膜板通过曝光、 显影、 刻蚀、 剥离等对 金属氧化物半导体薄膜进行构图工艺， 在基板上形成所述有源层 203。
5104、 在完成步骤 S103 的基板上， 制作金属薄膜， 通过一次构图工艺 形成如图 4所示的源电极 204a和漏电极 204b。
当然， 在该步骤中还可以形成数据线、 以及数据线引线。
例如， 可以在基板上沉积一层厚度在 1000A到 7000A之间的金属薄膜， 然后用掩膜板通过曝光、 显影、 刻蚀、 剥离等对金属薄膜进行构图工艺， 在 基板上形成所述源电极 204a和漏电极 204b、 数据线、 以及数据线引线。
通过上述步骤 S101-S104, 所述开关单元 20制备完成， 即所述开关单元
20包括栅电极 201、栅绝缘层 202、有源层 203以及源电极 204a和漏电极 204b。
需要说明的是，上述步骤 S101-S104中制备的开关单元 20为底栅型结构。 然而 , 本实施例并不局限于此， 所述开关单元 20也可以为顶栅型结构。
5105、 在完成步骤 S104 的基板上， 制作透明导电薄膜， 通过一次构图 工艺形成如图 5所示的像素电极 205， 所述像素电极 205与所述漏电极 204b 电连接。
例如， 可以利用化学气相沉积法在整个基板上沉积一层厚度在 100A至 1000A之间的透明导电薄膜。 例如， 透明导电薄膜可以为 ITO ( Indium Tin Oxides, 铟锡氧化物）或 IZO ( Indium Zinc Oxide, 铟锌氧化物）薄膜。 然后 用掩膜板通过曝光、 显影、 刻蚀、 剥离等对透明导电薄膜进行构图工艺， 在 基板上形成所述像素电极 205。
5106、 在完成步骤 S105的基板上， 如图 6所示， 制作有机树脂薄膜 34。 此处， 可以根据产品设计要求在基板上涂覆一层 3.5-4.2μπι厚的有机树 脂薄膜。
例如， 可以在基板上涂覆一层 4.0μπι厚的正性有机树脂薄膜 34。
5107、 在完成步骤 S106的基板上， 利用如图 7所示的灰色调掩膜板 50 对正性有机树脂薄膜 34进行曝光显影工艺后， 形成如图 8所示的钝化层 30 以及隔垫物 40， 且所述隔垫物 40与所述开关单元 20对应。
此处参考图 Ί , 对灰色调掩膜板 50的主要原理说明如下。
灰色调掩膜板 50是通过光栅效应，使曝光时在不同区域透过光的强度不 同， 而使光刻胶进行选择性曝光、 显影。 灰色调掩膜板 50 包括不透明部分 501、 半透明部分 502， 且所述不透明部分 501与要形成的所述隔垫物 40对 应， 所述半透明部分 502的透光率可以根据要形成的钝化层 30的厚度而定。
这里， 例如按目前一般显示产品为例， 其隔垫物 40的高度约为 3.5μηι, 钝化层 30的厚度约为 0.6μηι。 因此， 可以将所述灰色调掩膜板 50的半透明 部分 502的透光率设置为约 85% ( 3.5/4.1 ) , 这样， 经曝光显影后， 便可形 成厚度约为 0.6μΐΒ的钝化层 30, 以及高度约为 3.5μηι的隔垫物 40。
该步骤也可以采用半色调掩模板， 半色调掩膜板的原理与所述灰色调掩 膜板 50类似， 在此不再赘述。
此外， 在步骤 S106中， 制作的有机树脂薄膜 34可以是负性有机树脂， 在此情况下，所述灰色调掩膜板 50包括透明部分以及半透明部分，所述透明 部分与要形成的所述隔垫物 40对应，所述半透明部分 502的透光率可以根据 要形成的钝化层 30的厚度而定， 在此不再赘述。
进一步地， 本实施例提供的阵列基板可以适用于高级超维场转换型、 平 面转换型等类型的液晶显示装置。 在高级超维场转换型液晶显示装置中： 通 过同一平面内狭缝电极边缘所产生的电场以及狹缝电极层与板状电极层间产 生的电场形成多维电场， 使液晶盒内狭缝电极间、 电极正上方所有取向液晶 分子都能够产生旋转， 从而提高了液晶工作效率并增大了透光效率。 高级超 维场转换型阵列基板可以提高 TFT-LCD产品的画面品质， 具有高分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低色差、 无挤压水波纹（push Mura ) 等优点。
因此， 在步骤 S107的基础上， 所述方法还包括：
S108、 在完成步骤 S107 的基板上制作透明导电薄膜， 通过一次构图工 艺形成如图 9所示的公共电极 60。
需要说明的是， 在上述描述中， 所述钝化层和所述隔垫物由相同的材料 同时形成。 然而， 本实施例并不局限于此， 所述钝化层和所述隔垫物可以由 不同的材料形成， 并且所述钝化层和所述隔垫物可以通过不同的构图工艺分 开形成。
需要说明的是， 在上述描述中， 所述钝化层和所述隔垫物由有机树脂材 料形成。 然而， 本实施例并不局限于此， 所述钝化层和所述隔垫物也可以由 其他可以被图案化的材料形成。
需要说明的是， 在上述描述中， 所述钝化层和所述隔垫物直接接触。 然 而， 本实施例并不局限于此， 可以在所述钝化层和所述隔垫物之间插入其他 层而使所述钝化层和所述隔垫物不直接接触。
需要说明的是， 本实施例提供的阵列基板的制备方法并不限于上述列举 的制备方法， 也可以包括其他方法， 只需在基板上形成开关单元、 钝化层、 以及与所述开关单元对应的隔垫物即可， 在此不再赘述。
本实施例提供了一种阵列基板的制备方法， 该方法包括： 在基板上形成 包括栅电极、 栅绝缘层、 有源层、 以及源电极和楼电极的薄膜晶体管开关单 元， 像素电极， 钝化层， 与所述开关单元对应的隔垫物， 以及公共电极。 一 方面， 在阵列基板上形成所述隔垫物， 可以避免隔垫物与阵列基板位置偏移 的问题， 从而防止了由于对置基板和阵列基板对盒偏差导致的漏光现象， 并 且还可以使得对盒后的显示面板厚度更加均一， 进而改善显示效果。 另一方 面， 高级超维场转换型阵列基板具有高分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低色差、 无挤压水波纹等优点。
实施例二
本实施例提供了一种阵列基板， 如图 8和图 9所示， 该阵列基板包括基 板 10、设置在基板上的开关单元 20。 该阵列基板进一步还包括： 设置在基板 上的钝化层 30以及设置在所述钝化层上的隔垫物 40,且所述隔垫物 40与所 述开关单元 20对应。 例如，所述开关单元 20为薄膜晶体管并包括栅电极 201、栅绝缘层 202、 有源层 203以及源电极 204a和漏电极 204b。
需要说明的是，这里所描述的 "所述隔垫物 40与所述开关单元 20对应" 是指， 从垂直阵列基板的方向看过去， 所述隔垫物 40位于所述开关单元 20 上方。
本实施例提供了一种阵列基板， 该阵列基板包括设置在基板上的开关单 元 20、 钝化层 30、 以及设置在钝化层上与所述开关单元对应的隔垫物 40。 将所述隔垫物 40设置在阵列基板上，可以避免隔垫物与阵列基板位置偏移的 问题， 从而防止了由于对置基板和阵列基板对盒偏差导致的漏光现象， 并且 还可以使得对盒后的显示面板的厚度更加均一， 进而改善显示效果。
优选的 , 所述钝化层 30和所述隔垫物 40的材质可以为有机树脂材料。 由于有机树脂材料具有良好的介电常数， 因此其可以作为制备钝化层的 材料。 当所述钝化层 30和所述隔垫物 40的材质为有机树脂材料时， 所述钝 化层 30和所述隔垫物 40便可通过一次构图工艺形成，可减少构图工艺次数， 简化工艺流程， 从而节约了成本。
优选的， 所述阵列基板还可以包括公共电极。
本发明实施例提供了一种阵列基板， 该阵列基板包括设置在基板上的开 关单元 20、 钝化层 30、 设置在钝化层上与所述开关单元对应的隔垫物 40、 以及公共电极 60。 一方面， 将所述隔垫物 40设置在阵列基板上， 可以避免 隔垫物与阵列基板位置偏移的问题， 从而防止了由于对置基板和阵列基板对 盒偏差导致的漏光问题， 并且还可以使得对盒后显示面板的厚度更加均一， 进而改善显示效果。 另一方面， 高级超维场转换型阵列基板具有高分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低色差、 无挤压水波纹等优点。
实施例三
本发明实施例还提供了一种显示装置， 包括上述任意一种阵列基板。 所述显示装置可以为液晶显示器、 液晶电视、 数码相框、 手机、 平板电 脑等具有任何显示功能的产品或者部件。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护 范围应以所述权利要求的保护范围为准。

Claims

权利要求书
1、 一种阵列基板， 包括基板、 设置在基板上的开关单元， 其中 所述阵列基板还包括： 设置在基板上的钝化层以及设置在所述钝化层上 的隔垫物； 并且
所述隔垫物与所述开关单元对应。
2、根据权利要求 1所述的阵列基板，其中所述钝化层和所述隔垫物的材 质为有机树脂材料。
3、根据权利要求 1或 2所述的阵列基板，其中所述钝化层和所述隔垫物 一体形成。
4、根据权利要求 1-3任一项所述的阵列基板， 其中所述开关单元为薄膜 晶体管。
5、根据权利要求 4所述的阵列基板，其中所述薄膜晶体管为底栅型或顶 栅型。
6、根据权利要求 1-5任一项所述的阵列基板， 其中所述阵列基板还包括 公共电极。
7、根据权利要求 1-6任一项所述的阵列基板， 其中所述钝化层覆盖所述 开关单元。
8、 一种显示装置， 包括权利要求 1-7任一项所述的阵列基板。
9、 一种阵列基板的制备方法， 包括在基板上形成开关单元， 其中所述方 法还包括： 在基板上形成钝化层以及形成与所述开关单元对应的隔垫物。
10、 根据权利要求 9所述的方法， 其中所述钝化层和所述隔垫物的材质 为有机树脂材料。
11、根据权利要求 9或 10所述的方法，其中所述在基板上形成钝化层以 及形成与所述开关单元对应的隔垫物包括：
在基板上形成由正性或负性有机树脂材料制成的薄膜；
采用灰色调掩膜板或半色调掩膜板对所述薄膜进行曝光， 经显影后形成
12、根据权利要求 9-11任一项所述的方法， 其中所述开关单元为薄膜晶 体管。
13、根据权利要求 12所述的方法，其中所述薄膜晶体管为底栅型或顶栅 型。
14、根据权利要求 9至 13任一项所述的方法， 其中所述方法还包括： 在 基板上形成公共电极。
15、根据权利要求 9至 14任一项所述的方法，其中所述钝化层形成为覆 盖所述开关单元。
PCT/CN2013/087156 2013-05-07 2013-11-14 阵列基板及其制备方法、显示装置 WO2014180111A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/386,592 US9740053B2 (en) 2013-05-07 2013-11-14 Array substrate, fabrication method thereof, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310164803.6 2013-05-07
CN2013101648036A CN103293776A (zh) 2013-05-07 2013-05-07 一种阵列基板及其制备方法、显示装置

Publications (1)

Publication Number Publication Date
WO2014180111A1 true WO2014180111A1 (zh) 2014-11-13

Family

ID=49094922

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/087156 WO2014180111A1 (zh) 2013-05-07 2013-11-14 阵列基板及其制备方法、显示装置

Country Status (3)

Country Link
US (1) US9740053B2 (zh)
CN (1) CN103293776A (zh)
WO (1) WO2014180111A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103941482B (zh) * 2014-04-18 2016-06-22 京东方科技集团股份有限公司 制作隔垫物的装置及方法、基板和显示装置
CN104199220A (zh) * 2014-07-10 2014-12-10 合肥鑫晟光电科技有限公司 一种显示面板和显示装置
CN104600079B (zh) * 2014-12-30 2017-09-22 厦门天马微电子有限公司 一种液晶显示装置、薄膜晶体管阵列基板及其制作方法
CN104617114B (zh) 2015-02-15 2018-02-13 京东方科技集团股份有限公司 一种阵列基板及其制作方法和显示装置
CN104932152B (zh) * 2015-06-23 2018-11-02 武汉华星光电技术有限公司 液晶显示面板及液晶显示面板的制造方法
US11244930B2 (en) * 2018-08-10 2022-02-08 Innolux Corporation Electronic device with light emitting units with reduced power consumption
CN110488529A (zh) * 2019-09-20 2019-11-22 合肥京东方显示技术有限公司 显示面板、彩膜基板及其制造方法
CN112086471B (zh) * 2020-09-28 2022-11-29 成都中电熊猫显示科技有限公司 阵列基板的制造方法、阵列基板及显示面板
CN114613784A (zh) * 2020-12-07 2022-06-10 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板和显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040059001A (ko) * 2002-12-27 2004-07-05 엘지.필립스 엘시디 주식회사 공정을 단순화한 액정표시장치의 제조방법
US20050140858A1 (en) * 2003-12-30 2005-06-30 Lg Philips Lcd Co., Ltd. Liquid crystal display device and method of manufacturing the same
CN1888962A (zh) * 2005-06-29 2007-01-03 Lg.菲利浦Lcd株式会社 液晶显示设备及其制造方法
CN101657755A (zh) * 2007-04-06 2010-02-24 Lg化学株式会社 制备用于液晶显示器件的隔件的方法，具有由该方法制备的隔件的液晶显示器件的基板和具有该基板的液晶显示器件
CN102346340A (zh) * 2010-08-03 2012-02-08 胜华科技股份有限公司 液晶显示面板

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW507258B (en) * 2000-02-29 2002-10-21 Semiconductor Systems Corp Display device and method for fabricating the same
KR20070036286A (ko) * 2005-09-29 2007-04-03 삼성전자주식회사 액정 표시 장치 및 그 제조 방법
KR20070119280A (ko) * 2006-06-15 2007-12-20 삼성전자주식회사 표시 기판의 제조 방법, 표시 기판 및 이를 갖는액정표시장치
KR101329079B1 (ko) * 2007-04-09 2013-11-20 엘지디스플레이 주식회사 액정표시장치 및 그의 제조방법
JP5235363B2 (ja) * 2007-09-04 2013-07-10 株式会社ジャパンディスプレイイースト 液晶表示装置
US20110085121A1 (en) * 2009-10-08 2011-04-14 Hydis Technologies Co., Ltd. Fringe Field Switching Mode Liquid Crystal Display Device and Method of Fabricating the Same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040059001A (ko) * 2002-12-27 2004-07-05 엘지.필립스 엘시디 주식회사 공정을 단순화한 액정표시장치의 제조방법
US20050140858A1 (en) * 2003-12-30 2005-06-30 Lg Philips Lcd Co., Ltd. Liquid crystal display device and method of manufacturing the same
CN1888962A (zh) * 2005-06-29 2007-01-03 Lg.菲利浦Lcd株式会社 液晶显示设备及其制造方法
CN101657755A (zh) * 2007-04-06 2010-02-24 Lg化学株式会社 制备用于液晶显示器件的隔件的方法，具有由该方法制备的隔件的液晶显示器件的基板和具有该基板的液晶显示器件
CN102346340A (zh) * 2010-08-03 2012-02-08 胜华科技股份有限公司 液晶显示面板

Also Published As

Publication number Publication date
CN103293776A (zh) 2013-09-11
US9740053B2 (en) 2017-08-22
US20160139443A1 (en) 2016-05-19

Similar Documents

Publication Publication Date Title
WO2014180111A1 (zh) 阵列基板及其制备方法、显示装置
US9502436B2 (en) Thin film transistor, array substrate and method for fabricating the same, and display device
US10103173B2 (en) Manufacture method of array substrate and array substrate manufactured by the method
US9859304B2 (en) Manufacturing method of array substrate, array substrate and display device
WO2017166341A1 (zh) Tft基板的制作方法及制得的tft基板
JP6342132B2 (ja) アレイ基板、ディスプレイパネル及びアレイ基板の製造方法
US8179506B2 (en) Method for fabricating a pixel structure and the pixel structure
WO2014187113A1 (zh) 阵列基板及制备方法、显示装置
WO2014166181A1 (zh) 薄膜晶体管及其制造方法、阵列基板及其制造方法、显示装置
WO2014015453A1 (zh) 薄膜晶体管、阵列基板及其制作方法、显示装置
KR101900170B1 (ko) 어레이 기판의 제조 방법, 어레이 기판 및 디스플레이 디바이스
WO2015081652A1 (zh) 阵列基板及其制作方法、显示装置
WO2013155845A1 (zh) 阵列基板的制造方法、阵列基板及显示装置
WO2013155830A1 (zh) 阵列基板的制造方法、阵列基板及显示装置
TW201601292A (zh) 製作顯示面板之方法
KR20180098621A (ko) 저온 폴리실리콘 어레이 기판의 제조방법
WO2017031924A1 (zh) 薄膜晶体管阵列基板、其制作方法及显示装置
WO2015043069A1 (zh) 阵列基板及其制备方法、显示装置
WO2015027632A1 (zh) 一种阵列基板、显示装置及阵列基板的制造方法
WO2016177213A1 (zh) 阵列基板及其制造方法、显示装置
WO2015000257A1 (zh) 阵列基板及其制备方法、显示装置
CN109031833B (zh) 用于ads显示模式的阵列基板及其制作方法和应用
WO2014161258A1 (zh) 阵列基板、显示装置及阵列基板的制造方法
WO2013181908A1 (zh) 阵列基板及其制作方法和显示装置
US20160322404A1 (en) Methods for producing tft array substrate and display apparatus

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14386592

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13884197

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 08.03.2016)

122 Ep: pct application non-entry in european phase

Ref document number: 13884197

Country of ref document: EP

Kind code of ref document: A1