WO2014166181A1 - 薄膜晶体管及其制造方法、阵列基板及其制造方法、显示装置 - Google Patents

薄膜晶体管及其制造方法、阵列基板及其制造方法、显示装置 Download PDF

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WO2014166181A1
WO2014166181A1 PCT/CN2013/080646 CN2013080646W WO2014166181A1 WO 2014166181 A1 WO2014166181 A1 WO 2014166181A1 CN 2013080646 W CN2013080646 W CN 2013080646W WO 2014166181 A1 WO2014166181 A1 WO 2014166181A1
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substrate
area
electrode
photoresist
layer
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PCT/CN2013/080646
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English (en)
French (fr)
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高涛
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京东方科技集团股份有限公司
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Priority to US14/368,308 priority Critical patent/US9711544B2/en
Publication of WO2014166181A1 publication Critical patent/WO2014166181A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Definitions

  • Embodiments of the present invention relate to a thin film transistor and a method of fabricating the same, including an array substrate of the thin film transistor, a method of fabricating the same, and a display device including the array substrate. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the source and the drain are turned on through the semiconductor channel, and the data signal from the data line is applied to the pixel electrode via the TFT.
  • the total capacitance of the TFT . 88+ (channel + Cgd, where Cgs is the capacitance formed by the overlap of the gate and the source, and Cgd is the capacitance formed by the overlap of the gate and the drain. It is expected that both Cgs and Cgd can reach 0 to reduce the total capacitance of the TFT. However, there is a certain overlap between the source, the drain and the gate, because if the gap between the source and the drain is large, the conductivity of the TFT will be affected.
  • the relative positions between the source, the drain and the gate are inconsistent, so the values of Cgs and Cgd in each TFT are not equal, resulting in different total capacitances of the TFTs.
  • the data signals are equal.
  • the voltage charged by the pixel electrode is also inconsistent, which causes a problem of uneven chromaticity of the liquid crystal display.
  • the driving voltage of the TFT is also increased, thereby increasing the charging process. Time required. Summary of the invention
  • a thin film transistor includes a substrate and a gate electrode, a source electrode and a drain electrode disposed on the substrate, a projection of a gap between the source electrode and the drain electrode on the substrate, and a projection of the gate electrode on the substrate coincide.
  • the thin film transistor is a bottom gate type thin film transistor.
  • the thin film transistor further includes a gate insulating layer covering the gate electrode and a semiconductor active layer disposed on the gate insulating layer.
  • the thin film transistor further includes an ohmic contact layer disposed between the semiconductor active layer and the source and drain electrodes.
  • an array substrate is provided.
  • the array substrate includes the above-described thin film transistor.
  • the array substrate further includes a transparent conductive layer and a transparent conductive electrode disposed on the substrate, the transparent conductive layer is disposed under the gate electrode of the thin film transistor, and the transparent conductive electrode is in the same layer as the transparent conductive layer Settings.
  • the transparent conductive electrode functions as a pixel electrode and is electrically connected to a drain electrode of the thin film transistor.
  • a method of fabricating a thin film transistor includes the following steps:
  • a gate electrode, a gate insulating layer, a semiconductor active layer and an ohmic contact layer on the substrate Forming a gate electrode, a gate insulating layer, a semiconductor active layer and an ohmic contact layer on the substrate; using the gate electrode as a mask, exposing and developing the photoresist on the substrate from the back surface of the substrate, and developing The remaining photoresist corresponds to the position of the gate electrode;
  • the source/drain metal film is etched to form a source electrode and a drain electrode.
  • a method of fabricating an array substrate includes the following steps:
  • a gate electrode Forming a gate electrode, a gate line, a gate insulating layer, a semiconductor active layer, an ohmic contact layer, and a transparent conductive electrode on the substrate;
  • the gate electrode as a mask, exposing and developing the photoresist on the substrate from the back surface of the substrate, and the remaining photoresist after development corresponds to the position of the gate electrode;
  • a source electrode, a drain electrode, a data line, and a passivation layer are formed on the substrate.
  • the gate electrode, the gate line, the gate insulating layer, the semiconductor active layer, and the ohmic layer are formed on the substrate.
  • the steps of the contact layer and the transparent conductive electrode include:
  • the developed photoresist forms a completely reserved area, a semi-retained area, and a completely removed area, wherein the completely reserved area is formed correspondingly.
  • Etching the gate metal film and the transparent conductive film in the completely removed region by an etching process performing an ashing process to remove the photoresist in the semi-reserved region;
  • the developed photoresist forms a completely reserved area, a semi-retained area, and a completely removed area, wherein the completely reserved area is formed correspondingly.
  • the step of forming a source electrode, a drain electrode, a data line, and a passivation layer on the substrate includes:
  • the developed photoresist forms a completely reserved area, a semi-retained area and a completely removed area, wherein the completely reserved area is formed correspondingly
  • the area of the active layer of the thin film transistor, the semi-reserved area corresponding to the area where the data line is to be formed, and the rest being the completely removed area;
  • a display device includes the above array substrate.
  • FIG. 1 is a schematic structural view of a thin film transistor according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • 3a to 3g are schematic views showing a method of manufacturing an array substrate according to an embodiment of the present invention. detailed description
  • Embodiments of the present invention provide a thin film transistor (TFT).
  • the thin film transistor includes a substrate 1 and a gate electrode 2, a source electrode 41 and a drain electrode 42 which are disposed on the substrate 1.
  • the projection of the gap between the source electrode 41 and the drain electrode 42 on the substrate 1 coincides with the projection of the gate electrode 2 on the substrate 1. That is, the area of the projection of the gap between the source electrode 41 and the drain electrode 42 on the substrate 1 is equal to the area projected by the gate electrode 2 on the substrate 1.
  • the thin film transistor provided by the embodiment of the present invention is a bottom gate type thin film transistor, that is, the gate electrode 2 is located below the source electrode 41 and the drain electrode 42.
  • the TFT further includes a gate insulating layer 3 covering the gate electrode 2, a semiconductor active layer 51 disposed on the gate insulating layer 3, and a semiconductor active layer 51 disposed between the semiconductor active layer 51 and the source electrode 41 and the drain electrode 42.
  • Ohmic contact layer 52 Embodiments of the present invention provide an array substrate.
  • the array substrate includes a TFT as described above. For example, as shown in FIG.
  • the array substrate includes a substrate 1, a gate electrode 2, a gate line (not shown), a gate insulating layer 3, a semiconductor active layer 51, an ohmic contact layer 52, a source electrode 41, and a leakage current. Pole 42, data line (not shown).
  • the array substrate further includes a transparent conductive layer 60 and a transparent conductive electrode 61 disposed on the substrate 1.
  • the transparent conductive layer 60 is disposed under the gate electrode 2, and the transparent conductive electrode 61 is disposed in the same layer as the transparent conductive layer 60.
  • the array substrate according to an embodiment of the present invention can be applied to a Twisted Nematic (TN) liquid crystal display panel.
  • the transparent conductive electrode 61 functions as a pixel electrode and is electrically connected to the drain electrode 42 of the TFT as shown in FIG.
  • the array substrate according to an embodiment of the present invention can also be applied to an advanced super-dimensional field conversion type.
  • the transparent conductive electrode 61 can be used both as a pixel electrode and electrically connected to the drain electrode; it can also be used as a common electrode and is not electrically connected to the drain electrode.
  • ADSDS ADS
  • a multi-dimensional electric field is formed by an electric field generated by the edge of the slit electrode in the same plane and an electric field generated between the slit electrode layer and the plate electrode layer, so that the slit in the liquid crystal cell All the aligned liquid crystal molecules between the electrodes and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • the ADS type liquid crystal display panel has the advantages of high picture quality, high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no push mura. Improvements to ADS technology for different applications include high-transmission I-ADS technology, high aperture ratio H-ADS, and high-resolution S-ADS technology.
  • the array substrate according to the embodiment of the present invention can also be applied to other types of liquid crystal display panels, such as VA type, IPS type, and FFS type.
  • the array substrate according to an embodiment of the present invention may further include a passivation layer 7 disposed on the source electrode 41, the drain electrode 42, and the active layer 51.
  • the passivation layer 7 protects the TFT from damage, and also acts as an insulator to prevent external electrical signals from interfering with the TFT.
  • Embodiments of the present invention also provide a method of fabricating a TFT, including the following steps:
  • S11 forming a gate electrode, a gate insulating layer, a semiconductor active layer, and an ohmic contact layer on the substrate.
  • S12 using the gate electrode as a mask, exposing and developing the photoresist on the substrate from the back surface of the substrate, and the remaining photoresist after the development corresponds to the position of the gate electrode.
  • S13 depositing a source/drain metal film on the substrate.
  • S14 peeling off the remaining photoresist to form a gap between the source electrode and the drain electrode of the thin film transistor.
  • S16 etching the source/drain metal film to form a source electrode and a drain electrode.
  • the photoresist on the substrate may be the remaining portion of the photoresist used in step S11. Obviously, the photoresist on the substrate may also be a photoresist which is recoated on the substrate after the step S11 is completed.
  • Embodiments of the present invention also provide a method of fabricating an array substrate, comprising the steps of: S1: forming a gate electrode, a gate line, a gate insulating layer, a semiconductor active layer, an ohmic contact layer, and a transparent conductive electrode on the substrate.
  • a transparent conductive electrode can be used as the pixel electrode.
  • This step may employ a two-tone mask (for example, a gray tone mask or a halftone mask) and specifically includes the following steps:
  • S101 depositing a transparent conductive film and a gate metal film sequentially on the substrate.
  • the transparent conductive film and the gate metal film are sequentially deposited on a substrate by magnetron sputtering.
  • the transparent conductive film may be formed of indium tin oxide (ITO), indium oxide (IZO) or alumina, and may have a thickness of 40 ⁇ -150 ⁇ .
  • the gate metal film may be formed of a single layer film of molybdenum (Mo), aluminum (A1), copper (Cu), tungsten (W) or the like or may be formed of a composite film of the above metal, and may have a thickness of 150 ⁇ ⁇ - 250 ⁇ ⁇ .
  • S102 coating a layer of photoresist on the substrate, then exposing and developing using a two-tone (for example, gray tone or halftone) mask, and the developed photoresist forms a completely reserved area, a semi-reserved area, and completely removed.
  • S103 etching a gate metal film and a transparent conductive film in the completely removed region by an etching process to form a gate electrode and a gate line.
  • an etching process For example, a wet etching process can be employed.
  • S104 Perform an ashing process to remove the photoresist in the semi-reserved region. At the same time, the fully retained area of the photoresist is also removed to a certain thickness, but the fully retained area of the photoresist still exists.
  • S105 etching the gate metal film of the semi-reserved region by an etching process. That is, the gate metal film of the region where the transparent conductive electrode is to be formed is etched away to expose the transparent conductive film to form a transparent conductive electrode. For example, a wet etching process can be employed.
  • S106 Stripping the photoresist in the completely reserved area.
  • a gate electrode 2 As shown in Fig. 3a, a gate electrode 2, a gate line (not shown), and a transparent conductive electrode 61 are formed on the substrate 1 by this patterning process. As shown in Fig. 3a, the gate electrode 2 has a two-layer structure formed of a transparent conductive film and a gate metal film, whereby the conductivity of the gate electrode 2 can be improved.
  • S107 sequentially depositing a gate insulating film, a semiconductor active layer film, and an ohmic contact film on the substrate.
  • a plasma-enhanced chemical vapor deposition (PECVD) method can be used to deposit a gate insulating film.
  • the gate insulating film may be formed of a single film of SiNx or SiOx or may be formed of a composite film thereof, and may have a thickness of 250 ⁇ -400 ⁇ .
  • a semiconductor active layer film is then deposited, which may have a thickness of 80 ⁇ -150 ⁇ .
  • S108 coating a layer of photoresist on the substrate, then exposing and developing using a two-tone mask, and developing the photoresist to form a completely reserved area, a semi-reserved area, and a completely removed area, wherein the completely reserved area is formed correspondingly
  • the area of the active layer of the TFT, the semi-reserved area corresponds to the area where the gate line is formed, and the rest is the completely removed area.
  • S109 etching the ohmic contact layer film, the semiconductor active layer film, and the gate insulating layer film of the completely removed region by an etching process to form a semiconductor active layer and an ohmic contact layer.
  • the etching gas for etching the thin film of the semiconductor active layer may be a mixed gas of SiH 4 and 3 ⁇ 4 or a mixed gas of SiH 2 Cl 2 and H 2 .
  • the etching gas for etching the ohmic contact layer film may be a mixed gas of SiH 4 , PH 3 and H 2 or a mixed gas of SiH 2 Cl 2 , PH 3 and 11 2 .
  • the etching gas for etching the gate insulating film may be a mixed gas of SiH 4 , NH 3 and N 2 or a mixed gas of SiH 2 Cl 2 , NH 3 and N 2 .
  • Step S110 Perform an ashing process to remove the photoresist in the semi-reserved region. Similar to the above step S104, while the photoresist of the semi-reserved region is removed, the photoresist of the completely remaining region is also removed by a certain thickness, but the photoresist of the completely remaining region still exists.
  • S111 etching the ohmic contact layer film and the semiconductor active layer film of the semi-reserved region by an etching process. That is, the ohmic contact layer film and the semiconductor active layer film of the region where the gate line is to be formed Etching off to form a gate insulating layer covering the gate lines. For example, a dry etching process can be employed. At this point, as shown in Figure 3b, the fully retained area of the photoresist still completely covers the fully reserved area.
  • the above step S1 can also form the gate electrode, the gate line, the gate insulating layer, the semiconductor active layer, the ohmic contact layer, and the transparent conductive electrode by a patterning process using a normal mask.
  • a transparent conductive electrode and a transparent conductive layer are formed by a first patterning process using a common mask
  • a gate electrode and a gate line are formed by a second patterning process using a normal mask
  • a third pattern is formed by using a common mask.
  • the process forms a gate insulating layer, and finally a semiconductor active layer and an ohmic contact layer are formed by a fourth patterning process using a common mask, and the remaining photoresist on the ohmic contact layer is retained for use in the subsequent step S2.
  • the gate electrode 2 is formed of a metal material, the gate electrode 2 is opaque, and the opaque gate electrode 2 is used as a mask, and the photoresist is exposed and developed from the back surface of the substrate 1, and remains after development.
  • the photoresist 8 corresponds to the position of the gate electrode 2.
  • a source/drain metal thin film 4 is deposited on the substrate 1.
  • the source/drain metal thin film 4 is deposited by magnetron sputtering or thermal evaporation.
  • the source/drain metal film 4 may be selected from the same material as the gate metal film and may have a thickness of 200 ⁇ -300 ⁇ .
  • FIG. 3d is only a schematic diagram.
  • the thickness of the photoresist 8 is on the order of micrometers, and the thickness of the source/drain metal film 4 is nanometer, that is, the thickness of the photoresist 8 is required. It is much larger than the thickness of the source/drain metal film 4. Therefore, while the photoresist 8 is stripped, the source/drain metal thin film 4 deposited on the photoresist 8 is also removed, and the gap between the source electrode and the drain electrode of the formed TFT corresponds to the position of the gate electrode 2 .
  • the ohmic contact layer 52 at the above-described voids is etched away by a dry etching process.
  • the etching time is increased as much as possible, and a small portion of the semiconductor active layer 51 is also etched away, but does not affect the TFT. Electrical performance. From step S107 to this point, the second patterning process using the two-tone mask ends. As shown in FIG.
  • the patterning process forms a gap between the gate insulating layer 3, the semiconductor active layer 51, the ohmic contact layer 52, and the source electrode and the drain electrode of the TFT, and The projection of this void on the substrate 1 coincides with the gate electrode 2.
  • S6 forming a source electrode, a drain electrode, a data line, and a passivation layer on the substrate.
  • this step can employ a two-tone mask and includes the following steps:
  • a passivation layer film 7 is deposited on the substrate 1.
  • the passivation film 7 can be deposited by PECVD.
  • the passivation layer film 7 may be formed of a single layer film of SiNx or SiOx or may be formed of a composite film thereof, and may have a thickness of 1,000 to 3,000.
  • S602 coating a layer of photoresist on the substrate, then exposing and developing using a two-tone mask, and developing the photoresist to form a completely reserved area, a semi-reserved area, and a completely removed area, wherein the completely reserved area is formed correspondingly
  • the area of the active layer of the TFT, the semi-reserved area corresponds to the area where the data line is to be formed, and the rest is the completely removed area.
  • the etching gas for etching the passivation layer film 7 may be a mixed gas of SiH 4 , NH 3 and N 2 or a mixed gas of SiH 2 Cl 2 , NH 3 and N 2 .
  • S604 etching the source-drain metal film of the completely removed region by an etching process.
  • a wet etching process can be employed.
  • the pixel electrode is also located within the completely removed region, so that after etching away the source/drain metal film of the completely removed region, the source/drain metal film on the surface of the pixel electrode is etched away to expose the pixel electrode.
  • S605 performing an ashing process to remove the photoresist in the semi-reserved region. Similar to the above steps S104 and S110, while the photoresist of the semi-reserved region is removed, the photoresist of the completely remaining region is also removed by a certain thickness, but the photoresist of the completely remaining region still exists.
  • S606 etching the passivation layer film of the semi-reserved region by an etching process.
  • etching process For example, a dry etching process can be employed.
  • the passivation layer film of the semi-retained region is etched away by the same process as the above step S603, and the source/drain metal film is exposed to form a data line.
  • step S607 peeling off the remaining photoresist in the completely remaining region to form an array substrate, as shown in FIG. 3g.
  • the third patterning process using the two-tone mask ends.
  • the patterning process forms a source electrode 41, a drain electrode 42, a data line (not shown), and a passivation layer 7.
  • step S6 can also form the source electrode, the drain electrode, the data line, and the passivation layer by using a common mask patterning process.
  • the photoresist is exposed and developed from the back surface of the substrate by using the opaque gate electrode as a mask, and the remaining photoresist and gate electrode after development The location corresponds. While the remaining photoresist is stripped, the source/drain metal film deposited on the photoresist is also removed, so that the gap between the source electrode and the drain electrode is formed to correspond to the position of the gate electrode, that is, the The projection of the void on the substrate coincides with the gate electrode, so that there is no overlap between the source electrode, the drain electrode and the gate electrode, so that both Cgs and Cgd can reach 0, thereby avoiding the problem of uneven chromaticity. , reducing the driving voltage of the TFT and shortening the time required for the charging process.
  • the embodiment of the present invention adopts a patterning process using a two-tone mask, which can complete the fabrication of the array substrate by only three patterning processes, improve the production efficiency of the array substrate, and reduce the production cost of the array substrate.
  • An embodiment of the present invention further provides a display device including the above array substrate provided by the embodiment of the present invention.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.

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Abstract

提供一种薄膜晶体管及其制造方法、阵列基板及其制造方法以及显示装置。该薄膜晶体管包括基板（1）以及设置于基板（1）上的栅电极（2）、源电极（41）和漏电极（42），其中该源电极（41）与该漏电极（42）之间的空隙在该基板（1）上的投影与该栅电极（2）在该基板（1）上的投影重合。

Description

薄膜晶体管及其制造方法、 阵列基板及其制造方法、 显示装置 技术领域
本发明的实施例涉及薄膜晶体管及其制造方法， 包括该薄膜晶体管的阵 列基板及其制造方法， 以及包括该阵列基板的显示装置。 背景技术
薄膜晶体管液晶显示器（Thin Film Transistor Liquid Crystal Display, 筒 称 TFT-LCD )具有体积小、 功耗低、 无辐射等优点， 已在当前的平板显示器 领域中占据了主导地位。
在 TFT-LCD中， 当在 TFT的栅极上施加高电平， 源极与漏极通过半导 体沟道导通， 来自数据线的数据信号经由 TFT施加到像素电极。 TFT的总电 容=。88+( 沟道 +Cgd, 其中 Cgs是栅极与源极交叠形成的电容， Cgd是栅极 与漏极交叠形成的电容。 期望 Cgs与 Cgd都可以达到 0, 以降低 TFT的总电 容。 但是， 目前源极、 漏极与栅极之间都存在一定的交叠部分， 因为如果源 极与漏极之间的空隙较大， 将会影响 TFT的导电性能。 此外， 在多个 TFT 当中， 源极、 漏极与栅极之间的相对位置不一致， 因此各 TFT中 Cgs和 Cgd 的值是不相等的， 导致各 TFT的总电容不相同。 在此情形下， 在数据信号相 等的条件下， 像素电极被充入的电压也不一致， 从而引起液晶显示器出现色 度不均的不良现象。 另外， 由于 Cgs和 Cgd的存在， 使得 TFT的驱动电压 也增大了， 从而增加了充电过程所需的时间。 发明内容
根据本发明的一个方面， 提供一种薄膜晶体管。 该薄膜晶体管包括基板 以及设置于基板上的栅电极、 源电极和漏电极， 所述源电极与所述漏电极之 间的空隙在所述基板上的投影与所述栅电极在基板上的投影重合。
例如， 所述薄膜晶体管为底栅型薄膜晶体管。
例如， 所述薄膜晶体管还包括覆盖所述栅电极的栅绝缘层以及设置于所 述栅绝缘层上的半导体有源层。 例如， 所述薄膜晶体管还包括设置于半导体有源层和源、 漏电极之间的 欧姆接触层。
根据本发明的另一个方面， 提供一种阵列基板。 该阵列基板包括上述的 薄膜晶体管。
例如，阵列基板还包括设置于所述基板上的透明导电层和透明导电电极， 所述透明导电层设置于所述薄膜晶体管的栅电极下方， 所述透明导电电极与 所述透明导电层同层设置。
例如， 所述透明导电电极用作像素电极并与所述薄膜晶体管的漏电极电 连接。
根据本发明的再一个方面， 提供一种薄膜晶体管的制造方法。 该方法包 括以下步骤：
在基板上形成栅电极、 栅绝缘层、 半导体有源层和欧姆接触层； 以所述栅电极作为掩模板， 从所述基板的背面对所述基板上的光刻胶进 行曝光并显影， 显影后剩余的光刻胶与所述栅电极的位置相对应；
在所述基板上沉积源漏极金属薄膜；
剥离所述剩余的光刻胶， 形成所述薄膜晶体管的源电极与漏电极之间的 空隙；
刻蚀掉所述空隙处的所述欧姆接触层；
刻蚀所述源漏极金属薄膜形成源电极和漏电极。
根据本发明的又一个方面， 提供一种阵列基板的制造方法。 该方法包括 以下步骤：
在基板上形成栅电极、 栅线、 栅绝缘层、 半导体有源层、 欧姆接触层和 透明导电电极；
以所述栅电极作为掩模板， 从所述基板的背面对所述基板上的光刻胶进 行曝光并显影， 显影后剩余的光刻胶与所述栅电极的位置相对应；
在所述基板上沉积源漏极金属薄膜；
剥离所述剩余的光刻胶,形成薄膜晶体管的源电极与漏电极之间的空隙； 刻蚀掉所述空隙处的所述欧姆接触层；
在所述基板上形成源电极、 漏电极、 数据线和钝化层。
例如， 所述在基板上形成栅电极、 栅线、 栅绝缘层、 半导体有源层、 欧 姆接触层和透明导电电极的步骤包括：
在基板上依次沉积透明导电薄膜和栅极金属薄膜；
在所述基板上涂覆一层光刻胶，然后利用双色调掩模板进行曝光并显影， 显影后的光刻胶形成完全保留区域、 半保留区域和完全去除区域， 其中完全 保留区域对应要形成栅电极和栅线的区域， 半保留区域对应要形成透明导电 电极的区域， 其余为完全去除区域；
通过刻蚀工艺刻蚀掉完全去除区域的栅极金属薄膜和透明导电薄膜； 进行灰化工艺， 去除半保留区域的光刻胶；
通过刻蚀工艺刻蚀掉半保留区域的栅极金属薄膜；
剥离完全保留区域的光刻胶；
在所述基板上依次沉积栅绝缘层薄膜、 半导体有源层薄膜和欧姆接触层 薄膜；
在所述基板上涂覆一层光刻胶，然后利用双色调掩模板进行曝光并显影， 显影后的光刻胶形成完全保留区域、 半保留区域和完全去除区域， 其中完全 保留区域对应要形成薄膜晶体管的有源层的区域， 半保留区域对应形成有栅 线的区域， 其余为完全去除区域；
通过刻蚀工艺刻蚀掉完全去除区域的欧姆接触层薄膜、 半导体有源层薄 膜和栅绝缘层薄膜；
进行灰化工艺， 去除半保留区域的光刻胶；
通过刻蚀工艺刻蚀掉半保留区域的欧姆接触层薄膜和半导体有源层薄 膜；
保留完全保留区域的剩余的光刻胶。
例如， 所述在所述基板上形成源电极、 漏电极、 数据线和钝化层的步骤 包括：
在所述基板上沉积钝化层薄膜；
在所述基板上涂覆一层光刻胶，然后利用双色调掩模板进行曝光并显影， 显影后的光刻胶形成完全保留区域、 半保留区域和完全去除区域， 其中完全 保留区域对应形成有薄膜晶体管的有源层的区域， 半保留区域对应要形成数 据线的区域， 其余为完全去除区域；
通过刻蚀工艺刻蚀掉完全去除区域的钝化层薄膜； 通过刻蚀工艺刻蚀掉完全去除区域的源漏极金属薄膜；
进行灰化工艺， 去除半保留区域的光刻胶；
通过刻蚀工艺刻蚀掉半保留区域的钝化层薄膜；
剥离完全保留区域的光刻胶。
根据本发明的又一个方面， 提供一种显示装置。 该显示装置包括上述阵 列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明的实施例所提供的薄膜晶体管的结构示意图；
图 2为本发明的实施例所提供的阵列基板的结构示意图； 以及
图 3a至图 3g为本发明的实施例所提供的阵列基板的制造方法的示意图。 具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合附图， 对本发明实施例的技术方案进行清楚、 完整地描述。 显然， 所描述的实施例 是本发明的一部分实施例， 而不是全部的实施例。 基于所描述的本发明的实 施例， 本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实 施例， 都属于本发明保护的范围。
本发明的实施例提供一种薄膜晶体管 （TFT ) 。 如图 1所示， 该薄膜晶 体管包括基板 1以及设置于基板 1上的栅电极 2、源电极 41和漏电极 42。源 电极 41与漏电极 42之间的空隙在基板 1上的投影与栅电极 2在基板 1上的 投影重合。 也就是说， 源电极 41和漏电极 42之间的空隙在基板 1上的投影 的面积与栅电极 2在基板 1上的投影的面积相等。
例如， 本发明实施例提供的薄膜晶体管为底栅型薄膜晶体管， 也就是栅 电极 2位于源电极 41和漏电极 42的下方。 进一步的， 该 TFT还包括覆盖栅 电极 2的栅绝缘层 3、 设置于栅绝缘层 3上的半导体有源层 51 , 以及设置于 半导体有源层 51与源电极 41、 漏电极 42之间的欧姆接触层 52。 本发明的实施例提供一种阵列基板。 该阵列基板包括如上所述的 TFT。 例如， 如图 2所示， 该阵列基板包括基板 1、栅电极 2、栅线（图中未示出）、 栅绝缘层 3、 半导体有源层 51、 欧姆接触层 52、 源电极 41、 漏电极 42、 数 据线（图中未示出） 。 例如， 该阵列基板进一步包括设置于基板 1上的透明 导电层 60和透明导电电极 61 , 透明导电层 60设置于栅电极 2下方， 透明导 电电极 61与透明导电层 60同层设置。
根据本发明实施例的阵列基板可以应用到扭曲向列型（ Twisted Nematic, TN )的液晶显示面板。 此时， 透明导电电极 61用作像素电极， 与 TFT的漏 电极 42电连接， 如图 2所示。
根据本发明实施例的阵列基板也可以应用到高级超维场转换型
( ADvanced super Dimension Switch, ADSDS ) 的液晶显示面板。 J¾I时， 透 明导电电极 61既可以用作像素电极，与漏电极电连接；也可以用作公共电极， 不与漏电极电连接。 在 ADSDS (筒称 ADS )型的液晶显示面板中， 通过同 一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的 电场形成多维电场， 使液晶盒内狭缝电极间、 电极正上方所有取向液晶分子 都能够产生旋转， 从而提高了液晶工作效率并增大了透光效率。 因此， ADS 型的液晶显示面板具有高画面品质、 高分辨率、 高透过率、低功耗、 宽视角、 高开口率、 低色差、 无挤压水波纹（push Mura )等优点。 针对不同应用， ADS技术的改进技术有高透过率的 I-ADS技术、 高开口率的 H-ADS和高分 辨率的 S-ADS技术等。
当然， 根据本发明实施例的阵列基板也可以应用到其他类型的液晶显示 面板， 如 VA型、 IPS型及 FFS型等。
此外， 根据本发明实施例的阵列基板还可以进一步包括设置在源极 41、 漏极 42及有源层 51上的钝化层 7。钝化层 7对 TFT起到保护作用，防止 TFT 受损， 同时还能够起到绝缘作用， 避免外界电信号对 TFT产生干扰。
本发明的实施例还提供了一种 TFT的制造方法， 包括以下步骤：
S11: 在基板上形成栅电极、 栅绝缘层、 半导体有源层和欧姆接触层。 S12: 以栅电极作为掩模板， 从基板的背面对基板上的光刻胶进行曝光 并显影， 显影后剩余的光刻胶与栅电极的位置相对应。
S13: 在基板上沉积源漏极金属薄膜。 S14: 剥离剩余的光刻胶， 形成薄膜晶体管的源电极与漏电极之间的空 隙。
S15: 对所述空隙处的欧姆接触层进行刻蚀。
S16: 刻蚀所述源漏极金属薄膜形成源电极和漏电极。
在步骤 S12中， 所述基板上的光刻胶可以是步骤 S11所采用的光刻胶的 剩余部分。 显然， 所述基板上的光刻胶也可以是完成步骤 S11后重新涂覆在 基板上的光刻胶。
本发明的实施例还提供了一种阵列基板的制造方法， 包括以下步骤： S1: 在基板上形成栅电极、 栅线、 栅绝缘层、 半导体有源层、 欧姆接触 层和透明导电电极。
例如， 透明导电电极可以用作像素电极。
该步骤可以采用双色调掩模板 (例如， 灰色调掩模板或半色调掩模板 ) 并具体包括以下步骤：
S 101： 在基板上依次沉积透明导电薄膜和栅极金属薄膜。
例如， 在基板上利用磁控溅射法来依次沉积所述透明导电薄膜和所述栅 极金属膜。 所述透明导电薄膜可以由氧化铟锡（ITO )、 氧化铟辞（IZO )或 氧化铝辞等形成，厚度可以为 40θΑ-150θΑ。所述栅极金属膜可以由钼（Mo )、 铝（A1 ) 、 铜（Cu ) 、 钨（W )等的单层膜形成或者可以由上述金属的复合 膜形成， 厚度可以为 150θΑ-250θΑ。
S102: 在基板上涂覆一层光刻胶， 然后利用双色调 （例如， 灰色调或半 色调）掩模板进行曝光并显影， 显影后的光刻胶形成完全保留区域、 半保留 区域和完全去除区域， 其中完全保留区域对应要形成栅电极和栅线的区域， 半保留区域对应要形成透明导电电极的区域， 其余为完全去除区域。
S103: 通过刻蚀工艺刻蚀掉完全去除区域的栅极金属薄膜和透明导电薄 膜， 形成栅电极和栅线。 例如， 可以采用湿法刻蚀工艺。
S104: 进行灰化工艺， 去除半保留区域的光刻胶。 同时， 完全保留区域 的光刻胶也被去除掉了一定的厚度， 但是完全保留区域的光刻胶仍然存在。
S105: 通过刻蚀工艺刻蚀掉半保留区域的栅极金属薄膜。 也就是， 将要 形成透明导电电极的区域的栅极金属薄膜刻蚀掉， 露出透明导电薄膜， 形成 透明导电电极。 例如， 可以采用湿法刻蚀工艺。 S106: 剥离完全保留区域的光刻胶。
至此， 采用双色调掩模板的第一次构图工艺结束。 如图 3a所示， 通过本 次构图工艺， 在基板 1上形成了栅电极 2、 栅线（图中未示出）和透明导电 电极 61。 如图 3a所示， 栅电极 2具有由透明导电薄膜和栅极金属薄膜形成 的双层结构， 由此可以提高栅电极 2的导电性。
S107: 在基板上依次沉积栅绝缘层薄膜、 半导体有源层薄膜和欧姆接触 层薄膜。
例如， 可以采用等离子体增强化学气相沉积（PECVD )法来沉积栅绝缘 层薄膜。 栅绝缘层薄膜可以由 SiNx或 SiOx的单层膜形成或者可以由它们的 复合膜形成， 厚度可以为 250θΑ-400θΑ。 然后再沉积半导体有源层薄膜， 其 厚度可以为 80θΑ-150θΑ。 最后沉积欧姆接触层薄膜， 其厚度可以为
50oA-ioooA,
S108: 在基板上涂覆一层光刻胶， 然后利用双色调掩模板进行曝光并显 影， 显影后的光刻胶形成完全保留区域、 半保留区域和完全去除区域， 其中 完全保留区域对应要形成 TFT的有源层的区域，半保留区域对应形成有栅线 的区域， 其余为完全去除区域。
S109: 通过刻蚀工艺刻蚀掉完全去除区域的欧姆接触层薄膜、 半导体有 源层薄膜和栅绝缘层薄膜， 形成半导体有源层和欧姆接触层。
例如， 可以采用干法刻蚀工艺。 用于刻蚀半导体有源层薄膜的刻蚀气体 可以是 SiH4和 ¾的混合气体或者 SiH2Cl2和 H2的混合气体。 用于刻蚀欧姆 接触层薄膜的刻蚀气体可以是 SiH4、 PH3和 H2的混合气体或者 SiH2Cl2、 PH3 和 112的混合气体。 用于刻蚀栅绝缘层薄膜的刻蚀气体可以是 SiH4、 NH3和 N2的混合气体或 SiH2Cl2、 NH3和 N2的混合气体。 这样， 就可以仅保留要形 成 TFT的有源层的区域中及形成有栅线的区域中的欧姆接触层 52、 半导体 有源层 51和栅绝缘层 3, 如图 3b所示。
S110: 进行灰化工艺， 去除半保留区域的光刻胶。 与上述步骤 S104相 似， 去除半保留区域的光刻胶的同时， 完全保留区域的光刻胶也被去除掉了 一定的厚度， 但是完全保留区域的光刻胶仍然存在。
S111: 通过刻蚀工艺刻蚀掉半保留区域的欧姆接触层薄膜和半导体有源 层薄膜。 也就是将形成有栅线的区域的欧姆接触层薄膜和半导体有源层薄膜 刻蚀掉， 形成覆盖栅线的栅绝缘层。 例如， 可以采用干法刻蚀工艺。 此时， 如图 3b所示， 完全保留区域的光刻胶仍然完全覆盖完全保留区域。
应当说明的是， 上述步骤 S1 也可以通过采用普通掩模板的构图工艺来 形成栅电极、栅线、 栅绝缘层、 半导体有源层、 欧姆接触层和透明导电电极。 例如， 通过采用普通掩模板的第一次构图工艺形成透明导电电极和透明导电 层， 通过采用普通掩模板的第二次构图工艺形成栅电极和栅线， 通过采用普 通掩模板的第三次构图工艺形成栅绝缘层， 最后通过采用普通掩模板的第四 次构图工艺形成半导体有源层和欧姆接触层， 并保留欧姆接触层上剩余的光 刻胶， 以便于之后的步骤 S2中使用。
S2: 如图 3c所示， 以栅电极 2作为掩模板， 从基板 1的背面对基板 1 上的光刻胶进行曝光并显影， 显影后剩余的光刻胶 8与栅电极 2的位置相对 应。
因为栅电极 2是由金属材料形成， 所以栅电极 2是不透光的， 以不透光 的栅电极 2作为掩模板， 从基板 1的背面对光刻胶进行曝光并显影， 则显影 后剩余的光刻胶 8与栅电极 2的位置相对应。
S3: 如图 3d所示， 在基板 1上沉积源漏极金属薄膜 4。
例如， 利用磁控溅射法或者热蒸镀法沉积源漏极金属薄膜 4。 源漏极金 属薄膜 4所选用的材料可以与栅极金属薄膜相同，厚度可以为 200θΑ-300θΑ。
S4: 剥离欧姆接触层上剩余的光刻胶， 形成 TFT的源电极与漏电极之间 的空隙。
例如， 采用常规的光刻胶剥离方法即可。应当说明的是， 图 3d仅是示意 图， 实际的制造过程中， 光刻胶 8的厚度是微米级的， 而源漏极金属薄膜 4 的厚度是纳米级的，即光刻胶 8的厚度要远远大于源漏极金属薄膜 4的厚度。 因此剥离光刻胶 8的同时， 沉积在光刻胶 8上的源漏极金属薄膜 4也会被去 除， 所形成的 TFT的源电极与漏电极之间的空隙恰好对应于栅极 2的位置。
S5: 刻蚀掉所述空隙处的欧姆接触层， 如图 3e所示。
例如， 通过干法刻蚀工艺刻蚀掉上述空隙处的欧姆接触层 52。 在实际的 刻蚀过程中，为了保证欧姆接触层 52能够完全刻被蚀掉，会尽量增加刻蚀的 时间， 而使半导体有源层 51也有一小部分被刻蚀掉， 但是并不影响 TFT的 电性能。 从步骤 S107至此， 采用双色调掩模板的第二次构图工艺结束。 如图 3e 所示， 在第一次构图工艺的基础上本次构图工艺形成了栅绝缘层 3、 半导体 有源层 51、 欧姆接触层 52以及 TFT的源电极与漏电极之间的空隙， 并且该 空隙在基板 1上的投影恰好与栅电极 2重合。
S6: 在基板上形成源电极、 漏电极、 数据线和钝化层。
例如， 该步骤可以采用双色调掩模板并包括以下步骤：
S601 : 如图 3f所示， 在基板 1上沉积钝化层薄膜 7，。
例如， 可以采用 PECVD法来沉积钝化层薄膜 7，。 钝化层薄膜 7，可以由 SiNx 或 SiOx 的单层膜形成或者可以由它们的复合膜形成， 厚度可以为 1000人 -3000人。
S602: 在基板上涂覆一层光刻胶， 然后利用双色调掩模板进行曝光并显 影， 显影后的光刻胶形成完全保留区域、 半保留区域和完全去除区域， 其中 完全保留区域对应形成有 TFT的有源层的区域，半保留区域对应要形成数据 线的区域， 其余为完全去除区域。
S603: 通过刻蚀工艺刻蚀掉完全去除区域的钝化层薄膜 7，。
例如， 可以采用干法刻蚀工艺。 用于刻蚀钝化层薄膜 7，的刻蚀气体可以 为 SiH4、 NH3和 N2的混合气体或 SiH2Cl2、 NH3和 N2的混合气体。
S604: 通过刻蚀工艺刻蚀掉完全去除区域的源漏极金属薄膜。 例如， 可 以采用湿法刻蚀工艺。
像素电极也位于该完全去除区域之内， 所以刻蚀掉完全去除区域的源漏 极金属薄膜之后， 也就刻蚀掉了像素电极表面的源漏极金属薄膜从而露出像 素电极。
S605:进行灰化工艺，去除半保留区域的光刻胶。与上述步骤 S104、 S110 相似， 去除半保留区域的光刻胶的同时， 完全保留区域的光刻胶也被去除掉 了一定的厚度， 但是完全保留区域的光刻胶仍然存在。
S606: 通过刻蚀工艺刻蚀掉半保留区域的钝化层薄膜。 例如， 可以采用 干法刻蚀工艺。
利用与上述步骤 S603相同的工艺， 刻蚀掉半保留区域的钝化层薄膜， 露出源漏极金属薄膜， 形成数据线。
S607: 剥离完全保留区域剩余的光刻胶， 形成阵列基板， 如图 3g所示。 从步骤 S601 至此， 采用双色调掩模板的第三次构图工艺结束。 在前两 次构图工艺的基础上本次构图工艺形成了源电极 41、 漏电极 42、数据线（图 中未示出） ， 以及钝化层 7。
当然， 步骤 S6也可以通过采用普通掩模板构图工艺来形成源电极、 漏 电极、 数据线和钝化层。
在本发明实施例提供的阵列基板及其制造方法中， 以不透光的栅电极作 为掩模板， 从基板的背面对光刻胶进行曝光并显影， 显影后剩余的光刻胶与 栅电极的位置相对应。 剥离该剩余的光刻胶的同时， 沉积在光刻胶上的源漏 极金属薄膜也会被去除， 因此所形成的源电极与漏电极之间的空隙恰好对应 于栅电极的位置， 即该空隙在基板上的投影恰好与栅电极重合， 由此源电极、 漏电极与栅电极之间恰好不存在交叠部分， 使得 Cgs与 Cgd都可以达到 0, 从而避免了色度不均的不良现象， 降低了 TFT的驱动电压， 缩短了充电过程 所需的时间。
此外， 本发明实施例采用利用双色调掩模板的构图工艺， 只需要进行 3 次构图工艺即可完成阵列基板的制造， 提高了阵列基板的生产效率， 降低了 阵列基板的生产成本。
本发明的实施例还提供一种显示装置， 其包括本发明实施例所提供的上 述阵列基板。 该显示装置可以是液晶面板、 电子纸、 OLED面板、 液晶电视、 液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种薄膜晶体管， 包括基板以及设置于基板上的栅电极、 源电极和漏 电极， 其中所述源电极与所述漏电极之间的空隙在所述基板上的投影与所述 栅电极在所述基板上的投影重合。
2、根据权利要求 1所述的薄膜晶体管，其中所述薄膜晶体管为底栅型薄 膜晶体管。
3、根据权利要求 2所述的薄膜晶体管，其中所述薄膜晶体管还包括覆盖 所述栅电极的栅绝缘层以及设置于所述栅绝缘层上的半导体有源层。
4、根据权利要求 3所述的薄膜晶体管，其中所述薄膜晶体管还包括设置 于半导体有源层和源、 漏电极之间的欧姆接触层。
5、 一种阵列基板， 包括权利要求 1~4任一项所述的薄膜晶体管。
6、根据权利要求 5所述的阵列基板，其中还包括设置于所述基板上的透 明导电层和透明导电电极， 所述透明导电层设置于所述薄膜晶体管的栅电极 下方， 所述透明导电电极与所述透明导电层同层设置。
7、根据权利要求 6所述的阵列基板，其中所述透明导电电极用作像素电 极， 并与所述薄膜晶体管的漏电极电连接。
8、 一种薄膜晶体管的制造方法， 包括：
在基板上形成栅电极、 栅绝缘层、 半导体有源层和欧姆接触层； 以所述栅电极作为掩模板， 从所述基板的背面对所述基板上的光刻胶进 行曝光并显影， 显影后剩余的光刻胶与所述栅电极的位置相对应；
在所述基板上沉积源漏极金属薄膜；
剥离所述剩余的光刻胶， 形成所述薄膜晶体管的源电极与漏电极之间的 空隙；
刻蚀掉所述空隙处的所述欧姆接触层；
刻蚀所述源漏极金属薄膜形成源电极和漏电极。
9、 一种阵列基板的制造方法， 包括：
在基板上形成栅电极、 栅线、 栅绝缘层、 半导体有源层、 欧姆接触层和 透明导电电极；
以所述栅电极作为掩模板， 从所述基板的背面对所述基板上的光刻胶进 行曝光并显影， 显影后剩余的光刻胶与所述栅电极的位置相对应；
在所述基板上沉积源漏极金属薄膜；
剥离所述剩余的光刻胶,形成薄膜晶体管的源电极与漏电极之间的空隙； 刻蚀掉所述空隙处的所述欧姆接触层；
在所述基板上形成源电极、 漏电极、 数据线和钝化层。
10、 根据权利要求 9所述的阵列基板， 其中所述在基板上形成栅电极、 栅线、 栅绝缘层、 半导体有源层、 欧姆接触层和透明导电电极的步骤包括： 在基板上依次沉积透明导电薄膜和栅极金属薄膜；
在所述基板上涂覆一层光刻胶，然后利用双色调掩模板进行曝光并显影， 显影后的光刻胶形成完全保留区域、 半保留区域和完全去除区域， 其中完全 保留区域对应要形成栅电极和栅线的区域， 半保留区域对应要形成透明导电 电极的区域， 其余为完全去除区域；
通过刻蚀工艺刻蚀掉完全去除区域的栅极金属薄膜和透明导电薄膜； 进行灰化工艺， 去除半保留区域的光刻胶；
通过刻蚀工艺刻蚀掉半保留区域的栅极金属薄膜；
剥离完全保留区域的光刻胶；
在所述基板上依次沉积栅绝缘层薄膜、 半导体有源层薄膜和欧姆接触层 薄膜；
在所述基板上涂覆一层光刻胶，然后利用双色调掩模板进行曝光并显影， 显影后的光刻胶形成完全保留区域、 半保留区域和完全去除区域， 其中完全 保留区域对应要形成薄膜晶体管的有源层的区域， 半保留区域对应形成有栅 线的区域， 其余为完全去除区域；
通过刻蚀工艺刻蚀掉完全去除区域的欧姆接触层薄膜、 半导体有源层薄 膜和栅绝缘层薄膜；
进行灰化工艺， 去除半保留区域的光刻胶；
通过刻蚀工艺刻蚀掉半保留区域的欧姆接触层薄膜和半导体有源层薄 膜；
保留完全保留区域的剩余的光刻胶。
11、 根据权利要求 9所述的阵列基板， 其中所述在所述基板上形成源电 极、 漏电极、 数据线和钝化层的步骤包括： 在所述基板上沉积钝化层薄膜；
在所述基板上涂覆一层光刻胶，然后利用双色调掩模板进行曝光并显影， 显影后的光刻胶形成完全保留区域、 半保留区域和完全去除区域， 其中完全 保留区域对应形成有薄膜晶体管的有源层的区域， 半保留区域对应要形成数 据线的区域， 其余为完全去除区域；
通过刻蚀工艺刻蚀掉完全去除区域的钝化层薄膜；
通过刻蚀工艺刻蚀掉完全去除区域的源漏极金属薄膜；
进行灰化工艺， 去除半保留区域的光刻胶；
通过刻蚀工艺刻蚀掉半保留区域的钝化层薄膜；
剥离完全保留区域的光刻胶。
12、 一种显示装置， 包括权利要求 5~7任一项所述的阵列基板。
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CN103441129A (zh) * 2013-08-23 2013-12-11 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置
US9735177B2 (en) 2013-08-23 2017-08-15 Boe Technology Group Co., Ltd. Array substrate, method for manufacturing the same and display device
CN104051472A (zh) * 2014-06-19 2014-09-17 京东方科技集团股份有限公司 一种显示装置、阵列基板及其制作方法
CN104319278A (zh) * 2014-10-22 2015-01-28 京东方科技集团股份有限公司 阵列基板、显示面板和阵列基板的制作方法
TWI581317B (zh) * 2014-11-14 2017-05-01 群創光電股份有限公司 薄膜電晶體基板及具備該薄膜電晶體基板之顯示面板
CN104465512B (zh) * 2015-01-06 2018-07-17 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
US9443957B1 (en) 2015-03-12 2016-09-13 International Business Machines Corporation Self-aligned source and drain regions for semiconductor devices
CN105047723B (zh) * 2015-09-18 2017-12-19 京东方科技集团股份有限公司 一种薄膜晶体管、其制作方法、阵列基板及显示装置
CN109065551B (zh) * 2018-07-30 2020-01-14 深圳市华星光电技术有限公司 Tft阵列基板的制造方法及tft阵列基板
CN109860057B (zh) * 2019-03-25 2021-12-14 合肥鑫晟光电科技有限公司 薄膜晶体管、阵列基板及其制作方法、显示装置
CN110223989A (zh) * 2019-05-28 2019-09-10 深圳市华星光电半导体显示技术有限公司 薄膜晶体管基板及其制作方法
CN113053741A (zh) * 2021-03-08 2021-06-29 北海惠科光电技术有限公司 金属电极的制备方法、金属电极及显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1912725A (zh) * 2006-08-28 2007-02-14 友达光电股份有限公司 薄膜晶体管及包含此薄膜晶体管的显示器
CN102122620A (zh) * 2011-01-18 2011-07-13 北京大学深圳研究生院 一种自对准薄膜晶体管的制作方法
CN102543863A (zh) * 2012-02-06 2012-07-04 深圳市华星光电技术有限公司 一种薄膜晶体管阵列基板及其制作方法
CN102854677A (zh) * 2012-09-10 2013-01-02 京东方科技集团股份有限公司 阵列基板、阵列基板的制造方法及显示装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101661908B (zh) * 2008-08-27 2011-06-29 北京京东方光电科技有限公司 水平电场型半透过式液晶显示装置的阵列基板制造方法
CN101718950B (zh) * 2008-10-09 2011-12-28 北京京东方光电科技有限公司 薄膜构图方法及制造液晶显示装置的方法
CN101840922B (zh) * 2009-03-16 2012-05-30 北京京东方光电科技有限公司 阵列基板及制造方法
KR101218090B1 (ko) * 2009-05-27 2013-01-18 엘지디스플레이 주식회사 산화물 박막 트랜지스터 및 그 제조방법
CN101957526B (zh) * 2009-07-13 2013-04-17 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN101995709B (zh) * 2009-08-27 2012-10-03 北京京东方光电科技有限公司 Ffs型tft-lcd阵列基板及其制造方法
CN102237305B (zh) * 2010-05-06 2013-10-16 北京京东方光电科技有限公司 阵列基板及其制造方法和液晶显示器
CN102270604B (zh) * 2010-06-03 2013-11-20 北京京东方光电科技有限公司 阵列基板的结构及其制造方法
CN102135691B (zh) * 2010-09-17 2012-05-23 京东方科技集团股份有限公司 阵列基板及其制造方法和液晶显示器
JP5404963B2 (ja) * 2011-03-01 2014-02-05 シャープ株式会社 薄膜トランジスタおよび表示装置
US8563341B2 (en) 2012-02-06 2013-10-22 Shenzhen China Star Optoelectronics Technology Co., Ltd. Thin film transistor array substrate and manufacturing method for the same
CN102854667B (zh) * 2012-09-20 2017-05-17 京东方科技集团股份有限公司 一种液晶装置及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1912725A (zh) * 2006-08-28 2007-02-14 友达光电股份有限公司 薄膜晶体管及包含此薄膜晶体管的显示器
CN102122620A (zh) * 2011-01-18 2011-07-13 北京大学深圳研究生院 一种自对准薄膜晶体管的制作方法
CN102543863A (zh) * 2012-02-06 2012-07-04 深圳市华星光电技术有限公司 一种薄膜晶体管阵列基板及其制作方法
CN102854677A (zh) * 2012-09-10 2013-01-02 京东方科技集团股份有限公司 阵列基板、阵列基板的制造方法及显示装置

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