WO2013086909A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2013086909A1
WO2013086909A1 PCT/CN2012/083985 CN2012083985W WO2013086909A1 WO 2013086909 A1 WO2013086909 A1 WO 2013086909A1 CN 2012083985 W CN2012083985 W CN 2012083985W WO 2013086909 A1 WO2013086909 A1 WO 2013086909A1
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WIPO (PCT)
Prior art keywords
electrode
array substrate
pixel electrode
layer
forming
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PCT/CN2012/083985
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English (en)
French (fr)
Inventor
张锋
戴天明
姚琪
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京东方科技集团股份有限公司
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Priority to US13/806,190 priority Critical patent/US20130153911A1/en
Publication of WO2013086909A1 publication Critical patent/WO2013086909A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of manufacturing the same, and a display device. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • ITO indium tin oxide
  • TFT-LCD indium tin oxide
  • ITO is expensive, and ITO is prone to ion diffusion in the presence of acids and bases, which is harmful to the environment and human health, and the performance of the device is degraded when ions diffuse into the device.
  • the ITO material is brittle and is easily damaged when it is deformed. It is difficult to apply it to the flexible display field. Summary of the invention
  • a method of fabricating an array substrate comprising: a step of forming a pixel electrode and a step of forming a common electrode, wherein at least one of the pixel electrode and the common electrode is made of graphene.
  • an array substrate comprising a pixel electrode and a common electrode, wherein at least one of the pixel electrode and the common electrode is made of graphene.
  • a display device including a pixel electrode and a common electrode, wherein at least one of the pixel electrode and the common electrode is made of graphene.
  • FIG. 1 is a schematic plan view of an array substrate after a first patterning process according to an embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional view of an array substrate after a first patterning process according to an embodiment of the present invention
  • 3 is a schematic plan view of an array substrate after a second patterning process according to an embodiment of the present invention
  • FIG. 4 is a schematic cross-sectional view of the array substrate after a second patterning process according to an embodiment of the present invention
  • FIG. 6 is a schematic cross-sectional view of the array substrate after the third patterning process according to the first embodiment of the present invention
  • FIG. 7 is an array of the fourth patterning process according to the embodiment of the present invention
  • FIG. 8 is a schematic plan view of an array substrate after a fifth patterning process according to an embodiment of the present invention
  • FIG. 9 is a schematic cross-sectional view of the array substrate after a fifth patterning process according to an embodiment of the present invention
  • FIG. 11 is a schematic cross-sectional view of the array substrate after the first patterning process according to the second embodiment of the present invention
  • FIG. 12 is a second embodiment of the second embodiment of the present invention
  • FIG. 13 is a schematic plan view of the array substrate after the second patterning process according to Embodiment 2 of the present invention
  • FIG. FIG. 14 is a schematic plan view of the array substrate after the third patterning process according to the second embodiment of the present invention
  • Embodiment 15 is a schematic cross-sectional view of the array substrate after the third patterning process according to the second embodiment of the present invention.
  • Embodiment 2 is a schematic plan view of the array substrate after the fourth patterning process;
  • FIG. 17 is a schematic cross-sectional view of the array substrate after the fourth patterning process according to the second embodiment of the present invention.
  • Embodiments of the present invention are directed to the prior art that ITO is used as a pixel electrode and the common electrode is expensive, and ion diffusion is liable to occur, thereby causing a problem of deterioration in device performance.
  • Embodiments of the present invention provide an array substrate, a method of manufacturing the same, and a display device, which can reduce the manufacturing cost of the array substrate and improve the performance of the array substrate.
  • Embodiments of the present invention provide a method of fabricating an array substrate, wherein the fabrication method uses graphene to form a pixel electrode and/or a common electrode of an array substrate.
  • the manufacturing method can simultaneously form the source electrode, the drain electrode, and the pixel electrode of the array substrate by using one patterning process.
  • An embodiment of the present invention further provides an array substrate manufactured by the above method, the array substrate package A pixel electrode and a common electrode are included, wherein at least one of the pixel electrode and the common electrode is made of graphene.
  • the array substrate further includes a source electrode and a drain electrode, wherein the source electrode, the drain electrode and the pixel electrode are in the same layer, and the source electrode, the drain electrode and the pixel electrode are both Made of graphene.
  • the embodiment of the invention further provides a display device comprising the above array substrate.
  • Graphene is a new carbonaceous material in which a single layer of carbon atoms is closely packed into a two-dimensional honeycomb structure.
  • Graphene intrinsic electron mobility at room temperature up to 200000cm 2 / Vs is 140 times the Si (1400 cm 2 / Vs) of, GaAs (8500 cm 2 / Vs ) 20 times, GaN (2000 cm 2 / Vs ) of 100 times.
  • the resistance of graphene at room temperature is only 2/3 of that of copper (Cu).
  • Graphene can also withstand a current density of 100 million to 200 million A/cm 2 , which is about 100 times that of Cu.
  • graphene also has excellent light transmittance, electrical conductivity, thermal conductivity and chemical stability.
  • the source electrode, the drain electrode, the pixel electrode, and/or the common electrode of the array substrate are fabricated using graphene, which can reduce the manufacturing cost of the array substrate and improve the performance of the array substrate. Further, the present invention can simultaneously form the source electrode, the drain electrode and the pixel electrode of the array substrate by one patterning process, thereby reducing the number of process steps and thereby increasing the productivity.
  • This embodiment describes an array substrate of a liquid crystal display of an Advanced Super Dimension Switch (ADSDS) technology as an example.
  • ADSDS Advanced Super Dimension Switch
  • the ADSDS technology forms a multi-dimensional electric field by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that all the aligned liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the electrode can be Rotation is generated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field switching technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, push mura, etc. advantage.
  • the array substrate manufacturing method according to the embodiment of the present invention is not limited to the array substrate of the ADSDS technology, and can be applied to an array substrate of an array substrate of another mode liquid crystal display or an organic light emitting display or the like.
  • FIG. 1-9 are schematic flow charts of a method of manufacturing an array substrate of the embodiment.
  • the manufacturing method of the array substrate of this embodiment includes the following steps: Step 1: a first patterning process, forming a gate line made of a metal layer on a transparent substrate; depositing a metal layer on the transparent substrate 100, as shown in FIGS. 1 and 2, forming a gate line 11 by a patterning process .
  • the patterning process may include, for example, steps of coating, exposure, development, etching, and lift-off.
  • 1 is a schematic plan view
  • FIG. 2 is a schematic cross-sectional view taken along line AA' of the structure shown in FIG. 1.
  • the metal layer may be selected from any one selected from the group consisting of Nd, Cr, W, Ti, Ta, Mo, Al, and Cu, or an alloy of at least two of them;
  • Step 2 a second patterning process of forming a gate insulating layer and an active layer made of a semiconductor layer on the transparent substrate subjected to the first patterning process;
  • the gate insulating layer 12 and the semiconductor layer are successively deposited on the transparent substrate on which the step 1 is completed, and then the active layer 13 made of the semiconductor layer is formed by a patterning process.
  • 3 is a plan view
  • FIG. 4 is a cross-sectional view of the structure shown in FIG.
  • the gate insulating layer may be made of SiN x , SiO 2 or a resin
  • the semiconductor layer may be a-Si amorphous silicon, n+ a-Si amorphous silicon film, low temperature polysilicon or IGZO;
  • Step 3 a third patterning process, forming a source electrode, a drain electrode, and a pixel electrode made of a first graphene layer on a transparent substrate subjected to a second patterning process;
  • a graphene film that is, a first graphene layer, is deposited on the transparent substrate on which the step 2 is completed.
  • the source electrode 14, the drain electrode 15, and the pixel electrode 16 are formed by a patterning process.
  • Fig. 5 is a plan view schematically
  • Fig. 6 is a schematic cross-sectional view taken along line A-A' of the structure shown in Fig. 5.
  • the materials of the source electrode, the drain electrode, and the pixel electrode are all graphene films;
  • the data lines on the array substrate and the source electrode 14 can be integrally formed. Therefore, the data lines can also be made of graphene. Of course, in the actual production process, the data line and the source electrode can be made of different materials as needed.
  • Step 4 The fourth patterning process forms a passivation layer on the transparent substrate through the third patterning process, and the passivation layer has a passivation layer via hole for the peripheral circuit;
  • a passivation material layer is deposited on the transparent substrate on which step 3 is completed, and as shown in FIG. 7, a passivation layer 17 is formed by a patterning process.
  • the passivation layer 17 has a passivation layer via hole for the peripheral circuit.
  • the passivation layer may be made of SiN x , SiO 2 or a resin;
  • Step 5 The fifth patterning process is to form a common electrode made of the second graphene layer on the transparent substrate subjected to the fourth patterning process.
  • FIGS. 8 and 9 are schematic plan views of a layer of graphene film on the transparent substrate of step 4, that is, a second graphene layer, such as As shown in FIGS. 8 and 9, the common electrode layer 18 is formed by a patterning process.
  • Figure 8 is a schematic plan view
  • FIG. 9 is a cross-sectional view of the structure A-A of the structure shown in FIG.
  • the source electrode, the drain electrode, and the pixel electrode are formed by patterning the same material layer, they are disposed in the same layer.
  • the pixel electrode layer and the common electrode layer are preferably made of graphene.
  • the implementation of the present invention is not limited thereto, for example, one of the pixel electrode layer and the common electrode layer.
  • the structure is made of graphene, and the other layer is made of conventional ITO or indium oxide IZO.
  • the source electrode, the drain electrode, the pixel electrode, and the common electrode of the array substrate are made of graphene, which can reduce the manufacturing cost of the array substrate and improve the performance of the array substrate.
  • the source electrode, the drain electrode and the pixel electrode of the array substrate are simultaneously formed by one patterning process, which can reduce the number of process steps and thereby increase the productivity.
  • Figure 10-17 shows a schematic diagram of a method for fabricating an array substrate according to an embodiment of the present invention. As shown in Figure 10-17, the method for manufacturing the array substrate of the present embodiment includes the following steps:
  • Step 1 a first patterning process of forming a common electrode made of a first graphene layer on a transparent substrate;
  • a graphene film that is, a first graphene layer, is deposited on the transparent substrate 200, as shown in FIG. 10 and
  • the common electrode 21 is formed by a patterning process.
  • Figure 10 is a plan view
  • Figure 11 is a cross-sectional view of the structure of Figure 10 taken along line A-A.
  • the patterning process may include, for example, steps of coating, exposure, development, etching, and lift-off;
  • Step 2 a second patterning process, forming a gate line and a common electrode line made of a metal layer on the transparent substrate subjected to the first patterning process;
  • a metal layer is deposited on the transparent substrate on which the step 1 is completed, and as shown in Figs. 12 and 13, the gate line 22 and the common electrode line 23 are formed by a patterning process.
  • Figure 12 is a plan view
  • Figure 13 is a cross-sectional view of the structure of Figure 12 taken along line A-A.
  • the metal layer may be selected from any one selected from the group consisting of Nd, Cr, W, Ti, Ta, Mo, Al, and Cu or an alloy of these metals;
  • Step 3 The third patterning process forms a gate on the transparent substrate through the second patterning process An insulating layer, an active layer made of a semiconductor layer, and an etch stop layer made of an insulating layer;
  • the gate insulating layer 24, the semiconductor layer and the passivation layer are successively deposited on the transparent substrate on which the step 2 is completed. As shown in FIGS. 14 and 15, the active layer 25 and the etch stop are sequentially formed on the gate line 22 by a patterning process.
  • Figure 14 is a plan view
  • Figure 15 is a cross-sectional view of the structure of Figure 14 taken along line AA.
  • the gate insulating layer and the passivation layer may be made of SiN x , SiO 2 or a resin, and the etch barrier layer 26 functions as a protection channel to prevent damage and contamination of the channel in subsequent etching and other processes.
  • the semiconductor layer may be an a-Si amorphous silicon film, an n+ a-Si amorphous silicon film, a low temperature polysilicon or an IGZO;
  • Step 4 A fourth patterning process is performed to form a source electrode, a drain electrode, and a pixel electrode made of a second graphene layer on a transparent substrate subjected to a third patterning process.
  • a graphene film i.e., a second graphene layer, is deposited on the transparent substrate on which step 3 is completed.
  • the source electrode 27, the drain electrode 28, and the pixel electrode 29 are formed by a patterning process.
  • Figure 16 is a plan view
  • Figure 17 is a cross-sectional view of the structure of Figure 16 taken along line A-A.
  • the materials of the source electrode, the drain electrode, and the pixel electrode are all graphene films.
  • the data lines on the array substrate and the source electrode 27 can be integrally formed. Therefore, the data lines can also be made of graphene. Of course, in the actual production process, the data line and the source electrode can be made of different materials as needed.
  • the array substrate shown in Fig. 17 is formed through the above steps 1-4.
  • the source electrode, the drain electrode, and the pixel electrode are formed by patterning the same material layer, they are disposed in the same layer.
  • the pixel electrode layer and the common electrode layer are preferably made of graphene.
  • the implementation of the present invention is not limited thereto, for example, one of the pixel electrode layer and the common electrode layer.
  • the structure is made of graphene, and the other layer is made of conventional ITO or indium oxide IZO.
  • the source electrode, the drain electrode, the pixel electrode, and the common electrode of the array substrate are made of graphene, which can reduce the manufacturing cost of the array substrate and improve the performance of the array substrate.
  • the source electrode, the drain electrode and the pixel electrode of the array substrate are simultaneously formed by one patterning process, which can reduce the number of process steps and thereby increase the productivity.
  • the array substrate and the manufacturing method thereof according to the present invention can also be applied to other modes of the array substrate, such as in-plane. Switch (IPS) mode array substrate.
  • the array substrate according to the embodiment of the present invention does not necessarily include a common electrode.
  • the array substrate according to the embodiment of the present invention may be an array substrate in a liquid crystal display of a vertical electric field mode. In this case, the common electrode may not be formed in the array. On the substrate.
  • a display device including a pixel electrode and a common electrode, wherein at least one of the pixel electrode and the common electrode is made of graphene.
  • the display device may include any of the array substrates described above, and the pixel electrode and the common electrode are both formed on the array substrate; or, only the pixel electrode is formed on the array substrate, and the common electrode is formed on the display device. On the substrate (for example, the opposite substrate).
  • the array substrate according to the above embodiment can be applied to the display device according to the embodiment of the present invention. Therefore, the display device according to the embodiment of the present invention also has the above-described structural features and corresponding technical effects, and details are not described herein again.
  • the display device may be a liquid crystal display device such as a liquid crystal panel, a liquid crystal television, a mobile phone, a liquid crystal display or the like, which includes a color filter substrate, and the array substrate in the above embodiment.
  • the display device may be other types of display devices such as an e-reader or the like, which does not include a color filter substrate, but includes the array substrate in the above embodiment.
  • the display device according to the present invention may also be an organic light emitting display.
  • a method of manufacturing an array substrate comprising: a step of forming a pixel electrode and a step of forming a common electrode, wherein at least one of the pixel electrode and the common electrode is made of graphene.
  • the method further includes: before the step of forming the pixel electrode, the method further includes:
  • a gate insulating layer and an active layer made of a semiconductor layer are formed on the substrate on which the gate line is formed.
  • a passivation layer is formed on the substrate on which the pixel electrode is formed, and the passivation layer has a passivation layer via hole for the peripheral circuit.
  • the method further comprises:
  • a gate insulating layer, an active layer made of a semiconductor layer, and an etch stop layer made of an insulating layer are formed on the substrate on which the gate line and the common electrode line are formed.
  • the graphene layer is patterned to form the source electrode, the drain electrode, and the pixel electrode.
  • the graphene layer is patterned to form the common electrode.
  • an array substrate comprising a pixel electrode and a common electrode, wherein the pixel electrode and At least one of the common electrodes is made of graphene.
  • a display device comprising a pixel electrode and a common electrode, wherein at least one of the pixel electrode and the common electrode is made of graphene.
  • the display device according to (15) or (16), further comprising a source electrode and a drain electrode, wherein the source electrode, the drain electrode and the pixel electrode are disposed in a same layer, and the source The electrode, the drain electrode, and the pixel electrode are each made of graphene.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板的制造方法，包括：形成像素电极的步骤和形成公共电极（18）的步骤，其中所述像素电极和所述公共电极（18）中至少之一由石墨烯制成。本申请还提供一种由上述方法制造的阵列基板以及包括该阵列基板的显示装置。

Description

阵列基板及其制造方法、 显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制造方法、 显示装置。 背景技术
薄膜晶体管液晶显示器 ( Thin Film Transistor Liquid Crystal Display , TFT-LCD )具有体积小、 功耗低、 无辐射等特点， 在当前的平板显示器市场 占据了主导地位。
目前 TFT-LCD中多釆用氧化铟锡（ITO )作为像素电极以及公共电极。 但是 ITO价格很昂贵， 并且 ITO在酸和碱存在时， 容易出现离子扩散， 不但 会对环境和人体健康造成危害， 而且离子扩散到器件中时会造成器件性能下 降。另外 ITO材质较脆，在发生变形时容易损坏， 4艮难应用到柔性显示领域。 发明内容
根据本发明的一个实施例提供一种阵列基板的制造方法， 包括： 形成像 素电极的步骤和形成公共电极的步骤， 其中所述像素电极和所述公共电极中 至少之一由石墨烯制成。
根据本发明的另一个实施例提供一种阵列基板， 包括像素电极和公共电 极， 其中所述像素电极和所述公共电极中的至少之一由石墨烯制成。
根据本发明的再一个实施例提供一种显示装置， 包括像素电极和公共电 极， 其中所述像素电极和所述公共电极中的至少之一由石墨烯制成。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例一第一次构图工艺之后的阵列基板的平面示意图； 图 2为本发明实施例一第一次构图工艺之后的阵列基板的截面示意图； 图 3为本发明实施例一第二次构图工艺之后的阵列基板的平面示意图； 图 4为本发明实施例一第二次构图工艺之后的阵列基板的截面示意图； 图 5为本发明实施例一第三次构图工艺之后的阵列基板的平面示意图； 图 6为本发明实施例一第三次构图工艺之后的阵列基板的截面示意图； 图 7为本发明实施例一第四次构图工艺之后的阵列基板的截面示意图； 图 8为本发明实施例一第五次构图工艺之后的阵列基板的平面示意图； 图 9为本发明实施例一第五次构图工艺之后的阵列基板的截面示意图； 图 10为本发明实施例二第一次构图工艺之后的阵列基板的平面示意图； 图 11为本发明实施例二第一次构图工艺之后的阵列基板的截面示意图； 图 12为本发明实施例二第二次构图工艺之后的阵列基板的平面示意图； 图 13为本发明实施例二第二次构图工艺之后的阵列基板的截面示意图； 图 14为本发明实施例二第三次构图工艺之后的阵列基板的平面示意图； 图 15为本发明实施例二第三次构图工艺之后的阵列基板的截面示意图； 图 16为本发明实施例二第四次构图工艺之后的阵列基板的平面示意图； 图 17为本发明实施例二第四次构图工艺之后的阵列基板的截面示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明的实施例针对现有技术中釆用 ITO作为像素电极以及公共电极成 本较高， 并且容易出现离子扩散， 从而造成器件性能下降的问题。 本发明的 实施例提供一种阵列基板及其制造方法、 显示装置， 能够降低阵列基板的制 造成本， 提高阵列基板的性能。
本发明实施例提供了一种阵列基板的制造方法， 其中， 该制造方法釆用 石墨烯制作阵列基板的像素电极和 /或公共电极。 另外， 该制造方法可以釆用 一次构图工艺同时形成阵列基板的源电极、 漏电极和像素电极。
本发明实施例还提供了一种以上述方法制造的阵列基板， 该阵列基板包 括像素电极和公共电极， 其中所述像素电极和所述公共电极中的至少之一由 石墨烯制成。 另外， 该阵列基板还包括源电极和漏电极， 其中所述源电极、 所述漏电极与所述像素电极在同一层中， 且所述源电极、 所述漏电极和所述 像素电极均由石墨烯制成。
本发明实施例还提供了一种显示装置， 包括上述的阵列基板。
石墨烯（Graphene )是一种单层碳原子紧密堆积成二维蜂窝状结构的碳 质新材料。 石墨烯的室温本征电子迁移率可达 200000cm2/Vs, 是 Si ( 1400 cm2/Vs ) 的 140倍， GaAs ( 8500 cm2/Vs ) 的 20倍， GaN ( 2000 cm2/Vs ) 的 100倍。 石墨烯室温下的电阻值却只有铜 （Cu ) 的 2/3。 石墨烯还可耐受 1 亿〜 2亿 A/cm2的电流密度， 这是 Cu耐受量的 100倍左右。 同时， 石墨烯还 具有优良的透光性、 导电性、 导热性以及化学稳定性。 因此， 本发明釆用石 墨烯制作出阵列基板的源电极、 漏电极、 像素电极和 /或公共电极， 能够降低 阵列基板的制造成本， 提高阵列基板的性能。 进一步地， 本发明通过一次构 图工艺同时形成阵列基板的源电极、漏电极和像素电极，可以减少工艺步骤， 从而提高产能。
下面结合具体的实施例对本发明的阵列基板及其制造方法进行进一步介 绍：
实施例一
本实施例以高级超维场转换 （ Advanced Super Dimension Switch , ADSDS )技术液晶显示器的阵列基板作为示例进行描述。 ADSDS技术通过 同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生 的电场形成多维电场， 使液晶盒内狭缝电极间、 电极正上方所有取向液晶分 子都能够产生旋转， 从而提高液晶工作效率并增大了透光效率。 高级超维场 开关技术可以提高 TFT-LCD产品的画面品质， 具有高分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低色差、 无挤压水波紋（push Mura )等优点。 然而， 需要注意的是， 根据本发明实施例的阵列基板制造方法并不仅限于 ADSDS技术的阵列基板， 还可以应用于制造其他模式液晶显示器的阵列基 板或有机发光显示器等的阵列基板。
图 1-9为本实施例的阵列基板的制造方法的流程示意图。 如图 1-9所示， 本实施例的阵列基板的制造方法包括以下步骤： 步骤 1: 第一次构图工艺， 在透明基板上形成由金属层制成的栅线； 在透明基板 100上沉积一层金属层， 如图 1和图 2所示， 通过构图工艺 形成栅线 11。构图工艺例如可以包括涂覆、曝光、显影、刻蚀和剥离等步骤。 图 1为平面示意图， 图 2为图 1所示结构的 A-A' 截面示意图。 金属层可以 釆用选自 Nd、 Cr、 W、 Ti、 Ta、 Mo、 Al和 Cu中的任一种或者其中至少两 种金属的合金；
步骤 2: 第二次构图工艺， 在经过第一次构图工艺的透明基板上形成栅 绝缘层和由半导体层制成的有源层；
如图 3和图 4所示， 在完成步骤 1的透明基板上连续沉积栅绝缘层 12、 半导体层， 之后通过构图工艺形成由半导体层制成的有源层 13。 图 3为平面 示意图， 图 4为图 3所示结构的 A-A， 截面示意图。栅绝缘层可以釆用 SiNx, Si02或树脂等， 半导体层可以釆用 a-Si非晶硅、 n+ a-Si非晶硅薄膜、 低温多 晶硅或 IGZO等；
步骤 3: 第三次构图工艺， 在经过第二次构图工艺的透明基板上形成由 第一石墨烯层制成的源电极、 漏电极和像素电极；
在完成步骤 2的透明基板上沉积一层石墨烯薄膜， 即为第一石墨烯层， 如图 5和图 6所示， 通过构图工艺形成源电极 14、 漏电极 15以及像素电极 16。 图 5为平面示意图， 图 6为图 5所示结构的 A-A' 截面示意图。 本实施 例中， 源电极、 漏电极、 像素电极的材料均为石墨烯薄膜；
在本实施例中， 阵列基板上的数据线与源电极 14可以一体制作， 因此， 数据线也可釆用石墨烯制成。 当然， 在实际的生产过程中也可以根据需要将 数据线与源电极釆用不同材料来制作。
步骤 4: 第四次构图工艺， 在经过第三次构图工艺的透明基板上形成钝 化层， 钝化层中具有周边电路用钝化层过孔；
在完成步骤 3的透明基板上沉积一钝化材料层， 如图 7所示， 通过构图 工艺， 形成钝化层 17。 钝化层 17中具有周边电路用钝化层过孔。 该钝化层 可以釆用 SiNx, Si02或树脂等；
步骤 5: 第五次构图工艺， 在经过第四次构图工艺的透明基板上形成由 第二石墨烯层制成的公共电极。
在完成步骤 4的透明基板上沉积一层石墨烯薄膜， 即第二石墨烯层， 如 图 8和图 9所示， 通过构图工艺形成公共电极层 18。 图 8为平面示意图， 图
9为图 8所示结构的 A-A， 截面示意图。
最终， 经过上述步骤 1-5形成了如图 9所示的阵列基板。
在该阵列基板中， 因为源电极、 漏电极和像素电极通过将同一材料层图 案化而形成， 因此， 它们是设置在同一层中。
在本实施例中，优选地将像素电极层和公共电极层均釆用石墨烯来制作； 但本发明提供方案的实现方式不限于此， 比如可以将像素电极层和公共电极 层中的一层结构釆用石墨烯来制作， 而另一层还是釆用传统的 ITO或者铟辞 氧化物 IZO来制作。
本实施例中， 釆用石墨烯制作阵列基板的源电极、 漏电极、 像素电极和 公共电极， 能够降低阵列基板的制造成本， 提高阵列基板的性能。 同时， 本 实施例通过一次构图工艺同时形成阵列基板的源电极、 漏电极和像素电极， 可以减少工艺步骤， 从而提高产能。
实施例二
图 10-17所示为以制作 ADSDS型阵列基板为例， 本实施例的阵列基板 的制造方法的流程示意图， 如图 10-17所示， 本实施例的阵列基板的制造方 法包括以下步骤：
步骤 1: 第一次构图工艺， 在透明基板上形成由第一石墨烯层制成的公 共电极；
在透明基板 200上沉积一石墨烯薄膜， 即第一石墨烯层， 如图 10和图
11所示， 通过构图工艺形成公共电极 21。 图 10 为平面示意图， 图 11为图 10所示结构的 A-A， 截面示意图。构图工艺例如可以包括涂覆、曝光、显影、 刻蚀和剥离等步骤；
步骤 2: 第二次构图工艺， 在经过第一次构图工艺的透明基板上形成由 金属层制成的栅线和公共电极线；
在完成步骤 1的透明基板上沉积一金属层， 如图 12和图 13所示， 通过 构图工艺形成栅线 22以及公共电极线 23。 图 12为平面示意图， 图 13为图 12所示结构的 A-A， 截面示意图。 金属层可以釆用选自 Nd、 Cr、 W、 Ti、 Ta、 Mo、 Al和 Cu中的任一种或者这些金属的合金；
步骤 3: 第三次构图工艺， 在经过第二次构图工艺的透明基板上形成栅 绝缘层、 由半导体层制成的有源层和由绝缘层制成的刻蚀阻挡层；
在完成步骤 2的透明基板上连续沉积栅绝缘层 24、 半导体层和钝化层， 如图 14和图 15所示， 通过构图工艺， 先后在栅线 22上形成有源层 25和刻 蚀阻挡层 26。 图 14是平面示意图， 图 15为图 14所示结构的 A-A， 截面示 意图。 栅绝缘层和钝化层可以釆用 SiNx, Si02或树脂等， 刻蚀阻挡层 26起 保护沟道的作用 ,防止在后续的刻蚀及其他工艺中对沟道造成损伤以及污染。 半导体层可以釆用 a-Si非晶硅薄膜、 n+ a-Si非晶硅薄膜、低温多晶硅或 IGZO 等；
步骤 4: 第四次构图工艺， 在经过第三次构图工艺的透明基板上形成由 第二石墨烯层制成的源电极、 漏电极和像素电极。
在完成步骤 3的透明基板上沉积一层石墨烯薄膜， 即第二石墨烯层， 如 图 16和图 17所示， 通过构图工艺形成源电极 27、 漏电极 28以及像素电极 29。 图 16为平面示意图， 图 17为图 16所示结构的 A-A， 截面示意图。 本 实施例中， 源电极、 漏电极、 像素电极的材料均为石墨烯薄膜。
在本实施例中， 阵列基板上的数据线与源电极 27可以一体制作， 因此， 数据线也可釆用石墨烯制成。 当然， 在实际的生产过程中也可以根据需要将 数据线与源电极釆用不同材料来制作。
最终， 经过上述步骤 1-4形成了如图 17所示的阵列基板。
在该阵列基板中， 因为源电极、 漏电极和像素电极通过将同一材料层图 案化而形成， 因此， 它们是设置在同一层中。
在本实施例中，优选地将像素电极层和公共电极层均釆用石墨烯来制作； 但本发明提供方案的实现方式不限于此， 比如可以将像素电极层和公共电极 层中的一层结构釆用石墨烯来制作， 而另一层还是釆用传统的 ITO或者铟辞 氧化物 IZO来制作。
本实施例中， 釆用石墨烯制作阵列基板的源电极、 漏电极、 像素电极和 公共电极， 能够降低阵列基板的制造成本， 提高阵列基板的性能。 同时， 本 实施例通过一次构图工艺同时形成阵列基板的源电极、 漏电极和像素电极， 可以减少工艺步骤， 从而提高产能。
另外， 虽然以上以 ADSDS型阵列基板为例进行了描述， 然而， 根据本 发明的阵列基板及其制作方法也可以应用于其他模式的阵列基板， 例如面内 切换（IPS )模式阵列基板。 另外， 根据本发明实施例的阵列基板并不一定包 括公共电极， 例如， 根据本发明实施例的阵列基板可以为垂直电场模式的液 晶显示器中的阵列基板， 此时， 公共电极可以不形成在阵列基板上。
根据本发明的实施例还提供一种显示装置， 包括像素电极和公共电极， 其中所述像素电极和所述公共电极中的至少之一由石墨烯制成。 例如， 显示 装置可以包括以上所述的任一阵列基板， 且像素电极和公共电极均形成在所 述阵列基板上； 或者， 阵列基板上仅形成像素电极， 而公共电极形成在显示 装置的另一基板 (例如相对基板 )上。
根据以上实施例的阵列基板均可以应用于根据本发明实施例的显示装 置， 因此， 根据本发明实施例的显示装置也具有上述的结构特征和相应的技 术效果， 此处不再赘述。
例如， 根据本发明的显示装置可以为液晶显示装置， 例如液晶面板、 液 晶电视、 手机、 液晶显示器等， 其包括彩膜基板、 以及上述实施例中的阵列 基板。 除了液晶显示装置， 所述显示装置还可以是其他类型的显示装置， 比 如电子阅读器等， 其不包括彩膜基板， 但是包括上述实施例中的阵列基板。 另外， 根据本发明的显示装置也可以是有机发光显示器。
在本发明各方法实施例中， 各步骤的序号并不能用于限定各步骤的先后 顺序， 对于本领域普通技术人员来讲， 在不付出创造性劳动的前提下， 对各 步骤的先后变化也在本发明的保护范围之内。
( 1 )一种阵列基板的制造方法， 包括： 形成像素电极的步骤和形成公 共电极的步骤，其中所述像素电极和所述公共电极中至少之一由石墨烯制成。
( 2 )根据 ( 1 )所述的阵列基板的制造方法， 其中在所述形成像素电极 的步骤中， 源电极和漏电极与所述像素电极通过一次构图工艺同时形成， 且 所述源电极、 所述漏电极和所述像素电极均由石墨烯制成。
( 3 )根据（ 1 )或（ 2 )所述的阵列基板的制造方法， 其中所述形成像素 电极的步骤在所述形成公共电极的步骤之前进行， 且
其中在所述形成像素电极的步骤之前， 所述方法还包括：
在基板上形成由金属层制成的栅线；
在形成所述栅线的基板上形成栅绝缘层和由半导体层制成的有源层。 (4)根据 (3)所述的阵列基板的制造方法， 其中在所述形成像素电极 的步骤之后且在所述形成公共电极的步骤之前， 所述方法还包括：
在形成所述像素电极的基板上形成钝化层， 所述钝化层中具有周边电路 用钝化层过孔。
( 5 )根据（ 1 )或（ 2 )所述的阵列基板的制造方法， 其中所述形成公共 电极的步骤在所述形成像素电极的步骤之前进行， 且
其中在所述形成公共电极的步骤和所述形成像素电极的步骤之间， 所述 方法还包括：
在形成所述公共电极的基板上形成由金属层制成的栅线和公共电极线； 以及
在形成所述栅线和所述公共电极线的基板上形成栅绝缘层、 由半导体层 制成的有源层和由绝缘层制成的刻蚀阻挡层。
(6)根据（1) - (5) 中任一项所述的阵列基板的制造方法， 其中所述 形成像素电极的步骤包括：
形成石墨烯层； 以及
将所述石墨烯层图案化， 以形成所述源电极、 所述漏电极和所述像素电 极。
(7)根据 (1) - (6) 中任一项所述的阵列基板的制造方法， 其中所述 形成公共电极的步骤包括：
形成石墨烯层； 以及
将所述石墨烯层图案化， 以形成所述公共电极。
( 8 )根据（ 3 )或（ 5 )所述的阵列基板的制造方法， 其中所述金属层的 材料为选自 Nd、 Cr、 W、 Ti、 Ta、 Mo、 Al和 Cu中的至少一种。
( 9 )根据（ 3 )或（ 5 )所述的阵列基板的制造方法， 其中所述栅绝缘层 的材料为 SiNx、 Si02或树脂。
(10)根据（4)或（5)所述的阵列基板的制造方法， 其中所述钝化层 的材料为 SiNx、 Si02或树脂。
(11)根据（3)或（5)所述的阵列基板的制造方法， 其中所述半导体 层的材料为非晶硅、 低温多晶硅或铟镓辞氧化物。
(12) —种阵列基板， 包括像素电极和公共电极， 其中所述像素电极和 所述公共电极中的至少之一由石墨烯制成。
(13)根据（12)所述的阵列基板， 还包括源电极和漏电极， 其中所述 源电极、 所述漏电极与所述像素电极设置在同一层中， 且所述源电极、 所述 漏电极和所述像素电极均由石墨烯制成。
(14)根据（13)所述的阵列基板， 其中所述源电极、 所述漏电极和所 述像素电极釆用一次构图工艺同时形成。
(15) —种显示装置， 包括像素电极和公共电极， 其中所述像素电极和 所述公共电极中的至少之一由石墨烯制成。
(16)根据 (15)所述的显示装置， 其中所述显示装置包括阵列基板， 且所述像素电极和所述公共电极均形成在所述阵列基板上。
( 17)根据（15)或 （16)所述的显示装置， 还包括源电极和漏电极， 其中所述源电极、 所述漏电极与所述像素电极设置在同一层中， 且所述源电 极、 所述漏电极和所述像素电极均由石墨烯制成。
(18)根据（17)所述的显示装置， 其中所述源电极、 所述漏电极和所 述像素电极釆用一次构图工艺同时形成。

Claims

权利要求书
1. 一种阵列基板的制造方法， 包括： 形成像素电极的步骤和形成公共电 极的步骤， 其中所述像素电极和所述公共电极中至少之一由石墨烯制成。
2. 根据权利要求 1所述的阵列基板的制造方法，其中在所述形成像素电 极的步骤中， 源电极和漏电极与所述像素电极通过一次构图工艺同时形成， 且所述源电极、 所述漏电极和所述像素电极均由石墨烯制成。
3.根据权利要求 2所述的阵列基板的制造方法，其中所述形成像素电极 的步骤在所述形成公共电极的步骤之前进行， 且
其中在所述形成像素电极的步骤之前， 所述方法还包括：
在基板上形成由金属层制成的栅线；
在形成所述栅线的基板上形成栅绝缘层和由半导体层制成的有源层。
4. 根据权利要求 3所述的阵列基板的制造方法，其中在所述形成像素电 极的步骤之后且在所述形成公共电极的步骤之前， 所述方法还包括：
在形成所述像素电极的基板上形成钝化层， 所述钝化层中具有周边电路 用钝化层过孔。
5.根据权利要求 2所述的阵列基板的制造方法，其中所述形成公共电极 的步骤在所述形成像素电极的步骤之前进行， 且
其中在所述形成公共电极的步骤和所述形成像素电极的步骤之间， 所述 方法还包括：
在形成所述公共电极的基板上形成由金属层制成的栅线和公共电极线； 以及
在形成所述栅线和所述公共电极线的基板上形成栅绝缘层、 由半导体层 制成的有源层和由绝缘层制成的刻蚀阻挡层。
6. 根据权利要求 2所述的阵列基板的制造方法，其中所述形成像素电极 的步骤包括：
形成石墨烯层； 以及
将所述石墨烯层图案化， 以形成所述源电极、 所述漏电极和所述像素电 极。
7. 根据权利要求 2所述的阵列基板的制造方法，其中所述形成公共电极 的步骤包括：
形成石墨烯层； 以及
将所述石墨烯层图案化， 以形成所述公共电极。
8.根据权利要求 3所述的阵列基板的制造方法，其中所述金属层的材料 为选自 Nd、 Cr、 W、 Ti、 Ta、 Mo、 Al和 Cu中的至少一种。
9.根据权利要求 3所述的阵列基板的制造方法，其中所述栅绝缘层的材 料为 SiNx、 Si02或树脂。
10. 根据权利要求 4所述的阵列基板的制造方法， 其中所述钝化层的材 料为 SiNx、 Si02或树脂。
11. 根据权利要求 3所述的阵列基板的制造方法， 其中所述半导体层的 材料为非晶硅、 低温多晶硅或铟镓辞氧化物。
12. 一种阵列基板， 包括像素电极和公共电极， 其中所述像素电极和所 述公共电极中的至少之一由石墨烯制成。
13. 根据权利要求 12所述的阵列基板， 还包括源电极和漏电极， 其中所 述源电极、 所述漏电极与所述像素电极设置在同一层中， 且所述源电极、 所 述漏电极和所述像素电极均由石墨烯制成。
14. 根据权利要求 13所述的阵列基板， 其中所述源电极、 所述漏电极和 所述像素电极釆用一次构图工艺同时形成。
15. 一种显示装置， 包括像素电极和公共电极， 其中所述像素电极和所 述公共电极中的至少之一由石墨烯制成。
16. 根据权利要求 15所述的显示装置，其中所述显示装置包括阵列基板， 且所述像素电极和所述公共电极均形成在所述阵列基板上。
17. 根据权利要求 15所述的显示装置， 还包括源电极和漏电极， 其中所 述源电极、 所述漏电极与所述像素电极设置在同一层中， 且所述源电极、 所 述漏电极和所述像素电极均由石墨烯制成。
18. 根据权利要求 17所述的显示装置， 其中所述源电极、 所述漏电极和 所述像素电极釆用一次构图工艺同时形成。
PCT/CN2012/083985 2011-12-15 2012-11-02 阵列基板及其制造方法、显示装置 WO2013086909A1 (zh)

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