WO2014012334A1 - 阵列基板的制造方法及阵列基板、显示装置 - Google Patents

阵列基板的制造方法及阵列基板、显示装置 Download PDF

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Publication number
WO2014012334A1
WO2014012334A1 PCT/CN2012/086597 CN2012086597W WO2014012334A1 WO 2014012334 A1 WO2014012334 A1 WO 2014012334A1 CN 2012086597 W CN2012086597 W CN 2012086597W WO 2014012334 A1 WO2014012334 A1 WO 2014012334A1
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Prior art keywords
electrode
transparent electrode
metal oxide
forming
oxide film
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PCT/CN2012/086597
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English (en)
French (fr)
Inventor
崔承镇
金熙哲
宋泳锡
刘圣烈
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京东方科技集团股份有限公司
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Priority to JP2015521941A priority Critical patent/JP6129312B2/ja
Priority to EP12861051.6A priority patent/EP2876676B1/en
Priority to KR1020137019943A priority patent/KR101522481B1/ko
Priority to US13/984,090 priority patent/US9040344B2/en
Publication of WO2014012334A1 publication Critical patent/WO2014012334A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps

Definitions

  • Embodiments of the present invention relate to a method of fabricating an array substrate, an array substrate, and a display device. Background technique
  • a liquid crystal display is a commonly used flat panel display, and a Thin Film Transistor Liquid Crystal Display (TFT-LCD) is a main production port in a liquid crystal display.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • TFT-LCD based on ADvanced Super Dimension Switch is widely used due to its low power consumption and wide viewing angle.
  • the ADS technology mainly forms a multi-dimensional electric field by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that all the aligned liquid crystal molecules are directly between the slit electrodes in the liquid crystal cell and above the electrode. Both can produce rotation, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, wide viewing angle, high aperture ratio, low chromatic aberration, and push mura.
  • the common electrode is also formed on the array substrate in the ADS type TFT-LCD, an additional patterning process for forming the common electrode is required in the fabrication process of the array substrate of the ADS type TFT-LCD.
  • a multi-patterning process is usually required in the manufacturing process of an ADS type TFT-LCD array substrate, and each of the patterning processes includes a process of film formation, exposure, development, etching, and stripping, respectively. Therefore, reducing the number of patterning processes means reducing manufacturing costs.
  • the prior art discloses that an ADS type TFT-LCD array substrate is manufactured by six patterning processes.
  • the method includes:
  • Step 1 depositing a first metal thin film, and forming a gate line, a gate electrode 11 and a common electrode line 12 by a first patterning process.
  • Step 2 depositing a first insulating film, a semiconductor film, and a doped semiconductor film, and forming a gate insulating layer 13 and a semiconductor active layer 14 by a second patterning process (by the semiconductor layer and the doped semiconductor layer Composition).
  • Step 3 depositing a first transparent conductive film, and forming a plate-shaped pixel electrode 14' by a third patterning process.
  • step 4 a second metal thin film is deposited, and the source electrode 16, the drain electrode 17, and the data line are formed by a fourth patterning process.
  • Step 5 depositing a second insulating film to form a passivation layer 18, and forming a via hole penetrating the passivation layer 18 and the gate insulating layer 13 by a fifth patterning process to expose the common electrode line 12.
  • Step 6 depositing a second transparent conductive film, forming a common electrode 19 having slits through a sixth patterning process, and the common electrode 19 is electrically connected to the common electrode line 12 through the via holes formed in the step 5.
  • Embodiments of the present invention provide a method for fabricating an array substrate, an array substrate, and a display device for reducing the number of patterning processes in the manufacturing process of the array substrate and reducing the production cost.
  • a method of fabricating an array substrate forms a thin film transistor, a first transparent electrode, and a second transparent electrode, wherein the first transparent electrode and the second transparent electrode generate a multi-dimensional electric field, wherein Forming the first transparent electrode includes:
  • a portion of the metal oxide film is metallized to form a first transparent electrode, and a portion not subjected to the metallization process forms a semiconductor active layer.
  • the forming the thin film transistor, the first transparent electrode, and the second transparent electrode comprises: sequentially forming a metal oxide film and an etch barrier film on the substrate on which the gate line, the gate electrode, and the gate insulating layer are formed Processing the etch barrier film by a patterning process to form an etch barrier covering the channel region of the TFT; metallizing the metal oxide film not covered by the etch barrier to form a metal having conductor characteristics An oxide thin film; a portion of the metal oxide film covered by the etch barrier layer that is not subjected to the metallization treatment forms a semiconductor active layer; and the metal oxide film having the conductor property is processed by a patterning process to Forming a first transparent electrode and a source connection electrode and a drain connection electrode connected to the semiconductor active layer; Forming a source electrode, a drain electrode, a data line, a passivation layer and a second transparent electrode on the substrate of the semiconductor active layer, the etch barrier layer and the first transparent electrode, wherein the source electrode is electrically connected to the
  • the gate line, the gate electrode, and the common electrode line may be further formed on the substrate. And forming a gate insulating layer on the substrate, the gate line, the gate electrode, and the common electrode line.
  • Forming the source electrode, the drain electrode, the data line, the passivation layer, and the second transparent electrode on the substrate on which the semiconductor active layer, the etch barrier layer, and the first transparent electrode are formed may include: forming a semiconductor active layer, engraved Forming a data line, a source electrode, and a drain electrode electrically connected to the first transparent electrode on the substrate of the etch barrier layer and the first transparent electrode; forming a passivation layer including the first via hole, the first via hole penetrating The passivation layer and the gate insulating layer expose the common electrode line; and forming a second transparent electrode on the passivation layer, the second transparent electrode passing through the first via and the common The electrode wires are electrically connected.
  • the method further includes: forming a gate line, a gate electrode, and a common electrode on the substrate. And a gate insulating layer; a second via hole formed in the gate insulating layer, wherein the second via hole is used to connect the first transparent electrode and the common electrode line.
  • Forming the source electrode, the drain electrode, the data line, the passivation layer, and the second transparent electrode on the substrate on which the semiconductor active layer, the etch barrier layer, and the first transparent electrode are formed may include: forming the semiconductor active layer Forming a source electrode, a drain electrode, and a data line on the substrate of the etch barrier layer and the first transparent electrode; forming a passivation layer including a third via hole, the third via hole penetrating the passivation layer Exposing the drain electrode; and forming a second transparent electrode on the passivation layer, the second transparent electrode being electrically connected through the third via and the drain electrode.
  • the forming the first transparent electrode by metallizing a portion of the metal oxide film may include: forming a metallization process on a portion of the metal oxide film by a plasma process or an annealing process.
  • the first transparent electrode may include: forming a metallization process on a portion of the metal oxide film by a plasma process or an annealing process.
  • the first transparent electrode may be a pixel electrode or a common electrode.
  • the metal oxide film may be a transparent metal oxide material having semiconductor characteristics.
  • the metal oxide material may be InGaZnO, InGaO, ITZO, ⁇
  • an array substrate produced by the above method is provided.
  • a display device including the above array substrate is provided.
  • FIG. 1 is a schematic structural view of an array substrate in the prior art
  • FIG. 2 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention
  • FIG. 3 is a first schematic diagram of an array substrate according to Embodiment 2 of the present invention.
  • FIG. 4 is a second schematic diagram of an array substrate according to Embodiment 2 of the present invention.
  • FIG. 5 is a third schematic diagram of an array substrate according to Embodiment 2 of the present invention.
  • FIG. 6 is a fourth schematic diagram of an array substrate according to Embodiment 2 of the present invention.
  • FIG. 7 is a fifth schematic diagram of an array substrate according to Embodiment 2 of the present invention.
  • FIG. 8 is a sixth schematic diagram of an array substrate according to Embodiment 2 of the present invention.
  • FIG. 9 is a seventh schematic diagram of an array substrate according to Embodiment 2 of the present invention.
  • FIG. 10 is an eighth schematic diagram of an array substrate according to Embodiment 2 of the present invention.
  • FIG. 11 is a ninth schematic view of an array substrate according to Embodiment 2 of the present invention.
  • FIG. 12 is a schematic cross-sectional structural view of an array substrate according to Embodiment 2 of the present invention.
  • FIG. 13 is a first schematic diagram of an array substrate according to Embodiment 3 of the present invention.
  • FIG. 14 is a schematic cross-sectional structural view of an array substrate according to Embodiment 3 of the present invention.
  • FIG. 15 is a first schematic diagram of an array substrate according to Embodiment 4 of the present invention.
  • FIG. 16 is a cross-sectional structural diagram of an array substrate according to Embodiment 4 of the present invention.
  • a method for fabricating an array substrate according to an embodiment of the invention includes a process for fabricating a thin film transistor, a first transparent electrode, and a second transparent electrode.
  • the first transparent electrode and the second transparent electrode generate a multi-dimensional electric field.
  • the manufacturing process of the first transparent electrode includes:
  • a metal oxide film is formed, and the metal oxide film has semiconductor characteristics.
  • a portion of the metal oxide film is metallized to form a first transparent electrode, and a portion not subjected to the metallization treatment forms a semiconductor active layer.
  • forming the first transparent electrode by metallizing a portion of the metal oxide film may include: forming a metallization treatment on a part of the metal oxide film by a plasma process or an annealing process or the like A transparent electrode.
  • the first transparent electrode is a pixel electrode; or the first transparent electrode is a common electrode.
  • the thin metal oxide is thin
  • the film is metallized to exhibit a conductor characteristic to form a first transparent electrode, and a portion not subjected to metallization exhibits characteristics of a semiconductor to form a semiconductor active layer.
  • the semiconductor active layer and the first transparent electrode are formed by one patterning process in the same metal oxide film having the conductor characteristics and the semiconductor characteristics, and the step of separately preparing the first transparent electrode is omitted, which reduces the manufacturing cost.
  • a method for manufacturing an array substrate according to an embodiment of the present invention includes:
  • a first metal thin film is formed on a substrate 10 (such as a glass substrate or a quartz substrate) by plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering, thermal evaporation or other film forming methods.
  • the first metal film may be a single layer film formed of a metal such as molybdenum, aluminum, aluminum bismuth alloy, tungsten, chromium, copper, or the like, or may be a multilayer film formed by depositing the above metal layers.
  • a patterning process such as exposure, development, etching, and lift-off is performed through the mask to form the gate electrode 11 as shown in FIG. 3 and the gate line not shown in FIG. pattern.
  • a gate insulating layer 13 is formed on the substrate 10, the gate line, and the gate electrode 11 by a method such as chemical vapor deposition or evaporation.
  • a metal oxide film and an etch barrier film are sequentially formed on the substrate on which the gate line, the gate electrode, and the gate insulating layer are formed.
  • a metal oxide film 140 and an etch barrier film 150 are sequentially formed on a substrate 10 on which a gate line, a gate electrode 11 and a gate insulating layer 13 are formed.
  • the metal oxide film 140 and the etch barrier film 150 may be formed by magnetron sputtering, thermal evaporation, or chemical vapor deposition.
  • the metal oxide film 140 may be a transparent metal oxide material having a semiconductor property, for example, a transparent metal oxide material such as InGaZnO, InGaO, ITZO, ⁇ ; the etch barrier film 150 may be a dense silicon nitride. , silicon oxide, silicon oxynitride and other materials.
  • the etch stop film is processed by a patterning process to form a pattern of an etch stop layer covering the TFT channel region.
  • the film is retained on the TFT channel region as shown in FIG. 5.
  • the first photoresist 20, other regions are no photoresist.
  • the etch barrier film 150 not covered by the first photoresist 20 is etched, and only the etch barrier film of the first photoresist 20 covering region (ie, the TFT channel region) is left after the process to form a capping TFT.
  • the etch stop layer 15 of the channel region exposes the metal oxide film 140 not covered by the etch barrier layer 15.
  • the exposed metal oxide film 140 may be metallized by a plasma process or an annealing process. This step can be implemented in the following three ways.
  • Method 1 The substrate having the structure shown in Fig. 6 is placed in a vacuum chamber and heated to a certain temperature, and is kept in the air for a while and then cooled.
  • the certain temperature value can be 200 ⁇ 300 °C
  • the holding time can be 20 ⁇ 40 minutes.
  • Method 2 The substrate having the structure shown in Fig. 6 is subjected to heat treatment at 200 to 400 ° C in a reducing atmosphere.
  • Method 3 The substrate having the structure shown in FIG. 6 is placed in a vacuum chamber, and the plasma treatment method is generally performed at a power of 1500 2500 W, a pressure of 1000 to 2000 mtorr, and a hydrogen (H 2 ) plasma and oxygen ( 0 2 ) Plasma treatment Two methods, when using hydrogen plasma or oxygen plasma treatment, the gas flow rate of hydrogen or oxygen is generally 5000 15000 sccm.
  • the carrier concentration of the metallized metal oxide film 140 can be improved to exhibit conductor characteristics, and it can replace the conventional pixel electrode material.
  • the metal oxide film which is not subjected to metallization under the etching stopper layer 15 has a low carrier concentration and exhibits a semiconductor characteristic, that is, the semiconductor active layer 141.
  • a second photoresist layer is coated on the substrate 10, and after exposure and development processing through the mask.
  • the second photoresist 21 remaining on the etch stop layer 15 and on both sides thereof, and the corresponding first transparent electrode region remaining on the metal oxide film 140 having the conductor characteristics are obtained.
  • Three photoresists 22, other areas are no photoresist.
  • the exposed process is exposed by an etching process.
  • a metal oxide film having a conductor property is etched to form a first transparent electrode 14, a source electrode 142 and a drain electrode 143 connected to the semiconductor active layer 141, and finally the second light shown in FIG. 9 is peeled off.
  • the glue 21 and the third photoresist 22 are engraved.
  • the first transparent electrode 14 is used as the pixel electrode (that is, it is electrically connected to the drain electrode), but the embodiment is not limited to the first transparent electrode 14 As a pixel electrode, the first transparent electrode 14 may also be a common electrode.
  • the source and drain electrodes, the data line, the passivation layer, and the second transparent electrode may be formed by a three-time patterning process, respectively.
  • a metal thin film is formed on the substrate 10 by a conventional film forming method such as magnetron sputtering or thermal evaporation, and a source electrode 16 electrically connected to the source connection electrode 142 is formed by a patterning process, and a drain electrode is formed.
  • the drain electrode 17 electrically connected to the electrode 143 and the pattern of the data line (not shown in FIG. 10) are connected.
  • the metal thin film forming the source and drain electrodes and the data line may be a single-layer film formed of a metal such as molybdenum, aluminum, aluminum-bismuth alloy, tungsten, chromium, copper, or the like, or may be a multilayer film formed by depositing the above metal layers. .
  • an insulating film is formed on the substrate 10 by chemical vapor deposition or thermal evaporation to form a passivation layer 18.
  • the insulating film may be a single layer film of silicon nitride, silicon oxide or silicon oxynitride, or a multilayer film formed by multilayer deposition of the above materials.
  • a transparent conductive film is formed by magnetron sputtering or thermal evaporation, and a second transparent electrode 19 having slits is formed by a patterning process.
  • a multi-dimensional electric field can be formed between the first transparent electrode 14 and the second transparent electrode 19.
  • the material of the second transparent electrode 19 may be: a transparent conductive material such as ITO, ZnO, InGaZnO, InZnO or InGaO.
  • the method for fabricating an array substrate according to an embodiment of the present invention forms a first transparent electrode by metallizing a part of the metal oxide film to exhibit a conductor characteristic, and forming a semiconductor by a portion of the metallization process that exhibits semiconductor characteristics.
  • Active layer The semiconductor active layer and the first transparent electrode are formed by one patterning process in the same metal oxide film having the conductor characteristics and the semiconductor characteristics, and the step of separately preparing the first transparent electrode is omitted, which reduces the manufacturing cost.
  • the metal oxide semiconductor material in the TFT channel region is easily oxidized in water or air, the metal oxide semiconductor material in the TFT channel region is easily subjected to wet etching in a subsequent process. To the destruction, the TFT characteristics are low.
  • the corresponding TFT channel region is covered with an etch barrier layer, and the metal oxide semiconductor material of the TFT channel region can avoid the damage during etching under the protection of the etch barrier layer, thereby ensuring TFT characteristics, and further Ensure the display quality of the product.
  • the basic process of the method for manufacturing the array substrate provided by the embodiment of the present invention is similar to that of the second embodiment, and reference may be made to the second embodiment.
  • S201 of the second embodiment S201' of the embodiment includes: as shown in FIG. 13, a gate line (not shown in FIG. 13) is formed on the substrate 10, and the gate electrode 11 is formed. At the same time, the common electrode line 12 is also formed, and then the gate insulating layer 13 is formed on the substrate 10.
  • the common electrode line 12 and the gate electrode 11 and the gate line can be formed by one patterning process.
  • the example S206' includes: Referring to FIG. 14, a source electrode 16 and a drain electrode electrically connected to the first transparent electrode 14 are sequentially formed on the substrate on which the semiconductor active layer 141, the etch barrier layer 15 and the first transparent electrode 14 are formed. 17 and data lines.
  • a passivation layer 18 including a first via hole 181 is formed on the substrate on which the data line, the source electrode 16 and the drain electrode 17 are formed, and the first via hole 181 penetrates the passivation layer 18 and the gate insulating layer 13 to expose the common Electrode line 12.
  • a second transparent electrode 19 is formed on the passivation layer 18, and the second transparent electrode 19 is electrically connected to the common electrode line 12 through the first via 181, and the second transparent electrode 19 is a transparent electrode having a slit.
  • the first transparent electrode 14 and the second transparent electrode 19 having a slit form a multi-dimensional electric field.
  • the first transparent electrode 14 is a pixel electrode, which is in direct contact with the drain electrode 17 for electrical connection; the second transparent electrode 19 is a common electrode, and is electrically connected to the common electrode line 12 through the first via 181.
  • the method for manufacturing an array substrate provided by the embodiment of the present invention forms a first transparent electrode by metallizing a part of the metal oxide film to exhibit a conductor characteristic, and the portion not subjected to metallization exhibits characteristics of a semiconductor to form a semiconductor. Active layer. Forming a semiconductor active layer by one patterning process in the same metal oxide film having conductor characteristics and semiconductor characteristics
  • the first transparent electrode omits the step of separately preparing the first transparent electrode, which reduces the manufacturing cost.
  • the common electrode is electrically connected to the common electrode line, which can greatly reduce the resistance of the common electrode. As the size of the panel increases, the resistance of the common electrode can cause problems such as picture delay or display abnormality, and the first via common electrode The above problems can be completely solved by directly making electrical connection with the common electrode line.
  • the metal oxide semiconductor material of the TFT channel region is easily damaged in the wet etching in the subsequent process, resulting in poor TFT characteristics.
  • the corresponding TFT channel region is covered with an etch barrier layer, and the metal oxide semiconductor material of the TFT channel region can avoid the damage during etching under the protection of the etch barrier layer, thereby ensuring TFT characteristics, and further Ensure the display quality of the product.
  • the basic process of the method for manufacturing the array substrate provided by the embodiment of the present invention is similar to that of the second embodiment, and reference may be made to the second embodiment.
  • the S201 of the embodiment includes: as shown in FIG. 15, a gate line (not shown in FIG. 15) and a gate electrode are formed on the substrate 10. 11 and the common electrode line 12, and the gate insulating layer 13. Thereafter, a second via hole 131 is formed on the gate insulating layer 13, and the second via hole 131 exposes the common electrode line 12 for connecting the first process formed by the subsequent process.
  • the subsequent steps are similar to the steps S202-S204 of the second embodiment.
  • the first transparent electrode 14 in this embodiment is connected to the common electrode line 12 through the second via 131.
  • step S205 of the present embodiment includes: referring to FIG. 16, the formed metal oxide film having the conductor characteristics formed by the patterning process to form the first transparent electrode 14, and The source connection electrode 142 and the drain connection electrode 143 are connected to the semiconductor active layer 141.
  • the first transparent electrode 14 is electrically connected to the common electrode line 12 through the second via hole 131.
  • the step S206 of the present embodiment includes: referring to 16, the source electrode 16 is sequentially formed on the substrate 10 on which the semiconductor active layer 141, the etch barrier layer 15 and the first transparent electrode 14 are formed. After the drain electrode 17 and the data line (not shown in FIG. 16), a passivation layer 18 including a third via hole 182 is formed thereon, and the third via hole 182 penetrates the passivation layer 18 to expose leakage. The pole 17. Next, a second transparent electrode is formed on the passivation layer 18 on which the third via 182 is formed. 19. The second transparent electrode 19 is electrically connected to the drain electrode 17 through the third via 182.
  • the first transparent electrode 14 is a common electrode, and is electrically connected to the common electrode line 12 through the second via 131 on the gate insulating layer 13.
  • the second transparent electrode 19 is a pixel electrode and is electrically connected to the drain electrode 17 through a third via 182 on the passivation layer 18.
  • a portion of the metal oxide film is metallized to exhibit a conductor characteristic to form a first transparent electrode, and a portion not subjected to metallization is characterized by a semiconductor to form a semiconductor.
  • Active layer The semiconductor active layer and the first transparent electrode are formed by one patterning process in the same metal oxide film having the conductor characteristics and the semiconductor characteristics, and the step of separately preparing the first transparent electrode is omitted, which reduces the manufacturing cost.
  • the common electrode is electrically connected to the common electrode line, which can greatly reduce the resistance of the common electrode. As the size of the panel increases, the resistance of the common electrode can cause problems such as picture delay or display abnormality, and the first via common electrode The above problems can be completely solved by directly making electrical connection with the common electrode line.
  • the metal oxide semiconductor material of the TFT channel region is easily damaged in the wet etching in the subsequent process, resulting in poor TFT characteristics.
  • the corresponding TFT channel region is covered with an etch barrier layer, and the metal oxide semiconductor material of the TFT channel region can avoid the damage during etching under the protection of the etch barrier layer, thereby ensuring TFT characteristics, and further Ensure the display quality of the product.
  • the array substrate of the fifth embodiment includes a thin film transistor, a first transparent electrode and a second transparent electrode, the first transparent electrode and the second transparent electrode generate a multi-dimensional electric field, the semiconductor active layer of the thin film transistor and the first
  • the transparent electrode is formed by the same metal oxide film by one patterning process, wherein the first transparent electrode is obtained by metallizing the metal oxide film, and the semiconductor active layer is not metallized.
  • the metal oxide film is formed.
  • the array substrate provided with the pixel electrode and the common electrode in different layers is taken as an example for description. It can be understood that, when the pixel electrode and the common electrode are disposed on the array substrate in the above embodiment, the active layer, the pixel electrode, and the common layer may be formed on a metal oxide film by a patterning process, a metallization process, or the like. The pattern of the electrodes. Therefore, the array substrate provided by the embodiment of the present invention can also be applied to an IPS (in-plane switching) type and an AD-SDS type TFT array substrate by appropriate modification.
  • IPS in-plane switching
  • the array substrate provided by the embodiment of the present invention forms a first transparent electrode by metallizing a part of the metal oxide film to exhibit conductor characteristics, and the portion not subjected to metallization exhibits characteristics of a semiconductor to form a semiconductor active layer.
  • the semiconductor active layer and the first transparent electrode are formed by one patterning process in the same metal oxide film having the conductor characteristics and the semiconductor characteristics, and the step of separately preparing the first transparent electrode is omitted, which reduces the manufacturing cost.
  • the display device provided by the embodiment of the present invention includes the array substrate according to the fifth embodiment, and the array substrate is obtained by the method for fabricating any one of the array substrates of the above-mentioned first to fourth embodiments.
  • the array substrate includes a thin film transistor, a first transparent electrode and a second transparent electrode, the first transparent electrode and the second transparent electrode generate a multi-dimensional electric field, and the semiconductor active layer and the first transparent electrode of the thin film transistor are The same metal oxide film is formed by one patterning process, wherein the first transparent electrode is obtained by metallizing the metal oxide film, and the semiconductor active layer is formed of a metal oxide film which is not metallized.
  • a portion of the metal oxide film is metallized on the array substrate to exhibit a conductor characteristic to form a first transparent electrode, and a portion not subjected to metallization exhibits a semiconductor characteristic.
  • a semiconductor active layer is formed.
  • the semiconductor active layer and the first transparent electrode are formed by one patterning process in the same metal oxide film having the conductor characteristics and the semiconductor characteristics, and the step of separately preparing the first transparent electrode is omitted, which reduces the manufacturing cost.
  • the display device may be: a product or a component having any display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.

Abstract

一种阵列基板的制造方法及阵列基板、显示装置。该阵列基板的制造方法包括形成薄膜晶体管、第一透明电极（14）和第二透明电极（19），其中所述第一透明电极（17）和第二透明电极（19）产生多维电场，其中，所述形成第一透明电极（17）包括：形成金属氧化物薄膜，所述金属氧化物薄膜呈半导体特性；通过对部分所述金属氧化物薄膜进行金属化处理而形成第一透明电极（17），未进行所述金属化处理的部分形成半导体有源层（141）。

Description

阵列基板的制造方法及阵列基板、 显示装置 技术领域
本发明实施例涉及阵列基板的制造方法及阵列基板、 显示装置。 背景技术
液晶显示器是目前常用的平板显示器，其中薄膜晶体管液晶显示器（ Thin Film Transistor Liquid Crystal Display, 简称 TFT-LCD )是液晶显示器中的主 流产口 。
基于高级超维场转换技术（ ADvanced Super Dimension Switch, AD-SDS, 简称 ADS ) 的 TFT-LCD凭借其低功耗、 宽视角等特点， 应用越来越广泛。 ADS 技术主要是通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极 层与板状电极层间产生的电场形成多维电场， 使液晶盒内狭缝电极间、 电极 正上方所有取向液晶分子都能够产生旋转， 从而提高了液晶工作效率并增大 了透光效率。 高级超维场转换技术可以提高 TFT-LCD产品的画面品质， 具 有高分辨率、高透过率、宽视角、高开口率、低色差、无挤压水波紋（ push Mura ) 等优点。
由于 ADS型 TFT-LCD 中， 公共电极也是形成在阵列基板上， 因此在 ADS型 TFT-LCD的阵列基板制作工艺中需要额外增加一次形成公共电极的 构图工艺。
目前， ADS型 TFT-LCD阵列基板的制造过程中通常需要多次构图工艺， 而每一次构图工艺中又分别包括成膜、 曝光、 显影、 刻蚀和剥离等工艺。 因 此， 减少构图工艺的次数就意味着能够降低制造成本。
现有技术中公开有通过六次构图工艺制造 ADS型 TFT-LCD 阵列基板
(如图 1所示） 的方法， 该方法包括：
步骤 1 , 沉积第一金属薄膜， 通过第一次构图工艺形成栅线、 栅电极 11 及公共电极线 12。
步骤 2, 沉积第一绝缘薄膜、 半导体薄膜、 掺杂半导体薄膜， 通过第二 次构图工艺形成栅绝缘层 13、半导体有源层 14 (由半导体层和掺杂半导体层 构成） 。
步骤 3 , 沉积第一透明导电薄膜， 通过第三次构图工艺形成板状的像素 电极 14' 。
步骤 4, 沉积第二金属薄膜， 通过第四次构图工艺形成源电极 16、 漏电 极 17和数据线。
步骤 5, 沉积第二绝缘薄膜以形成钝化层 18, 通过第五次构图工艺形成 贯穿钝化层 18和栅绝缘层 13的过孔， 露出公共电极线 12。
步骤 6, 沉积第二透明导电薄膜， 通过第六次构图工艺形成具有狭缝的 公共电极 19,该公共电极 19通过步骤 5形成的过孔与公共电极线 12电连接。
这种方法需要 6次构图工艺，制造成本仍然较高。为了增强市场竟争力， 提高市场占有率， 需要进一步减小阵列基板制造过程中构图工艺的次数。 发明内容
本发明的实施例提供一种阵列基板的制造方法及阵列基板、 显示装置， 用以减少阵列基板制造过程中构图工艺的次数， 降低生产成本。
为达到上述目的， 本发明的实施例釆用如下技术方案。
根据本发明实施例的一方面，一种阵列基板的制造方法形成薄膜晶体管、 第一透明电极和第二透明电极， 其中所述第一透明电极和第二透明电极产生 多维电场， 其中， 所述形成第一透明电极包括：
形成金属氧化物薄膜， 该金属氧化物薄膜呈半导体特性；
通过对部分所述金属氧化物薄膜进行金属化处理而形成第一透明电极， 未进行所述金属化处理的部分形成半导体有源层。
在一个实施例中， 所述形成薄膜晶体管、 第一透明电极和第二透明电极 包括： 在形成有栅线、 栅电极和栅绝缘层的基板上依次形成金属氧化物薄膜 和刻蚀阻挡层薄膜； 通过构图工艺对所述刻蚀阻挡层薄膜进行处理以形成覆 盖 TFT沟道区域的刻蚀阻挡层；对未被蝕刻阻挡层覆盖的金属氧化物薄膜进 行金属化处理， 形成具有导体特性的金属氧化物薄膜； 金属氧化物薄膜的被 所述刻蚀阻挡层覆盖的未进行所述金属化处理的部分形成半导体有源层； 通 过构图工艺对所述具有导体特性的金属氧化物薄膜进行处理以形成第一透明 电极和与所述半导体有源层连接的源连接电极、 漏连接电极； 在形成有所述 半导体有源层、 刻蚀阻挡层和第一透明电极的基板上形成源电极、 漏电极、 数据线、 钝化层和第二透明电极， 其中， 所述源电极与所述源连接电极电连 接， 所述漏电极与所述漏连接电极电连接。
在一个实施例中， 在形成有栅线、 栅电极和栅绝缘层的基板上依次形成 金属氧化物薄膜和刻蚀阻挡层薄膜之前还可以包括在基板上形成栅线、 栅电 极、 公共电极线以及在所述基板、 所述栅线、 所述栅电极、 所述公共电极线 上形成栅绝缘层。 在形成有半导体有源层、 刻蚀阻挡层和第一透明电极的基 板上形成源电极、 漏电极、 数据线、 钝化层和第二透明电极可以包括： 在形 成有半导体有源层、 刻蚀阻挡层和第一透明电极的基板上形成数据线、 源电 极、 和与所述第一透明电极电连接的漏电极； 形成含有第一过孔的钝化层， 所述第一过孔贯穿所述钝化层和所述栅绝缘层， 露出所述公共电极线； 以及 在所述钝化层上形成第二透明电极， 所述第二透明电极通过所述第一过孔和 所述公共电极线电连接。
在一个实施例中， 在形成有栅线、 栅电极和栅绝缘层的基板上依次形成 金属氧化物薄膜和刻蚀阻挡层薄膜之前还可以包括： 在基板上形成栅线、 栅 电极、 公共电极线、 以及栅绝缘层； 在形成所述栅绝缘层中第二过孔， 所述 第二过孔用以连接所述第一透明电极与所述公共电极线。 在形成有半导体有 源层、 刻蚀阻挡层和第一透明电极的基板上形成源电极、 漏电极、 数据线、 钝化层和第二透明电极可以包括： 在形成有所述半导体有源层、 所述刻蚀阻 挡层和所述第一透明电极的基板上形成源电极、 漏电极和数据线； 形成含有 第三过孔的钝化层， 所述第三过孔贯穿所述钝化层， 露出所述漏电极； 以及 在所述钝化层上形成第二透明电极， 所述第二透明电极通过所述第三过孔和 所述漏电极电连接。
在一个实施例中， 所述通过对部分所述金属氧化物薄膜进行金属化处理 而形成第一透明电极可以包括： 通过等离子工艺或退火工艺对部分所述金属 氧化物薄膜进行金属化处理而形成第一透明电极。
在一个实施例中， 所述第一透明电极可以为像素电极或者公共电极。 在一个实施例中， 所述金属氧化物薄膜可以釆用呈半导体特性的透明金 属氧化物材料。 例如， 所述金属氧化物材料可以为 InGaZnO、 InGaO、 ITZO, ΑΙΖηΟο 根据本发明实施例的另一方面， 提供一种由上述方法制得的阵列基板。 根据本发明实施例的另一方面， 提供一种显示装置， 该显示装置包括上 述阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术中阵列基板的结构示意图；
图 2为本发明实施例提供的阵列基板的制造方法的流程图；
图 3为本发明实施例二提供的阵列基板的第一示意图；
图 4为本发明实施例二提供的阵列基板的第二示意图；
图 5为本发明实施例二提供的阵列基板的第三示意图；
图 6为本发明实施例二提供的阵列基板的第四示意图；
图 7为本发明实施例二提供的阵列基板的第五示意图；
图 8为本发明实施例二提供的阵列基板的第六示意图；
图 9为本发明实施例二提供的阵列基板的第七示意图；
图 10为本发明实施例二提供的阵列基板的第八示意图；
图 11为本发明实施例二提供的阵列基板的第九示意图；
图 12为本发明实施例二提供的阵列基板的剖面结构示意图；
图 13为本发明实施例三提供的阵列基板的第一示意图；
图 14为本发明实施例三提供的阵列基板的剖面结构示意图；
图 15为本发明实施例四提供的阵列基板的第一示意图；
图 16为本发明实施例四提供的阵列基板的剖面结构示意图。
附图标记说明： 1-栅线； 2-数据线； 10-基板， 11-栅电极； 12-公共电极 线； 13-栅绝缘层， 131-第二过孔； 141-半导体有源层； 142-源连接电极， 143- 漏连接电极， 14-第一透明电极， 140-金属氧化物薄膜； 15-刻蚀阻挡层， 150- 刻蚀阻挡层薄膜； 16-源电极； 17-漏电极； 18-钝化层， 181-第一过孔， 182- 第三过孔； 19-第二透明电极； 20-第一光刻胶、 21-第二光刻胶； 22-第三光刻 胶。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性，而只是用来区分不同的组成部分。同样， "一个 "或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包 含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵 盖出现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排 除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语并非限定于物理 的或者机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被描述对 象的绝对位置改变后， 则该相对位置关系也可能相应地改变。
实施例一
本发明实施例提供的阵列基板的制造方法， 包括薄膜晶体管、 第一透明 电极和第二透明电极的制作工艺。 该第一透明电极和第二透明电极产生多维 电场。 其中， 该第一透明电极的制作工艺包括：
步骤一， 形成金属氧化物薄膜， 该金属氧化物薄膜呈半导体特性。
步骤二， 通过对部分该金属氧化物薄膜进行金属化处理而形成第一透明 电极， 未进行所述金属化处理的部分形成半导体有源层。
进一步地， 步骤二中 "通过对部分该金属氧化物薄膜进行金属化处理而 形成第一透明电极" 可以包括： 通过等离子工艺或退火工艺等对部分该金属 氧化物薄膜进行金属化处理而形成第一透明电极。
进一步地， 在本实施例中， 所述第一透明电极为像素电极； 或者， 所述 第一透明电极为公共电极。
本发明实施例提供的阵列基板的制造方法中， 通过对部分金属氧化物薄 膜进行金属化处理而使其呈现导体特性从而形成第一透明电极， 未进行金属 化处理的部分呈现半导体的特性从而形成半导体有源层。 在具有导体特性和 半导体特性的同一层金属氧化物薄膜中通过一次构图工艺形成半导体有源层 和第一透明电极， 省略了单独制备第一透明电极的步骤， 降低了生产制造成 本。
实施例二
本发明实施例提供的阵列基板的制造方法， 如图 2所示， 该方法包括：
5201 , 在基板上形成栅线、 薄膜晶体管的栅电极和栅绝缘层。
示例性的， 参照图 3, 首先釆用等离子增强化学气相沉积（PECVD ) 、 磁控溅射、 热蒸发或其它成膜方法， 在基板 10 (如玻璃基板或石英基板）上 形成第一金属薄膜。 其中， 该第一金属薄膜可以是钼、 铝、 铝铷合金、 钨、 铬、铜等金属形成的单层薄膜，也可以是以上金属多层沉积形成的多层薄膜。 在第一金属薄膜上涂覆光刻胶层后， 通过掩模板进行曝光、 显影、 刻蚀和剥 离等构图工艺处理，形成如图 3所示的栅电极 11和图 3中未表示的栅线图案。 随后， 通过化学气相沉积方或蒸镀等方法在基板 10、 栅线和栅电极 11上形 成栅绝缘层 13。
5202, 在形成有栅线、 栅电极和栅绝缘层的基板上依次形成金属氧化物 薄膜和刻蚀阻挡层薄膜。
示例性的， 如图 4所示， 在形成有栅线、 栅电极 11和栅绝缘层 13的基 板 10上依次形成金属氧化物薄膜 140和刻蚀阻挡层薄膜 150。 例如， 可以釆 用磁控溅射、 热蒸发或化学气相沉积等方法形成金属氧化物薄膜 140和刻蚀 阻挡层薄膜 150。 例如， 金属氧化物薄膜 140可以釆用呈半导体特性的透明 金属氧化物材料， 例如可以是 InGaZnO、 InGaO、 ITZO, ΑΙΖηΟ等透明金属 氧化物材料； 刻蚀阻挡层薄膜 150可以是致密的氮化硅、 氧化硅、 氮氧化硅 等材料。
5203,通过构图工艺对所述刻蚀阻挡层薄膜进行处理以形成覆盖 TFT沟 道区域的刻蚀阻挡层的图形。
示例性的， 参照图 5, 在刻蚀阻挡层薄膜 150上涂覆第一光刻胶层后， 通过掩模板进行曝光、显影处理后， 得到如图 5所示的保留在 TFT沟道区域 上的第一光刻胶 20, 其他区域则无光刻胶。 之后， 如图 6所示， 通过刻蚀工 艺对没有第一光刻胶 20覆盖的刻蚀阻挡层薄膜 150进行刻蚀，处理后仅保留 第一光刻胶 20覆盖区域 (即 TFT沟道区域） 的刻蚀阻挡层薄膜， 形成覆盖 TFT沟道区域的刻蚀阻挡层 15, 露出未被刻蚀阻挡层 15覆盖的金属氧化物 薄膜 140。
S204, 对未被蝕刻阻挡层 15覆盖的金属氧化物薄膜 140进行金属化处 理， 形成具有导体特性的金属氧化物薄膜， 其中金属氧化物薄膜的被所述刻 蚀阻挡层 15覆盖的未进行所述金属化处理的部分形成半导体有源层。
示例性的， 如图 7所示， 可以通过等离子工艺或退火工艺等对外露的金 属氧化物薄膜 140进行金属化处理。 该步骤可以通过以下三种方式实现。
方式一： 将具有图 6所示结构的基板置于真空腔室中加热到一定温度， 并保持一时间后在空气中冷却。 例如， 该一定温度值可以为 200~300°C , 保 持时间可以为 20~40分钟。
方式二： 将具有图 6所示结构的基板置于还原性气氛中在 200~400°C进 行热处理。
方式三： 将具有图 6所示结构的基板置于真空腔室中， 釆用等离子体处 理的方法， 一般功率为 1500 2500W, 压力为 1000~2000mtorr, 有氢气（H2 ) 等离子体和氧气（02 )等离子体处理两种方法， 使用氢气等离子体或氧气等 离子体处理时， 氢气或氧气的气体流量一般为 5000 15000sccm。
通过上述三种方式， 可以使被金属化处理的金属氧化物薄膜 140的载流 子浓度提高， 呈现导体特性， 可以取代现有的像素电极材料。 而刻蚀阻挡层 15下面的未进行金属化处理的金属氧化物薄膜的载流子浓度较低，呈现半导 体特性， 即为半导体有源层 141。
S205, 通过构图工艺对所述具有导体特性的金属氧化物薄膜进行处理以 形成第一透明电极， 以及与所述半导体有源层连接的源连接电极、 漏连接电 极。
示例性的， 剥离图 7所示的覆盖刻蚀阻挡层 15的第一光刻胶 20后， 再 在该基板 10上涂覆第二光刻胶层， 通过掩模板进行曝光、显影处理后，如图 8所示，得到保留在刻蚀阻挡层 15之上及其两侧的第二光刻胶 21 , 以及保留 在具有导体特性的金属氧化物薄膜 140上的对应第一透明电极区域的第三光 刻胶 22, 其他区域则无光刻胶。 之后， 如图 9所示， 通过刻蚀工艺对露出的 具有导体特性的金属氧化物薄膜进行刻蚀， 形成第一透明电极 14, 以及与所 述半导体有源层 141连接的源电极 142、漏电极 143 ,最后剥离掉图 9中所示 的第二光刻胶 21、 第三光刻胶 22。
S206, 在形成有半导体有源层、 刻蚀阻挡层和第一透明电极的基板上依 次形成源电极、 漏电极、 数据线、 钝化层和第二透明电极的图形。
需要说明的是：在本实施例中，是以第一透明电极 14作为像素电极（即， 其与漏电极电连接）为例进行说明的， 但本实施例并不限于第一透明电极 14 必须为像素电极， 该第一透明电极 14也可以是公共电极。
本步骤中源和漏电极、 数据线、 钝化层和第二透明电极可以分别通过三 次构图工艺形成。
参见图 10, 釆用现有的成膜方法如磁控溅射或热蒸发等方法在基板 10 上形成金属薄膜，并通过构图工艺形成与源连接电极 142电连接的源电极 16 , 和与漏连接电极 143电连接的漏电极 17以及数据线（图 10中未显示出） 的 图案。 在此， 形成源和漏电极以及数据线的金属薄膜可以是钼、 铝、 铝铷合 金、 钨、 铬、 铜等金属形成的单层薄膜， 也可以是以上金属多层沉积形成的 多层薄膜。
接着， 如图 11所示， 再在基板 10上通过化学气相沉积或热蒸发等方法 制备绝缘薄膜形成钝化层 18。 其中， 该绝缘薄膜可以釆用氮化硅、 氧化硅或 氮氧化硅的单层薄膜， 也可以釆用上述材料的多层沉积形成的多层薄膜。
最后， 如图 12所示， 通过磁控溅射或热蒸发等方法形成透明导电薄膜， 并通过构图工艺形成具有狭缝的第二透明电极 19。 第一透明电极 14与第二 透明电极 19之间可以形成多维电场。其中，第二透明电极 19的材料可以是： ITO、 ZnO、 InGaZnO, InZnO、 InGaO等透明导电材料。
本发明实施例提供的阵列基板的制造方法， 通过对部分金属氧化物薄膜 进行金属化处理以使其呈现导体特性而形成第一透明电极， 未进行金属化处 理的部分呈现半导体的特性而形成半导体有源层。 在具有导体特性和半导体 特性的同一层金属氧化物薄膜中通过一次构图工艺形成半导体有源层和第一 透明电极， 省略了单独制备第一透明电极的步骤， 降低了生产制造成本。
此外， 由于金属氧化物半导体材料很容易在水中或空气中被氧化， 因而 在后续工艺中 TFT 沟道区域的金属氧化物半导体材料极易在湿法刻蚀时受 到破坏， 导致 TFT特性低下。 本发明实施例中对应 TFT沟道区域覆盖有刻 蚀阻挡层， TFT沟道区域的金属氧化物半导体材料可以在刻蚀阻挡层的保护 下避免刻蚀时的破坏， 从而能够保证 TFT特性， 进而确保产品的显示品质。
实施例三
本发明实施例提供的阵列基板的制造方法的基本过程与实施例二类似， 可以参照实施例二。
本实施例与实施例二的不同在于， 代替实施例二的 S201 , 本实施例的 S201'包括： 如图 13所示， 在基板 10上形成栅线（图 13中未表示） 、 栅电 极 11的同时，还形成公共电极线 12,之后，再在基板 10上形成栅绝缘层 13。
进一步的， 公共电极线 12与栅电极 11和栅线可以通过一次构图工艺形 成。
形成栅线、 栅电极及公共电极线之后的步骤与实施例二的步骤 S202-S205相同， 不再赘述。
在形成有半导体有源层、 刻蚀阻挡层和第一透明电极的基板上形成源电 极、漏电极、数据线、钝化层和第二透明电极的图形，代替实施例二的 S206, 本实施例的 S206'包括： 参照图 14, 在形成有半导体有源层 141、 刻蚀阻挡 层 15和第一透明电极 14的基板上依次形成源电极 16、 与第一透明电极 14 电连接的漏电极 17和数据线。 然后再在形成有数据线、 源电极 16和漏电极 17的基板上形成包含第一过孔 181的钝化层 18,该第一过孔 181贯穿钝化层 18和栅绝缘层 13 , 露出公共电极线 12。 接着， 再在钝化层 18上形成第二透 明电极 19, 该第二透明电极 19通过第一过孔 181与公共电极线 12电连接， 该第二透明电极 19为具有狭缝的透明电极， 第一透明电极 14和具有狭缝的 第二透明电极 19形成多维电场。
因此， 在本实施例中， 第一透明电极 14为像素电极， 与漏电极 17直接 接触实现电连接； 第二透明电极 19为公共电极，通过第一过孔 181与公共电 极线 12电连接。
本发明实施例提供的阵列基板的制造方法， 通过对部分金属氧化物薄膜 进行金属化处理以使其呈现导体特性从而形成第一透明电极， 未进行金属化 处理的部分呈现半导体的特性从而形成半导体有源层。 在具有导体特性和半 导体特性的同一层金属氧化物薄膜中通过一次构图工艺形成半导体有源层和 第一透明电极，省略了单独制备第一透明电极的步骤，降低了生产制造成本。 同时， 将公共电极与公共电极线电连接， 可大幅降低公共电极的电阻， 随着 面板尺寸的增大， 公共电极的电阻可导致画面延迟或显示异常等问题， 通过 上述第一过孔公共电极与公共电极线直接实现电连接， 可以彻底解决上述问 题。
此外， 由于金属氧化物半导体材料很容易在水中或空气中被氧化， 因而 在后续工艺中 TFT 沟道区域的金属氧化物半导体材料极易在湿法刻蚀时受 到破坏导致 TFT特性低下。 本发明实施例中对应 TFT沟道区域覆盖有刻蚀 阻挡层， TFT沟道区域的金属氧化物半导体材料可以在刻蚀阻挡层的保护下 避免刻蚀时的破坏， 从而能够保证 TFT特性， 进而确保产品的显示品质。
实施例四
本发明实施例提供的阵列基板的制造方法的基本过程与实施例二类似， 可以参照实施例二。
本实施例与实施例二的不同在于， 代替实施例二的步骤 S201 , 本实施例 的 S201"包括： 如图 15所示， 在基板 10上形成栅线（图 15中未表示 )、 栅 电极 11和公共电极线 12、 以及栅绝缘层 13。之后，再在栅绝缘层 13上形成 第二过孔 131 , 该第二过孔 131露出公共电极线 12, 用以连接后续工艺形成 的第一透明电极 14和公共电极线 12。
之后的步骤与实施例二的步骤 S202-S204类似， 参照图 16, 本实施例中 的第一透明电极 14通过第二过孔 131与公共电极线 12连接。
代替实施例二的步骤 S205, 本实施例的步骤 S205"包括： 参照图 16, 通过构图工艺对所形成的具有导体特性的金属氧化物薄膜进行处理以形成第 一透明电极 14, 和与所述半导体有源层 141连接的源连接电极 142、 漏连接 电极 143。 其中， 第一透明电极 14通过第二过孔 131和公共电极线 12电连 接。
代替实施例二的步骤 S206, 本实施例的步骤 S206"包括： 参照 16, 在 形成有半导体有源层 141、 刻蚀阻挡层 15和第一透明电极 14， 的基板 10上 依次形成源电极 16、 漏电极 17、 数据线（图 16中未示出）后， 再在其上形 成含有第三过孔 182的钝化层 18,该第三过孔 182贯穿所述钝化层 18,露出 漏电极 17。 接着， 在形成有第三过孔 182的钝化层 18上形成第二透明电极 19, 该第二透明电极 19通过第三过孔 182与漏电极 17电连接。
因此， 在本实施例中， 第一透明电极 14为公共电极， 通过栅绝缘层 13 上的第二过孔 131与公共电极线 12电连接。 第二透明电极 19为像素电极， 通过钝化层 18上的第三过孔 182与漏电极 17电连接。
本发明实施例提供的阵列基板的制造方法中， 通过对部分金属氧化物薄 膜进行金属化处理以使其呈现导体特性而形成第一透明电极， 未进行金属化 处理的部分呈现半导体的特性形成半导体有源层。 在具有导体特性和半导体 特性的同一层金属氧化物薄膜中通过一次构图工艺形成半导体有源层和第一 透明电极， 省略了单独制备第一透明电极的步骤， 降低了生产制造成本。 同 时， 将公共电极与公共电极线电连接， 可大幅降低公共电极的电阻， 随着面 板尺寸的增大， 公共电极的电阻可导致画面延迟或显示异常等问题， 通过上 述第一过孔公共电极与公共电极线直接实现电连接，可以彻底解决上述问题。
此外， 由于金属氧化物半导体材料很容易在水中或空气中被氧化， 因而 在后续工艺中 TFT 沟道区域的金属氧化物半导体材料极易在湿法刻蚀时受 到破坏导致 TFT特性低下。 本发明实施例中对应 TFT沟道区域覆盖有刻蚀 阻挡层， TFT沟道区域的金属氧化物半导体材料可以在刻蚀阻挡层的保护下 避免刻蚀时的破坏， 从而能够保证 TFT特性， 进而确保产品的显示品质。
实施例五 得的阵列基板包括薄膜晶体管、 第一透明电极和第二透明电极， 所述第一透 明电极和第二透明电极产生多维电场， 所述薄膜晶体管的半导体有源层和所 述第一透明电极是由同一金属氧化薄膜通过一次构图工艺形成的， 其中， 所 述所述第一透明电极由所述金属氧化物薄膜通过金属化处理得到， 所述半导 体有源层由未被金属化处理的金属氧化物薄膜形成。
需要说明的是， 上述各个实施例中是以像素电极和公共电极异层设置的 阵列基板为例进行的说明。 可以理解的是， 以上实施例中像素电极和公共电 极同层设置在阵列基板上时， 也可以通过构图工艺、 金属化处理等在一层金 属氧化物薄膜上形成有源层、 像素电极和公共电极的图案。 因此， 本发明实 施例提供的阵列基板通过适当的变形也可以适用于 IPS (平面内开关）型和 AD-SDS型的 TFT阵列基板。 本发明实施例提供的阵列基板， 通过对部分金属氧化物薄膜进行金属化 处理以使其呈现导体特性而形成第一透明电极， 未进行金属化处理的部分呈 现半导体的特性形成半导体有源层。 在具有导体特性和半导体特性的同一层 金属氧化物薄膜中通过一次构图工艺形成半导体有源层和第一透明电极， 省 略了单独制备第一透明电极的步骤， 降低了生产制造成本。
实施例六
本发明实施例提供的显示装置包括实施例五所述的阵列基板， 该阵列基 板由上述实施一至实施例四中的任意一种阵列基板的制作方法制得。 该阵列 基板包括薄膜晶体管、第一透明电极和第二透明电极,所述第一透明电极和第 二透明电极产生多维电场， 所述薄膜晶体管的半导体有源层和所述第一透明 电极是由同一金属氧化薄膜通过一次构图工艺形成的， 其中， 所述第一透明 电极由该金属氧化物薄膜通过金属化处理得到， 所述半导体有源层由未被金 属化处理的金属氧化物薄膜形成。
本发明实施例提供的显示装置中， 在其阵列基板上通过对部分金属氧化 物薄膜进行金属化处理以使其呈现导体特性而形成第一透明电极， 未进行金 属化处理的部分呈现半导体的特性形成半导体有源层。 在具有导体特性和半 导体特性的同一层金属氧化物薄膜中通过一次构图工艺形成半导体有源层和 第一透明电极，省略了单独制备第一透明电极的步骤，降低了生产制造成本。
需要说明的是本发明实施例所提供的显示装置可以为： 液晶面板、 电子 纸、 OLED面板、 液晶电视、 液晶显示器、 数码相框、 手机、 平板电脑等具 有任何显示功能的产品或部件。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种阵列基板的制造方法， 包括形成薄膜晶体管、第一透明电极和第 二透明电极， 其中所述第一透明电极和第二透明电极产生多维电场， 其中， 所述形成第一透明电极包括：
形成金属氧化物薄膜， 所述金属氧化物薄膜呈半导体特性；
通过对部分所述金属氧化物薄膜进行金属化处理而形成第一透明电极， 未进行所述金属化处理的部分金属氧化物薄膜形成半导体有源层。
2、根据权利要求 1所述的方法， 其中， 所述形成薄膜晶体管、 第一透明 电极和第二透明电极包括：
在形成有栅线、 栅电极和栅绝缘层的基板上依次形成金属氧化物薄膜和 刻蚀阻挡层薄膜；
通过构图工艺对所述刻蚀阻挡层薄膜进行处理以形成覆盖 TFT 沟道区 域的刻蚀阻挡层；
对未被蝕刻阻挡层覆盖的金属氧化物薄膜进行金属化处理， 形成具有导 体特性的金属氧化物薄膜； 金属氧化物薄膜的被所述刻蚀阻挡层覆盖的未进 行所述金属化处理的部分形成半导体有源层；
通过构图工艺对所述具有导体特性的金属氧化物薄膜进行处理以形成第 一透明电极和与所述半导体有源层连接的源连接电极、 漏连接电极；
在形成有所述半导体有源层、 刻蚀阻挡层和第一透明电极的基板上形成 源电极、 漏电极、 数据线、 钝化层和第二透明电极， 其中， 所述源电极与所 述源连接电极电连接， 所述漏电极与所述漏连接电极电连接。
3、 根据权利要求 2所述的方法， 其中，
在形成有栅线、 栅电极和栅绝缘层的基板上依次形成金属氧化物薄膜和 刻蚀阻挡层薄膜之前还包括在基板上形成栅线、 栅电极、 公共电极线以及在 所述基板、 所述栅线、 所述栅电极、 所述公共电极线上形成栅绝缘层；
在形成有半导体有源层、 刻蚀阻挡层和第一透明电极的基板上形成源电 极、 漏电极、数据线、钝化层和第二透明电极包括： 在形成有半导体有源层、 刻蚀阻挡层和第一透明电极的基板上形成数据线、 源电极、 和与所述第一透 明电极电连接的漏电极； 形成含有第一过孔的钝化层， 所述第一过孔贯穿所 述钝化层和所述栅绝缘层， 露出所述公共电极线； 以及在所述钝化层上形成 第二透明电极， 所述第二透明电极通过所述第一过孔和所述公共电极线电连 接。
4、 根据权利要求 2所述的方法， 其中，
在形成有栅线、 栅电极和栅绝缘层的基板上依次形成金属氧化物薄膜和 刻蚀阻挡层薄膜之前， 还包括： 在基板上形成栅线、 栅电极、 公共电极线、 以及栅绝缘层； 在形成所述栅绝缘层中第二过孔， 所述第二过孔用以连接所 述第一透明电极与所述公共电极线；
在形成有半导体有源层、 刻蚀阻挡层和第一透明电极的基板上形成源电 极、 漏电极、 数据线、 钝化层和第二透明电极包括： 在形成有所述半导体有 源层、 所述刻蚀阻挡层和所述第一透明电极的基板上形成源电极、 漏电极和 数据线； 形成含有第三过孔的钝化层， 所述第三过孔贯穿所述钝化层， 露出 所述漏电极； 以及在所述钝化层上形成第二透明电极， 所述第二透明电极通 过所述第三过孔和所述漏电极电连接。
5、 根据权利要求 1-4的任一项所述的方法， 其中， 所述通过对部分所述 金属氧化物薄膜进行金属化处理而形成第一透明电极包括：
通过等离子工艺或退火工艺对部分所述金属氧化物薄膜进行金属化处理 而形成第一透明电极。
6、根据权利要求 5所述的方法， 其中， 所述第一透明电极为像素电极或 者公共电极。
7、 根据权利要求 1~6 中任一项所述的方法， 其中， 所述金属氧化物薄 膜釆用呈半导体特性的透明金属氧化物材料。
8、根据权利要求 7所述的方法，其中，所述金属氧化物材料为 InGaZnO、 InGaO、 ΙΤΖΟ, Α1ΖηΟ„
9、 一种阵列基板， 其中， 由权利要求 1~8的任一项所述的方法制得。
10、 一种显示装置， 所述显示装置包括权利要求 9所述的阵列基板。
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EP2876676A1 (en) 2015-05-27
KR20140037808A (ko) 2014-03-27
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