WO2014166176A1 - 薄膜晶体管及其制作方法、阵列基板和显示装置 - Google Patents

薄膜晶体管及其制作方法、阵列基板和显示装置 Download PDF

Info

Publication number
WO2014166176A1
WO2014166176A1 PCT/CN2013/079346 CN2013079346W WO2014166176A1 WO 2014166176 A1 WO2014166176 A1 WO 2014166176A1 CN 2013079346 W CN2013079346 W CN 2013079346W WO 2014166176 A1 WO2014166176 A1 WO 2014166176A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
contact layer
substrate
contact
active layer
Prior art date
Application number
PCT/CN2013/079346
Other languages
English (en)
French (fr)
Inventor
张立
姜春生
王东方
陈海晶
刘凤娟
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/348,763 priority Critical patent/US9368637B2/en
Publication of WO2014166176A1 publication Critical patent/WO2014166176A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous

Definitions

  • Embodiments of the present invention relate to a thin film transistor and a method of fabricating the same, an array substrate, and a display device. Background technique
  • an oxide thin film transistor In the field of display technology, an oxide thin film transistor (TFT) is compared with an amorphous silicon TFT because of its high carrier mobility (carrier mobility is about ten times that of an amorphous silicon TFT). , as well as high thermal and chemical stability, has become a research hotspot.
  • a display device driven by an oxide TFT can meet the requirements of a large-sized, high-resolution display device, and in particular, can meet the requirements of a next-generation active matrix organic light emitting device (AMOLED). It occupies an important position in the field of flat panel display.
  • AMOLED active matrix organic light emitting device
  • oxide TFTs At present, there is a high demand for the production of oxide TFTs. Therefore, under the premise of ensuring the production of high-performance oxide TFTs, the structure and process flow of the device are always pursued.
  • Existing oxide TFTs generally use a top gate type.
  • FIG. 1 shows a conventional pixel electrode driving structure using a top gate type oxide TFT, comprising: a substrate 101, an active layer 102 on the substrate 101, a gate insulating layer 103 on the active layer 102, a gate 104 on the gate insulating layer 103, an etch stop layer 105 on the gate 104, a source and drain layer 106 (including source and drain) on the etch stop layer 105, and a source/drain layer 106 A passivation protective layer 107, and a pixel electrode 108 on the passivation protective layer 107 connected to the drain in the source and drain layers 106.
  • the top gate type TFT shown in FIG. 1 is fabricated by the following 6Mask process, and the patterning process generally includes at least masking, exposure, development, photolithography, and etching processes, and each exposure process uses a mask corresponding to the pattern to be formed ( Mask ) for exposure.
  • the gate insulating layer 103 and the gate 104 pattern are formed by the second patterning process.
  • the gate 104 pattern is first formed by wet etching, and then the gate insulating layer 103 is formed by dry etching. Graphics.
  • the etch barrier layer 105 pattern is formed by the third patterning process.
  • the source and drain layer 106 patterns are formed by the fourth patterning process.
  • the passivation protective layer 107 pattern is formed by the fifth patterning process, wherein the passivation protective layer 107 is formed with a contact hole for connecting the drain and the pixel electrode 108 formed later.
  • the pixel electrode pattern 108 is formed by the sixth patterning process.
  • Embodiments of the present invention provide a thin film transistor, a method of fabricating the same, an array substrate, and a display device to provide a TFT having a structural unit and a better performance.
  • a thin film transistor comprising: a substrate; an active layer formed on the substrate; an electrically conductive first contact layer and a second contact layer formed on the active layer An etch stop layer formed on the first contact layer and the second contact layer; a source formed on the etch stop layer connected to the first contact layer, connected to the second contact layer a drain, and a gate between the source and the drain.
  • the first contact layer and the second contact layer are arranged in mirror symmetry.
  • a projection area of the gate and the first contact layer in a vertical direction is equal to a projected area of the gate and the second contact layer in a vertical direction.
  • the distance between the first contact layer and the second contact layer is
  • the thin film transistor further includes an isolation layer between the active layer and the substrate for isolating light.
  • the thin film transistor further includes a pixel electrode on the protective layer, the pixel electrode being electrically connected to a drain under the protective layer through a via hole on the protective layer.
  • an array substrate including the above thin film transistor is provided.
  • a display device including the above array substrate is provided.
  • a method of fabricating a thin film transistor includes: forming a pattern including an active layer on a substrate;
  • a protective layer pattern covering the entire substrate is formed on the substrate on which the gate, the source and the drain are formed.
  • a pattern including an active layer is formed on a substrate, and a set region of the active layer is ion-implanted to form a pattern of a first contact layer and a second contact layer on the active layer
  • the steps include:
  • the photoresist on the active layer is stripped.
  • the method may further include: forming a spacer layer capable of isolating light on the substrate before forming the active layer.
  • the forming the spacer layer comprises: forming an aluminum oxide layer, an amorphous silicon layer or a mixed layer of metal and silicon oxide on the substrate.
  • the step of ion-implanting the exposed active layer portion to form a pattern of the first contact layer and the second contact layer comprises: performing plasma treatment of hydrogen on the exposed active layer portion to A pattern of the first contact layer and the second contact layer is formed.
  • the method may further include: forming a pixel electrode connected to the drain on the protective layer after forming the protective layer.
  • FIG. 1 is a schematic view of a top gate type TFT structure in the prior art
  • FIG. 2 is a schematic view of a TFT structure in accordance with an embodiment of the present invention.
  • FIG. 3 is a schematic view showing the structure of the TFT shown in FIG. 2 having a protective layer and a pixel electrode;
  • FIG. 4 is a schematic view showing the structure of the array substrate according to an example of the present invention.
  • FIG. 5 is a schematic flow chart of a TFT manufacturing method according to an embodiment of the present invention.
  • FIG. 6 is a schematic view showing a halftone or gray tone mask structure according to an embodiment of the present invention
  • FIG. 7 is a schematic plan view of the TFT shown in FIG. 6;
  • FIG. 9 is a schematic view showing a structure in which the TFT shown in FIG. 8 is formed with an active layer on an active layer and a corresponding region of the first contact layer and the second contact layer;
  • FIG. 10 is a schematic structural view of the TFT shown in FIG. 9 with a first contact layer and a second contact layer;
  • FIG. 11 is a schematic structural view of the TFT shown in FIG. 10 with an etch stop layer;
  • Figure 12 is a top plan view of the TFT shown in Figure 11;
  • Fig. 13 is a structural schematic view showing the formation of a source, a drain and a gate of the TFT shown in Fig. 11. detailed description
  • Embodiments of the present invention provide a thin film transistor (TFT), a method of fabricating the same, an array substrate, and a display device.
  • TFT thin film transistor
  • the provided TFT structure is simple and has better performance.
  • the embodiment of the present invention can make the source, the drain and the gate of the TFT in the same layer, thereby squeezing the TFT structure; in addition, since the process of fabricating the TFT adopts the 5Mask process, a total of 5 masks are used. Therefore, the TFT fabrication process is completed. In addition, since the first contact layer connected to the source and the second contact layer connected to the drain are disposed on the active layer, the generation of the non-channel high resistance region can be avoided, and the gate and the source can be avoided. The formation of parasitic capacitance between the gate and the drain ensures good electrical performance of the TFT.
  • the TFT provided by the embodiment of the present invention will be described in detail below with reference to the accompanying drawings.
  • the TFT 2 shows a TFT according to an embodiment of the present invention, comprising: a substrate 1; an active layer 2 formed on the substrate 1; a first contact layer 3 and a conductive layer formed on the active layer 2 Two contact layers 4; an etch stop layer 5 covering the entire substrate over the first contact layer 3 and the second contact layer 4; a source 6, a drain 7, and a gate 8 formed on the etch barrier layer 5.
  • the source 6 and the first contact layer 3 are connected by via holes on the etch barrier layer 5; the drain electrode 7 and the second contact layer 4 are connected by via holes on the etch barrier layer 5.
  • the active layer 2 is a metal oxide semiconductor layer.
  • the substrate 1 may be a glass substrate, a quartz substrate, a plastic substrate or the like.
  • the source 6, the drain 7, and the gate 8 are located in the same layer, thereby constituting the structure of the TFT.
  • the first contact layer 3 is located between the source 6 and the active layer 2, and is in contact with the source 6 and the active layer 2 at the same time; the second contact layer 4 is located at the drain 7 and the active layer Between 2 and at the same time, the drain 7 and the active layer 2 are in contact.
  • the first contact layer 3 and the second contact layer 4 may function as an ohmic contact layer, which may reduce contact resistance between the source 6 and the active layer 2, and improve contact characteristics between the active layer 2 and the source 6.
  • the second contact layer 4 can reduce the contact resistance between the drain electrode 7 and the active layer 2, can improve the contact characteristics between the active layer 2 and the drain electrode 7, and improve the performance of the TFT.
  • first contact layer 3 and the second contact layer 4 are located under the gate 8, which can avoid the formation of the non-channel high resistance region and avoid the formation of parasitic capacitance between the gate and the source or between the gate and the drain. , further improving the performance of the TFT.
  • the first contact layer 3 may be directly under the source 6, the second contact layer 4 may be directly under the drain 7, and the first contact layer 3 and the second contact layer 4 may be mirror-symmetrical to each other.
  • the first contact layer 3 and the second contact layer 4 may be located directly above the active layer 2.
  • the overlap area of the gate electrode 8 and the first contact layer 3 may be equal to the overlap area of the gate electrode 8 and the second contact layer 4, and the overlap area is not zero.
  • the projected area of the gate 8 and the first contact layer 3 in the vertical direction may be equal to the projected area of the gate 8 and the second contact layer 4 in the vertical direction, whereby the formation of the non-channel high resistance region can be effectively avoided.
  • Embodiments of the present invention can flexibly control the width of the active layer channel by controlling the distance between the first contact layer and the second contact layer (the channel width is the spacing between the first contact layer and the second contact layer) For example, the width of the channel can be reduced as small as possible to improve the performance of the TFT.
  • the minimum spacing between the first contact layer and the second contact layer can control the limit parameters of the mask or the exposure machine as needed, and the limit parameters and the light source and mask used in the corresponding exposure process. Board and other parameters related.
  • the minimum spacing between the first contact layer and the second contact layer can be controlled to be in the range of about 2-3 ⁇ .
  • the TFT shown in Fig. 2 may further include an isolation layer 9 (e.g., a film layer that can isolate light) between the substrate 1 and the active layer 2.
  • the isolation layer 9 can effectively block the light transmitted from the back of the substrate 1, and in particular, effectively block the ultraviolet rays of the active layer 2, thereby further improving the performance of the TFT.
  • the isolation layer 9 may be an aluminum oxide layer ( ⁇ 1 2 0 3 ), an amorphous silicon layer (a-Si) or a combination of a combination of metal and silicon oxide (Metal+Si0 2 ). Wait.
  • the isolation layer 9 generally has a strong adhesion to the substrate 1. Therefore, the isolation layer 9 can also serve as a buffer between the substrate 1 and the active layer 2, that is, as a buffer, and the active layer is improved. 2 Adhesion ability on the substrate 1.
  • the TFT may further include a protective layer 10 covering the entire substrate 1 over the gate 8, the source 6, and the drain 7. If the TFT is used for driving the pixel unit, the TFT for driving the structure (array substrate) may further include a pixel electrode 11 connected to the drain electrode 7 on the protective layer 10, as shown in FIG.
  • the protective layer 10 is provided with a via hole exposing the drain electrode 7, which ensures that the drain electrode 7 is electrically connected to the pixel electrode 11 on the protective layer 10.
  • the active layer may be a metal oxide semiconductor layer, for example, Indium Gallium Zinc Oxide (IGZO), Hafnium Indium Zinc Oxide (HIZO) ), Indium Zinc Oxide (IZO), amorphous indium oxide (a-InZnO), amorphous oxide-doped oxyfluoride (ZnO:F), indium oxide-doped tin oxide (In 2 0 3 :Sn ), amorphous indium oxide doped molybdenum oxide (In 2 0 3 :Mo ), chromium tin oxide (Cd 2 Sn0 4 ), amorphous oxide-doped aluminum oxide ( ⁇ : ⁇ 1), amorphous titanium oxide doped lanthanum oxide (Ti0 2 : Nb ), chromium tin oxide (Cd-Sn-O) or other metal oxides.
  • IGZO Indium Gallium Zinc Oxide
  • HZO Hafnium Indium Zinc Oxide
  • the first contact layer and the second contact layer may be a metal layer or an alloy layer.
  • the source, the drain and the gate may be formed of molybdenum (Mo) or an aluminum-niobium alloy (AlNd) or the like.
  • the etch stop layer may be a silicon oxide layer (SiO x ), a silicon nitride layer (SiN x ), or a silicon oxynitride layer, and may be a single layer or a double layer or a plurality of layers.
  • the protective layer may be a silicon oxide or silicon nitride layer.
  • the pixel electrode may be a transparent metal oxide film layer such as indium tin oxide ITO or indium oxide
  • An embodiment of the present invention further provides an array substrate including the above thin film transistor, for example, as a switching element of each pixel unit.
  • the array substrate in the embodiment of the present invention may be an array substrate in a liquid crystal display panel, or may be an array substrate in an organic light emitting display panel.
  • an array substrate used in an organic light emitting display panel includes a plurality of sub-pixel structures, and each sub-pixel structure may include two TFTs, which are a switching TFT (TO) and a driving TFT ( T1).
  • TFTs which are a switching TFT (TO) and a driving TFT ( T1).
  • the drain of the switch TFT (TO) is connected to the gate of the driving TFT (T1) through a connection line 41; the source of the switching TFT (TO) is connected to the data line 32, and the gate is connected to the gate line 31.
  • the data line 32 is disposed across the gate line 31.
  • the V DD line is disposed in parallel with the gate line 31.
  • the disconnected data line 32 is electrically connected through the connecting line 35.
  • the method for fabricating the TFT provided by the embodiment of the present invention is described in detail below.
  • the method of fabricating the TFT may include the following steps.
  • This step involves the first Mask process made by the TFT.
  • This step involves the third Mask process made by TFT.
  • a pattern including an active layer is formed on a substrate by a plating process and a patterning process, and a set region of the active layer is ion-implanted to form a first contact layer on the active layer and
  • the steps of the pattern of the second contact layer include:
  • Coating a layer of photoresist on the metal oxide semiconductor layer Masking, exposing, and developing the photoresist using a halftone or gray tone mask; forming the active layer pattern by wet etching;
  • the photoresist on the active layer is stripped (removed).
  • the method may further include: forming an isolation layer on the substrate by a process before forming the active layer.
  • the forming the spacer layer may include: forming a layer of an aluminum oxide layer, an amorphous silicon layer, or a combination of a metal and a silicon oxide on the substrate by a plating process.
  • the step of ion-implanting the exposed active layer portion to form a pattern of the first contact layer and the second contact layer comprises: performing plasma treatment of hydrogen on the exposed active layer portion to A pattern of the first contact layer and the second contact layer is formed.
  • the method may further include: forming a pixel electrode connected to the drain on the protective layer by plating and patterning after forming the protective layer. This step involves the fifth Mask process.
  • the patterning or patterning process includes a process of masking, exposing, developing, photolithography, etching, etc. of the pattern.
  • the photoresist used can be a positive or negative photoresist.
  • the coating process can be a process such as chemical vapor deposition, sputtering, or the like.
  • the embodiment of the present invention requires five Mask processes to prepare the TFT, so that compared with the existing process, the process flow can be saved, the possibility of contamination of the TFT can be reduced, and the performance of the TFT can be improved.
  • examples of the method for fabricating an array substrate shown in the embodiment of the present invention include:
  • Step S21 First, a film layer covering the entire substrate is formed by sputtering or thermal evaporation on a transparent glass substrate or a quartz substrate, and the film layer may be an aluminum oxide layer (A1 2 0 3 ), an amorphous silicon layer. (a-Si) or a film layer (Metal+SiO 2 ) deposited by a combination of a metal and a silicon oxide.
  • Step S22 On the basis of step S21, a metal oxide film layer such as IGZO is plated.
  • Step S23 On the basis of the step S22, a layer of photoresist covering the entire substrate is applied, and then the following process is performed.
  • the photoresist is first masked and developed using a half-tone or gray-tone mask.
  • a halftone or gray tone mask is used during the exposure process to completely remove the photoresist layer 14 after the development process.
  • the completely remaining region C of the photoresist layer 14 corresponds to an insulating region between the first contact layer and the second contact layer to be formed, in which the photoresist is substantially completely retained.
  • the completely removed region A of the photoresist layer 14 corresponds to a substrate region other than the active layer pattern in which the photoresist is substantially completely removed.
  • the semi-reserved region B of the photoresist layer 14 corresponds to the region where the first contact layer and the second contact layer are to be formed, wherein the photoresist is substantially partially retained, so that the thickness of the photoresist is lower than that in the completely reserved region. The thickness of the photoresist.
  • the photoresist layer 14 completely removes the photoresist corresponding to the region A and the film layer above the substrate 1 under the photoresist, as shown in FIG.
  • the photoresist layer of the semi-retained region B of the photoresist layer 14 is ashed, the photoresist of the semi-retained region B of the photoresist layer is removed, and the corresponding partial active layer 2 is exposed, and the photoresist layer is simultaneously removed.
  • the photoresist layer in the fully-retained region C is partially retained and still covers the corresponding portion of the active layer 2, as shown in FIG.
  • the adhesive layer completely retains the active layer in the region C without being implanted with ions due to the remaining photoresist, as shown in FIG.
  • the implanted ions may be, for example, H ions, that is, plasma H.
  • the first contact layer 3 and the second contact layer 4 can also be realized by doping the exposed active layer 2.
  • the first contact layer 3 and the second contact layer 4 are a metal or alloy layer in which a metal oxide semiconductor layer (active layer) is subjected to H ions. They have a small contact resistance with the metal oxide semiconductor layer and excellent adhesion to the metal oxide semiconductor layer. Moreover, since the first contact layer 3 and the second contact layer 4 are metal or alloy layers, and the source and the drain are also metal or alloy layers, the first contact layer 3 and the second contact layer 4 can avoid the source and the gate. The formation of parasitic capacitance between the poles can also avoid the formation of parasitic capacitance between the drain and the gate, thereby improving the performance of the TFT.
  • Step S24 forming an insulating layer on the basis of the TFT formed in the step S23 by a plating process, for example, forming a silicon nitride layer or a silicon oxide layer.
  • An etch barrier layer is formed by one mask, exposure development, and dry etching.
  • Figure 11 (cross-sectional view) and Figure 12 (top view) are formed Contact hole), which is located at the source and drain to be formed, and ensures that the first contact layer 3 and the second contact layer 4 are exposed.
  • Step S25 forming a conductive film layer such as a molybdenum (Mo) or an aluminum-niobium alloy (AlNd) layer or the like on the basis of the TFT formed in the step S24 by plating.
  • the source 6, drain 7, and gate 8 as shown in Fig. 13 are formed by a patterning process, for example, by wet etching.
  • the overlapping area of the gate electrode 8 with the first contact layer 3 can be made equal to the overlapping area of the gate electrode 8 and the second contact layer 4.
  • Step S26 forming an insulating layer on the basis of the TFT formed in the step S25 by a coating process, and performing a masking, exposure and development, dry etching, etc. on the insulating layer to form the protective layer 10.
  • a via hole is disposed over the drain layer 7 on the protective layer 10 to ensure that the drain electrode 7 is exposed, as shown in FIG.
  • Step S27 forming a conductive film layer, such as ITO, by a coating process on the basis of the TFT formed in step S26, performing a process including masking, exposure development, dry etching, etc., forming a pattern including the pixel electrode 11, and forming a TFT.
  • a conductive film layer such as ITO
  • a gate line connected to the gate is simultaneously formed when the gate is formed; a data line connected to the source (or the drain) is formed while the source is being formed; one of the gate line or the data line may be a minute
  • the segments are formed.
  • the data lines 32 are formed in segments.
  • the embodiment of the invention further provides a display device, which comprises the above array substrate, and the display device can be a display device such as a liquid crystal panel, a liquid crystal display, a liquid crystal television, an OLED panel, an OLED display, an OLED television or an electronic paper.
  • a display device such as a liquid crystal panel, a liquid crystal display, a liquid crystal television, an OLED panel, an OLED display, an OLED television or an electronic paper.
  • An example of the display device is a liquid crystal display device in which an array substrate and a counter substrate are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, a color filter substrate.
  • the pixel electrode of each pixel unit of the array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display further includes a backlight that provides backlighting for the array substrate.
  • the display device is an organic electroluminescence (OLED) display device, wherein a thin film transistor of each pixel unit of the array substrate is connected to an anode or a cathode of the organic electroluminescence device for driving the organic light-emitting material to emit light for performing Display operation.
  • OLED organic electroluminescence
  • the TFT structure is formed by fabricating the source, the drain, and the gate of the TFT in the same layer.
  • the process of fabricating the TFT uses the 5Mask process, the TFT fabrication process is completed.
  • the active layer is provided with a first contact layer connected to the source and a second contact layer connected to the drain, the non-channel high resistance region is avoided, and the gate and the source are avoided.
  • the formation of parasitic capacitance between the gate and the drain ensures good electrical performance of the TFT.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

一种薄膜晶体管（TFT）及其制作方法、阵列基板和显示装置。该薄膜晶体管包括：基板；形成在所述基板上的有源层；形成在所述有源层上可导电的第一接触层和第二接触层；形成在所述第一接触层和第二接触层上的刻蚀阻挡层；形成在所述刻蚀阻挡层上与所述第一接触层相连的源极、与所述第二接触层相连的漏极，以及位于所述源极和漏极之间的栅极。该TFT结构筒单、性能更佳。

Description

薄膜晶体管及其制作方法、 阵列基板和显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管及其制作方法、 阵列基板和显示装 置。 背景技术
在显示技术领域， 氧化物薄膜晶体管 （Thin Film Transistor, TFT )相比 较非晶硅 TFT,因其具有较高的载流子迁移率（载流子迁移率约为非晶硅 TFT 的十倍）， 以及较高的热学、化学稳定性， 成为人们的研究热点。 使用氧化物 TFT驱动的显示装置， 能满足大尺寸、 高分辨率显示器件的要求， 特别是能 够满足下一代有源矩阵式有机发光显示器件 （Active Matrix Organic Light Emitting Device , AMOLED )的要求， 因此在平板显示领域占据重要的位置。
目前， 对于制作氧化物 TFT 的要求较高， 因此在保证制作出高性能的 氧化物 TFT的前提下， 筒化器件结构和工艺流程是人们一直追求的目标。 现 有氧化物 TFT—般采用顶栅型。 图 1 示出了一种现有的采用顶栅型氧化物 TFT的像素电极驱动结构， 其包括： 基板 101、 基板 101上的有源层 102、 有源层 102上的栅极绝缘层 103、 栅极绝缘层 103上的栅极 104、 栅极 104 上的刻蚀阻挡层 105、刻蚀阻挡层 105上的源漏极层 106 (包括源极和漏极）、 源漏极层 106上的钝化保护层 107, 以及钝化保护层 107上与源漏极层 106 中的漏极相连的像素电极 108。
制作图 1所示的顶栅型 TFT采用如下 6Mask工艺， 构图工艺一般至少 包括掩膜、 曝光、 显影、 光刻和刻蚀过程， 每次曝光工艺使用与将要形成的 图形相对应的掩模 ( Mask )进行曝光。
第一、 通过第一次构图工艺形成有源层 102图形；
第二、 通过第二次构图工艺形成栅极绝缘层 103和栅极 104图形， 在此 过程中， 首先通过湿法刻蚀形成栅极 104图形， 然后通过干法刻蚀形成栅极 绝缘层 103图形。
第三、 通过第三次构图工艺形成刻蚀阻挡层 105图形。
第四、 通过第四次构图工艺形成源漏极层 106图形。 第五、 通过第五次构图工艺形成钝化保护层 107图形， 其中钝化保护层 107上形成有接触孔， 该接触孔用于连接漏极和之后形成的像素电极 108。
第六、 通过第六次构图工艺形成像素电极图形 108。
因此， 现有的 TFT结构复杂， 而且由于制作高性能氧化物 TFT采用的 是 6Mask工艺， 因此工艺流程较复杂。 此外， 由于每增加一次构图工艺都可 能会引起氧化物 TFT的各功能膜层受到污染， 因此， 此种方法降低了氧化物 TFT的性能。 发明内容
本发明的实施例提供一种薄膜晶体管及其制作方法、 阵列基板和显示装 置， 以提供一种结构筒单、 性能较佳的 TFT。
根据本发明的一个方面， 提供一种薄膜晶体管， 其包括： 基板； 形成在 所述基板上的有源层； 形成在所述有源层上的可导电的第一接触层和第二接 触层； 形成在所述第一接触层和第二接触层上的刻蚀阻挡层； 形成在所述刻 蚀阻挡层上与所述第一接触层相连的源极、 与所述第二接触层相连的漏极， 以及位于所述源极和漏极之间的栅极。
根据本发明的一个实施例， 所述第一接触层和第二接触层镜像对称设置。 根据本发明的一个实施例， 所述栅极与所述第一接触层在垂直方向的投 影面积等于所述栅极与所述第二接触层在垂直方向的投影面积。
根据本发明的一个实施例， 所述第一接触层和第二接触层之间的距离为
2-3 μ m。
根据本发明的一个实施例， 该薄膜晶体管还包括位于所述有源层和所述 基板之间用于隔离光线的隔离层。
根据本发明的一个实施例， 该薄膜晶体管还包括位于所述保护层上的像 素电极， 所述像素电极通过保护层上的过孔与位于所述保护层下方的漏极电 性相连。
根据本发明的另一个方面， 提供一种阵列基板， 其包括上述薄膜晶体管。 根据本发明的另一个方面， 提供一种显示装置， 包括上述阵列基板。 根据本发明的又另一个方面， 提供一种薄膜晶体管的制作方法， 其包括： 在基板上形成包括有源层的图形；
对所述有源层的设定区域进行离子注入以形成有源层上的第一接触层和 第二接触层的图形；
在形成有所述第一接触层和第二接触层的基板上形成包括刻蚀阻挡层的 图形；
在所述刻蚀阻挡层上形成与所述第一接触层相连的源极图形， 与所述第 二接触层相连的漏极图形， 以及位于所述源极和漏极之间的栅极图形；
在形成有所述栅极、 源极和漏极的基板上形成覆盖整个基板的保护层图 形。
根据本发明的一个实施例， 在基板上形成包括有源层的图形， 对所述有 源层的设定区域进行离子注入以形成有源层上的第一接触层和第二接触层的 图形的步骤包括：
在所述基板上形成一层金属氧化物半导体层；
在所述金属氧化物半导体层上涂覆一层光刻胶；
采用半色调或灰色调掩模板对所述光刻胶进行掩膜、 曝光和显影； 采用湿法刻蚀形成所述有源层图形；
对有源层上保留的光刻胶进行灰化处理， 露出与待形成的第一接触层和 第二接触层对应区域的有源层；
对露出的有源层部分进行离子注入以形成所述第一接触层和第二接触层 的图形；
剥离有源层上的光刻胶。
根据本发明的一个实施例， 所述方法还可以包括： 在形成所述有源层之 前， 在所述基板上形成一层可隔离光线的隔离层。
根据本发明的一个实施例， 形成所述隔离层的步骤包括： 在所述基板上 形成一层氧化铝层、 非晶硅层或者金属和氧化硅的混合层。
根据本发明的一个实施例， 对露出的有源层部分进行离子注入以形成所 述第一接触层和第二接触层的图形的步骤包括： 对露出的有源层部分进行氢 的等离子处理以形成所述第一接触层和第二接触层的图形。
根据本发明的一个实施例， 所述方法还可以包括： 在形成所述保护层之 后， 在所述保护层上形成与所述漏极相连的像素电极。 附图说明
以下将结合附图对本发明的实施例进行更详细的说明， 以使本领域普通 技术人员更加清楚地理解本发明， 其中：
图 1为现有技术中顶栅型 TFT结构的示意图；
图 2为根据本发明的实施例的 TFT结构的示意图；
图 3为图 2所示的 TFT具有保护层和像素电极的结构的示意图； 图 4为根据本发明的实例施的阵列基板结构的示意图；
图 5为根据本发明的实施例的 TFT制作方法流程示意图；
图 6为根据本发明的实施例的半色调或灰色调掩模板结构的示意图； 图 7为图 6所示的 TFT俯视示意图； 结构的示意图；
图 9为图 8所示的 TFT形成有有源层上与第一接触层和第二接触层相应 区域露出有源层的结构的示意图；
图 10为图 9所示的 TFT形成有第一接触层和第二接触层的结构示意图； 图 11为图 10所示的 TFT形成有刻蚀阻挡层的结构示意图；
图 12为图 11所示的 TFT俯视示意图；
图 13为图 11所示的 TFT形成有源极、 漏极和栅极的结构示意图。 具体实施方式
为使本发明的实施例的目的、 技术方案和优点更加清楚， 下面将结合本 发明实施例的附图对本发明的实施例的技术方案进行清楚、 完整的描述。 显 然， 所描述的实施例仅是本发明的一部分示例性实施例， 而不是全部的实施 例。 基于所描述的本发明的示例性实施例， 本领域普通技术人员在无需创造 性劳动的前提下所获得的所有其它实施例都属于本发明的保护范围。
本发明的实施例提供了一种薄膜晶体管（TFT )及其制作方法、 阵列基板 和显示装置。 所提供的 TFT结构筒单、 性能较佳。
本发明的实施例可以将 TFT的源极、 漏极和栅极制作在同一层， 由此筒 化了 TFT结构； 此外， 由于制作 TFT的过程采用 5Mask工艺， 即共使用了 5 道掩模， 所以筒化了 TFT制作工艺。 另外， 由于在有源层上设置有与源极相 连的第一接触层和与漏极相连的第二接触层， 可以避免非沟道高阻区的产生， 而且可以避免栅极与源极或栅极与漏极之间寄生电容的形成， 从而保证了 TFT良好的电学性能。 下面通过结合附图详细说明本发明的实施例提供的 TFT。
图 2示出了本发明一个实施例提供的一种 TFT, 其包括： 基板 1; 形成在 基板 1上的有源层 2;形成在有源层 2上可导电的第一接触层 3和第二接触层 4; 形成在第一接触层 3和第二接触层 4上方覆盖整个基板的刻蚀阻挡层 5； 形成在刻蚀阻挡层 5上的源极 6、 漏极 7以及栅极 8。 源极 6与第一接触层 3 通过刻蚀阻挡层 5上的过孔连接； 漏极 7与第二接触层 4通过刻蚀阻挡层 5 上的过孔连接。 有源层 2为金属氧化物半导体层。 基板 1可以为玻璃基板、 石英基板或塑料基板等。
根据本发明实施例提供的 TFT, 源极 6、 漏极 7和栅极 8位于同一层， 由 此筒化了 TFT的结构。
如图 2所示， 第一接触层 3位于源极 6和有源层 2之间，且同时与源极 6 和有源层 2相接触； 第二接触层 4位于漏极 7和有源层 2之间， 且同时与漏 极 7和有源层 2相接触。 第一接触层 3和第二接触层 4可以起到欧姆接触层 的功能，可以降低源极 6与有源层 2之间的接触电阻， 改善有源层 2和源极 6 之间的接触特性； 同理， 第二接触层 4可以降低漏极 7与有源层 2之间的接 触电阻， 可以改善有源层 2和漏极 7之间的接触特性， 提高 TFT的性能。
另外， 第一接触层 3和第二接触层 4位于栅极 8的下方， 可以避免非沟 道高阻区的形成， 且避免栅极与源极或栅极与漏极之间寄生电容的形成， 进 一步提高了 TFT的性能。
例如， 参见图 2, 第一接触层 3可以位于源极 6的正下方， 第二接触层 4 可以位于漏极 7的正下方， 第一接触层 3和第二接触层 4可以彼此镜像对称 设置， 第一接触层 3和第二接触层 4可以位于有源层 2的正上方。
例如，栅极 8与第一接触层 3的交叠面积可以等于栅极 8与第二接触层 4 的交叠面积， 且交叠面积不为零。
例如， 栅极 8与第一接触层 3在垂直方向的投影面积可以等于栅极 8与 第二接触层 4在垂直方向的投影面积， 由此可有效避免非沟道高阻区的形成。
本发明的实施例通过控制第一接触层和第二接触层之间的距离， 可以灵 活控制有源层沟道的宽度（沟道宽度为第一接触层和第二接触层之间的间 距）， 例如， 可以尽可能小地减小沟道的宽度， 提高 TFT的性能。
例如， 第一接触层和第二接触层之间最小间距根据需要可以控制在掩模 板或曝光机的极限参数， 该极限参数与相应的曝光工艺中采用的光源、 掩模 板等参数有关。 例如， 所述第一接触层和第二接触层之间的最小间距可以控 制在约 2-3 μ ηι的范围内。
根据本发明的一个实施例， 参见图 3 , 图 2所示的 TFT还可以包括位于 基板 1和有源层 2之间的隔离层 9 (例如， 可隔离光线的膜层）。 隔离层 9可 以有效遮挡从基板 1背部透射来的光线， 尤其是有效遮挡有源层 2较敏感的 紫外线， 进一步提高 TFT的性能。
根据本发明的一个实施例， 隔离层 9可以为氧化铝层（Α1203 )、 非晶硅 层（a-Si )或金属和氧化硅组合沉积而成的膜层（Metal+Si02 )等。 隔离层 9 通常与基板 1的附着力较强， 因此， 隔离层 9还可以起到基板 1与有源层 2 之间的緩沖作用， 即起到緩沖层（buffer ) 的作用， 提高有源层 2在基板 1上 的附着能力。
根据本发明的一个实施例， 参见图 3 , TFT还可以包括位于栅极 8、 源极 6、 漏极 7上方覆盖整个基板 1的保护层 10。 如果该 TFT用于像素单元的驱 动， 则用于驱动结构（阵列基板）的 TFT还可以包括位于保护层 10上与漏极 7相连的像素电极 11 , 如图 3所示。
保护层 10上设置有露出漏极 7的过孔， 保证漏极 7与保护层 10上的像 素电极 11电性相连。
根据本发明的一个实施例， 所述有源层可以是金属氧化物半导体层， 例 如可以是铟镓辞氧化物（Indium Gallium Zinc Oxide, IGZO )、 铪铟辞氧化物 ( Hafnium Indium Zinc Oxide , HIZO )、铟辞氧 4匕物（ Indium Zinc Oxide , IZO )、 非晶铟辞氧化物（a-InZnO )、 非晶氧化辞掺杂氟氧化物 （ZnO:F )、 氧化铟掺 杂锡氧化物（In203:Sn )、 非晶氧化铟掺杂钼氧化物（In203:Mo )、 铬锡氧化物 ( Cd2Sn04 )、 非晶氧化辞掺杂铝氧化物（ΖηΟ:Α1 )、 非晶氧化钛掺杂铌氧化物 ( Ti02:Nb )、 铬锡氧化物（Cd-Sn-O )或其他金属氧化物等。
第一接触层和第二接触层可以为金属层或合金层。
源极、 漏极和栅极可以由钼 （Mo )或铝钕合金 (AlNd)等形成。
刻蚀阻挡层可以为氧化硅层（SiOx )、 氮化硅层（SiNx ), 或氮氧化硅层， 可以是单层也可以是双层或多层。
保护层（PVX层）可以是氧化硅或氮化硅层。
像素电极可以为透明金属氧化物膜层， 如铟锡氧化物 ITO或铟辞氧化物
IZO膜层。 本发明实施例还提供一种阵列基板， 包括上述薄膜晶体管， 该薄膜晶体 管例如作为每个像素单元的开关元件。
本发明实施例所述的阵列基板可以是液晶显示面板中的阵列基板， 也可 以是有机发光显示面板中的阵列基板。
例如， 参见图 4, 其为一种用于有机发光显示面板中的阵列基板， 包括多 个亚像素结构， 每一个亚像素结构可以包括两个 TFT, 分别为开关 TFT ( TO ) 和驱动 TFT ( T1 )。
开关 TFT ( TO )的漏极通过连接线 41与驱动 TFT ( T1 )的栅极相连； 开 关 TFT ( TO ) 的源极与数据线 32相连， 栅极与栅线 31相连。
驱动 TFT ( T1 ) 的源极与 VDD线相连， 该 VDD线用于为驱动 TFT ( T1 ) 提供正常工作时的供电电压， 驱动 TFT ( Tl ) 的漏极与像素电极 11相连。
数据线 32与栅线 31交叉设置。 VDD线与栅线 31平行设置。
断开的数据线 32通过连接线 35电性连接。
下面详细说明本发明实施例提供的上述 TFT的制作方法。 例如， 参见图 5, TFT的制作方法可以包括以下步骤。
sii、 通过! ¾ 工艺和构图工艺在基板上形成包括有源层的图形， 对所述 有源层的设定区域进行离子注入形成有源层上的第一接触层和第二接触层的 图形。 该步骤涉及 TFT制作的第一次 Mask工艺。
512、通过镀膜工艺和构图工艺在形成有所述第一接触层和第二接触层的 基板上形成包括刻蚀阻挡层的图形。 该步骤涉及 TFT制作的第二次 Mask工 艺
513、通过镀膜工艺和构图工艺在所述刻蚀阻挡层上形成与所述第一接触 层相连的源极图形， 与所述第二接触层相连的漏极图形， 以及位于所述源极 和漏极之间的栅极图形。 该步骤涉及 TFT制作的第三次 Mask工艺。
S14、 通过镀膜工艺和构图工艺在形成有所述栅极、 源极和漏极的基板上 形成覆盖整个基板的保护层图形。 该步骤涉及 TFT制作的第四次 Mask工艺。
根据本发明的一个实施例， 通过镀膜工艺和构图工艺在基板上形成包括 有源层的图形， 对所述有源层的设定区域进行离子注入以形成有源层上的第 一接触层和第二接触层的图形的步骤包括：
通过镀膜工艺在所述基板上形成一层金属氧化物半导体层；
在所述金属氧化物半导体层上涂覆一层光刻胶； 采用半色调或灰色调掩模板对所述光刻胶进行掩膜、 曝光和显影； 采用湿法刻蚀形成所述有源层图形；
对有源层上保留的光刻胶进行灰化处理， 露出与待形成的第一接触层和 第二接触层对应区域的有源层；
对露出的有源层部分进行离子注入以形成所述第一接触层和第二接触层 的图形；
剥离 （去除）有源层上的光刻胶。
根据本发明的一个实施例， 所述方法还可以包括： 在形成有源层之前， 通过! ¾莫工艺在所述基板上形成一层隔离层。
根据本发明的一个实施例， 形成所述隔离层的步骤可以包括： 通过镀膜 工艺在所述基板上形成一层氧化铝层、 非晶硅层或者金属和氧化硅组合形成 的膜层。
根据本发明的一个实施例， 对露出的有源层部分进行离子注入以形成所 述第一接触层和第二接触层的图形的步骤包括： 对露出的有源层部分进行氢 的等离子处理以形成所述第一接触层和第二接触层的图形。
根据本发明的一个实施例， 所述方法还可以包括： 在形成所述保护层之 后， 通过镀膜和构图在所述保护层上形成与所述漏极相连的像素电极。 该步 骤涉及第五次 Mask工艺。
这里， 所述构图或构图工艺包括制作图形的掩膜、 曝光、 显影、 光刻、 刻蚀等过程。 所使用的光刻胶可以为正性或负性光刻胶。 镀膜工艺可以为化 学气相沉积、 溅射等工艺。
本发明的实施例制备 TFT需要五次 Mask工艺， 因此与现有的工艺相比， 可以节约工艺流程， 降低 TFT被污染的可能性， 提高了 TFT的性能。
下面详细说明图 5所示的 TFT制作方法的示例的工艺流程。 例如， 本发 明实施例所示的阵列基板制作方法的示例包括：
步骤 S21: 首先在透明玻璃基板或者石英基板上采用溅射或热蒸发的方 法， 形成一层覆盖整个基板的膜层， 该膜层可以为氧化铝层（A1203 )、 非晶 硅层 ( a-Si )或金属和氧化硅组合沉积而成的膜层（Metal+Si02 )等。
步骤 S22: 在步骤 S21的基础上， 镀一层金属氧化物膜层如 IGZO。
步骤 S23: 在步骤 S22的基础上， 涂覆一层覆盖整个基板的光刻胶， 然 后进行如下工艺。 首先利用半色调（half-tone )或灰色调（Gray-tone )掩模板对所述光刻胶 进行掩膜、 曝光显影。
例如， 如图 6所示 （截面图）和图 7所示（俯视图 ), 在曝光的过程中， 采用半色调或者灰色调的掩模板， 通过显影工艺后产生光刻胶层 14上的完全 去除区域 A、 光刻胶半保留区域 B及光刻胶完全保留区域 C。 光刻胶层 14的 完全保留区域 C对应待形成的第一接触层和第二接触层之间的绝缘区域， 其 中的光刻胶被基本上完全保留。光刻胶层 14的完全去除区域 A对应有源层图 形之外的基板区域， 其中的光刻胶被基本上完全去除。 光刻胶层 14的半保留 区域 B对应待形成的第一接触层和第二接触层所在区域， 其中的光刻胶被基 本上被部分保留， 从而光刻胶的厚度低于完全保留区域中的光刻胶的厚度。
接着， 经过一次湿法刻蚀工艺，将光刻胶层 14完全去除区域 A对应的光 刻胶和位于光刻胶下方基板 1上方的膜层刻蚀掉， 如图 8所示。
然后， 对光刻胶层 14半保留区域 B的光刻胶层进行灰化处理， 去除光刻 胶层半保留区域 B的光刻胶， 露出对应的部分有源层 2, 同时光刻胶层完全 保留区域 C中的光刻胶层被部分保留， 仍然覆盖对应的部分有源层 2, 如图 9 所示。
接下来对露出的有源层 2部分的表层进行离子注入， 注入离子的有源层 部分的表层形成分别位于完全保留区域 C两侧的第一接触层 3和第二接触层 4,而光刻胶层完全保留区域 C中的有源层由于保留的光刻胶而没有被注入离 子， 如图 10所示。 注入的离子例如可以是 H离子， 即等离子体 H。 也可以通 过对露出的有源层 2进行掺杂， 实现第一接触层 3和第二接触层 4。
该第一接触层 3和第二接触层 4为金属氧化物半导体层（有源层）经 H 离子作用后的金属或合金层。 它们与金属氧化物半导体层的接触电阻较小， 且与金属氧化物半导体层的附着性非常好。 并且， 由于第一接触层 3和第二 接触层 4为金属或合金层， 源极和漏极也为金属或者合金层， 所以第一接触 层 3和第二接触层 4可以避免源极与栅极之间寄生电容的形成， 也可以避免 漏极与栅极之间寄生电容的形成， 从而可以提高 TFT的性能。
最后， 对完全保留区域 C的光刻胶层 14进行剥离。
步骤 S24: 通过镀膜工艺在步骤 S23形成的 TFT的基础上形成一层绝缘 层， 例如形成一层氮化硅层或氧化硅层。 通过一次掩膜、 曝光显影， 干法刻 蚀， 形成刻蚀阻挡层。 图 11所示 （截面图）和图 12所示（俯视图）为形成 接触孔）， 该过孔 34位于待形成的源极和漏极处， 且保证第一接触层 3和第 二接触层 4露出。
步骤 S25:通过镀膜在步骤 S24形成的 TFT的基础上形成一层导电膜层， 例如钼 （Mo )或铝钕合金 (AlNd)层等。 通过一次构图工艺， 例如采用湿法刻 蚀， 形成如图 13所示的源极 6、 漏极 7, 以及栅极 8。 例如， 可以使得栅极 8 与第一接触层 3的交叠面积等于栅极 8与第二接触层 4的交叠面积。
步骤 S26: 通过镀膜工艺在步骤 S25形成的 TFT的基础上形成一层绝缘 层， 对该绝缘层进行掩膜、 曝光显影， 干法刻蚀等工艺， 形成保护层 10。 保 护层 10上位于漏极 7上方设置有过孔， 保证漏极 7露出， 如图 3所示。
步骤 S27: 通过镀膜工艺在步骤 S26形成的 TFT的基础上形成一层导电 膜层， 如 ITO, 经过掩膜、 曝光显影， 干法刻蚀等工艺， 形成包括像素电极 11的图形， 形成的 TFT如图 3所示。
需要说明的是， 在制作栅极时同时制作与栅极连接的栅线； 在制作源极 的同时制作与源极（或漏极）相连的数据线； 栅线或数据线之一可以是分段 形成的， 如图 4所示的示例中， 数据线 32分段形成。 根据需要在制备像素电 极时， 同时制备连接分段的栅线或数据线的连接线， 例如图 4所示的示例中 的连接线 35。
需要说明的是， 上述制作 TFT的步骤适用于液晶显示领域， 也适用于有 机发光显示技术领域。
本发明实施例还提供一种显示装置， 其包括上述阵列基板， 该显示装置 可以为液晶面板、液晶显示器、液晶电视、 OLED面板、 OLED显示器、 OLED 电视或电子纸等显示装置。
所述显示装置的一个示例为液晶显示装置，其中阵列基板与对置基板 彼此对置以形成液晶盒， 在液晶盒中填充有液晶材料。 该对置基板例如为 彩膜基板。 阵列基板的每个像素单元的像素电极用于施加电场对液晶材料 的旋转的程度进行控制从而进行显示操作。 在一些示例中， 该液晶显示器 还包括为阵列基板提供背光的背光源。
该显示装置的另一个示例为有机电致发光（ OLED )显示装置，其中， 阵列基板的每个像素单元的薄膜晶体管连接有机电致发光装置的阳极或阴 极， 用于驱动有机发光材料发光以进行显示操作。 综上所述，本发明实施例通过将 TFT的源极、漏极和栅极制作在同一层， 筒化了 TFT结构。 而且， 由于制作 TFT的过程采用 5Mask工艺， 筒化了 TFT 制作工艺。 此外， 由于有源层上设置有与源极相连的第一接触层， 和与漏极 相连的第二接触层， 从而避免非沟道高阻区的产生， 而且可以避免栅极与源 极或栅极与漏极之间寄生电容的形成， 保证了 TFT良好的电学性能。 发明的精神和范围。 本发明也意图包含属于本发明权利要求范围之内的这些 修改和变形及其任何等同物。

Claims

权利要求书
1、 一种薄膜晶体管， 包括：
基板；
形成在所述基板上的有源层；
形成在所述有源层上可导电的第一接触层和第二接触层；
形成在所述第一接触层和第二接触层上的刻蚀阻挡层； 以及
形成在所述刻蚀阻挡层上与所述第一接触层相连的源极、 与所述第二接 触层相连的漏极， 以及位于所述源极和漏极之间的栅极。
2、 根据权利要求 1所述的薄膜晶体管， 其中所述第一接触层和第二接触 层镜像对称设置。
3、 根据权利要求 1或 2所述的薄膜晶体管， 其中所述栅极与所述第一接 触层在垂直方向的投影面积等于所述栅极与所述第二接触层在垂直方向的投 影面积。
4、 根据权利要求 1-3任一所述的薄膜晶体管， 其中所述第一接触层和第 二接触层之间的距离为 2-3 μ ηι。
5、 根据权利要求 1-4任一所述的薄膜晶体管， 还包括： 位于所述有源层 和所述基板之间的隔离层。
6、 根据权利要求 5所述的薄膜晶体管， 其中所述隔离层为隔离光线层。
7、 根据权利要求 5所述的薄膜晶体管， 其中所述隔离层为緩沖层。
8、根据权利要求 1-7任一所述的薄膜晶体管，还包括： 形成在所述源极、 漏极和栅极上的保护层。
9、 根据权利要求 8所述的薄膜晶体管， 还包括： 位于所述保护层上的像 素电极， 其中所述像素电极通过保护层上的过孔与位于所述保护层下方的漏 极电性相连。
10、 一种阵列基板， 包括权利要求 1~9任一所述的薄膜晶体管。
11、 一种显示装置， 包括权利要求 10所述的阵列基板。
12、 一种薄膜晶体管的制作方法， 包括：
在基板上形成包括有源层的图形，
对所述有源层的设定区域进行离子注入以形成有源层上的第一接触层和 第二接触层的图形； 在形成有所述第一接触层和第二接触层的基板上形成包括刻蚀阻挡层的 图形；
在所述刻蚀阻挡层上形成与所述第一接触层相连的源极图形， 与所述第 二接触层相连的漏极图形， 以及位于所述源极和漏极之间的栅极图形；
在形成有所述栅极、 源极和漏极的基板上形成覆盖整个基板的保护层图 形。
13、 根据权利要求 12所述的方法， 其中， 在基板上形成包括有源层的图 形， 对所述有源层的设定区域进行离子注入以形成有源层上的第一接触层和 第二接触层的图形的步骤包括：
在所述基板上形成一层金属氧化物半导体层；
在所述金属氧化物半导体层上涂覆一层光刻胶；
采用半色调或灰色调掩模板对所述光刻胶进行掩膜、 曝光和显影； 采用湿法刻蚀形成所述有源层图形；
对有源层上保留的光刻胶进行灰化处理， 露出与待形成的第一接触层和 第二接触层对应区域的有源层；
对露出的有源层部分进行离子注入以形成所述第一接触层和第二接触层 的图形；
剥离所述有源层上的光刻胶。
14、 根据权利要求 13 所述的方法， 其中， 所述对露出的有源层部分进 行离子注入以形成所述第一接触层和第二接触层的图形包括： 对露出的有源 层部分进行氢的等离子处理以形成所述第一接触层和第二接触层的图形。
15、根据权利要求 12-14任一所述的方法，还包括： 在形成所述有源层之 前， 在所述基板上形成一层隔离层。
16、 根据权利要求 15所述的方法， 其中， 形成所述隔离层包括： 在所述 基板上形成一层氧化铝层、 非晶硅层或者金属和氧化硅组合形成的膜层。
17、 根据权利要求 12-16任一所述的方法， 还包括： 在形成所述保护层 之后， 在所述保护层上形成与所述漏极相连的像素电极。
PCT/CN2013/079346 2013-04-07 2013-07-15 薄膜晶体管及其制作方法、阵列基板和显示装置 WO2014166176A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/348,763 US9368637B2 (en) 2013-04-07 2013-07-15 Thin film transistor and manufacturing method thereof, array substrate and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310117218.0 2013-04-07
CN201310117218.0A CN103219391B (zh) 2013-04-07 2013-04-07 一种薄膜晶体管及其制作方法、阵列基板和显示装置

Publications (1)

Publication Number Publication Date
WO2014166176A1 true WO2014166176A1 (zh) 2014-10-16

Family

ID=48817013

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/079346 WO2014166176A1 (zh) 2013-04-07 2013-07-15 薄膜晶体管及其制作方法、阵列基板和显示装置

Country Status (3)

Country Link
US (1) US9368637B2 (zh)
CN (1) CN103219391B (zh)
WO (1) WO2014166176A1 (zh)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103456795A (zh) * 2013-09-02 2013-12-18 合肥京东方光电科技有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置
CN103762245B (zh) * 2013-12-13 2019-08-16 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制备方法、显示装置
JP6537341B2 (ja) * 2014-05-07 2019-07-03 株式会社半導体エネルギー研究所 半導体装置
CN104103584A (zh) * 2014-06-25 2014-10-15 京东方科技集团股份有限公司 阵列基板制作方法
CN104091832B (zh) 2014-06-27 2018-07-17 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置
CN104241392B (zh) * 2014-07-14 2017-07-14 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、显示基板和显示设备
CN104253159B (zh) * 2014-08-19 2017-06-13 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法和显示装置
CN104362180B (zh) * 2014-10-15 2017-02-22 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、显示基板和显示装置
CN104867942B (zh) * 2015-04-29 2018-03-06 深圳市华星光电技术有限公司 Tft基板的制作方法及其结构
CN105226015B (zh) * 2015-09-28 2018-03-13 深圳市华星光电技术有限公司 一种tft阵列基板及其制作方法
CN105206626B (zh) 2015-11-09 2018-11-20 深圳市华星光电技术有限公司 阵列基板及其制备方法、显示装置
CN105845694A (zh) * 2016-03-28 2016-08-10 深圳市华星光电技术有限公司 薄膜晶体管、薄膜晶体管的制备方法及液晶显示面板
CN106024804A (zh) * 2016-05-31 2016-10-12 武汉华星光电技术有限公司 阵列基板、显示器及阵列基板的制备方法
CN106952827A (zh) * 2017-03-16 2017-07-14 深圳市华星光电技术有限公司 薄膜晶体管及其制造方法、显示面板
US10205028B2 (en) 2017-03-16 2019-02-12 Shenzhen China Star Optoelectroncis Semiconductor Display Technology Co., Ltd Thin-film transistor, manufacturing method for the same, display panel
CN108878515B (zh) 2017-05-12 2022-02-25 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板
CN107452808B (zh) * 2017-07-04 2021-10-22 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示装置
CN107342260B (zh) * 2017-08-31 2020-08-25 京东方科技集团股份有限公司 一种低温多晶硅tft阵列基板制备方法及阵列基板
CN109585298A (zh) 2018-10-22 2019-04-05 惠科股份有限公司 一种显示面板的制作方法和显示面板
CN109585297A (zh) * 2018-10-22 2019-04-05 惠科股份有限公司 一种显示面板的制作方法和显示面板
CN110211925B (zh) * 2019-04-04 2021-07-06 Tcl华星光电技术有限公司 顶发光型氧化铟镓锌薄膜晶体管器件制造方法
CN110010701B (zh) * 2019-06-04 2019-09-17 成都京东方光电科技有限公司 薄膜晶体管和制作方法、阵列基板、显示面板、显示装置
CN110444567B (zh) * 2019-07-26 2021-09-24 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制作方法
CN111243548B (zh) * 2020-03-23 2021-10-08 武汉华星光电技术有限公司 阵列基板、液晶显示面板及其公共电压的调节方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201121055A (en) * 2009-10-12 2011-06-16 Samsung Mobile Display Co Ltd Thin film transistor, method of manufacturing the thin film transistor and organic light emitting display device having the thin film transistor
CN102184865A (zh) * 2011-04-15 2011-09-14 福州华映视讯有限公司 薄膜晶体管及其制造方法
CN102208452A (zh) * 2010-03-30 2011-10-05 索尼公司 薄膜晶体管及其制造方法、以及显示装置
WO2012044344A1 (en) * 2010-09-29 2012-04-05 Guardian Industries Corp. Method of making oxide thin film transistor array, and device incorporating the same
CN102646715A (zh) * 2011-12-29 2012-08-22 京东方科技集团股份有限公司 薄膜晶体管及其制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6646287B1 (en) * 1999-11-19 2003-11-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with tapered gate and insulating film
JP4439766B2 (ja) * 2001-08-02 2010-03-24 シャープ株式会社 薄膜トランジスタ装置及びその製造方法
WO2010058532A1 (ja) * 2008-11-20 2010-05-27 シャープ株式会社 半導体装置およびその製造方法、ならびに半導体装置を用いた表示装置
KR101146988B1 (ko) * 2010-05-04 2012-05-22 삼성모바일디스플레이주식회사 유기 발광 표시 장치
CN102569185A (zh) 2010-12-22 2012-07-11 京东方科技集团股份有限公司 阵列基板及其制造方法和液晶显示器
CN203179897U (zh) * 2013-04-07 2013-09-04 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201121055A (en) * 2009-10-12 2011-06-16 Samsung Mobile Display Co Ltd Thin film transistor, method of manufacturing the thin film transistor and organic light emitting display device having the thin film transistor
CN102208452A (zh) * 2010-03-30 2011-10-05 索尼公司 薄膜晶体管及其制造方法、以及显示装置
WO2012044344A1 (en) * 2010-09-29 2012-04-05 Guardian Industries Corp. Method of making oxide thin film transistor array, and device incorporating the same
CN102184865A (zh) * 2011-04-15 2011-09-14 福州华映视讯有限公司 薄膜晶体管及其制造方法
CN102646715A (zh) * 2011-12-29 2012-08-22 京东方科技集团股份有限公司 薄膜晶体管及其制造方法

Also Published As

Publication number Publication date
US9368637B2 (en) 2016-06-14
US20150214373A1 (en) 2015-07-30
CN103219391B (zh) 2016-03-02
CN103219391A (zh) 2013-07-24

Similar Documents

Publication Publication Date Title
WO2014166176A1 (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
US9748280B2 (en) Thin film transistor and method of fabricating the same, array substrate and method of fabricating the same, and display device
KR101325053B1 (ko) 박막 트랜지스터 기판 및 이의 제조 방법
KR101213708B1 (ko) 어레이 기판 및 이의 제조방법
US8329523B2 (en) Array substrate for dislay device and method of fabricating the same
WO2016026246A1 (zh) 薄膜晶体管及其制备方法、阵列基板及其制备方法和显示装置
US20160370621A1 (en) Array substrate, manufacturing method thereof and liquid crystal display
WO2016023294A1 (zh) 阵列基板及制备方法和显示装置
US20160300866A1 (en) Array substrate, manufacturing method thereof, display device, thin-film transistor (tft) and manufacturing method thereof
CN104362125A (zh) 阵列基板及其制作方法、显示装置
WO2015100898A1 (zh) 薄膜晶体管、tft阵列基板及其制造方法和显示装置
WO2014127645A1 (zh) 薄膜晶体管及其制作方法和显示器件
WO2016000342A1 (zh) 阵列基板及其制作方法、显示装置
WO2014206035A1 (zh) 阵列基板及其制作方法、显示面板和显示装置
WO2015089964A1 (zh) 薄膜晶体管及其制备方法、阵列基板及其制备方法、以及显示装置
WO2015123975A1 (zh) 阵列基板及制备方法、显示面板
WO2018176784A1 (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
WO2016123974A1 (zh) 薄膜晶体管、像素结构及其制作方法、阵列基板、显示装置
CN105097552A (zh) 薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置
WO2016019602A1 (zh) 高解析度amoled背板制造方法
WO2013170574A1 (zh) 氧化物薄膜晶体管及其制作方法、阵列基板和显示装置
WO2015096307A1 (zh) 氧化物薄膜晶体管、显示器件、及阵列基板的制造方法
WO2015161523A1 (zh) 薄膜晶体管及有机发光二极管显示器制备方法
WO2015043082A1 (zh) 薄膜晶体管及其制造方法、阵列基板及显示装置
KR20130098709A (ko) 박막트랜지스터 기판 및 이의 제조 방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14348763

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13882052

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 25.01.2016)

122 Ep: pct application non-entry in european phase

Ref document number: 13882052

Country of ref document: EP

Kind code of ref document: A1