WO2016123974A1 - 薄膜晶体管、像素结构及其制作方法、阵列基板、显示装置 - Google Patents

薄膜晶体管、像素结构及其制作方法、阵列基板、显示装置 Download PDF

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WO2016123974A1
WO2016123974A1 PCT/CN2015/089139 CN2015089139W WO2016123974A1 WO 2016123974 A1 WO2016123974 A1 WO 2016123974A1 CN 2015089139 W CN2015089139 W CN 2015089139W WO 2016123974 A1 WO2016123974 A1 WO 2016123974A1
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film transistor
thin film
passivation layer
gate
layer
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PCT/CN2015/089139
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English (en)
French (fr)
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姜春生
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京东方科技集团股份有限公司
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Priority to US15/120,736 priority Critical patent/US9741750B2/en
Priority to EP15880921.0A priority patent/EP3101693B1/en
Publication of WO2016123974A1 publication Critical patent/WO2016123974A1/zh

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Definitions

  • Embodiments of the present invention relate to a display device, and more particularly to a thin film transistor, a pixel structure, an array substrate, and a method of fabricating a thin film transistor and a pixel structure.
  • TFTs Thin Film Transistors
  • LCDs liquid crystal displays
  • OLED organic light emitting diode
  • AMOLEDs Active Matrix Organic Light Emitting Diodes
  • a metal oxide such as an In-Ga-Zn-O (IGZO) thin film has been developed as an active layer of a TFT, and the mobility of the metal oxide is several tens of times that of the amorphous silicon layer, and is excellent.
  • the semiconductor characteristics can greatly improve the charge and discharge rate of the TFT electrode, improve the response speed of the pixel, achieve a faster refresh rate, and significantly improve the line scan rate of the pixel.
  • a thin film transistor formed of an active layer by IGZO generally has an etch barrier layer, that is, an insulating layer needs to be deposited thereon after forming an IGZO active layer, in order to protect the metal oxide during subsequent etching of the source and drain metal electrodes.
  • the IGZO layer is not destroyed, thereby improving the performance of the TFT having the metal oxide IGZO.
  • an additional photolithography process is required to form an etch barrier layer, which increases the fabrication process of the TFT.
  • Embodiments of the present invention provide a thin film transistor, a pixel structure, an array substrate, a display device, and a method for fabricating a thin film transistor and a pixel structure, which can simplify the fabrication process of the thin film transistor, improve the performance of the thin film transistor, and reduce the channel region. size.
  • a thin film transistor including a gate, a source, and a drain, and a first passivation layer made of an alumina material is disposed on the source and the drain, The first passivation layer The region corresponding to the gate has an active layer formed of an alumina material by doping ions.
  • the doped ions include gallium ions and tin ions such that the doped alumina material forms aluminum gallium tin oxide.
  • a thin film transistor is a bottom gate thin film transistor, and two sides of the active layer respectively cover sides of the source and drain away from the gate On the edge.
  • a second passivation layer is provided on the first passivation layer.
  • a pixel structure includes: a substrate; a driving thin film transistor disposed on the substrate, the driving thin film transistor being the thin film transistor according to any of the above embodiments; A switching thin film transistor disposed on the substrate, the switching thin film transistor being the thin film transistor according to any of the above embodiments, wherein a drain of the switching thin film transistor is electrically connected to a gate of the driving thin film transistor.
  • the source and the drain of the switching thin film transistor, and the source and the drain of the driving thin film transistor are made of the same material and disposed in the same layer.
  • a second passivation layer is disposed on the first passivation layer.
  • a pixel structure according to an embodiment of the present invention further includes a pixel electrode electrically connected to a drain of the driving thin film transistor through a via hole formed in the first passivation layer and the second passivation layer connection.
  • an array substrate comprising a plurality of pixel structures according to any of the above embodiments.
  • a display device comprising the array substrate according to the above embodiments.
  • a method of fabricating a thin film transistor includes forming a thin film transistor on a substrate, wherein the step of forming a thin film transistor on the substrate includes: a source and a drain of the thin film transistor Forming a first passivation layer from an aluminum oxide material; and forming an active layer by doping ions in a region of the first passivation layer corresponding to a gate of the thin film transistor.
  • the doped ions comprise gallium ions and tin ions such that the doped alumina material forms aluminum gallium tin oxide (AGTO).
  • AGTO aluminum gallium tin oxide
  • the step of forming a thin film transistor on the substrate further includes: forming a gate on the substrate; forming a gate insulating layer on the substrate forming the gate; and at the gate A source and a drain are formed on the insulating layer.
  • the step of forming an active layer by doping ions in a region of the first passivation layer corresponding to the gate includes: at the first blunt Forming a second passivation layer on the layer; and implanting gallium ions and tin ions into a region of the first passivation layer corresponding to the gate through the second passivation layer.
  • the step of forming an active layer by doping ions in a region of the first passivation layer corresponding to the gate further includes: A photoresist layer is formed on the passivation layer to implant gallium ions and tin ions through the photoresist layer and the second passivation layer.
  • both sides of the active layer are respectively formed to cover edges of the sides of the source and the drain remote from the gate.
  • a method of fabricating a pixel structure includes forming a switching thin film transistor and a driving thin film transistor on a substrate, wherein the step of forming a switching thin film transistor and a driving thin film transistor on the substrate comprises:
  • An active layer of the switching thin film transistor and the driving thin film transistor is formed by doping ions in a region of the first passivation layer corresponding to a gate of the switching thin film transistor and the driving thin film transistor, respectively.
  • the step of forming the switching thin film transistor and the driving thin film transistor on the substrate further includes:
  • the switching film is formed by doping ions in a region of the first passivation layer corresponding to the gates of the switching thin film transistor and the driving thin film transistor, respectively.
  • the steps of the transistor and the active layer of the driving thin film transistor include:
  • Gallium ions and tin ions are respectively implanted into the region of the first passivation layer corresponding to the gates of the switching thin film transistor and the driving thin film transistor through the second passivation layer.
  • the switching film is formed by doping ions in a region of the first passivation layer corresponding to the gates of the switching thin film transistor and the driving thin film transistor, respectively.
  • the steps of the transistor and the active layer of the driving thin film transistor further include:
  • a pixel electrode is formed on the second passivation layer, and the pixel electrode is electrically connected to a drain of the driving thin film transistor through the second via hole.
  • both sides of the active layer are respectively formed to cover edges of the sides of the source and the drain remote from the gate.
  • the doped ions comprise gallium ions and tin ions such that the doped alumina material forms aluminum gallium tin oxide.
  • the thin film transistor the pixel structure, the array substrate, the display device, and the method of fabricating the array substrate of the above-described embodiments of the present invention
  • the first passivation layer as the insulating material forms an active layer by ion doping
  • the thin film transistor is simplified.
  • the fabrication process can omit the etch stop layer, thereby simplifying the structure of the thin film transistor.
  • FIG. 1 is a cross-sectional view of a thin film transistor in accordance with a first exemplary embodiment of the present invention
  • FIG. 2a-2f are schematic views showing an operation process of fabricating the thin film transistor shown in Fig. 1;
  • FIG. 3 is an equivalent circuit diagram of an array substrate of a display device in accordance with an exemplary embodiment of the present invention.
  • FIG. 4 is a cross-sectional view showing a pixel structure in the array substrate shown in FIG. 3;
  • FIG. 5a-5h are schematic diagrams showing the operation of fabricating the pixel structure shown in Fig. 4.
  • a thin film transistor includes a gate, a source, and a drain, and a first passivation layer made of an alumina material is disposed on the source and the drain.
  • the region of the first passivation layer corresponding to the gate has an active layer formed of an alumina material by doping ions.
  • the doped ions include gallium ions and tin ions such that the doped alumina material forms aluminum gallium tin oxide. Since the first passivation layer as the insulating material forms the active layer by ion doping, the fabrication process of the thin film transistor (TFT) is simplified, and the etch stop layer (ESL) can be omitted to simplify the structure of the thin film transistor.
  • a thin film transistor according to an embodiment of the present invention includes a gate electrode 11, a source electrode 13 and a drain electrode 14, and a first passivation layer 15 made of an alumina material is disposed on the source electrode 13 and the drain electrode 14, A region of the first passivation layer 15 corresponding to the gate electrode 11 has an active layer 16 formed of aluminum gallium tin oxide.
  • the active layer 16 is formed by doping gallium ions and tin ions from a region of the first passivation layer 15 corresponding to the gate electrode 11, while the first passivation layer 15 that does not perform the ion doping process still functions. To insulation.
  • the first passivation layer as an insulating material forms a semiconductor metal oxide layer as the active layer 16 by ion doping, the fabrication process of the thin film transistor (TFT) is simplified, and the etch stop layer (ESL) can be omitted, thereby simplifying The structure of a thin film transistor.
  • the gate electrode 11 is disposed on a substrate 20 made of, for example, glass, a transparent resin, or a quartz material.
  • a gate insulating layer 12 covering the gate electrode 11 is further provided on the substrate 20.
  • the gate insulating layer 12 may be formed by using an oxide, a nitride or an oxynitride compound such as SiO 2 or SiNx material.
  • the source 13 and the drain 14 are disposed on the gate insulating layer 12.
  • the source 13 and the drain 14 may be made of one of a metal such as Cu, Cr, W, Ti, Ta, Mo, Al, or the like and an alloy material thereof.
  • the thin film transistor is a bottom gate thin film transistor, that is, the gate 11 is closer to the substrate 20 with respect to the source 13 and the drain 14.
  • the active layer 16 is formed by doping gallium ions and tin ions from a region of the first passivation layer 15 corresponding to the gate electrode 11, two sides of the active layer 16 are respectively covered at the source 13 and the drain.
  • the edge of 14 is away from the edge of the side of the gate 11. That is, a portion of the active layer is disposed on the upper portions of the source 13 and the drain 14.
  • the process of fabricating the source 13 and the drain 14 is performed prior to the process of fabricating the active layer 16, so that the active layer 16 does not form the source 13 and the drain 14 by performing a patterning process. And is affected so that it does not need to be in the active layer 16
  • An etch barrier layer is provided between the source and the drain to simplify the structure and fabrication process of the thin film transistor.
  • the second passivation layer 17 is provided on the first passivation layer 15.
  • the first passivation layer 15 may be ion-doped by the second passivation layer 17, such that the second passivation layer 17 serves as a barrier to reduce the influence on the gate electrode during ion doping.
  • the thin film transistor according to an embodiment of the present invention can be applied to, for example, a liquid crystal display (LCD), an organic light emitting diode (OLED) display, and an active matrix organic light emitting diode (AMOLED).
  • LCD liquid crystal display
  • OLED organic light emitting diode
  • AMOLED active matrix organic light emitting diode
  • a display device such as a display.
  • an array substrate and a display device including the thin film transistor of the embodiment of the present invention will be described by taking an organic light emitting diode (OLED)-based display device as an example.
  • FIG. 3 is an equivalent circuit diagram of an array substrate of a display device according to an exemplary embodiment of the present invention
  • FIG. 4 is a cross-sectional view showing a pixel structure in the array substrate shown in FIG.
  • the array substrate includes a plurality of pixel structures P arranged in an array by the first wiring W1, the second wiring W2, and the third wiring W3.
  • the first wiring W1 is formed as a scanning line S arranged in the horizontal direction for transmitting a scanning signal
  • the second wiring W2 is formed as a data line D arranged in a vertical direction for transmitting data
  • the third wiring W3 is formed as a driving voltage line V arranged in the vertical direction for transmitting the data driving voltage.
  • each pixel structure in accordance with an exemplary embodiment of the present invention includes a substrate 20; a driving thin film transistor 30 disposed on the substrate 20, the driving thin film transistor 30 being in accordance with an embodiment of the present invention a thin film transistor; a switching thin film transistor 10 disposed on a substrate 20, the switching thin film transistor 10 being a thin film transistor according to an embodiment of the present invention, wherein a drain electrode 14 of the switching thin film transistor 10 and a driving thin film transistor 30 The gate 31 is electrically connected.
  • a storage capacitor Cst is provided between the gate 31 and the source of the driving thin film transistor 30, and the drain is electrically connected to the pixel electrode 40 of the organic light emitting diode (OLED), and may be, for example, a cathode or an anode. The other end of the OLED is connected to the power supply Vss.
  • OLED organic light emitting diode
  • the active layers of the switching thin film transistor 10 and the driving thin film transistor 30 are formed by doping the gallium ion and tin ions from the first passivation layer 15 without performing the ion doping process.
  • the first passivation layer 15 still functions as an insulator. Since the first passivation layer as the insulating material forms the active layer by ion doping, the etch stop layer of the respective thin film transistors can be omitted, thereby simplifying the structure of the thin film transistor.
  • the switching thin film transistor 10 and the driving thin film transistor 30 can be disposed on the same layer, thereby switching
  • the thin film transistor 10 and the driving thin film transistor 30 are formed in a coplanar structure to facilitate the preparation of a high resolution display backplane.
  • the source 13 and drain 14 of the switching thin film transistor 10, and the source and drain (not shown) of the driving thin film transistor 30 are made of the same material and disposed in the same layer. In this way, the source and drain of the two thin film transistors can be formed by one patterning process, which reduces the number of patterning processes and reduces the number of masks used.
  • the second passivation layer 17 is provided on the first passivation layer 15.
  • the first passivation layer 15 may be ion-doped by the second passivation layer 17, such that the second passivation layer 17 serves as a barrier to reduce the influence on the gate electrode during ion doping.
  • the pixel electrode 40 of the pixel structure passes through the second via hole 41 formed in the first passivation layer 15 and the second passivation layer 17 and the drain of the driving thin film transistor 30 (not shown) ) Electrical connection.
  • the pixel electrode 40 may be a cathode or an anode to drive the light emitting layer of the organic light emitting diode to emit light.
  • an array substrate comprising a plurality of pixel structures according to various embodiments described above.
  • a display device including the array substrate described in the above embodiments is provided.
  • the array substrate and the color filter substrate may be paired with a liquid crystal material between the array substrate and the color filter substrate to form a liquid crystal display device.
  • the array substrate of the embodiment of the invention may be applied to an OLED display device or an AMOLED display device.
  • These display devices can be any products or components having display functions such as mobile phones, tablets, televisions, displays, notebook computers, digital photo frames, navigators, electronic papers, and the like.
  • a method of fabricating a thin film transistor including forming a thin film transistor on a substrate 20 and forming a thin film transistor on the substrate 20 includes: a thin film transistor a first passivation layer 15 is formed of an alumina material on the source 13 and the drain 14; a region corresponding to the gate 11 of the thin film transistor of the first passivation layer 15 is formed by doping gallium ions and tin ions Active layer 16.
  • the active layer 16 is formed by doping gallium ions and tin ions from a region of the first passivation layer 15 corresponding to the gate electrode 11, while the first passivation layer 15 that does not perform the ion doping process still functions.
  • the first passivation layer as an insulating material forms a semiconductor metal oxide layer as an active layer by ion doping, the fabrication process of the thin film transistor is simplified, and the etching stopper layer can be omitted, thereby simplifying the structure of the thin film transistor.
  • the step of forming a thin film transistor on the substrate 20 further comprises: forming a gate electrode 11 on a substrate 20 made of, for example, glass, a transparent resin or a quartz material, as shown in FIG. 2a; forming a gate electrode A gate insulating layer 12 is formed on the substrate 20 of 11, as shown in FIG. 2a, an oxide, a nitride or an oxynitride compound such as SiO 2 or SiNx material may be selected to form the gate insulating layer 12; and a gate insulating layer A source 13 and a drain 14 are formed on 12.
  • a conductive layer made of one of a metal such as Cu, Cr, W, Ti, Ta, Mo, Al, and an alloy thereof is formed on the gate insulating layer 12;
  • the source 13 and the drain 14 are formed by performing a patterning process including a process of coating photoresist, exposure, development, and etching on the conductive layer.
  • an alumina (Al 2 O 3 ) material is deposited on the source 13 and the drain 14 to form a first passivation layer 15.
  • the step of forming the active layer 16 by doping gallium ions and tin ions in a region of the first passivation layer 15 corresponding to the gate includes depositing SiNx or silicon oxide by a CVD deposition method.
  • a (SiO 2 ) material, a second passivation layer 17 is formed on the first passivation layer 15, as shown in FIG. 2d; gallium (Ga) ions and tin are passed through the second passivation layer 17 by an ion implantation process.
  • (Sn) ions are implanted into a region of the first passivation layer 15 corresponding to the gate electrode 11 to ion doping the region of the first passivation layer 15 to form the active layer 16.
  • the step of forming the active layer 16 by doping gallium ions and tin ions in a region of the first passivation layer 15 corresponding to the gate electrode 11 further includes: on the second passivation layer 17 A photoresist layer 50 is formed, as shown in FIG. 2e, to implant gallium ions (Ga 3+ ) and tin ions (Sn 2+ ) through the photoresist layer 50 and the second passivation layer 17, as shown in FIG. 2f.
  • a photoresist layer 50 is formed on the second passivation layer 17, and the photoresist layer 50 is partially exposed and developed by using a halftone mask or a gray tone mask to be in the gate.
  • the corresponding portion of the pole 11 forms a photoresist semi-retaining portion 51; thereafter, as shown in FIG. 2f, the photoresist layer 50 and the second passivation layer 17 are passed through the photoresist half-retaining portion 51 by an ion implantation process.
  • the first passivation layer 15 is doped with gallium ions and tin ions.
  • the first passivation layer 15 having an insulating property in the doped region is converted into a semiconductor metal oxide, that is, aluminum gallium tin oxide (AGTO), so that the doped region forms the active layer 16;
  • ATO aluminum gallium tin oxide
  • the photoresist layer 50 is removed and finally the thin film transistor shown in FIG. 1 is formed.
  • the first passivation layer 15 overlying the source 13 and the drain 14 is ion-doped to have an insulating property.
  • the first passivation layer 15 is converted into a semiconductor metal oxide such that the doped regions form the active layer 16.
  • Both sides of the active layer 16 are formed to cover the edges of the sides of the source 13 and the drain 14 away from the gate 11, respectively.
  • a method of fabricating a pixel structure comprising forming a switching thin film transistor 10 and a driving thin film transistor 30 on a substrate 20, wherein the substrate 20 is
  • the step of forming the switching thin film transistor 10 and the driving thin film transistor 30 includes: forming a first passivation layer 15 from an aluminum oxide material on the source and the drain of the switching thin film transistor 10 and the driving thin film transistor 30;
  • a region corresponding to the gate 11 of the switching thin film transistor 10 and the gate 31 of the driving thin film transistor 30 of the first passivation layer 15 is doped with gallium ions (Ga 3+ ) and tin ions (Sn 2+ ), respectively.
  • An active layer 16 of the switching thin film transistor 10 and an active layer (not shown) that drives the thin film transistor 30 are formed.
  • the active layer is formed by ion doping as the first passivation layer of the insulating material
  • the etch barrier layer of the respective thin film transistor can be omitted, thereby simplifying the structure of the thin film transistor.
  • the switching thin film transistor 10 and the driving thin film transistor 30 can be disposed in the same layer, so that the switching thin film transistor 10 and the driving thin film transistor 30 can be formed into a coplanar structure, which is advantageous for the preparation of the high resolution display back sheet.
  • the step of forming the switching thin film transistor 10 and the driving thin film transistor 30 on the substrate 20 further includes the following steps:
  • a gate electrode 11 of a switching thin film transistor 10 and a gate electrode 31 of a driving thin film transistor 30 are formed on a substrate 20 made of, for example, glass, a transparent resin or a quartz material, as shown in FIG. 5a;
  • a gate insulating layer 12 is formed on the substrate 20 on which the gate electrodes 11 and 31 are formed; an oxide, a nitride or an oxynitride compound such as SiO 2 or SiNx material may be selected to form the gate insulating layer 12; thereafter, the gate insulating layer is formed A first via 121 is formed at a position of the layer 12 corresponding to the gate 31 of the driving thin film transistor 30, as shown in FIG. 5a;
  • a conductive layer made of one of a metal such as Cu, Cr, W, Ti, Ta, Mo, Al, or an alloy thereof is formed on the gate insulating layer 12, as shown in FIG. 5b, the conductive layer is worn.
  • the first via 121 is electrically connected to the gate 31; thereafter, the source 13 and the drain 14 of the switching thin film transistor 10 and the source and drain of the driving thin film transistor 30 are respectively formed by the conductive layer by a patterning process ( Not shown), and the drain electrode 14 of the switching thin film transistor is electrically connected to the gate 31 of the driving thin film transistor through the first via 121 as shown in FIG. 5c.
  • forming the source and drain of the two thin film transistors by one patterning process reduces the number of patterning processes and reduces the number of masks used.
  • the region of the first passivation layer 15 corresponding to the gate 11 of the switching thin film transistor and the gate 31 of the driving thin film transistor is respectively formed by doping gallium ions and tin ions.
  • the step of switching the active layer 16 of the thin film transistor and the active layer (not shown) of driving the thin film transistor includes: depositing a SiNx or silicon oxide (SiO 2 ) material by a CVD deposition method to form on the first passivation layer 15 a second passivation layer 17, as shown in FIG.
  • gallium ions and tin ions are respectively implanted into the regions of the first passivation layer 15 corresponding to the gate electrodes 11 and 31 through the second passivation layer 17,
  • the region of a passivation layer 15 is doped to form an active layer 16 of the switching thin film transistor and an active layer (not shown) that drives the thin film transistor.
  • the switching film is formed by doping gallium ions and tin ions in a region of the first passivation layer 15 corresponding to the gate 11 of the switching thin film transistor and the gate 31 of the driving thin film transistor, respectively.
  • the step of the transistor and the active layer of the driving thin film transistor further includes the following steps:
  • a photoresist layer 50 is formed on the second passivation layer 17, as shown in FIG. 5e; and the gate electrode 11 of the photoresist layer 50 is formed by a halftone mask or a gray tone mask (not shown).
  • a corresponding area of 31 is subjected to partial exposure, and a region corresponding to a drain (not shown) of the driving thin film transistor of the photoresist layer 50 is fully exposed, thereby forming a photoresist semi-retained portion at a portion corresponding to the gate electrode.
  • 51 the photoresist half-retaining portion corresponding to the gate 31 is not shown in the figure, forming a photoresist completely removed portion 52 at a portion corresponding to the drain of the driving thin film transistor;
  • the photoresist completely removed portion 52 of the photoresist layer 50 is formed by a dry etching process to form a second via 41 of the drain of the driving thin film transistor;
  • an ion implantation process is used to pass the photoresist layer having a partial thickness and the second passivation layer 17 on the gate of the first passivation layer 15 and the switching thin film transistor in the semi-reserved portion of the photoresist.
  • 11 implanting gallium ions and tin ions in a region corresponding to the gate 31 of the driving thin film transistor; thus, the first passivation layer 15 having insulating properties in the doped region is converted into a semiconductor metal oxide, that is, aluminum gallium tin oxide An object (AGTO) such that the doped region forms an active layer 16 of the switching thin film transistor and an active layer (not shown) of the driving thin film transistor;
  • the residual photoresist is stripped; finally, the pixel electrode 40 is formed on the second passivation layer 15, and the pixel electrode 40 is electrically connected to the drain of the driving thin film transistor through the second via 41, thereby A pixel structure as shown in FIG. 4 is formed.
  • the first passivation having the insulating property is performed by ion doping the first passivation layer overlying the source and the drain.
  • the layer is converted into a semiconducting metal oxide such that the doped regions form an active layer. Both sides of the active layer are respectively formed to cover the edges of the sides of the source and the drain remote from the gate.
  • the process of fabricating the source and the drain is performed prior to the process of fabricating the active layer, so that the active layer is not affected by the formation of the source and drain by performing the patterning process, thereby An etch stop layer is required between the active layer and the source and the drain, which simplifies the structure and fabrication process of the thin film transistor.
  • the active layer is formed without using a patterning process, which further reduces the number of use of the mask and improves the product excellent rate.
  • a method of fabricating an array substrate including the method of fabricating a pixel structure described in the above embodiments, is provided.
  • the source and drain of the thin film transistor may be fabricated from graphene or nano-silver lines using an inkjet printing process.
  • Graphene or nano silver wires have good light transmittance and excellent electrical conductivity.
  • the graphite thin or nano silver wire can be formed into nanometer-sized fine particles, and can be mixed with deionized water, ethanol or the like as a solvent to form a nano conductive ink, thereby forming a conductive wire having a very small line width by an inkjet printing process. .
  • the size of the thin film transistor can be reduced, and the size of the display area can be increased, thereby increasing the aperture ratio of the array substrate.
  • the gate of the thin film transistor can be made of graphene or nano-silver lines using an inkjet printing process.
  • the switching thin film transistor and the driving thin film transistor can be formed into a coplanar structure, which is advantageous for high resolution display.

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Abstract

公开了一种薄膜晶体管、像素结构、阵列基板、显示装置、及薄膜晶体管和像素结构的制作方法。一种薄膜晶体管，包括栅极、源极和漏极，在所述源极和漏极上设有由氧化铝材料制成的第一钝化层，所述第一钝化层的与所述栅极相对应的区域具有由氧化铝材料通过掺杂离子形成的有源层。掺杂的离子包括镓离子和锡离子，使得被掺杂的氧化铝材料形成铝镓锡氧化物。由于作为绝缘材料的第一钝化层通过离子掺杂形成有源层，简化了薄膜晶体管的制作工艺，可以省略刻蚀阻挡层，从而简化薄膜晶体管的结构。 (图4)

Description

薄膜晶体管、像素结构及其制作方法、阵列基板、显示装置
相关申请的交叉引用
本申请要求于2015年2月4日递交的中国专利申请CN201510059734.1的权益，其全部内容通过参考并入本文中。
技术领域
本发明的实施例涉及一种显示装置，尤其涉及一种薄膜晶体管、像素结构、阵列基板、及薄膜晶体管和像素结构的制作方法。
背景技术
薄膜晶体管(Thin Film Transistor，TFT)在诸如液晶显示器(Liquid Crystal Display，LCD)、有机发光二极管(Organic Light Emitting Diode，OLED)显示器、以及主动矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)显示器之类的平面显示装置中用作开关元件。例如，在常规的LCD中，TFT的沟道层主要由非晶硅层形成，其迁移率较低。随着显示器变得更大，对显示器的分辨率和高频驱动性能的要求越来越高，由此需要提高TFT的沟道层的迁移率。
目前已研发出利用金属氧化物，例如，In-Ga-Zn-O(IGZO)薄膜作为TFT的有源层，金属氧化物的迁移率是非晶硅层的迁移率的几十倍，表现出优良的半导体特性，可以大大提高TFT对像素电极的充放电速率，提高像素的响应速度，实现更快的刷新率，显著提高像素的行扫描速率。
由IGZO形成有源层的薄膜晶体管一般具有刻蚀阻挡层，即在形成IGZO有源层后需要在其上沉积一层绝缘层，以期在随后的刻蚀源、漏金属电极时保护金属氧化物IGZO层不被破坏，从而提高具有金属氧化物IGZO的TFT的性能。这样，需要一次额外的光刻工艺形成刻蚀阻挡层，增加了TFT的制作工艺流程。
发明内容
本发明的实施例提供一种薄膜晶体管、像素结构、阵列基板、显示装置、及薄膜晶体管和像素结构的制作方法，可以简化薄膜晶体管的制作工艺，可以提高薄膜晶体管的性能，降低沟道区域的尺寸。
根据本发明一方面的实施例，提供一种薄膜晶体管，包括栅极、源极和漏极，在所述源极和漏极上设有由氧化铝材料制成的第一钝化层，所述第一钝化层的与所 述栅极相对应的区域具有由氧化铝材料通过掺杂离子形成的有源层。
根据本发明的一种实施例的薄膜晶体管，掺杂的离子包括镓离子和锡离子，使得被掺杂的氧化铝材料形成铝镓锡氧化物。
根据本发明的一种实施例的薄膜晶体管，所述薄膜晶体管为底栅薄膜晶体管，而且所述有源层的两侧分别覆盖在所述源极和漏极的远离所述栅极的侧部的边缘上。
根据本发明的一种实施例的薄膜晶体管，所述第一钝化层上设有第二钝化层。
根据本发明另一方面的实施例，提供一种像素结构，包括：基板；设置在所述基板上的驱动薄膜晶体管，所述驱动薄膜晶体管为根据上述任一实施例所述的薄膜晶体管；以及设置在所述基板上的开关薄膜晶体管，所述开关薄膜晶体管为根据上述任一实施例所述的薄膜晶体管，其中所述开关薄膜晶体管的漏极与所述驱动薄膜晶体管的栅极电连接。
根据本发明的一种实施例的像素结构，所述开关薄膜晶体管的源极和漏极、以及驱动薄膜晶体管的源极和漏极由相同的材料制成并设置在同一层。
根据本发明的一种实施例的像素结构，第一钝化层上设有第二钝化层。
根据本发明的一种实施例的像素结构还包括像素电极，所述像素电极通过形成在所述第一钝化层和第二钝化层中的过孔与所述驱动薄膜晶体管的漏极电连接。
根据本发明进一步方面的实施例，提供一种阵列基板，包括多个根据上述任一实施例所述的像素结构。
根据本发明再进一步方面的实施例，提供一种显示装置，包括根据上述实施例所述的阵列基板。
根据本发明再进一步方面的实施例，提供一种薄膜晶体管的制作方法，包括在基板上形成薄膜晶体管，其中，在基板上形成薄膜晶体管的步骤包括：在所述薄膜晶体管的源极和漏极上由氧化铝材料形成第一钝化层；以及在所述第一钝化层的与所述薄膜晶体管的栅极相对应的区域通过掺杂离子而形成有源层。
根据本发明的一种实施例所述的方法，掺杂的离子包括镓离子和锡离子，使得被掺杂的氧化铝材料形成铝镓锡氧化物(AGTO)。
根据本发明的一种实施例所述的方法，在基板上形成薄膜晶体管的步骤还包括：在基板上形成栅极；在形成栅极的基板上形成栅极绝缘层；以及在所述栅极绝缘层上形成源极和漏极。
根据本发明的一种实施例所述的方法，在所述第一钝化层的与所述栅极相对应的区域通过掺杂离子而形成有源层的步骤包括：在所述第一钝化层上形成第二钝化层；以及通过所述第二钝化层将镓离子和锡离子注入到所述第一钝化层的与所述栅极相对应的区域。
根据本发明的一种实施例所述的方法，在所述第一钝化层的与所述栅极相对应的区域通过掺杂离子而形成有源层的步骤还包括：在所述第二钝化层上形成光刻胶层，以通过所述光刻胶层和第二钝化层注入镓离子和锡离子。
根据本发明的一种实施例所述的方法，所述有源层的两侧分别形成为覆盖在所述源极和漏极的远离所述栅极的侧部的边缘上。
根据本发明再进一步方面的实施例，提供一种制作像素结构的方法，包括在基板上形成开关薄膜晶体管和驱动薄膜晶体管，其中，在基板上形成开关薄膜晶体管和驱动薄膜晶体管的步骤包括：
在所述开关薄膜晶体管和驱动薄膜晶体管的源极和漏极上由氧化铝材料形成第一钝化层；以及
分别在所述第一钝化层的与所述开关薄膜晶体管和驱动薄膜晶体管的栅极相对应的区域通过掺杂离子而形成所述开关薄膜晶体管和驱动薄膜晶体管的有源层。
根据本发明的一种实施例所述的方法，在基板上形成开关薄膜晶体管和驱动薄膜晶体管的步骤还包括：
在基板上形成开关薄膜晶体管和驱动薄膜晶体管的栅极；
在形成栅极的基板上形成栅极绝缘层，并在所述栅极绝缘层的与所述驱动薄膜晶体管的栅极对应的位置形成第一过孔；
在所述栅极绝缘层上形成导电层；以及
采用构图工艺利用所述导电层分别形成所述开关薄膜晶体管和驱动薄膜晶体管的源极和漏极，而且所述开关薄膜晶体管的漏极通过所述第一过孔与所述驱动薄膜晶体管的栅极电连接。
根据本发明的一种实施例所述的方法，分别在所述第一钝化层的与所述开关薄膜晶体管和驱动薄膜晶体管的栅极相对应的区域通过掺杂离子而形成所述开关薄膜晶体管和驱动薄膜晶体管的有源层的步骤包括：
在所述第一钝化层上形成第二钝化层；
通过所述第二钝化层将镓离子和锡离子分别注入到所述第一钝化层的与所述开关薄膜晶体管和驱动薄膜晶体管的栅极相对应的区域。
根据本发明的一种实施例所述的方法，分别在所述第一钝化层的与所述开关薄膜晶体管和驱动薄膜晶体管的栅极相对应的区域通过掺杂离子而形成所述开关薄膜晶体管和驱动薄膜晶体管的有源层的步骤还包括：
在所述第二钝化层上形成光刻胶层；
采用半色调掩模板或者灰色调掩模板对光刻胶层的与所述开关薄膜晶体管和驱动薄膜晶体管的栅极对应的区域进行局部曝光，对光刻胶层的与驱动薄膜晶体管的漏极对应的区域进行全曝光；
在光刻胶层的光刻胶完全去除部分通过刻蚀形成到达驱动薄膜晶体管的漏极的第二过孔；
通过所述光刻胶层和第二钝化层在第一钝化层的与所述开关薄膜晶体管和驱动薄膜晶体管的栅极相对应的区域注入镓离子和锡离子；
剥离残余的光刻胶；以及
在所述第二钝化层上形成像素电极，所述像素电极通过第二过孔与驱动薄膜晶体管的漏极电连接。
根据本发明的一种实施例所述的方法，所述有源层的两侧分别形成为覆盖在所述源极和漏极的远离所述栅极的侧部的边缘上。
根据本发明的一种实施例所述的方法，掺杂的离子包括镓离子和锡离子，使得被掺杂的氧化铝材料形成铝镓锡氧化物。
根据本发明上述实施例的薄膜晶体管、像素结构、阵列基板、显示装置、及阵列基板的制作方法，由于作为绝缘材料的第一钝化层通过离子掺杂形成有源层，简化了薄膜晶体管的制作工艺，可以省略刻蚀阻挡层，从而简化薄膜晶体管的结构。
附图说明
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明，其中：
图1是根据本发明的第一种示例性实施例的薄膜晶体管的剖视图；
图2a-2f是示出制作图1所示的薄膜晶体管的操作过程的示意图；
图3是根据本发明的一种示例性实施例的显示装置的阵列基板的等效电路图；
图4是图3所示的阵列基板中一个像素结构的剖视示意图；以及
图5a-5h是示出制作图4所示的像素结构的操作过程的示意图。
具体实施方式
下面通过实施例，并结合附图，对本发明的技术方案作进一步具体的说明。在说 明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本发明实施方式的说明旨在对本发明的总体发明构思进行解释，而不应当理解为对本发明的一种限制。
根据本发明总体上的发明构思，提供一种薄膜晶体管，包括栅极、源极和漏极，在所述源极和漏极上设有由氧化铝材料制成的第一钝化层，所述第一钝化层的与所述栅极相对应的区域具有由氧化铝材料通过掺杂离子形成的有源层。掺杂的离子包括镓离子和锡离子，使得被掺杂的氧化铝材料形成铝镓锡氧化物。由于作为绝缘材料的第一钝化层通过离子掺杂形成有源层，简化了薄膜晶体管(TFT)的制作工艺，可以省略刻蚀阻挡层(ESL)从而简化薄膜晶体管的结构。
在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其他情况下，公知的结构和装置以图示的方式体现以简化附图。
图1是根据本发明的第一种示例性实施例的薄膜晶体管的剖视图。参见图1，根据本发明实施例的薄膜晶体管包括栅极11、源极13和漏极14，在源极13和漏极14上设有由氧化铝材料制成的第一钝化层15，所述第一钝化层15的与栅极11相对应的区域具有由铝镓锡氧化物形成的有源层16。该有源层16是由第一钝化层15的与栅极11相对应的区域通过掺杂镓离子和锡离子而形成的，而未执行离子掺杂工艺的第一钝化层15仍然起到绝缘作用。由于作为绝缘材料的第一钝化层通过离子掺杂形成作为有源层16的半导体金属氧化物层，简化了薄膜晶体管(TFT)的制作工艺，可以省略刻蚀阻挡层(ESL)，从而简化薄膜晶体管的结构。
在一种示例性实施例中，如图1所示，栅极11设置在由例如玻璃、透明树脂或者石英材料制成的基板20上。在基板20上还设有覆盖栅极11的栅极绝缘层12。可以选用氧化物、氮化物或者氧氮化合物，例如SiO2或SiNx材料，形成栅极绝缘层12。源极13和漏极14设置在栅极绝缘层12上。源极13和漏极14可以由Cu、Cr、W、Ti、Ta、Mo、Al等金属及其合金材料中的一种制成。
根据本发明的一种实施例，薄膜晶体管为底栅薄膜晶体管，即，栅极11相对于源极13和漏极14更靠近基板20。由于有源层16是由第一钝化层15的与栅极11相对应的区域通过掺杂镓离子和锡离子而形成的，有源层16的两侧分别覆盖在源极13和漏极14的远离栅极11的侧部的边缘上。也就是说，部分有源层设置在源极13和漏极14的上部。这样，在制作薄膜晶体管的过程中，制作源极13和漏极14的工艺先于制作有源层16的工艺执行，使得有源层16不会由于执行构图工艺形成源极13和漏极14而受到影响，从而不需在有源层16 与源极和漏极之间设置刻蚀阻挡层，简化了薄膜晶体管的结构和制作工艺。
根据本发明的一种实施例，第一钝化层15上设有第二钝化层17。可以通过第二钝化层17对第一钝化层15进行离子掺杂，这样第二钝化层17起到阻挡作用，可以降低离子掺杂时对栅极的影响。
根据本发明实施例的薄膜晶体管可以应用到诸如液晶显示器(Liquid Crystal Display，LCD)、有机发光二极管(Organic Light Emitting Diode，OLED)显示器、以及主动矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)显示器之类的显示装置中。下面以基于有机发光二极管(OLED)的显示装置为例，对包括本发明实施例的薄膜晶体管的阵列基板和显示装置进行说明。
图3是根据本发明的一种示例性实施例的显示装置的阵列基板的等效电路图，图4是图3所示的阵列基板中一个像素结构的剖视示意图。参见图3，阵列基板包括多个像素结构P，该多个像素结构P通过第一接线W1、第二接线W2和第三接线W3以阵列形式排列。在一种示例性实施例中，第一接线W1形成为沿水平方向排列的扫描线S，用于传输扫描信号；第二接线W2形成为沿竖直方向排列的数据线D，用于传输数据信号；第三接线W3形成为沿竖直方向排列的驱动电压线V，用于传输数据驱动电压。
参见图3和4，根据本发明的一种示例性实施例的每个像素结构包括基板20；设置在基板20上的驱动薄膜晶体管30，所述驱动薄膜晶体管30为根据本发明的实施例所述的薄膜晶体管；设置在基板20上的开关薄膜晶体管10，所述开关薄膜晶体管10为根据本发明的实施例所述的薄膜晶体管，其中开关薄膜晶体管10的漏极14与驱动薄膜晶体管30的栅极31电连接。另外，在驱动薄膜晶体管30的栅极31和源极之间设有存储电容Cst，漏极电连接至有机发光二极管(OLED)的像素电极40，例如，可以是阴极或者阳极。OLED的另一端连接至电源Vss。
需要说明的是，为了清楚地示出开关薄膜晶体管10的漏极14与驱动薄膜晶体管30的栅极31的电连接关系，图4中没有示出驱动薄膜晶体管的源极和漏极。
根据本发明实施例的像素结构，开关薄膜晶体管10和驱动薄膜晶体管30的有源层都是由第一钝化层15通过掺杂镓离子和锡离子而形成，而未执行离子掺杂工艺的第一钝化层15仍然起到绝缘作用。由于作为绝缘材料的第一钝化层通过离子掺杂形成有源层，可以省略各自薄膜晶体管的刻蚀阻挡层，从而简化薄膜晶体管的结构。可以将开关薄膜晶体管10和驱动薄膜晶体管30设置在同一层，从而将开关 薄膜晶体管10和驱动薄膜晶体管30形成为共面结构，有利于高分辨率显示背板的制备。
在一种实施例中，开关薄膜晶体管10的源极13和漏极14、以及驱动薄膜晶体管30的源极和漏极(未示出)由相同的材料制成并设置在同一层。这样，可以通过一次构图工艺形成两个薄膜晶体管的源极和漏极，减少了构图工艺的次数，降低了掩模板的使用数量。
根据本发明的一种实施例，第一钝化层15上设有第二钝化层17。可以通过第二钝化层17对第一钝化层15进行离子掺杂，这样第二钝化层17起到阻挡作用，可以降低离子掺杂时对栅极的影响。
根据本发明的一种实施例的像素结构的像素电极40通过形成在第一钝化层15和第二钝化层17中的第二过孔41与驱动薄膜晶体管30的漏极(未示出)电连接。像素电极40可以是阴极或者阳极，以驱动有机发光二极管的发光层发光。
根据本发明另一方面的实施例，提供一种阵列基板，包括多个根据上述各种实施例所述的像素结构。根据本发明进一步方面的实施例，提供一种显示装置，包括上述实施例所述的阵列基板。例如，可以将该阵列基板与彩膜基板进行对盒，并在阵列基板和彩膜基板之间填充液晶材料，从而形成液晶显示装置。在另外的实施例中，本发明实施例的阵列基板可以应用于OLED显示装置或者AMOLED显示装置。这些显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、电子纸等任何具有显示功能的产品或部件。
根据本发明再进一步方面的实施例，参见图1和2a-2f，提供一种薄膜晶体管的制作方法，包括在基板20上形成薄膜晶体管，在基板20上形成薄膜晶体管的步骤包括：在薄膜晶体管的源极13和漏极14上由氧化铝材料形成第一钝化层15；在第一钝化层15的与薄膜晶体管的栅极11相对应的区域通过掺杂镓离子和锡离子而形成有源层16。该有源层16是由第一钝化层15的与栅极11相对应的区域通过掺杂镓离子和锡离子而形成的，而未执行离子掺杂工艺的第一钝化层15仍然起到绝缘作用。由于作为绝缘材料的第一钝化层通过离子掺杂形成作为有源层的半导体金属氧化物层，简化了薄膜晶体管的制作工艺，可以省略刻蚀阻挡层，从而简化薄膜晶体管的结构。
在一种实施例中，在基板20上形成包括薄膜晶体管的步骤还包括：在例如玻璃、透明树脂或者石英材料制成的基板20上形成栅极11，如图2a所示；在形成栅极11的基板20上形成栅极绝缘层12，如图2a所示，可以选用氧化 物、氮化物或者氧氮化合物，例如SiO2或SiNx材料，形成栅极绝缘层12；以及在栅极绝缘层12上形成源极13和漏极14。
例如，如图2b所示，在栅极绝缘层12上形成由Cu、Cr、W、Ti、Ta、Mo、Al等金属及其合金材料中的一种制成的导电层；之后，如图2c所示，通过对导电层执行包括涂覆光刻胶、曝光、显影和刻蚀等工艺的构图工艺制成源极13和漏极14。之后，在源极13和漏极14上沉积氧化铝(Al2O3)材料以形成第一钝化层15。
在一种实施例中，在第一钝化层15的与栅极相对应的区域通过掺杂镓离子和锡离子而形成有源层16的步骤包括：如通过CVD沉积方法沉积SiNx或者氧化硅(SiO2)材料，在第一钝化(Passivation)层15上形成第二钝化层17，如图2d所示；采用离子注入工艺通过第二钝化层17将镓(Ga)离子和锡(Sn)离子注入到第一钝化层15的与栅极11相对应的区域，以对第一钝化层15的所述区域进行离子掺杂，从而形成有源层16。
在一种实施例中，在第一钝化层15的与栅极11相对应的区域通过掺杂镓离子和锡离子而形成有源层16的步骤还包括：在第二钝化层17上形成光刻胶层50，如图2e所示，以通过光刻胶层50和第二钝化层17注入镓离子(Ga3+)和锡离子(Sn2+)，如图2f所示。
具体而言，参见图2e，在第二钝化层17上形成光刻胶层50，并利用半色调掩模板或者灰色调掩模板对光刻胶层50进行部分曝光和显影，以在与栅极11相对应的部位形成光刻胶半保留部分51；之后，如图2f所示，采用离子注入工艺在光刻胶半保留部分51上穿过光刻胶层50、第二钝化层17对第一钝化层15掺杂镓离子和锡离子。这样，被掺杂的区域中具有绝缘性质的第一钝化层15转换成半导体金属氧化物，即铝镓锡氧化物(AGTO)，从而使得被掺杂的区域形成有源层16；之后，清除光刻胶层50，并最终形成图1所示的薄膜晶体管。
根据本发明的薄膜晶体管的制作方法，在形成源极13和漏极14之后，通过对覆盖在源极13和漏极14上的第一钝化层15进行离子掺杂，而使具有绝缘性质的第一钝化层15转换成半导体金属氧化物，从而使得被掺杂的区域形成有源层16。有源层16的两侧分别形成为覆盖在源极13和漏极14的远离栅极11的侧部的边缘上。这样，在制作薄膜晶体管的过程中，制作源极13和漏极14的工艺先于制作有源层16的工艺执行，使得有源层16不会由于执行构图工艺形成源极13和漏极14而受到影响，从而不需在有源层与源极和漏极之间设置刻蚀阻挡层，简化了薄膜晶体管的结构和制作工艺。
根据本发明再进一步方面的实施例，参见图3、4和5a-5h，提供一种制作像素结构的方法，包括在基板20上形成开关薄膜晶体管10和驱动薄膜晶体管30，其中，在基板20上形成开关薄膜晶体管10和驱动薄膜晶体管30的步骤包括：在开关薄膜晶体管10和驱动薄膜晶体管30的源极和漏极上由氧化铝材料形成第一钝化层15；以及
分别在第一钝化层15的与开关薄膜晶体管10的栅极11和驱动薄膜晶体管30的栅极31相对应的区域通过掺杂镓离子(Ga3+)和锡离子(Sn2+)而形成开关薄膜晶体管10的有源层16和驱动薄膜晶体管30的有源层(未示出)。
根据本发明实施例的制作像素结构的方法，由于作为绝缘材料的第一钝化层通过离子掺杂形成有源层，可以省略各自薄膜晶体管的刻蚀阻挡层，从而简化薄膜晶体管的结构。可以将开关薄膜晶体管10和驱动薄膜晶体管30设置在同一层，从而可以将开关薄膜晶体管10和驱动薄膜晶体管30形成为共面结构，有利于高分辨率显示背板的制备。
在一种实施例中，在基板20上形成开关薄膜晶体管10和驱动薄膜晶体管30的步骤还包括如下步骤：
首先，在例如玻璃、透明树脂或者石英材料制成的基板20上形成开关薄膜晶体管10的栅极11和驱动薄膜晶体管30的栅极31，如图5a所示；
在形成栅极11和31的基板20上形成栅极绝缘层12；可以选用氧化物、氮化物或者氧氮化合物，例如SiO2或SiNx材料，形成栅极绝缘层12；之后，在栅极绝缘层12的与驱动薄膜晶体管30的栅极31对应的位置形成第一过孔121，如图5a所示；
之后，在栅极绝缘层12上形成由Cu、Cr、W、Ti、Ta、Mo、Al等金属及其合金材料中的一种制成的导电层，如图5b所示，该导电层穿过第一过孔121与栅极31电连接；之后，采用构图工艺利用所述导电层分别形成开关薄膜晶体管10的源极13和漏极14、以及驱动薄膜晶体管30的源极和漏极(未示出)，而且开关薄膜晶体管的漏极14通过第一过孔121与驱动薄膜晶体管的栅极31电连接，如图5c所示。这样，通过一次构图工艺形成两个薄膜晶体管的源极和漏极，减少了构图工艺的次数，降低了掩模板的使用数量。
根据本发明的一种实施例，分别在第一钝化层15的与开关薄膜晶体管的栅极11和驱动薄膜晶体管的栅极31相对应的区域通过掺杂镓离子和锡离子而形成所述开关薄膜晶体管的有源层16和驱动薄膜晶体管的有源层(未示出)的步骤包括：如通过CVD沉积方法沉积SiNx或者氧化硅(SiO2)材料，在第一钝化层 15上形成第二钝化层17，如图5d所示；通过第二钝化层17将镓离子和锡离子分别注入到第一钝化层15的与栅极11和31相对应的区域，以对第一钝化层15的所述区域进行掺杂，以形成开关薄膜晶体管的有源层16和驱动薄膜晶体管的有源层(未示出)。
在一种实施例中，分别在第一钝化层15的与开关薄膜晶体管的栅极11和驱动薄膜晶体管的栅极31相对应的区域通过掺杂镓离子和锡离子而形成所述开关薄膜晶体管和驱动薄膜晶体管的有源层的步骤还包括如下步骤：
首先，在第二钝化层17上形成光刻胶层50，如图5e所示；采用半色调掩模板或者灰色调掩模板(未示出)对光刻胶层50的与栅极11和31对应的区域进行局部曝光，对光刻胶层50的与驱动薄膜晶体管的漏极(未示出)对应的区域进行全曝光，从而在与栅极相对应的部位形成光刻胶半保留部分51(图中未示出与栅极31相对应的光刻胶半保留部分)，在与驱动薄膜晶体管的漏极相对应的部位形成光刻胶完全去除部分52；
之后，如图5f所示，在光刻胶层50的光刻胶完全去除部分52通过干刻蚀工艺形成到达驱动薄膜晶体管的漏极的第二过孔41；
之后，如图5g所示，采用离子注入工艺在光刻胶半保留部分通过具有部分厚度的光刻胶层和第二钝化层17在第一钝化层15的与开关薄膜晶体管的栅极11和驱动薄膜晶体管的栅极31相对应的区域注入镓离子和锡离子；这样，被掺杂的区域中具有绝缘性质的第一钝化层15转换成半导体金属氧化物，即铝镓锡氧化物(AGTO)，从而使得被掺杂的区域形成开关薄膜晶体管的有源层16和驱动薄膜晶体管的有源层(未示出)；
之后；如图5h所示，剥离残余的光刻胶；最后，在第二钝化层15上形成像素电极40，像素电极40通过第二过孔41与驱动薄膜晶体管的漏极电连接，从而形成如图4所示的像素结构。
根据本发明的像素结构的制作方法，在形成源极和漏极之后，通过对覆盖在源极和漏极上的第一钝化层进行离子掺杂，而使具有绝缘性质的第一钝化层转换成半导体金属氧化物，从而使得被掺杂的区域形成有源层。有源层的两侧分别形成为覆盖在源极和漏极的远离栅极的侧部的边缘上。这样，在制作薄膜晶体管的过程中，制作源极和漏极的工艺先于制作有源层的工艺执行，使得有源层不会由于执行构图工艺形成源极和漏极而受到影响，从而不需在有源层与源极和漏极之间设置刻蚀阻挡层，简化了薄膜晶体管的结构和制作工艺。而且不需采用构图工艺形成有源层，进一步减少了掩模板的使用数量，提高了产品优良率。
在本发明进一步方面的实施例中，提供一种阵列基板的制作方法，包括上述实施例所述的制作像素结构的方法。
在一种示例性实施例中，可以采用喷墨打印工艺由石墨烯或者纳米银线制成薄膜晶体管的源极和漏极。石墨烯或者纳米银线具有良好的透光率和优良的导电性。特别是，石墨稀或者纳米银线可以形成为纳米级的细微颗粒，能够以去离子水、乙醇等为溶剂混合形成纳米导电墨水，由此可以采用喷墨打印工艺形成线宽非常小的导电丝线。这样，可以降低薄膜晶体管的尺寸，增加显示区域的尺寸，从而提高了阵列基板的开口率。另外，也可以采用喷墨打印工艺由石墨烯或者纳米银线制成薄膜晶体管的栅极。
根据本发明上述实施例的薄膜晶体管、像素结构、阵列基板、显示装置、及薄膜晶体管和像素结构的制作方法，可以将开关薄膜晶体管和驱动薄膜晶体管形成为共面结构，有利于高分辨率显示背板的制备；由于作为绝缘材料的第一钝化层通过离子掺杂形成有源层，简化了薄膜晶体管的制作工艺，可以省略刻蚀阻挡层，从而简化了薄膜晶体管的结构和制作工艺。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (22)

  1. 一种薄膜晶体管，包括栅极、源极和漏极，其特征在于，在所述源极和漏极上设有由氧化铝材料制成的第一钝化层，所述第一钝化层的与所述栅极相对应的区域具有由氧化铝材料通过掺杂离子形成的有源层。
  2. 根据权利要求1所述的薄膜晶体管，其特征在于，掺杂的离子包括镓离子和锡离子，使得被掺杂的氧化铝材料形成铝镓锡氧化物。
  3. 根据权利要求1或2所述的薄膜晶体管，其特征在于，所述薄膜晶体管为底栅薄膜晶体管，而且所述有源层的两侧分别覆盖在所述源极和漏极的远离所述栅极的侧部的边缘上。
  4. 根据权利要求1或2所述的薄膜晶体管，其特征在于，所述第一钝化层上设有第二钝化层。
  5. 一种像素结构，其特征在于，包括：
    基板；
    设置在所述基板上的驱动薄膜晶体管，所述驱动薄膜晶体管为根据权利要求1-4中的任一项所述的薄膜晶体管；以及
    设置在所述基板上的开关薄膜晶体管，所述开关薄膜晶体管为根据权利要求1-4中的任一项所述的薄膜晶体管，其中所述开关薄膜晶体管的漏极与所述驱动薄膜晶体管的栅极电连接。
  6. 根据权利要求5所述的像素结构，其特征在于，所述开关薄膜晶体管的源极和漏极、以及驱动薄膜晶体管的源极和漏极由相同的材料制成并设置在同一层。
  7. 根据权利要求5或6所述的像素结构，其特征在于，第一钝化层上设有第二钝化层。
  8. 根据权利要求7所述的像素结构，其特征在于，还包括像素电极，所述像素电极通过形成在所述第一钝化层和第二钝化层中的过孔与所述驱动薄膜晶体管的漏极电连接。
  9. 一种阵列基板，其特征在于，包括多个根据权利要求5-8中的任一项所述的像素结构。
  10. 一种显示装置，其特征在于，包括根据权利要求9所述的阵列基板。
  11. 一种薄膜晶体管的制作方法，其特征在于，包括在基板上形成薄膜晶体管，其中，在基板上形成薄膜晶体管的步骤包括：
    在所述薄膜晶体管的源极和漏极上由氧化铝材料形成第一钝化层；以及
    在所述第一钝化层的与所述薄膜晶体管的栅极相对应的区域通过掺杂离子而形成有源层。
  12. 根据权利要求11所述的方法，其特征在于，掺杂的离子包括镓离子和锡离子，使得被掺杂的氧化铝材料形成铝镓锡氧化物。
  13. 根据权利要求11或12所述的方法，其特征在于，在基板上形成薄膜晶体管的步骤还包括：
    在基板上形成栅极；
    在形成栅极的基板上形成栅极绝缘层；以及
    在所述栅极绝缘层上形成源极和漏极。
  14. 根据权利要求11-13中任一项所述的方法，其特征在于，在所述第一钝化层的与所述栅极相对应的区域通过掺杂离子而形成有源层的步骤包括：
    在所述第一钝化层上形成第二钝化层；
    通过所述第二钝化层将镓离子和锡离子注入到所述第一钝化层的与所述栅极相对应的区域。
  15. 根据权利要求14所述的方法，其特征在于，在所述第一钝化层的与所述栅极相对应的区域通过掺杂离子而形成有源层的步骤还包括：
    在所述第二钝化层上形成光刻胶层，以通过所述光刻胶层和第二钝化层注入镓离子和锡离子。
  16. 根据权利要求11-15中任一项所述的方法，其特征在于，所述有源层的两侧分别形成为覆盖在所述源极和漏极的远离所述栅极的侧部的边缘上。
  17. 一种制作像素结构的方法，其特征在于，包括在基板上形成开关薄膜晶体管和驱动薄膜晶体管，其中，在基板上形成开关薄膜晶体管和驱动薄膜晶体管的步骤包括：
    在所述开关薄膜晶体管和驱动薄膜晶体管的源极和漏极上由氧化铝材料形成第一钝化层；以及
    分别在所述第一钝化层的与所述开关薄膜晶体管和驱动薄膜晶体管的栅极相对应的区域通过掺杂离子而形成所述开关薄膜晶体管和驱动薄膜晶体管的有源层。
  18. 根据权利要求17所述的方法，其特征在于，在基板上形成开关薄膜晶体管和驱动薄膜晶体管的步骤还包括：
    在基板上形成开关薄膜晶体管和驱动薄膜晶体管的栅极；
    在形成栅极的基板上形成栅极绝缘层，并在所述栅极绝缘层的与所述驱动薄膜晶体管的栅极对应的位置形成第一过孔；
    在所述栅极绝缘层上形成导电层；以及
    采用构图工艺利用所述导电层分别形成所述开关薄膜晶体管和驱动薄膜晶体管的源极和漏极，而且所述开关薄膜晶体管的漏极通过所述第一过孔与所述驱动薄膜晶体管的栅极电连接。
  19. 根据权利要求17或18所述的方法，其特征在于，分别在所述第一钝化层的与所述开关薄膜晶体管和驱动薄膜晶体管的栅极相对应的区域通过掺杂离子而形成所述开关薄膜晶体管和驱动薄膜晶体管的有源层的步骤包括：
    在所述第一钝化层上形成第二钝化层；
    通过所述第二钝化层将镓离子和锡离子分别注入到所述第一钝化层的与所述开关薄膜晶体管和驱动薄膜晶体管的栅极相对应的区域。
  20. 根据权利要求19所述的方法，其特征在于，分别在所述第一钝化层的与所述开关薄膜晶体管和驱动薄膜晶体管的栅极相对应的区域通过掺杂离子而形成所述开关薄膜晶体管和驱动薄膜晶体管的有源层的步骤还包括：
    在所述第二钝化层上形成光刻胶层；
    采用半色调掩模板或者灰色调掩模板对光刻胶层的与所述开关薄膜晶体管和驱动薄膜晶体管的栅极对应的区域进行局部曝光，对光刻胶层的与驱动薄膜晶体管的漏极对应的区域进行全曝光；
    在光刻胶层的光刻胶完全去除部分通过刻蚀形成到达驱动薄膜晶体管的漏极的第二过孔；
    通过所述光刻胶层和第二钝化层在第一钝化层的与所述开关薄膜晶体管和驱动薄膜晶体管的栅极相对应的区域注入镓离子和锡离子；
    剥离残余的光刻胶；以及
    在所述第二钝化层上形成像素电极，所述像素电极通过第二过孔与驱动薄膜晶体管的漏极电连接。
  21. 根据权利要求17-20中任一项所述的方法，其特征在于，所述有源层的两侧分别形成为覆盖在所述源极和漏极的远离所述栅极的侧部的边缘上。
  22. 根据权利要求17-21中任一项所述的方法，其特征在于，掺杂的离子包括镓离子和锡离子，使得被掺杂的氧化铝材料形成铝镓锡氧化物。
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CN104638017A (zh) * 2015-02-04 2015-05-20 京东方科技集团股份有限公司 薄膜晶体管、像素结构及其制作方法、阵列基板、显示装置

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