WO2017173712A1 - 薄膜晶体管及其制作方法、阵列基板、显示装置 - Google Patents

薄膜晶体管及其制作方法、阵列基板、显示装置 Download PDF

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WO2017173712A1
WO2017173712A1 PCT/CN2016/082609 CN2016082609W WO2017173712A1 WO 2017173712 A1 WO2017173712 A1 WO 2017173712A1 CN 2016082609 W CN2016082609 W CN 2016082609W WO 2017173712 A1 WO2017173712 A1 WO 2017173712A1
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gate
layer
film transistor
thin film
substrate
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PCT/CN2016/082609
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English (en)
French (fr)
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王美丽
闫梁臣
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京东方科技集团股份有限公司
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Priority to US15/529,645 priority Critical patent/US10622483B2/en
Publication of WO2017173712A1 publication Critical patent/WO2017173712A1/zh

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    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a thin film transistor and a method of fabricating the same, an array substrate, and a display device.
  • polycrystalline silicon especially low temperature polysilicon thin film transistors, have gradually replaced amorphous silicon thin film transistors with higher electron mobility, better liquid crystal characteristics and less leakage current. Become the mainstream of thin film transistors.
  • the structure of the existing polysilicon thin film transistor is as shown in FIG. 1 , and includes a base substrate 1 , an active layer 2 on the base substrate 1 , a gate insulating layer 3 on the active layer 2 , and a gate electrode.
  • the channel of the offset region cannot receive the voltage of the gate, which is increased.
  • the resistance of the carrier transfer reduces the on-state current of the thin film transistor.
  • the present disclosure provides a thin film transistor and a method of fabricating the same, an array substrate, and a display device for increasing an on-state current of a thin film transistor and improving current characteristics of the thin film transistor.
  • a base substrate a gate insulating layer and a gate disposed above the base substrate;
  • a conductive layer is further disposed between the gate insulating layer and the gate;
  • the projection of the conductive layer on the base substrate is larger than the projection of the gate on the base substrate.
  • the thin film transistor provided by the embodiment of the present disclosure further includes: an active layer disposed between the base substrate and the gate insulating layer.
  • a projection of the conductive layer on the substrate substrate and a projection of the active layer on the substrate substrate are at least partially overlapping.
  • the material of the conductive layer includes one or more of a conductive carbon material, a metal material, and a metal oxide.
  • the thin film transistor provided by the embodiment of the present disclosure further includes: a source region electrically connected to the source to be formed and disposed opposite to the active layer And a drain region for electrically connecting to the drain to be formed.
  • the thin film transistor provided by the embodiment of the present disclosure further includes: a source and a drain located above the gate.
  • the thin film transistor provided by the embodiment of the present disclosure further includes: an interlayer dielectric layer between the source and the drain and the gate; wherein
  • the source is electrically connected to the source region through a first via hole penetrating through the interlayer dielectric layer and the gate insulating layer, and the drain passes through the interlayer dielectric layer and the gate insulating layer
  • the second via is electrically connected to the drain region.
  • an embodiment of the present disclosure further provides an array substrate, including any of the above-mentioned thin film transistors provided by the embodiments of the present disclosure.
  • the above array substrate provided by the embodiment of the present disclosure further includes: a flat layer and a pixel electrode layer sequentially located above the thin film transistor; wherein
  • the pixel electrode is electrically connected to a drain of the thin film transistor through a contact hole.
  • an embodiment of the present disclosure further provides a display device, including any of the above array substrates provided by the embodiments of the present disclosure.
  • an embodiment of the present disclosure further provides a method for fabricating a thin film transistor, the method comprising:
  • the projection of the pattern of the electrical layer on the substrate is greater than the projection of the gate on the substrate.
  • the method before the forming the pattern of the gate insulation, the method further includes: forming an active layer on the substrate picture of.
  • the projection of the conductive layer on the substrate substrate and the active layer on the base substrate The projections on at least partially overlap.
  • the patterning process is used to process the conductive layer and form a pattern of the conductive layer, including:
  • the conductive layer is plasma bombarded by a plasma process such that a projection of the pattern of the conductive layer on the substrate is greater than a projection of the active layer on the substrate.
  • the same layer as the active layer is formed and disposed opposite to be formed.
  • the method for fabricating the above thin film transistor provided by the embodiment of the present disclosure further includes forming a pattern of a source and a drain after forming a pattern of the gate.
  • the method further includes:
  • the second via is used to electrically connect the drain to be formed to the drain region.
  • the material of the conductive layer includes one or more of a conductive carbon material, a metal material, and a metal oxide.
  • the thin film transistor provided by the embodiment of the present disclosure, the manufacturing method thereof, the array substrate, In the display panel, the thin film transistor includes a base substrate, a gate insulating layer formed over the base substrate, a gate formed over the gate insulating layer, and a gate insulating layer and a gate electrode a conductive layer therebetween; wherein a projection of the conductive layer on the base substrate is greater than a projection of the gate on the base substrate.
  • a conductive layer is disposed between the gate insulating layer and the gate, and a projection of the conductive layer on the substrate is larger than the gate is Projecting on the substrate, so that the projection of the conductive layer on the substrate covers the projection of the gate on the substrate, that is, the cross-sectional width of the conductive layer is larger than the cross-sectional width of the gate, so that the gate and the thin film transistor have A conductive layer electrically connected to the gate exists in the offset region between the source layers.
  • the voltage of the offset region can be increased by the action of the conductive layer, and the resistance of the carrier can be reduced, thereby increasing the on-state current of the thin film transistor and improving the current characteristics of the thin film transistor.
  • FIG. 1 is a schematic structural view of a thin film transistor provided by the prior art
  • FIG. 2 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of another thin film transistor according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic flow chart of a method for fabricating a thin film transistor according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a method for fabricating a thin film transistor according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • a thin film transistor provided by an embodiment of the present disclosure includes:
  • a conductive layer 05 is further disposed between the gate insulating layer 03 and the gate electrode 04; wherein the projection of the conductive layer 05 on the substrate substrate is greater than the projection of the gate electrode 04 on the substrate substrate.
  • an active layer 02 disposed between the base substrate 01 and the gate insulating layer 03 is further included.
  • a conductive layer is disposed between the gate insulating layer and the gate, and a projection of the conductive layer on the substrate substrate is larger than a projection of the gate on the substrate. Therefore, the projection of the conductive layer on the substrate substrate covers the projection of the gate on the substrate, that is, the cross-sectional width of the conductive layer is larger than the cross-sectional width of the gate, so that the offset region P between the gate and the active layer exists and A conductive layer that is electrically connected to the gate.
  • the voltage of the offset region can be increased by the action of the conductive layer, and the resistance of the carrier can be reduced, thereby increasing the on-state current of the thin film transistor and improving the current characteristics of the thin film transistor.
  • the above-described thin film transistor provided by the embodiment of the present disclosure is described by taking a top gate type structure as an example.
  • the thin film transistor provided by the embodiment of the present disclosure may also be a bottom gate type structure, which is not specifically limited herein.
  • the above thin film transistor provided by the embodiment of the present disclosure is generally a top gate type structure, that is, the gate is located above the active layer. This is because the material of the active layer is polysilicon, and the preparation of polysilicon generally requires high temperatures, and the high temperature affects the film layer underneath. Therefore, in the above thin film transistor provided by the embodiment of the present disclosure, referring to FIG. 2, the gate electrode 04 is located above the active layer 02.
  • the projection of the conductive layer 05 on the substrate substrate 01 partially overlaps with the projection of the active layer 02 on the substrate substrate 01.
  • the projection of the conductive layer 05 on the base substrate 01 overlaps with the projection of the active layer 02 on the base substrate 01.
  • the conductive layer is provided to cover the offset region P between the active layer and the gate.
  • the thin film transistor provided by the embodiment of the present disclosure is electrically conductive.
  • the material of layer 05 includes one or more of a conductive carbon material, a metal material, and a metal oxide.
  • the conductive layer may be composed of a carbon material or a metal material.
  • the metal oxide may include one or more of an oxide of indium (In), zinc (Zn), gallium (Ga), and tin (Sn), which is not limited herein.
  • the thin film transistor provided by the embodiment of the present disclosure further includes: a source region electrically connected to the source to be formed in the same layer and opposite to the active layer 02 06 and a drain region 07 for electrically connecting to the drain to be formed.
  • the source region and the drain region may be formed simultaneously with the active layer or form a source region and a drain region after forming the active layer. This is not specifically limited.
  • the thin film transistor provided by the embodiment of the present disclosure further includes a source 08 and a drain 09 located above the gate 04.
  • the drain of the thin film transistor when a thin film transistor is applied to a display panel, the drain of the thin film transistor generally needs to be electrically connected to the pixel electrode located above it. Therefore, as shown in FIG. 4, the source 08 and the drain 09 are both located above the gate 04.
  • the source and the drain may be located above the gate or below the gate, as long as the gate and the source and the drain are ensured. It can be insulated, and is not limited herein.
  • the thin film transistor further includes: an interlayer dielectric layer 10 between the source 08 and the drain 09 and the gate 04, wherein the source The pole 08 is electrically connected to the source region 06 through the first via 11 penetrating through the interlayer dielectric layer 10 and the gate insulating layer 03, and the drain 09 passes through the first of the interlayer dielectric layer 10 and the gate insulating layer 03.
  • the two vias 12 are electrically connected to the drain region 07.
  • an embodiment of the present disclosure further provides a method for fabricating a thin film transistor. Referring to FIG. 5, the method includes:
  • step S501 a pattern of a gate insulating layer is formed on the base substrate
  • step S502 forming a conductive layer on the gate insulating layer
  • step S503 a pattern of gate electrodes is formed on the conductive layer
  • step S504 the conductive layer is processed by a patterning process and a pattern of the conductive layer is formed such that the projection of the pattern of the conductive layer on the substrate substrate is greater than the projection of the gate on the substrate.
  • a conductive layer is formed on the gate insulating layer on the conductive layer.
  • a pattern of the gate is formed, and then the conductive layer is processed to form a pattern of the conductive layer such that the projection of the conductive layer on the substrate is greater than the projection of the gate on the substrate.
  • a conductive layer is added between the gate insulating layer and the gate, and the projection of the conductive layer on the substrate covers the projection of the gate on the substrate, that is, the cross-sectional width of the conductive layer is larger than the gate.
  • the width of the pole is such that there is a conductive layer electrically connected to the gate in the offset region between the gate and the active layer.
  • the voltage of the offset region can be increased by the action of the conductive layer, and the resistance of the carrier can be reduced, thereby increasing the on-state current of the thin film transistor and improving the current characteristics of the thin film transistor.
  • the method before forming the pattern of the gate insulation, the method further includes: forming a pattern of the active layer on the substrate.
  • the projection of the pattern of the conductive layer on the substrate substrate at least partially overlaps the projection of the active layer on the substrate.
  • the projection of the pattern of the conductive layer on the substrate substrate overlaps with the projection of the active layer on the substrate substrate such that the disposed conductive layer covers the offset region between the active layer and the gate.
  • the formation of the pattern of the conductive layer may be formed simultaneously by one patterning process, or may be formed by two patterning processes, which is not limited herein.
  • the pattern of the conductive layer may be formed after the pattern of the gate is formed, the conductive layer is processed by a patterning process to form a pattern of the conductive layer, or the patterning process may be used to form the conductive layer before the pattern of the gate is formed.
  • a pattern of the conductive layer is formed. This is not specifically limited.
  • the conductive layer under the gate is processed.
  • the patterning process is used to process the conductive layer and form a pattern of the conductive layer, including plasma bombarding the conductive layer by a plasma process to make the conductive layer
  • the projection of the pattern on the substrate substrate is greater than the projection of the gate on the substrate.
  • the plasma can be used before the gate insulating layer is dry-etched.
  • the conductive layer outside the region corresponding to the source layer is subjected to plasma bombardment so that the conductive layer outside the region corresponding to the active layer is removed.
  • the conductive layer may be etched by a dry etching process, or other patterning process, which is not specifically limited in the embodiment of the present disclosure.
  • the same layer as the active layer is formed and disposed opposite to the source to be formed. a source region and a drain region for electrically connecting to a drain to be formed.
  • the gate electrode may be formed after the source region and the drain region are formed. Since the temperature required for forming the active layer of the polysilicon material is relatively high, the high temperature affects the film layer located underneath, and therefore, in the above fabrication method, after the pattern of the source region and the drain region is formed, the formation is performed. The pattern of the gate.
  • the gate when a pattern of a gate is formed after forming a pattern of a source region and a drain region which are disposed in the same layer and disposed opposite to the active layer, the gate may be The pattern is prepared simultaneously with the pattern of the source and the drain.
  • the pattern of the gate is formed to form a pattern of the source and the drain.
  • the pattern of the source and the drain may be formed to form a pattern of the gate. This is not limited here.
  • a pattern of a source and a drain is formed.
  • the drain of the thin film transistor when the thin film transistor is used to control a pixel unit in the display panel, the drain of the thin film transistor generally needs to be electrically connected to the pixel electrode in the pixel unit, and the pixel electrode is generally located above the thin film transistor. Therefore, in the above fabrication method provided by the embodiment of the present disclosure, the pattern of the gate is formed before the pattern of the source and the drain is formed. Since the source and the drain are located above the gate, it is convenient to electrically connect the drain to the pixel electrode.
  • the pattern of the source and the drain may be formed simultaneously by using one patterning process, or may be separately formed by two patterning processes, which is not limited herein. .
  • the pattern of the source and the drain is simultaneously formed by one patterning process.
  • the method for fabricating the above thin film transistor in order to insulate the gate from the source and the drain, a pattern of the source and the drain is formed after the pattern of the gate is formed.
  • the method further includes: forming an interlayer dielectric layer covering the gate; Forming a first via and a second via extending through the interlayer dielectric layer and the gate insulating layer, the first via is used to electrically connect the source to be formed, and the second via is used for The drain and drain regions to be formed are electrically connected.
  • the method for fabricating the above thin film transistor provided by the embodiment of the present disclosure is described below by using a specific embodiment.
  • the preparation method comprises the following steps:
  • a buffer layer 13 is formed on the base substrate 01, wherein the buffer layer 13 comprises a single layer film or a multilayer film of silicon oxide, silicon nitride, or silicon oxynitride, as shown in Fig. 6a.
  • a pattern of the active layer 02 is formed on the buffer layer 13, as shown in Fig. 6b.
  • a source region 06 for electrically connecting to the source to be formed and a source for electrically connecting to the drain to be formed are formed in the same layer of the active layer 02 by a patterning process. Drain region 07, as shown in Figure 6c.
  • a gate insulating layer 03 covering the active layer 02 and the source region 06 and the drain region 07 is formed as shown in FIG. 6d.
  • a conductive layer 05 covering the gate insulating layer 03 is formed as shown in Fig. 6e.
  • a pattern of the gate electrode 04 is formed as shown in Fig. 6f.
  • the conductive layer 05 in Fig. 6f is subjected to plasma bombardment to form a pattern as shown in Fig. 6g.
  • the interlayer dielectric layer 10 is formed as shown in Fig. 6h.
  • the first via hole 11 and the second via hole 12 penetrating the interlayer dielectric layer 10 and the gate insulating layer 03 are formed as shown in Fig. 6i.
  • a pattern of the source electrode 08 and the drain electrode 09 is formed, wherein the source electrode 08 is electrically connected to the source region 06 through the first via hole 11, and the drain electrode 09 passes through the second via hole 12 and the drain region. 07 is electrically connected, as shown in Figure 6j.
  • the thin film transistor is formed by the above steps, wherein the second, third, sixth, ninth and tenth steps each require patterning to pattern.
  • the patterning process may include only a photolithography process, or may include a photolithography process and an etching process, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, and the like.
  • the photolithography process refers to a process of forming a pattern using a photoresist, a mask, an exposure machine, or the like including a process of film formation, exposure, development, and the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present disclosure.
  • an embodiment of the present disclosure further provides an array substrate, as shown in FIG. 7 , including any of the above-described thin film transistors 200 provided by the embodiments of the present disclosure. Since the principle of solving the problem of the array substrate is similar to that of the above-mentioned thin film transistor, the implementation of the array substrate can be referred to the implementation of the above-mentioned thin film transistor, and the repeated description will not be repeated.
  • the method further includes: a planarization layer 201 and a pixel electrode 202 sequentially disposed above the thin film transistor 200, wherein the pixel electrode 202 passes through the via and the film The drains 09 in the transistor 200 are electrically connected.
  • the above-mentioned array substrate provided by the embodiment of the present disclosure can be applied to a liquid crystal display panel, and can also be applied to an organic electroluminescence display panel, which is not limited herein.
  • the pixel electrode refers to a pixel electrode in the liquid crystal display panel; when the array substrate is applied to the organic electroluminescence display panel, the pixel electrode may refer to a cathode layer in the organic electrode illuminating pixel structure or Anode layer.
  • an embodiment of the present disclosure further provides a display device, including any of the above array substrates provided by the embodiments of the present disclosure.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device refer to the embodiment of the above array substrate, and the repeated description is omitted.
  • the thin film transistor includes a base substrate, and a gate insulating layer formed over the base substrate is formed over the gate insulating layer a gate electrode, and a conductive layer formed between the gate insulating layer and the gate electrode; wherein a projection of the conductive layer on the substrate substrate is greater than a gate of the gate substrate on the substrate substrate projection.
  • a conductive layer is disposed between the gate insulating layer and the gate, and a projection of the conductive layer on the substrate is larger than the gate is Projection on the substrate, such that the projection of the conductive layer on the substrate covers the projection of the gate on the substrate, ie the cross-sectional width of the conductive layer is greater than the cross-sectional width of the gate such that between the gate and the active layer
  • a conductive layer electrically connected to the gate in the offset region.

Abstract

一种薄膜晶体管及其制作方法、阵列基板、显示装置，用以增大薄膜晶体管的开态电流，提高薄膜晶体管的电流特性。所述薄膜晶体管，包括衬底基板（01），设置在所述衬底基板（01）上的栅极绝缘层（03）和栅极（04）；其中，在所述栅极绝缘层（03）与栅极（04）之间还设置有导电层（05）；其中，所述导电层（05）在所述衬底基板（01）上的投影大于所述栅极（04）在所述衬底基板（01）上的投影。

Description

薄膜晶体管及其制作方法、阵列基板、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及薄膜晶体管及其制作方法、阵列基板、显示装置。
背景技术
与非晶硅(a-Si)薄膜晶体管相比，多晶硅尤其是低温多晶硅薄膜晶体管具有更高的电子迁移率、更好的液晶特性以及较少的漏电流，已经逐渐取代非晶硅薄膜晶体管，成为薄膜晶体管的主流。
目前，现有的多晶硅薄膜晶体管的结构如图1所示，包括衬底基板1、位于衬底基板1上的有源层2、位于有源层2上的栅极绝缘层3、位于栅极绝缘层3上的栅极4、位于栅极4上的介质层5、与有源层同层且相对设置的用于与源极电性相连的源极区域6和用于与漏极电性相连的漏极区域7、以及位于介质层5上的源极8和漏极9；且源极8和漏极9分别通过贯穿介质层5和栅极绝缘层3的过孔与源极区域6和漏极区域7电连接。
在上述多晶硅薄膜晶体管中，由于薄膜晶体管栅极4与有源层2之间的沟道存在偏移区(offset)P，使得offset区域的沟道不能接收到栅极的电压作用，增大了载流子传输的电阻，减小了薄膜晶体管的开态电流。
因此，如何改善多晶硅薄膜晶体管的开态电流是本领域技术人员亟待解决的技术问题。
发明内容
本公开提供一种薄膜晶体管及其制作方法、阵列基板、显示装置，用以增大薄膜晶体管的开态电流，提高薄膜晶体管的电流特性。
本公开实施例提供了一种薄膜晶体管，包括：
衬底基板，设置在所述衬底基板上方的栅极绝缘层和栅极；
其中，在所述栅极绝缘层与栅极之间还设置有导电层；
其中，所述导电层在所述衬底基板上的投影大于所述栅极在所述衬底基板上的投影。
在一种可能的实施方式中，本公开实施例提供的上述薄膜晶体管中，还包括：设置在所述衬底基板和所述栅极绝缘层之间的有源层。
在一种可能的实施方式中，本公开实施例提供的上述薄膜晶体管中，所述导电层在所述衬底基板上的投影与所述有源层在所述衬底基板上的投影至少部分重叠。
在一种可能的实施方式中，本公开实施例提供的上述薄膜晶体管中，所述导电层的材料包括具有导电性的碳材料、金属材料和金属氧化物中的一个或多个。
在一种可能的实施方式中，本公开实施例提供的上述薄膜晶体管中，还包括：与所述有源层同层且相对设置的用于与待形成的源极电性相连的源极区域和用于与待形成的漏极电性相连的漏极区域。
在一种可能的实施方式中，本公开实施例提供的上述薄膜晶体管中，还包括：位于所述栅极上方的源极和漏极。
在一种可能的实施方式中，本公开实施例提供的上述薄膜晶体管中，还包括：位于所述源极和所述漏极与所述栅极之间的层间介质层；其中，
所述源极通过贯穿所述层间介质层和栅极绝缘层中的第一过孔与所述源极区域电性相连，所述漏极通过贯穿所述层间介质层和栅极绝缘层中的第二过孔与所述漏极区域电性相连。
相应地，本公开实施例还提供了一种阵列基板，包括本公开实施例提供的上述任一种薄膜晶体管。
在一种可能的实施方式中，本公开实施例提供的上述阵列基板中，还包括：依次位于所述薄膜晶体管上方的平坦层和像素电极层；其中，
所述像素电极通过接触孔与所述薄膜晶体管中的漏极电性相连。
相应地，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述任一种阵列基板。
相应地，本公开实施例还提供了一种薄膜晶体管的制作方法，该方法包括：
在衬底基板上形成栅极绝缘层的图案；
在所述栅极绝缘层上形成导电层；
在所述导电层上形成栅极的图案；
采用构图工艺处理所述导电层并形成导电层的图案，使得所述导 电层的图案在所述衬底基板上的投影大于所述栅极在所述衬底基板上的投影。
在一种可能的实施方式中，本公开实施例提供的上述薄膜晶体管的制作方法中，在形成所述栅极绝缘的图案之前，该方法还包括：在所述衬底基板上形成有源层的图案。
在一种可能的实施方式中，本公开实施例提供的上述薄膜晶体管的制作方法中，所述导电层的图案在所述衬底基板上的投影与所述有源层在所述衬底基板上的投影至少部分重叠。
在一种可能的实施方式中，本公开实施例提供的上述薄膜晶体管的制作方法中，采用构图工艺处理所述导电层并形成导电层的图案，包括：
采用等离子体工艺对所述导电层进行等离子轰击，使得所述导电层的图案在所述衬底基板上的投影大于所述有源层在所述衬底基板上的投影。
在一种可能的实施方式中，本公开实施例提供的上述薄膜晶体管的制作方法中，在形成有源层的同时，形成与所述有源层同层且相对设置的用于与待形成的源极电性相连的源极区域和用于与待形成的漏极电性相连的漏极区域。
在一种可能的实施方式中，本公开实施例提供的上述薄膜晶体管的制作方法中，还包括在形成所述栅极的图案之后，形成源极和漏极的图案。
在一种可能的实施方式中，本公开实施例提供的上述薄膜晶体管的制作方法中，在形成所述栅极的图案之后，并且在形成源极和漏极的图案之前，还包括：
形成覆盖所述栅极的层间介质层；
形成贯穿所述层间介质层和栅极绝缘层中的第一过孔和第二过孔，所述第一过孔用于使待形成的源极与所述源极区域电性相连，所述第二过孔用于使待形成的漏极与所述漏极区域电性相连。
在一种可能的实施方式中，本公开实施例提供的上述薄膜晶体管的制作方法中，所述导电层的材料包括具有导电性的碳材料、金属材料和金属氧化物中的一个或多个。
在本公开实施例提供的上述薄膜晶体管及其制作方法、阵列基板、 显示面板中，薄膜晶体管包括衬底基板，形成在所述衬底基板上方的栅极绝缘层，形成在所述栅极绝缘层上方的栅极，以及设置在所述栅极绝缘层与栅极之间的导电层；其中，所述导电层在所述衬底基板上的投影大于所述栅极在所述衬底基板上的投影。与现有技术相比，在本公开实施例提供的薄膜晶体管中，通过在栅极绝缘层和栅极之间设置导电层，且导电层位于衬底基板上的投影大于所述栅极在所述衬底基板上的投影，因此导电层在衬底基板上的投影覆盖栅极在衬底基板上的投影，即导电层的截面宽度大于栅极的截面宽度，使得栅极与薄膜晶体管的有源层之间的offset区域中存在与栅极电性相连的导电层。当栅极中存在电压时，可以通过导电层的作用增加offset区域的电压，减小载流子的电阻，从而增加薄膜晶体管的开态电流，提高薄膜晶体管的电流特性。
附图说明
图1为现有技术提供的一种薄膜晶体管的结构示意图；
图2为本公开实施例提供的一种薄膜晶体管的结构示意图；
图3为本公开实施例提供的另一种薄膜晶体管的结构示意图；
图4为本公开实施例提供的又一种薄膜晶体管的结构示意图；
图5为本公开实施例提供的一种薄膜晶体管的制作方法的流程示意图；
图6a至图6j为本公开实施例提供的薄膜晶体管的制作方法对应的结构示意图；
图7为本公开实施例提供的一种阵列基板的结构示意图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开作进一步地详细描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本公开保护的范围。
下面结合附图，对本公开实施例提供的薄膜晶体管及其制作方法、阵列基板、显示装置的具体实施方式进行详细地说明。
应当说明的是，附图中各膜层厚度和形状不反映薄膜晶体管的真实比例，目的只是示意说明本公开内容。
参见图2，本公开实施例提供的一种薄膜晶体管，包括：
衬底基板01，设置在衬底基板01上方的栅极绝缘层03和栅极04；
其中，在栅极绝缘层03与栅极04之间还设置有导电层05；其中，导电层05在衬底基板上的投影大于栅极04在衬底基板上的投影。
在具体实施例中，本公开实施例提供的上述薄膜晶体管中，参见图2，还包括设置在衬底基板01和栅极绝缘层03之间的有源层02。
在本公开实施例提供的上述薄膜晶体管中，在栅极绝缘层和栅极之间设置导电层，且导电层在衬底基板上的投影大于栅极在衬底基板上的投影。因此导电层在衬底基板上的投影覆盖栅极在衬底基板上的投影，即导电层的截面宽度大于栅极的截面宽度，使得栅极与有源层之间的offset区域P中存在与栅极电性相连的导电层。当栅极中存在电压时，可以通过导电层的作用增加offset区域的电压，减小载流子的电阻，从而增加薄膜晶体管的开态电流，提高薄膜晶体管的电流特性。
在本公开中，以顶栅型结构为例来说明本公开实施例提供的上述薄膜晶体管。然而，如本领域技术人员将领会到的，本公开实施例提供的薄膜晶体管也可以为底栅型结构，在此不做具体限定。
本公开实施例提供的上述薄膜晶体管一般为顶栅型结构，即栅极位于有源层的上方。这是由于有源层的材料为多晶硅，而多晶硅的制备一般需要高温，而高温会对位于其下方的膜层造成影响。因此，本公开实施例提供的上述薄膜晶体管中，参见图2，栅极04位于有源层02的上方。
在具体实施例中，本公开实施例提供的上述薄膜晶体管中，参见图2，导电层05在衬底基板01上的投影与有源层02在衬底基板01上的投影部分重叠。可替换地，参见图3，导电层05在衬底基板01上的投影与有源层02在衬底基板01上的投影重叠。在这种情况下，所设置的导电层覆盖有源层与栅极之间的offset区域P。当栅极存在电压时，通过导电层的作用，将栅极的电压施加在包括offset区域在内的整个有源层，从而减小载流子的电阻，增加薄膜晶体管的开态电流，进一步提高薄膜晶体管的电流特性。
在具体实施例中，本公开实施例提供的上述薄膜晶体管中，导电 层05的材料包括具有导电性的碳材料、金属材料和金属氧化物中的一个或多个。具体地，导电层可以由碳材料组成，也可以由金属材料组成。金属氧化物可以包含有铟(In)、锌(Zn)、镓(Ga)、锡(Sn)的氧化物中的一种或多种，在此不作限定。
在具体实施例中，本公开实施例提供的上述薄膜晶体管中，参见图4，还包括：与有源层02同层且相对设置的用于与待形成的源极电性相连的源极区域06和用于与待形成的漏极电性相连的漏极区域07。
源极区域和漏极区域可以和有源层同时形成，或者在形成有源层后形成源极区域和漏极区域。在此不做具体限定。
在具体实施例中，本公开实施例提供的上述薄膜晶体管中，参见图4，还包括位于栅极04上方的源极08和漏极09。在具体实施时，当薄膜晶体管应用于显示面板时，薄膜晶体管的漏极一般需要与位于其上方的像素电极电连接。因此，如图4所示，源极08和漏极09均位于栅极04的上方。
进一步地，当本公开实施例提供的上述薄膜晶体管为顶栅型结构时，源极和漏极可以位于栅极的上方，也可以位于栅极的下方，只要保证栅极与源极和漏极均绝缘即可，在此不作限定。
在具体实施例中，本公开实施例提供的上述薄膜晶体管中，参见图4，薄膜晶体管还包括：位于源极08和漏极09与栅极04之间的层间介质层10，其中，源极08通过贯穿层间介质层10和栅极绝缘层03中的第一过孔11与源极区域06电性相连，漏极09通过贯穿层间介质层10和栅极绝缘层03中的第二过孔12与漏极区域07电性相连。
基于同一公开思想，本公开实施例还提供了一种薄膜晶体管的制作方法，参见图5，该方法包括：
在步骤S501中，在衬底基板上形成栅极绝缘层的图案；
在步骤S502中，在栅极绝缘层上形成导电层；
在步骤S503中，在导电层上形成栅极的图案；
在步骤S504中，采用构图工艺处理导电层并形成导电层的图案，使得导电层的图案在衬底基板上的投影大于栅极在衬底基板上的投影。
本公开实施例提供的薄膜晶体管的制作方法中，在衬底基板上形成栅极绝缘层的图案之后，在栅极绝缘层上形成导电层，在导电层上 形成栅极的图案，然后处理导电层形成导电层的图案，使得导电层在衬底基板上的投影大于栅极在衬底基板上的投影。与现有技术相比，在栅极绝缘层和栅极之间增加导电层，且导电层在衬底基板上的投影覆盖栅极在衬底基板上的投影，即导电层的截面宽度大于栅极的截面宽度，使得栅极与有源层之间的offset区域中存在与栅极电性相连的导电层。当栅极中存在电压时，可以通过导电层的作用增加offset区域的电压，减小载流子的电阻，从而增加薄膜晶体管的开态电流，提高薄膜晶体管的电流特性。
在具体实施例中，本公开实施例提供的上述薄膜晶体管的制作方法中，在形成栅极绝缘的图案之前，该方法还包括：在衬底基板上形成有源层的图案。
在具体实施例中，本公开实施例提供的上述薄膜晶体管的制作方法中，导电层的图案在衬底基板上的投影与有源层在衬底基板上的投影至少部分重叠。例如，导电层的图案在衬底基板上的投影与有源层在衬底基板上的投影重叠，使得所设置的导电层覆盖有源层与栅极之间的offset区域。当栅极存在电压时，通过导电层的作用，将栅极的电压施加在包括offset区域在内的整个有源层，从而减小载流子的电阻，增加薄膜晶体管的开态电流，进一步提高薄膜晶体管的电流特性。
具体地，导电层的图案的形成可以采用一次构图工艺同时形成，也可以采用两次构图工艺形成，在此不作限定。
需要说明的是，导电层的图案的形成可以在栅极的图案形成之后，采用构图工艺对导电层进行处理形成导电层的图案，也可以在形成栅极的图案之前，采用构图工艺对导电层进行处理形成导电层的图案。在此不做具体限定。
为了使得形成的导电层的图案可以位于offset区域，因此在形成栅极绝缘层之后，形成整层的导电层，在导电层上形成栅极的图案后，对栅极下方的导电层进行处理。
在具体实施例中，本公开实施例提供的上述薄膜晶体管的制作方法中，采用构图工艺处理导电层并形成导电层的图案，包括采用等离子体工艺对所述导电层进行等离子轰击，使得导电层的图案在衬底基板上的投影大于栅极在衬底基板上的投影。
具体地，可以在对栅极绝缘层进行干刻之前，采用等离子体对有 源层所对应的区域之外的导电层进行等离子体轰击，使得有源层所对应的区域之外的导电层去除掉。也可以干刻工艺对导电层进行刻蚀，或者其他构图工艺，本公开实施例不做具体限定。
在具体实施例中，本公开实施例提供的上述薄膜晶体管的制作方法中，在形成有源层的同时，形成与有源层同层且相对设置的用于与待形成的源极电性相连的源极区域和用于与待形成的漏极电性相连的漏极区域。
需要说明的是，本公开实施例提供的上述薄膜晶体管的制作方法中，可以在形成源极区域和漏极区域之后形成栅极。由于形成多晶硅材料的有源层时所需的温度比较高，高温会对位于其下方的膜层造成影响，因此，在上述制作方法中，在形成源极区域和漏极区域的图案之后，形成栅极的图案。
进一步地，在本公开实施例提供的上述制备方法中，当在形成与有源层同层设置且相对设置的源极区域和漏极区域的图案之后形成栅极的图案时，可以将栅极的图案与源极和漏极的图案同时制备，也可以先形成栅极的图案再形成源极和漏极的图案，当然也可以先形成源极和漏极的图案再形成栅极的图案，在此不作限定。
在具体实施例中，本公开实施例提供的上述薄膜晶体管的制作方法中，形成所述栅极的图案之后，形成源极和漏极的图案。
在具体实施时，当薄膜晶体管用于控制显示面板中的像素单元时，薄膜晶体管的漏极一般需要与像素单元中的像素电极电连接，而像素电极一般位于薄膜晶体管的上方。因此，在本公开实施例提供的上述制作方法中，在形成源极和漏极的图案之前，形成栅极的图案。由于源极和漏极位于栅极的上方，因而便于将漏极与像素电极电性相连。
在具体实施时，在本公开实施例提供的上述薄膜晶体管的制作方法中，源极和漏极的图案可以是采用一次构图工艺同时形成，也可以采用两次构图工艺分别形成，在此不作限定。
可替换地，在本公开实施例提供的上述制备方法中，采用一次构图工艺同时形成源极和漏极的图案。
在具体实施例中，本公开实施例提供的上述薄膜晶体管的制作方法中，为了使栅极与源极和漏极均绝缘，在形成栅极的图案之后，在形成源极和漏极的图案之前，还包括：形成覆盖栅极的层间介质层； 形成贯穿所述层间介质层和栅极绝缘层中的第一过孔和第二过孔，第一过孔用于使待形成源极与源极区域电性相连，第二过孔用于使待形成的漏极与漏极区域电性相连。
下面通过一个具体的实施例说明本公开实施例提供的上述薄膜晶体管的制备方法。所述制备方法包括以下步骤：
在第一步骤中，在衬底基板01上形成缓冲层13，其中缓冲层13包括氧化硅、氮化硅、或者氮氧化硅的单层膜或者多层膜，如图6a所示。
在第二步骤中，在缓冲层13上形成有源层02的图案，如图6b所示。
在第三步骤中，通过一次构图工艺在有源层02同层形成相对设置的用于与待形成的源极电性相连的源极区域06和用于与待形成的漏极电性相连的漏极区域07，如图6c所示。
在第四步骤中，形成覆盖有源层02以及源极区域06和漏极区域07的栅极绝缘层03，如图6d所示。
在第五步骤中，形成覆盖栅极绝缘层03的导电层05，如图6e所示。
在第六步骤中，形成栅极04的图案，如图6f所示。
在第七步骤中，对图6f中的导电层05进行等离子体轰击，形成如图6g的图案。
在第八步骤中，形成层间介质层10，如图6h所示。
在第九步骤中，形成贯穿层间介质层10和栅极绝缘层03的第一过孔11和第二过孔12，如图6i所示。
在第十步骤中，形成源极08和漏极09的图案，其中，源极08通过第一过孔11与源极区域06电性相连，漏极09通过第二过孔12与漏极区域07电性相连，如图6j所示。
通过上述步骤形成薄膜晶体管，其中第二、第三、第六、第九和第十步骤均需要采用构图工艺进行构图。构图工艺可只包括光刻工艺，或，可以包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图案的工艺。光刻工艺是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图案的工艺。在具体实施时，可根据本公开中所形成的结构选择相应的构图工艺。
基于同一发明构思，本公开实施例还提供了一种阵列基板，如图7所示，包括本公开实施例提供的上述任一种薄膜晶体管200。由于该阵列基板解决问题的原理与上述一种薄膜晶体管相似，因此该阵列基板的实施可以参见上述薄膜晶体管的实施，重复之处不再赘述。
进一步地，在本公开实施例提供的上述阵列基板中，如图7所示，还包括：依次位于薄膜晶体管200上方的平坦化层201和像素电极202，其中，像素电极202通过过孔与薄膜晶体管200中的漏极09电性相连。
具体地，本公开实施例提供的上述阵列基板可以应用于液晶显示面板，也可以应用于有机电致发光显示面板，在此不作限定。
当上述阵列基板应用于液晶显示面板时，像素电极指液晶显示面板中的像素电极；当上述阵列基板应用于有机电致发光显示面板时，像素电极可以指有机电极发光像素结构中的阴极层或阳极层。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述任一种阵列基板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述阵列基板的实施例，重复之处不再赘述。
在本公开实施例提供的上述薄膜晶体管及其制作方法、阵列基板、显示面板中，薄膜晶体管包括衬底基板，形成在衬底基板上方的栅极绝缘层，形成在所述栅极绝缘层上方的栅极，以及形成在所述栅极绝缘层与栅极之间的导电层；其中，所述导电层在所述衬底基板上的投影大于所述栅极在所述衬底基板上的投影。现有技术相比，在本公开实施例提供的薄膜晶体管中，通过在栅极绝缘层和栅极之间设置导电层，且导电层位于衬底基板上的投影大于所述栅极在所述衬底基板上的投影，因此导电层在衬底基板上的投影覆盖栅极在衬底基板上的投影，即导电层的截面宽度大于栅极的截面宽度，使得栅极与有源层之间的offset区域中存在与栅极电性相连的导电层。当栅极中存在电压时，可以通过导电层的作用增加offset区域的电压，减小载流子的电阻，从而增加薄膜晶体管的开态电流，提高薄膜晶体管的电流特性。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些 改动和变型在内。

Claims (18)

  1. 一种薄膜晶体管，包括：
    衬底基板，设置在所述衬底基板上方的栅极绝缘层和栅极；
    其中，在所述栅极绝缘层与栅极之间还设置有导电层；
    其中，所述导电层在所述衬底基板上的投影大于所述栅极在所述衬底基板上的投影。
  2. 根据权利要求1所述的薄膜晶体管，还包括：设置在所述衬底基板和所述栅极绝缘层之间的有源层。
  3. 根据权利要求2所述的薄膜晶体管，其中，所述导电层在所述衬底基板上的投影与所述有源层在所述衬底基板上的投影至少部分重叠。
  4. 根据权利要求1所述的薄膜晶体管，其中，所述导电层的材料包括具有导电性的碳材料、金属材料和金属氧化物中的一个或多个。
  5. 根据权利要求2所述的薄膜晶体管，还包括：与所述有源层同层且相对设置的用于与待形成的源极电性相连的源极区域和用于与待形成的漏极电性相连的漏极区域。
  6. 根据权利要求5所述的薄膜晶体管，还包括：位于所述栅极上方的源极和漏极。
  7. 根据权利要求6所述的薄膜晶体管，还包括：位于所述源极和所述漏极与所述栅极之间的层间介质层；其中，
    所述源极通过贯穿所述层间介质层和栅极绝缘层中的第一过孔与所述源极区域电性相连，所述漏极通过贯穿所述层间介质层和栅极绝缘层中的第二过孔与所述漏极区域电性相连。
  8. 一种阵列基板，包括权利要求1-7任一权项所述的薄膜晶体管。
  9. 根据权利要求8所述的阵列基板，还包括：依次位于所述薄膜晶体管上方的平坦层和像素电极层；其中，
    所述像素电极通过接触孔与所述薄膜晶体管中的漏极电性相连。
  10. 一种显示装置，包括如权利要求8或9所述的阵列基板。
  11. 一种薄膜晶体管的制作方法，包括：
    在衬底基板上形成栅极绝缘层的图案；
    在所述栅极绝缘层上形成导电层；
    在所述导电层上形成栅极的图案；
    采用构图工艺处理所述导电层并形成导电层的图案，使得所述导电层的图案在所述衬底基板上的投影大于所述栅极在所述衬底基板上的投影。
  12. 根据权利要求11所述的方法，其中，在形成所述栅极绝缘的图案之前，该方法还包括：
    在所述衬底基板上形成有源层的图案。
  13. 根据权利要求12所述的方法，其中，所述导电层的图案在所述衬底基板上的投影与所述有源层在所述衬底基板上的投影至少部分重叠。
  14. 根据权利要求11所述的方法，其中，采用构图工艺处理所述导电层并形成导电层的图案，包括：
    采用等离子体工艺对所述导电层进行等离子轰击，使得所述导电层的图案在所述衬底基板上的投影大于所述栅极在所述衬底基板上的投影。
  15. 根据权利要求12所述的方法，其中，在形成有源层的同时，形成与所述有源层同层且相对设置的用于与待形成的源极电性相连的源极区域和用于与待形成的漏极电性相连的漏极区域。
  16. 根据权利要求15所述的方法，还包括，在形成所述栅极的图案之后，形成源极和漏极的图案。
  17. 根据权利要求16所述的方法，其中，在形成所述栅极的图案之后，并且在形成源极和漏极的图案之前，还包括：
    形成覆盖所述栅极的层间介质层；
    形成贯穿所述层间介质层和栅极绝缘层中的第一过孔和第二过孔，所述第一过孔用于使待形成的源极与所述源极区域电性相连，所述第二过孔用于使待形成的漏极与所述漏极区域电性相连。
  18. 根据权利要求11-17任一权项所述的方法，其中，所述导电层的材料包括具有导电性的碳材料、金属材料和金属氧化物中的一个或多个。
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