WO2015096355A1 - 阵列基板及其制作方法、显示装置 - Google Patents
阵列基板及其制作方法、显示装置 Download PDFInfo
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- WO2015096355A1 WO2015096355A1 PCT/CN2014/077378 CN2014077378W WO2015096355A1 WO 2015096355 A1 WO2015096355 A1 WO 2015096355A1 CN 2014077378 W CN2014077378 W CN 2014077378W WO 2015096355 A1 WO2015096355 A1 WO 2015096355A1
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- thin film
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- 239000000758 substrate Substances 0.000 title claims abstract description 119
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000010409 thin film Substances 0.000 claims abstract description 149
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims description 44
- 239000004065 semiconductor Substances 0.000 claims description 39
- 229920005591 polysilicon Polymers 0.000 claims description 35
- 230000008569 process Effects 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 238000000059 patterning Methods 0.000 claims description 19
- 230000000295 complement effect Effects 0.000 claims description 8
- 230000008901 benefit Effects 0.000 description 12
- 239000010408 film Substances 0.000 description 11
- 239000013078 crystal Substances 0.000 description 10
- 238000002425 crystallisation Methods 0.000 description 10
- 230000008025 crystallization Effects 0.000 description 10
- 239000004020 conductor Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000002161 passivation Methods 0.000 description 4
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- -1 oxygen oxide compound Chemical class 0.000 description 2
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
Definitions
- Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
- an Organic Light-Emitting Diode (OLED) display and a Cathode Ray Tube (CRT) display or a Thin Film Transistor-Liquid Crystal Display (Thin Film Transistor-Liquid Crystal Display, TFT-LCD) OLED display has become a next-generation display device due to its lighter and thinner design, wider viewing angle, faster response speed, and lower power consumption. People's attention.
- the OLED display device is a self-luminous device which generally includes a pixel electrode, a counter electrode disposed opposite to the pixel electrode, and an organic light-emitting layer disposed between the pixel electrode and the counter electrode.
- the OLED display device enables electrons and holes to recombine with each other in the organic light-emitting layer by applying a voltage to the pixel electrode and the counter electrode to form an electric field across the organic light-emitting layer disposed between the pixel electrode and the counter electrode. Glowing.
- the display effect of the OLED display device can be controlled by controlling the voltage applied to the pixel electrode by the array substrate having the circuit unit. Summary of the invention
- At least one embodiment of the present invention provides an array substrate, including: a substrate, a plurality of complementary thin film transistors on the substrate, the plurality of complementary thin film transistors including an N-type first thin film transistor and P A second thin film transistor of the type, the first thin film transistor is an oxide thin film transistor, and the second thin film transistor is a polysilicon thin film transistor.
- the first thin film transistor includes: a first gate, a first source, and a first drain; and the second thin film transistor includes a second gate, a second source, and a second drain, The first gate and the second source and the second drain are formed by one patterning process.
- the second gate is formed by a patterning process with the first source and the first drain.
- a polysilicon semiconductor active layer, a gate insulating layer, a second gate metal layer, an oxide semiconductor active layer, a dielectric layer, and a first gate metal layer are sequentially disposed on the substrate;
- the second second gate metal metal layer package includes: the second second gate electrode, the first first source and the source, and the Said first first drain drain;
- the first first gate metal metal layer package includes: the first first gate electrode, the second second source and the source, and the The second second leak
- first source and drain electrodes and the first drain drain electrode are in direct contact with the active source layer of the oxygen oxide compound semi-conductive conductor body.
- the second electrical source and the second and second drains Connected to the second electrical source and the second and second drains, and the second and second drains are passed through the via and with the polycrystalline silicon silicon
- the semi-conductive conductor body has an active source layer electrical connection. .
- the array array substrate board further includes a plurality of sub-pixel pixel single cells, and each of the sub-images
- the 1100-element single-element package includes a first thin film film crystal tube and the second second thin film crystal tube, and the first The one drain drain electrode is electrically connected to the second second gate gate through the interconnective connection electrode.
- the array array substrate substrate further includes an image pixel electrode, and the pixel electrode is The second second drain drain is electrically connected to the second. .
- the present invention provides at least one embodiment of the invention, and provides a method for fabricating an array substrate substrate, the package comprising: 1155 on the base substrate a polycrystalline crystalline silicon semi-conductive conductor having an upper upper surface formed into a second second thin film film crystal tube has an active source layer;
- An oxy-oxide hydride semi-conductive conductor formed on the substrate substrate having the first thin film film crystal tube has an active source layer; and 2200 at the Forming a second second source electrode and a second second drain drain of the second second thin film film transistor on the base substrate, and the first thin a first first gate of the thin film film transistor.
- the second second thin film is formed on the substrate substrate by a one-time construction process.
- the second second gate of the memristive crystal tube and the first source of the first thin film crystal tube The poles and the first first drain drain are described. .
- the second and second thin forms are formed on the base substrate by the one-time construction process.
- the second and second drain source poles of the thin film film crystal tube and the second and second drain drain electrodes and the first thin film crystal of the first thin film The first first gate of the body tube. .
- the crystalline silicon silicon semi-conductive conductor has an active source layer package including:
- the doped polysilicon layer is doped.
- the second source and the second drain of the second thin film transistor and the first gate of the first thin film transistor are formed on the substrate,
- connection electrode is formed on the substrate, and the connection electrode is connected to the first drain and the second gate, respectively.
- the method further includes:
- a pixel electrode is formed on the substrate, and the pixel electrode is electrically connected to the second drain.
- At least one embodiment of the present invention provides a display device comprising the array substrate of any of the embodiments of the present invention.
- 1 is a top plan view showing a partial structure of an array substrate
- Figure 2 is a cross-sectional view taken along line A-A of Figure 1;
- FIG. 3 is a cross-sectional view of an array substrate according to an embodiment of the present invention.
- FIG. 4 is a cross-sectional view of another array substrate according to an embodiment of the present invention.
- FIG. 5 is a schematic structural view of a substrate on which a polysilicon semiconductor active layer is formed
- FIG. 6 is a schematic structural view of a substrate on which a first source, a first drain, and a second gate are formed;
- FIG. 7 is a schematic structural view of a substrate on which an active layer of an oxide semiconductor is formed;
- FIG. 8 is a schematic structural view of a substrate on which a second source, a second drain, and a first gate are formed; and FIG. 9 is a schematic structural view of a substrate on which a connection electrode is formed.
- CMOS complementary thin film transistor
- the CMOS fabrication process is mainly to form a pattern required for a device such as a thin film transistor on each thin film layer therein by a patterning process.
- This requires multiple patterning processes. For example, it is common to require eleven mask lithography processes and three doping processes to complete, and the cost of each patterning process is expensive. Therefore, the inventors have noticed that for the fabrication of OLED display devices based on CMOS fabrication driving circuits, the number of patterning processes and complicated fabrication steps are constraints that hinder their development; moreover, to adapt to the lighter and thinner development of OLED display devices. Demand, how to reasonably reduce its thickness is also an urgent problem to be solved.
- the "patterning process” is a process of forming a film into a layer containing at least one pattern.
- the patterning process generally comprises: coating a photoresist on the film, exposing the photoresist by using a mask, etching the photoresist to be removed by using a developing solution, and etching away the uncovered photoresist. The film portion is finally stripped of the remaining photoresist.
- “one-time patterning process” refers to a layer structure process required for one exposure to form.
- At least one embodiment of the present invention provides an array substrate comprising: a plurality of complementary thin film transistors.
- the complementary thin film transistor includes an N-type first thin film transistor (TFT) and a P-type second thin film transistor.
- the first thin film transistor is an oxide thin film transistor
- the second thin film transistor is a polysilicon thin film transistor.
- the array substrate divides a plurality of sub-pixel units on the substrate by horizontally and vertically intersecting gate lines and data lines.
- the active layer of the oxide thin film transistor (also referred to as the thin film transistor) is an oxide semiconductor layer
- the active layer of the polysilicon thin film transistor (also referred to as the thin film transistor) is a polysilicon semiconductor layer.
- the oxide forming the oxide semiconductor layer may be Indium Gallium Zinc Oxide (IGZO), Mg-Indium-Ox-Oxygen (Mg-In-Zn-0,
- FIG. 1 shows an array substrate. Taking the same pixel unit of the CMOS two transistors in the OLED display device as an example, each of the sub-pixel units includes one switching thin film transistor 11 (first thin film transistor) and one driving thin film transistor 12 (second thin film transistor). Grid The line 13 is connected to the gate of the switching thin film transistor 11, that is, the first gate 111, and the data line 14 is connected to the source of the switching thin film transistor 11, that is, the first source 112, and the first drain 113 of the switching thin film transistor 11 is passed through. The hole a is connected to the second gate 121 which is the gate of the driving thin film transistor 12.
- the Vdd line 15 parallel to the data line 14 is connected to the source of the driving thin film transistor 12, that is, the second source 122, and the second drain 123 of the driving thin film transistor 12 is connected to the pixel electrode 16.
- 2 is a cross-sectional view taken along line AA of FIG. 1.
- two TFTs are formed on the substrate 10, and the bottom gate structure is uniformly used, and the first gate 111 and the second gate 121 are sequentially formed on the second gate 111 and the second gate 121.
- the first drain electrode 113 is connected to the connection electrode 17 through the via hole a
- the second gate electrode 121 is connected to the connection electrode 17 through the via hole b.
- the connection electrode 17 can connect the first drain 113 and the second gate 121.
- the first thin film transistor and the second thin film transistor in the general technology are both polysilicon thin film transistors. Since the second thin film transistor is a PMOS transistor, the first thin film transistor is an NMOS transistor, and the array substrate needs to be formed when forming an active layer of the PMOS transistor.
- One P+ doping (P+ doping), N+ doping (N+ doping) and LDD doping (LDD doping) are required to form the source and drain of the NMOS transistor, and the source-drain source of the active layer is formed by doping. Drain zone.
- P+ doping P+ doping
- N+ doping N+ doping
- LDD doping LDD doping
- polysilicon thin film transistors generally require ion implantation and at least two crystallizations. In the embodiment of the present invention, only one crystallization is performed, the number of crystallizations can be reduced, the time is saved, and the production cost is reduced.
- the first thin film transistor in the complementary thin film transistor (CMOS) on the array substrate is an oxide thin film transistor
- the second thin film transistor is a polysilicon thin film transistor. Since the second thin film transistor only needs to be doped once, the oxide thin film transistor can be directly formed by deposition without doping and crystallization, and at least two doping processes and one crystallization are reduced with respect to the general technique. It simplifies the production process and reduces the production difficulty and production cost of the product.
- the array substrate further includes a positive power input Vdd line 15.
- the second source of the second thin film transistor in the sub-pixel unit of the same row may be connected to the Vdd line, and the source signal is supplied to the second source through the Vdd line.
- the first thin film transistor includes: a first gate 111, a first source 112, and a first drain 113.
- the second thin film transistor includes a second gate 121, a second source 122, and a second drain 123.
- the first gate 111 and the second source 122 and the second drain The pole 123 is formed by a patterning process. That is, the first gate of the first thin film transistor and the second source and the second drain of the second thin film transistor are formed by one patterning process.
- the second gate 121 and the first source 111 and the first drain 112 are formed by one patterning process. That is, the first source and the first drain of the first thin film transistor and the second gate of the second thin film transistor are formed by one patterning process.
- the array substrate includes a substrate, and a polysilicon semiconductor active layer, a gate insulating layer, a second gate metal layer, an oxide semiconductor active layer, a dielectric layer, and a first gate metal layer sequentially disposed on the substrate .
- the second gate metal layer includes: a second gate, a first source, and a first drain.
- the first gate metal layer includes: a first gate, a second source, and a second drain. The first source and the first drain are in direct electrical contact with the oxide semiconductor active layer. The second source and the second drain are electrically connected to the polysilicon semiconductor active layer through via holes.
- the array substrate includes a substrate 10 and a polysilicon semiconductor active layer, a gate insulating layer, a second gate metal layer, an oxide semiconductor active layer, and a dielectric layer sequentially disposed on the substrate 10. And a first gate metal layer.
- the polysilicon semiconductor active layer includes a second active layer 1062.
- the second gate metal layer includes: a second gate 121, a first source 112, and a first drain 113.
- the oxide semiconductor active layer includes a first active layer 1061.
- the first gate metal layer includes a first gate 111 and a second source 122 and a second drain 123.
- the first source 112 and the first drain 123 are in direct contact with the oxide semiconductor active layer, that is, the first active layer 1061, and electrically connect the second source 122 and the second drain 123 through the via and the
- the polysilicon semiconductor active layer, that is, the second active layer 1062 is electrically connected.
- the second active layer forms a corresponding source and drain region by doping in a region corresponding to the second source and the second drain, and the source and drain are respectively connected to the source and drain regions of the active layer.
- the array substrate includes a plurality of sub-pixel units, each of the sub-pixel units includes a first thin film transistor 11 and a second thin film transistor 12, and the first drain
- the second gate 121 is electrically connected to the second gate 121 through the connection electrode 17.
- Each of the sub-pixel units includes a first thin film transistor 11 and a second thin film transistor 12, the first thin film transistor is a switching thin film transistor, and the second thin film transistor is a driving thin film transistor.
- the functions of the first thin film transistor and the second thin film transistor may be different according to different structures of the array substrate. The embodiments of the present invention are described by way of example only.
- the array substrate further includes a pixel electrode, and the pixel electrode is electrically connected to the second drain.
- the array substrate further includes a pixel electrode 16, and as shown in FIG. The pixel electrode 16 is electrically connected to the second drain 123 through the via c, and the current signal is supplied to the pixel electrode 16 through the second drain 123.
- the array substrate further includes a pixel electrode 16, and the pixel electrode 16 is electrically connected to the second drain electrode 123 through the via hole, and the current signal is supplied to the pixel electrode 16 through the second drain electrode 123.
- the array substrate provided by the embodiment of the present invention is not limited to the array substrate shown in FIG. 3 and FIG. 4, and other thin film or layer structure array substrates can be formed according to the structure of the existing array substrate.
- the positions of the first thin film transistor and the second thin film transistor of FIG. 3 and FIG. 4 in the embodiment of the present invention are only examples.
- the positions of the first thin film transistor and the second thin film transistor may be Variety.
- the first thin film transistor may not necessarily be disposed under the pixel electrode 16.
- the embodiment of the invention further provides a method for fabricating an array substrate, comprising:
- Step 101 Form a polysilicon semiconductor active layer of the second thin film transistor on the substrate.
- a polysilicon semiconductor active layer (second active layer) 1062 is formed on the substrate 10.
- the above step 101 includes:
- Step 1011 A polysilicon layer semiconductor active layer is formed on the substrate.
- the formation of the polycrystalline silicon semiconductor active layer is formed, for example, by forming single crystal silicon on the substrate and then performing crystallization.
- Step 1012 Doping the polysilicon layer semiconductor active layer.
- the doping of the polysilicon layer semiconductor active layer is performed, for example, by ion implantation. Doping the both ends of the polysilicon layer semiconductor active layer may form a source region and a drain region corresponding to the source and drain electrodes on the polysilicon semiconductor active layer.
- Step 102 Form a gate insulating layer on the substrate.
- Step 103 Form a second gate of the second thin film transistor and a first source and a first drain of the first thin film transistor on the substrate.
- the second gate electrode 121 of the second thin film transistor and the first source electrode 112 and the first drain electrode 113 of the first thin film transistor are formed on the substrate by one patterning process, that is, by one exposure.
- a data line and a Vdd line are further formed on the substrate, and the data line is connected to the first source, Providing a source signal to the first source; the Vdd line is connected to the second source, To provide a source signal to the second source.
- Step 104 Form an oxide semiconductor active layer of the first thin film transistor on the substrate.
- an oxide semiconductor active layer (first active layer) 1061 is formed at a position corresponding to the first source 112 and the first drain 113.
- the material forming the active layer of the oxide semiconductor may be IGZO, MIZO or the like.
- Step 105 Form a second source and a second drain of the second thin film transistor and a first gate of the first thin film transistor on the substrate.
- the method further includes forming a dielectric layer 102 on the substrate, as shown in FIG.
- the second source 122 and the second drain 123 of the second thin film transistor 12 and the first gate 111 of the first thin film transistor are formed on the substrate 10 by one patterning process.
- the second source 122 is electrically connected to the Vdd line through a via (not shown).
- the method further includes: A connection electrode 17 is formed on the substrate 10, and the connection electrode 17 is connected to the first drain electrode 113 and the second gate electrode 121, respectively.
- connection electrodes 17 are connected to the first drain 113 and the second gate 121 through vias a and b, respectively, to electrically connect the first drain 113 and the second gate 121.
- the method further includes: forming a pixel electrode on the substrate, and the pixel electrode is electrically connected to the second drain.
- the array substrate further includes a pixel electrode 16, and as shown in FIG. 1, the pixel electrode 16 is electrically connected to the second drain 123 through a via, and is controlled to the pixel electrode by the second drain 123. 16 provides a current signal.
- the array substrate further includes a pixel electrode 16, and the pixel electrode is electrically connected to the second drain electrode 123 through the via hole, and the current signal is supplied to the pixel electrode 16 through the second drain electrode 123.
- the array substrate provided by the embodiment of the present invention is not limited to the array substrate shown in FIG. 3 and FIG. 4, and other thin film or layer structure array substrates may be formed according to the structure of the array substrate.
- the method for fabricating the array substrate provided by the embodiment of the present invention is not limited to the above method.
- the thin film transistors are classified into two types according to the relationship between the gate and the source and drain of the thin film transistor.
- One type is that the gate is located under the source and the drain, and this type is called a bottom gate type thin film transistor;
- the class is where the gate is above the source and drain.
- This type of device is called a top-gate thin film transistor.
- the array substrate provided by the embodiment of the present invention is described by taking the first thin film transistor as a top gate thin film transistor and the second thin film transistor as a bottom gate thin film transistor.
- the first thin film transistor on the array substrate may also be a bottom gate thin film transistor, and the second thin film transistor may also be a top gate thin film transistor. If this method is used, the above fabrication sequence needs to be adjusted accordingly, but The production method is similar to the above.
- An array substrate known in the prior art requires two crystallizations to form a polysilicon thin film transistor and 13 mask exposures to form a gate layer, a gate insulating layer, an active layer, a P+ doping, and an N+ doping, respectively. , LDD doping, dielectric layer, source and drain electrode layer, passivation layer, connection electrode layer, planarization layer, pixel electrode, and pixel defining layer.
- the method for fabricating the array substrate performs one crystallization and 12 mask exposures to form a polysilicon semiconductor active layer, a P+ doping, a gate insulating layer, and a second gate metal layer (including the first source, the first a drain and a second gate), an oxide semiconductor active layer, a dielectric layer, a first gate metal layer (including a second source, a second drain, and a first gate), a passivation layer, and a connection electrode layer
- the planarization layer, the pixel electrode and the pixel defining layer form an array substrate as shown in FIG.
- a polysilicon semiconductor active layer a P+ doping, a gate insulating layer, and a second gate metal layer (including a first source, a first drain, and a second gate) by one crystallization and nine mask exposures, respectively
- the method for fabricating an array substrate is a method for fabricating a polysilicon thin film transistor by forming an oxide first thin film transistor and a polysilicon second thin film transistor on a substrate, and the first thin film transistor and the second thin film transistor are At least two doping and one crystallization processes are reduced, thus simplifying the manufacturing process and reducing the production difficulty and production cost of the product.
- the embodiment of the invention provides a display device comprising the array substrate according to any one of the embodiments of the present invention.
- the display device may be a liquid crystal display device, an OLED display device, and any display product or component of a television, a digital camera, a mobile phone, a tablet computer, or the like including the display device.
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Abstract
一种阵列基板及其制作方法、显示装置。该阵列基板包括:基板(10),位于该基板(10)之上的多个互补型薄膜晶体管,该多个互补型薄膜晶体管包括N型的第一薄膜晶体管(11)和P型的第二薄膜晶体管(12),该第一薄膜晶体管(11)为氧化物薄膜晶体管,该第二薄膜晶体管(12)为多晶硅薄膜晶体管。该阵列基板具有简化的制作工艺,降低了产品生产难度和生产成本。
Description
阵列基板及其制作方法、 显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制作方法、 显示装置。 背景技术
在现有的各种显示装置中, 由于有机发光二极管 ( Organic Light-Emitting Diode, OLED )显示器与阴极射线管 (Cathode Ray Tube, CRT ) 显示器或薄膜晶体管液晶显示器( Thin Film Transistor-Liquid Crystal Display, TFT-LCD ) 相比具有更轻和更薄的外观设计、 更宽的可视视角、 更快的响应速度以及更低的功耗等特点, 因此 OLED显示器已逐渐成为下 一代显示设备而备受人们的关注。
OLED显示装置是自发光装置,其通常包括像素电极、与像素电极相对 设置的对电极以及设置于像素电极与对电极之间的有机发光层。 OLED显示 装置通过将电压施加到包括像素电极和对电极上以使设置于像素电极和对 电极之间的有机发光层两端形成电场, 从而使得电子和空穴能够在有机发 光层中彼此复合而发光。 可以通过具有电路单元的阵列基板控制施加在像 素电极上的电压来控制 OLED显示装置的显示效果。 发明内容
本发明的至少一个实施例提供了一种阵列基板, 包括: 基板, 位于所 述基板之上的多个互补型薄膜晶体管, 所述多个互补型薄膜晶体管包括 N 型的第一薄膜晶体管和 P型的第二薄膜晶体管, 所述第一薄膜晶体管为氧 化物薄膜晶体管, 以及所述第二薄膜晶体管为多晶硅薄膜晶体管。
在一个示例中, 所述第一薄膜晶体管包括: 第一栅极、 第一源极和第 一漏极; 所述第二薄膜晶体管包括第二栅极、 第二源极和第二漏极, 所述 第一栅极与所述第二源极以及第二漏极经过一次构图工艺形成。
在一个示例中, 所述第二栅极与所述第一源极以及第一漏极经过一次 构图工艺形成。
在一个示例中, 所述基板上依次设置有多晶硅半导体有源层、 栅绝缘 层、 第二栅金属层、 氧化物半导体有源层、 介质层以及第一栅金属层; 其
中中,,
所所述述第第二二栅栅金金属属层层包包括括:: 所所述述第第二二栅栅极极、、 所所述述第第一一源源极极和和所所述述第第一一漏漏 极极;;
所所述述第第一一栅栅金金属属层层包包括括:: 所所述述第第一一栅栅极极、、 所所述述第第二二源源极极和和所所述述第第二二漏漏
55 极极;;
其其中中,, 所所述述第第一一源源极极和和所所述述第第一一漏漏极极与与氧氧化化物物半半导导体体有有源源层层直直接接接接触触 电电连连接接,, 所所述述第第二二源源极极和和所所述述第第二二漏漏极极通通过过过过孔孔与与所所述述多多晶晶硅硅半半导导体体有有源源 层层电电连连接接。。
在在一一个个示示例例中中,, 所所述述阵阵列列基基板板还还包包括括多多个个子子像像素素单单元元,, 每每一一所所述述子子像像 1100 素素单单元元包包括括第第一一薄薄膜膜晶晶体体管管和和所所述述第第二二薄薄膜膜晶晶体体管管,, 且且所所述述第第一一漏漏极极与与所所 述述第第二二栅栅极极通通过过连连接接电电极极电电连连接接。。
在在一一个个示示例例中中,, 所所述述阵阵列列基基板板还还包包括括像像素素电电极极,, 且且所所述述像像素素电电极极与与所所 述述第第二二漏漏极极电电连连接接。。
本本发发明明的的至至少少一一个个实实施施例例提提供供了了阵阵列列基基板板的的制制作作方方法法,, 包包括括:: 1155 在在基基板板上上形形成成第第二二薄薄膜膜晶晶体体管管的的多多晶晶硅硅半半导导体体有有源源层层;;
在在所所述述基基板板上上形形成成栅栅绝绝缘缘层层;;
在在所所述述基基板板上上形形成成第第二二薄薄膜膜晶晶体体管管的的第第二二栅栅极极以以及及第第一一薄薄膜膜晶晶体体管管的的 第第一一源源极极和和第第一一漏漏极极;;
在在所所述述基基板板上上形形成成第第一一薄薄膜膜晶晶体体管管的的氧氧化化物物半半导导体体有有源源层层;; 以以及及 2200 在在所所述述基基板板上上形形成成第第二二薄薄膜膜晶晶体体管管的的第第二二源源极极和和第第二二漏漏极极以以及及第第一一薄薄 膜膜晶晶体体管管的的第第一一栅栅极极。。
在在一一个个示示例例中中,, 通通过过一一次次构构图图工工艺艺在在所所述述基基板板上上形形成成所所述述第第二二薄薄膜膜晶晶 体体管管的的所所述述第第二二栅栅极极以以及及所所述述第第一一薄薄膜膜晶晶体体管管的的所所述述第第一一源源极极和和所所述述第第一一 漏漏极极。。
2255 在在一一个个示示例例中中,, 通通过过一一次次构构图图工工艺艺在在所所述述基基板板上上形形成成所所述述第第二二薄薄膜膜晶晶 体体管管的的所所述述第第二二源源极极和和所所述述第第二二漏漏极极以以及及所所述述第第一一薄薄膜膜晶晶体体管管的的所所述述第第一一 栅栅极极。。
在在一一个个示示例例中中,, 所所述述在在基基板板上上形形成成所所述述第第二二薄薄膜膜晶晶体体管管的的所所述述多多晶晶硅硅 半半导导体体有有源源层层包包括括::
对对所所述述多多晶晶硅硅层层进进行行掺掺杂杂。。
在一个示例中, 在所述基板上形成所述第二薄膜晶体管的所述第二源 极和所述第二漏极以及所述第一薄膜晶体管的所述第一栅极之后,
在所述基板上形成连接电极, 所述连接电极分别与所述第一漏极和所 述第二栅极连接。
在一个示例中, 所述方法还包括:
在所述基板上形成像素电极, 且所述像素电极与所述第二漏极电连接。 本发明的至少一个实施例提供了一种显示装置, 包括本发明实施例提 供的任一所述的阵列基板。 附图说明
以下将结合附图对本发明的实施例进行更详细的说明, 以使本领域普通 技术人员更加清楚地理解本发明, 其中:
图 1为一种阵列基板的局部结构俯视图;
图 2为图 1的 A-A向剖视图;
图 3为本发明实施例提供的一种阵列基板的剖视图;
图 4为本发明实施例提供的另一种阵列基板的剖视图;
图 5为形成有多晶硅半导体有源层的基板结构示意图;
图 6为形成有第一源极、 第一漏极以及第二栅极的基板结构示意图; 图 7为形成有氧化物半导体有源层的基板结构示意图;
图 8为形成有第二源极、 第二漏极以及第一栅极的基板结构示意图; 图 9为形成有连接电极的基板结构示意图。 具体实施方式
下面将结合本发明实施例中的附图, 对本发明实施例中的技术方案进行 清楚、 完整地描述。 显然, 所描述的实施例仅仅是本发明一部分实施例, 而 不是全部的实施例。 基于本发明中的实施例, 本领域普通技术人员在无需创 造性劳动前提下所获得的所有其他实施例, 都属于本发明保护的范围。
除非另作定义, 本文使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一"、 "第二" 以及类似的词语并不表示任何顺序、 数 量或者重要性, 而只是用来区分不同的组成部分。 同样, "一个"、 "一"或者
"该"等类似词语也不表示数量限制, 而是表示存在至少一个。 "包括 "或者 "包含" 等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后 面列举的元件或者物件及其等同,而不排除其他元件或者物件。 "上"、 "下"、 等仅用于表示相对位置关系, 当被描述对象的绝对位置改变后, 则该相对位 置关系也可能相应地改变。
在 OLED显示装置中, 在驱动电路部分经常会用到互补型薄膜晶体管 ( CMOS )。 CMOS制作工艺主要是通过构图工艺在其内的各薄膜层上形成 如薄膜晶体管等器件所需的图形。 这就需要进行多次构图工艺。 例如, 通 常需要十一次的掩模光刻工艺以及三次掺杂工艺才能制作完成, 而每次构 图工艺所需的资金很昂贵。 因此, 发明人注意到, 对于基于 CMOS制作驱 动电路的 OLED显示装置制作而言, 构图工艺的次数、 复杂的制作步骤是 制约其发展的难题; 而且, 为适应 OLED显示装置更轻更薄的发展需求, 如何合理地减小其厚度也是急需解决的问题。
需要说明的是, "构图工艺" 是将薄膜形成包含至少一个图案的层的工 艺。 构图工艺通常包含: 在薄膜上涂光刻胶, 利用掩模板对所述光刻胶进行 曝光, 再利用显影液将需去除的光刻胶冲蚀掉, 再刻蚀掉未覆盖光刻胶的薄 膜部分,最后将剩下的光刻胶剥离。而在本发明所有实施例中, "一次构图工 艺" 是指经过一次曝光形成所需要的层结构工艺。
本发明的至少一个实施例提供了一种阵列基板, 包括: 多个互补型薄 膜晶体管。 所述互补型薄膜晶体管包括 N型的第一薄膜晶体管(TFT )和 P 型的第二薄膜晶体管。 所述第一薄膜晶体管为氧化物薄膜晶体管, 所述第 二薄膜晶体管为多晶硅薄膜晶体管。
需要说明的是, 阵列基板由横纵交叉的栅线和数据线在基板上划分出 多个子像素单元。 所述氧化物薄膜晶体管 (也称为所述薄膜晶体管) 的有 源层为氧化物半导体层, 所述多晶硅薄膜晶体管 (也称为所述薄膜晶体管) 的有源层为多晶硅半导体层。 形成所述氧化物半导体层的氧化物可以是铟 镓辞氧化物 (Indium Gallium Zinc Oxide, IGZO)、 镁 -铟-辞-氧( Mg-In-Zn-0,
MIZO )等。
图 1示出一种阵列基板。 以 CMOS的两个晶体管设置在 OLED显示器 件中的同一个像素单元为例, 每一个子像素单元包括一个开关薄膜晶体管 11 (第一薄膜晶体管)和一个驱动薄膜晶体管 12 (第二薄膜晶体管) 。 栅
线 13与开关薄膜晶体管 11的栅极即第一栅极 111连接, 数据线 14与开关 薄膜晶体管 11的源极即第一源极 112相连, 开关薄膜晶体管 11的第一漏 极 113透过过孔 a连接到驱动薄膜晶体管 12的栅极即第二栅极 121。 平行 于数据线 14的 Vdd线 15连接到驱动薄膜晶体管 12的源极即第二源极 122, 驱动薄膜晶体管 12的第二漏极 123与像素电极 16连接。图 2为图 1的 A-A 向截面图, 由图 2可知, 两个 TFT形成于基板 10上, 且均釆用底栅结构, 在第一栅极 111和第二栅极 121上依次还形成有栅绝缘层 101、多晶硅有源 层 106、 介质层 102、 钝化层 103、 平坦层 104 以及像素界定层 105。 第一 漏极 113通过过孔 a与连接电极 17相连, 第二栅极 121通过过孔 b与连接 电极 17相连。 这样, 连接电极 17可以连接第一漏极 113与第二栅极 121。
一般技术中的第一薄膜晶体管和第二薄膜晶体管均为多晶硅薄膜晶体 管, 由于第二薄膜晶体管为 PMOS管, 第一薄膜晶体管为 NMOS管, 且阵 列基板在形成 PMOS管的有源层时需要进行一次 P+掺杂(P+ doping ), 在 形成 NMOS管的源漏极时需要进行 N+掺杂( N+ doping )和 LDD掺杂( LDD doping ) ,并通过掺杂形成有源层对应源漏极的源漏区。但掺杂的工艺复杂, 需要曝光才能形成、 设备成本高。
另外, 多晶硅薄膜晶体管一般需要进行离子注入, 再进行至少两次晶 化。 本发明实施例中只需进行一次晶化, 可以减少晶化的次数, 节省了时 间, 且降低了生产成本。 本发明实施例中, 所述阵列基板上的互补型薄膜 晶体管( CMOS )中的第一薄膜晶体管为氧化物薄膜晶体管, 所述第二薄膜 晶体管为多晶硅薄膜晶体管。 由于第二薄膜晶体管只需进行一次掺杂, 氧 化物薄膜晶体管可以通过沉积直接形成而无需进行掺杂和晶化, 相对于一 般技术至少减少了两次掺杂工艺和一次晶化。 简化了制作工艺, 降低了产 品的生产难度和生产成本。
另外, 如图 1所示, 阵列基板还包括正电源输入 Vdd线 15。 在实际应 用中, 位于同一行的子像素单元中的第二薄膜晶体管的第二源极均可以与 该 Vdd线相连接, 通过该 Vdd线向第二源极提供源极信号。 由于图 3为图
1的局部剖视图, 则该 Vdd线在图 3中未示出。
可选的, 如图 3所示, 所述第一薄膜晶体管包括: 第一栅极 111、 第一 源极 112和第一漏极 113。 所述第二薄膜晶体管包括第二栅极 121、 第二源 极 122和第二漏极 123。所述第一栅极 111与所述第二源极 122以及第二漏
极 123 经过一次构图工艺形成。 即, 所述第一薄膜晶体管的第一栅极与所 述第二薄膜晶体管的第二源极和第二漏极通过一次构图工艺形成。
可选的, 如图 3所示, 所述第二栅极 121与所述第一源极 111以及第 一漏极 112 经过一次构图工艺形成。 即, 所述第一薄膜晶体管的第一源极 和第一漏极与所述第二薄膜晶体管的第二栅极通过一次构图工艺形成。
可选的, 所述阵列基板包括基板以及依次设置在所述基板上的多晶硅 半导体有源层、 栅绝缘层、 第二栅金属层、 氧化物半导体有源层、 介质层 以及第一栅金属层。 所述第二栅金属层包括: 第二栅极、 第一源极和第一 漏极。 所述第一栅金属层包括: 第一栅极、 第二源极和第二漏极。 所述第 一源极和第一漏极与氧化物半导体有源层直接接触电连接。 所述第二源极 和第二漏极通过过孔与所述多晶硅半导体有源层电连接。
例如, 如图 4所示, 所述阵列基板包括基板 10以及依次设置在所述基 板 10上的多晶硅半导体有源层、 栅绝缘层、 第二栅金属层、 氧化物半导体 有源层、 介质层以及第一栅金属层。 所述多晶硅半导体有源层包括第二有 源层 1062。 所述第二栅金属层包括: 第二栅极 121、 第一源极 112以及第 一漏极 113。 所述氧化物半导体有源层包括第一有源层 1061。 所述第一栅 金属层包括第一栅极 111以及第二源极 122和第二漏极 123。所述第一源极 112和第一漏极 123与氧化物半导体有源层即第一有源层 1061直接接触电 连接所述第二源极 122和第二漏极 123通过过孔与所述多晶硅半导体有源 层即第二有源层 1062电连接。 例如, 第二有源层在对应第二源极和第二漏 极的区域通过掺杂形成对应的源漏区, 所述源极和漏极分别与有源层的源 漏区 目连。
可选的, 如图 1、 图 3所示, 所述阵列基板包括多个子像素单元, 每一 所述子像素单元包括第一薄膜晶体管 11和第二薄膜晶体管 12,且所述第一 漏极 113与所述第二栅极 121通过连接电极 17电连接。 每一所述子像素单 元包括第一薄膜晶体管 11和第二薄膜晶体管 12,所述第一薄膜晶体管为开 关薄膜晶体管, 所述第二薄膜晶体管为驱动薄膜晶体管。 当然, 根据阵列 基板的不同结构, 第一薄膜晶体管和第二薄膜晶体管的作用也可以不同, 本发明实施例仅以附图所示的示例为例进行说明。
可选的, 所述阵列基板还包括像素电极, 且所述像素电极与所述第二 漏极电连接。 例如如图 3所示, 阵列基板还包括像素电极 16, 且如图 1所
示,所述像素电极 16通过过孔 c与第二漏极 123电连接,通过第二漏极 123 控制向所述像素电极 16提供电流信号。 或者如图 4所示, 阵列基板还包括 像素电极 16, 且像素电极 16通过过孔与第二漏极 123电连接, 通过第二漏 极 123控制向所述像素电极 16提供电流信号。
需要说明的是, 上述图 3中所示的结构是将 NMOS管和 PMOS管置于
OLED显示器件的同一个像素单元中为例进行说明的。但是,本发明实施例 提供的阵列基板不局限于图 3和图 4所示的阵列基板, 根据现有的阵列基 板的结构, 还可以形成其他薄膜或层结构的阵列基板。
同时, 本发明实施例中的图 3和图 4的第一薄膜晶体管和第二薄膜晶 体管的位置只是示例, 对于不同的实施例, 所述第一薄膜晶体管和所述第 二薄膜晶体管的位置可以变化。 例如, 在图 4 所示的示例中, 第一薄膜晶 体管也可以不必设置在像素电极 16的下方。
本发明实施例还提供了一种阵列基板的制作方法, 包括:
步骤 101、 在基板上形成第二薄膜晶体管的多晶硅半导体有源层。
例如, 如图 5所示, 在基板 10上形成多晶硅半导体有源层 (第二有源 层) 1062。 例如, 如图 11所示, 上述步骤 101包括:
步骤 1011、 在基板上形成多晶硅层半导体有源层。
而形成多晶硅半导体有源层例如通过在基板上形成单晶硅再进行晶化 形成的。
步骤 1012、 对所述多晶硅层半导体有源层进行掺杂。
而对所述多晶硅层半导体有源层进行掺杂例如通过离子注入的方式完 成。 对所述多晶硅层半导体有源层的两端进行掺杂, 可以在所述多晶硅半 导体有源层上形成对应源极和漏极的源极区和漏极区。
步骤 102、 在所述基板上形成栅绝缘层。
步骤 103、在所述基板上形成第二薄膜晶体管的第二栅极以及第一薄膜 晶体管的第一源极和第一漏极。
例如, 如图 6 所示, 通过一次构图工艺即通过一次曝光在所述基板上 形成第二薄膜晶体管的第二栅极 121 以及第一薄膜晶体管的第一源极 112 和第一漏极 113。 需要说明的是, 在所述基板上形成第一源极和第一漏极的 同时还在所述基板上形成数据线以及 Vdd线, 且所述数据线与所述第一源 极连接, 以向所述第一源极提供源极信号; 所述 Vdd线与第二源极相连,
以向第二源极提供源极信号。
步骤 104、 在所述基板上形成第一薄膜晶体管的氧化物半导体有源层。 例如, 如图 7所示, 在对应第一源极 112和第一漏极 113的位置处形 成氧化物半导体有源层 (第一有源层) 1061。 其中, 形成所述氧化物半导 体有源层的材料可以是 IGZO、 MIZO等。
步骤 105、在所述基板上形成第二薄膜晶体管的第二源极和第二漏极以 及第一薄膜晶体管的第一栅极。
例如, 在上述步骤 105 之前, 所述方法还包括在所述衬底上形成介质 层 102, 如图 8所示。 如图 8所示, 通过一次构图工艺在所述基板 10上形 成第二薄膜晶体管 12的第二源极 122和第二漏极 123以及第一薄膜晶体管 的第一栅极 111。 需要说明的是, 所述第二源极 122通过过孔(未示出)与 Vdd线电连接。
可选的, 在所述基板 10上形成第二薄膜晶体管 12的第二源极 122和 第二漏极 123以及第一薄膜晶体管 11的第一栅极 111之后, 所述方法还包 括: 在所述基板 10上形成连接电极 17, 所述连接电极 17分别与所述第一 漏极 113和所述第二栅极 121连接。
如图 9所示,所述连接电极 17分别通过过孔 a、 b与第一漏极 113以及 第二栅极 121连接, 实现第一漏极 113与第二栅极 121的电连接。
可选的, 所述方法还包括: 在所述基板上形成像素电极, 且所述像素 电极与所述第二漏极电连接。
如图 3所示, 阵列基板还包括像素电极 16, 且如图 1所示, 所述像素 电极 16通过过孔与第二漏极 123电连接, 通过第二漏极 123控制向所述像 素电极 16提供电流信号。 或者如图 4所示, 阵列基板还包括像素电极 16, 且像素电极通过过孔与第二漏极 123 电连接, 通过第二漏极 123控制向所 述像素电极 16提供电流信号。
需要说明的是, 本发明实施例提供的阵列基板不局限于图 3和图 4所 示的阵列基板, 根据阵列基板的结构, 还可以形成其他薄膜或层结构的阵 列基板。
需要说明的, 本发明实施例提供的阵列基板的制作方法也不局限于上 述方法, 例如根据薄膜晶体管的栅极和源漏极的关系将薄膜晶体管分为两 类。 一类是栅极位于源极和漏极的下面, 这类称之为底栅型薄膜晶体管; 一
类是栅极位于源极和漏极的上面, 这类称之为顶栅型薄膜晶体管。 本发明实 施例提供的阵列基板以所述第一薄膜晶体管为顶栅型薄膜晶体管, 所述第二 薄膜晶体管为底栅型薄膜晶体管为例进行说明的。 但阵列基板上的第一薄膜 晶体管也可以为底栅型薄膜晶体管, 第二薄膜晶体管也可以为顶栅型薄膜晶 体管, 如果釆用这种方式, 则上述的制作顺序需要进行相应的调整, 但制作 方法与上述类似。
一种发明所知的阵列基板在制作过程中需要进行两次晶化形成多晶硅 薄膜晶体管以及 13次掩模曝光以分别形成栅极层、 栅绝缘层、 有源层、 P+ 掺杂、 N+掺杂、 LDD掺杂、 介质层、 源漏电极层、 钝化层、 连接电极层、 平坦化层、 像素电极和像素界定层。 本发明实施例提供的阵列基板的制作 方法进行一次晶化和 12次掩模曝光分别形成多晶硅半导体有源层、 P+掺杂、 栅绝缘层、 第二栅金属层 (包括第一源极、 第一漏极以及第二栅极) 、 氧 化物半导体有源层、 介质层、 第一栅金属层 (包括第二源极、 第二漏极以 及第一栅极) 、 钝化层、 连接电极层、 平坦化层、 像素电极和像素界定层, 来形成如图 3所示的阵列基板。 或经过一次晶化和 9次掩模曝光分别形成 多晶硅半导体有源层、 P+掺杂、 栅绝缘层、 第二栅金属层(包括第一源极、 第一漏极以及第二栅极) 、 氧化物半导体有源层、 介质层、 第一栅金属层 (包括第二源极、 第二漏极以及第一栅极) 、 钝化层、 平坦层、 像素电极 和像素界定层, 来形成如图 4所示的阵列基板。
本发明实施例提供的阵列基板的制作方法, 通过在基板上形成氧化物 第一薄膜晶体管和多晶硅第二薄膜晶体管, 相对于第一薄膜晶体管和第二 薄膜晶体管均为多晶硅薄膜晶体管的制作方法, 至少减少了两次掺杂和一 次晶化工艺, 因此简化了制作工艺, 降低了产品的生产难度和生产成本。
本发明实施例提供了一种显示装置, 包括本发明实施提供的任一所述 的阵列基板。 所述显示装置可以为液晶显示器件、 OLED显示器件以及包括 这些显示器件的电视、 数码相机、 手机、 平板电脑等任何具有显示功能的产 品或者部件。
以上实施方式仅用于说明本发明, 而并非对本发明的限制, 本技术领域 的普通技术人员, 在不脱离本发明的精神和范围的情况下, 还可以做出各种 变化和变型, 这些变化、 变型和以及所有等同的技术方案也应属于本发明的 范畴, 本发明的保护范围由权利要求限定。
本申请要求于 2013年 12月 27日提交的名称为"一种阵列基板及其制作 方法、 显示装置" 的中国专利申请 No. 201310741137.8的优先权, 该申请全 文以引用方式合并于本文。
Claims
1、 一种阵列基板, 包括:
基板,
位于所述基板之上的多个互补型薄膜晶体管,所述多个互补型薄膜晶 体管包括 N型的第一薄膜晶体管和 P型的第二薄膜晶体管, 所述第一薄 膜晶体管为氧化物薄膜晶体管, 所述第二薄膜晶体管为多晶硅薄膜晶体 管。
2、根据权利要求 1所述的阵列基板,其中所述第一薄膜晶体管包括: 第一栅极、第一源极和第一漏极;以及所述第二薄膜晶体管包括第二栅极、 第二源极和第二漏极,所述第一栅极与所述第二源极以及所述第二漏极经 过一次构图工艺形成。
3、 根据权利要求 2所述的阵列基板, 其中所述第二栅极与所述第一 源极以及所述第一漏极经过一次构图工艺形成。
4、 根据权利要求 2或 3所述的阵列基板, 其中所述基板上依次设置 有多晶硅半导体有源层、栅绝缘层、第二栅金属层、氧化物半导体有源层、 介质层以及第一栅金属层; 其中,
所述第二栅金属层包括: 所述第二栅极、所述第一源极和所述第一漏 极;
所述第一栅金属层包括: 所述第一栅极、所述第二源极和所述第二漏 极;
其中,所述第一源极和所述第一漏极与所述氧化物半导体有源层直接 接触电连接,所述第二源极和所述第二漏极通过过孔与所述多晶硅半导体 有源层电连接。
5、 根据权利要求 2-4任一项所述的阵列基板, 还包括多个子像素单 元, 每一所述子像素单元包括所述第一薄膜晶体管和所述第二薄膜晶体 管, 且所述第一漏极与所述第二栅极通过连接电极电连接。
6、 根据权利要求 2-5任一项所述的阵列基板, 还包括像素电极, 所 述像素电极与所述第二漏极电连接。
7、 一种阵列基板的制作方法, 包括:
在基板上形成第二薄膜晶体管的多晶硅半导体有源层;
在所述基板上形成栅绝缘层;
在所述基板上形成第二薄膜晶体管的第二栅极以及第一薄膜晶体管
的第一源极和第一漏极;
在所述基板上形成第一薄膜晶体管的氧化物半导体有源层; 以及 在所述基板上形成第二薄膜晶体管的第二源极和第二漏极以及第一 薄膜晶体管的第一栅极。
8、 根据权利要求 7所述的制作方法, 其中, 通过一次构图工艺在所 述基板上形成所述第二薄膜晶体管的所述第二栅极以及所述第一薄膜晶 体管的所述第一源极和所述第一漏极。
9、 根据权利要求 7或 8所述的制作方法, 其中, 通过一次构图工艺 在所述基板上形成所述第二薄膜晶体管的所述第二源极和所述第二漏极 以及所述第一薄膜晶体管的所述第一栅极。
10、 根据权利要求 7-9任一项所述的制作方法, 其中, 所述在基板上 形成所述第二薄膜晶体管的所述多晶硅半导体有源层包括:
在基板上形成多晶硅层; 以及
对所述多晶硅层进行掺杂。
11、 根据权利要求 7所述的制作方法, 还包括:
在所述基板上形成所述第二薄膜晶体管的所述第二源极和所述第二 漏极以及所述第一薄膜晶体管的所述第一栅极之后,
在所述基板上形成连接电极,所述连接电极分别与所述第一漏极和所 述第二栅极连接。
12、 根据权利要求 7-11任一项所述的制作方法, 还包括:
在所述基板上形成像素电极, 且所述像素电极与所述第二漏极电连 接。
13、 一种显示装置, 包括权利要求 1-6任一项所述的阵列基板。
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