WO2014190712A1 - 阵列基板及其制作方法，显示装置 - Google Patents

阵列基板及其制作方法，显示装置 Download PDF

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Publication number
WO2014190712A1
WO2014190712A1 PCT/CN2013/088826 CN2013088826W WO2014190712A1 WO 2014190712 A1 WO2014190712 A1 WO 2014190712A1 CN 2013088826 W CN2013088826 W CN 2013088826W WO 2014190712 A1 WO2014190712 A1 WO 2014190712A1
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Prior art keywords
thin film
film transistor
pattern
active layer
array substrate
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PCT/CN2013/088826
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English (en)
French (fr)
Inventor
任章淳
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京东方科技集团股份有限公司
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Priority to US14/355,505 priority Critical patent/US9515100B2/en
Publication of WO2014190712A1 publication Critical patent/WO2014190712A1/zh

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    • H—ELECTRICITY
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
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    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Definitions

  • Embodiments of the present invention relate to an array substrate and a method of fabricating the same, and a display device. Background technique
  • CMOS Complementary Metal Oxide Semiconductor
  • PMOS Positive Channel Metal Oxide Semiconductor
  • NMOS Negative channel-Metal-Oxide- Semiconductor
  • the semiconductor layers of the PMOS region and the NMOS region in the CMOS circuit are generally prepared by low temperature poly-silicon (LTPS) technology.
  • the array substrate is The first order includes: a substrate 101, an active layer (a PMOS active layer 102 and an NMOS active layer 102'), a gate insulating layer 103, a gate (a gate 104 of the PMOS transistor, and a gate 104' of the NMOS transistor).
  • Insulating spacer layer 105 (including vias thereon), source and drain electrodes (source drain 106 of PMOS transistor and source drain 106' of NMOS transistor), passivation layer 107, flat layer 108, pixel electrode 109, and pixel The electrode defines a layer 110.
  • the fabrication of the array substrate by the low-temperature polysilicon process requires more than five coating processes and 11 masks. The steps of the 11 photomasks are as follows:
  • the embodiment of the invention provides a method for fabricating an array substrate, comprising the step S1: forming a pattern of an active layer of a switching thin film transistor and a corresponding pixel electrode on a substrate.
  • the step S1 is performed to include: forming a metal oxide semiconductor film, patterning the metal oxide semiconductor film to form a pattern of an active layer and a pixel electrode of the switching thin film transistor.
  • the step S1 is performed to: form a transparent conductive film, and pattern the transparent conductive film to form a pattern of the pixel electrode; and form a metal oxide semiconductor film, and pattern the metal oxide semiconductor film A transistor forms a pattern of an active layer of the switching thin film transistor.
  • the step S1 further includes forming a pattern of the active layer that drives the thin film transistor on the same level.
  • the pattern of forming an active layer of the driving thin film transistor on the same level includes forming an amorphous silicon film, and crystallizing the amorphous silicon film to form a polysilicon film; Forming a pattern of an active layer of the driving thin film transistor by a patterning process;
  • the metal oxide semiconductor thin film is an IGZO, ZnO, IZO, ITZO or tantalum film.
  • the method for fabricating the array substrate further includes:
  • Step S2 forming a pattern of a gate insulating layer, a pattern of driving a gate of the thin film transistor, and a pattern of a gate of the switching thin film transistor on the substrate of the step S1;
  • Step S3 doping the active layer of the driving thin film transistor on the substrate of the step S2;
  • Step S4 forming a pattern including an insulating spacer layer, a via hole on the insulating spacer layer, and a pixel electrode recess on the base substrate completing the step S3, wherein the pixel electrode recess exposes a portion of the pixel electrode pattern ;
  • Step S5 forming a pattern including a source and a drain of the driving thin film transistor, and a pattern of a source and a drain of the switching thin film transistor on the substrate of the step S4, and connecting the drain of the driving thin film transistor to the pixel electrode;
  • Step S6 forming a pattern including the pixel electrode defining layer on the base substrate on which the step S5 is completed.
  • the step S2 includes:
  • Forming a first metal thin film on the gate insulating layer, and patterning the first metal thin film to form the driving thin film transistor respectively in a region corresponding to an active layer pattern of the driving thin film transistor and an active layer pattern of the switching thin film transistor The pattern of the gate and the pattern of the gate of the switching thin film transistor.
  • the step S3 includes:
  • Coating the photoresist exposing and developing the photoresist through the mask, leaving the active layer pattern region of the switching thin film transistor and the photoresist of the pixel electrode pattern region, and developing the active layer pattern of the driving thin film transistor a photoresist of the region exposing an active layer pattern of the driving thin film transistor; and doping the active layer of the driving thin film transistor, and stripping the remaining photoresist after the doping is completed.
  • the step S4 includes: forming a second insulating film as the insulating spacer layer; and forming an active layer pattern that passes through the insulating spacer layer and the gate insulating layer to the driving thin film transistor by a patterning process a via hole and a second via hole, a third via hole and a fourth via hole passing through the insulating spacer layer and the gate insulating layer to the active layer pattern of the switching transistor device, and through the insulating spacer layer and a gate insulating layer reaching a pixel electrode recess of the pattern of the pixel electrode, wherein the first via and the second via correspond to a source and drain region of a driving thin film transistor to be formed; the third via And the fourth via corresponds to the source and drain regions of the switching thin film transistor to be formed.
  • the step S5 includes: forming a second metal thin film, patterning the second metal thin film to form a pattern of a source and a drain of the driving thin film transistor, and patterning a source and a drain of the switching thin film transistor, And connecting the drain of the driving thin film transistor to the pixel electrode.
  • the step S6 includes: forming a third insulating film, patterning the third insulating film such that only a portion of the pixel electrode pattern underneath is retained to form a pattern of the pixel electrode defining layer.
  • Another embodiment of the present invention provides an array substrate, including: a driving thin film transistor, a switching thin film transistor, and a pixel electrode on a substrate, wherein a drain of the switching thin film transistor is connected to the driving A source of the thin film transistor, a drain of the driving thin film transistor is connected to the pixel electrode, wherein the pixel electrode and the active layer of the switching thin film transistor are both at the same level.
  • the active layer of the driving thin film transistor is located at the same level.
  • the driving thin film transistor is a polysilicon thin film transistor.
  • the switching thin film transistor is a metal oxide thin film transistor.
  • the pixel electrode is made of the same material as the active layer of the switching thin film transistor.
  • a further embodiment of the invention provides a display device comprising the array substrate of any of the above.
  • FIG. 1 is a schematic structural view of an array substrate in the prior art
  • FIG. 2 is a schematic structural view showing an active layer of a driving thin film transistor formed on a base substrate in an array substrate manufacturing method according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of forming an active layer of a driving thin film transistor, an active layer of a switching thin film transistor, and a pixel electrode pattern on a substrate substrate in the method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of an embodiment of the present invention. A schematic structural view of forming a gate insulating layer and a gate pattern on a substrate in an array substrate manufacturing method;
  • FIG. 5 is a schematic diagram of doping an active layer of a driving thin film transistor in an array substrate manufacturing method according to an embodiment of the present invention
  • FIG. 6 is a schematic structural view showing a pattern of forming an insulating spacer layer, a via hole, and a pixel electrode recess on a base substrate in the method for fabricating an array substrate according to an embodiment of the invention
  • FIG. 7 is a schematic structural view showing a pattern of forming a source and a drain of a driving thin film transistor and a source and a drain of a switching thin film transistor on a substrate in the method of fabricating an array substrate according to an embodiment of the present invention
  • FIG. 8 is a schematic structural view of an array substrate fabricated by the method for fabricating an array substrate according to an embodiment of the present invention. detailed description
  • One of the technical problems to be solved by the embodiments of the present invention is how to form an array substrate in a single-sheet process.
  • the method of fabricating the array substrate according to the embodiment of the present invention includes, for example, the following steps S1 to S6.
  • Step S1 forming an active layer including a driving thin film transistor on the same level on the base substrate 201
  • a pattern of an active layer and a pixel electrode of a switching thin film transistor is a pattern of an active layer and a pixel electrode of a switching thin film transistor.
  • This step S1 is performed, for example, as follows: As shown in Fig. 2, an amorphous silicon (a-Si) film is formed on the base substrate 201 and the a-Si film is crystallized to form a polysilicon film.
  • the amorphous silicon film can be formed by various methods such as deposition, coating, sputtering, and the like.
  • the crystallization process may be carried out by using u-crystallization, laser annealing, metal induced crystallization (MIC), metal induced lateral crystallization or continuous granular silicon.
  • a pattern of the active layer 202 of the driving thin film transistor is formed by a patterning process on the polysilicon film.
  • the patterning process includes, for example, a process of photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • the driving thin film transistor active layer 202 thus formed is a polysilicon material.
  • the drive film transistor can be a PMOS transistor.
  • the active layer 203 and the corresponding pixel electrode 204 of the corresponding switching thin film transistor are next formed at the same level of the active layer 202 of the driving thin film transistor.
  • the active layer 203 and the pixel electrode 204 forming the thin film transistor can be formed in two ways:
  • Method 1 A transparent conductive film is formed, and a pattern of the pixel electrode 204 is formed by a patterning process.
  • a metal oxide semiconductor thin film is formed, a pattern of the active layer 203 of the switching thin film transistor is formed by a patterning process, and the active layer 202 of the driving thin film transistor, the active layer 203 of the switching thin film transistor, and the pixel electrode 204 are located at the same level.
  • Method 2 forming a metal oxide semiconductor film (for example, IGZO, ZnO, IZO, ITZO, and germanium film), forming a pattern of the active layer 203 and the pixel electrode 204 of the switching thin film transistor by a patterning process, that is, the pixel electrode 204 and the switching film
  • the active layer 203 of the transistor is made of the same material Material production.
  • the active layer 202 of the driving thin film transistor, the active layer 203 of the switching thin film transistor, and the pixel electrode 204 are located at the same level.
  • Mode 2 can reduce the use of Mask once compared to Mode 1, which saves the process.
  • the switching thin film transistor can be an NMOS transistor.
  • Step S2 As shown in Fig. 4, a pattern including a gate insulating layer 205, a gate electrode 206 for driving the thin film transistor, and a gate 207 of the switching thin film transistor is formed on the base substrate shown in Fig. 3.
  • This step S2 can be performed, for example, as follows:
  • a gate insulating film is formed as the gate insulating layer 205. Forming a gate metal film on the gate insulating layer 205, and forming a gate electrode 206 and a switching thin film transistor of the driving thin film transistor in a region corresponding to the active layer 202 pattern of the driving thin film transistor and the active layer 203 pattern of the switching thin film transistor by a patterning process, respectively The pattern of the gate 207.
  • Step S3 Doping the active layer 202 of the driving thin film transistor shown in FIG. This step S3 is performed, for example, as follows:
  • the photoresist 300 is coated, the photoresist 300 is exposed and developed through the mask, the pattern region of the active layer 203 of the switching thin film transistor and the photoresist region 300 of the pattern region of the pixel electrode 204 are retained, and the driving thin film transistor is developed.
  • the photoresist 300 of the pattern region of the active layer 202 exposes a pattern of the active layer 202 of the driving thin film transistor.
  • the photoresist 300 is used to block the active layer 203 pattern region of the switching thin film transistor and the pattern region of the pixel electrode 204, and the gate 206 above the active layer 202 blocks a portion of the active layer 202.
  • the region is doped to the region of the active layer 202 that drives the thin film transistor that is not blocked by the gate 206.
  • the remaining photoresist 300 is stripped after the doping is completed.
  • An active layer 202 of the doped driving thin film transistor is formed.
  • the driving thin film transistor is, for example, a PMOS transistor.
  • the above doping process is, for example, a P+ doping process.
  • Step S4 forming a pattern including an insulating spacer layer 208, a via hole on the insulating spacer layer 208, and a pixel electrode recess 800, and the pixel electrode recess 800 exposes a portion of the pattern of the pixel electrode 204.
  • the substrate after the completion of the processing in this step is as shown in FIG. 6.
  • Step S4 is performed, for example, as follows: An insulating film is formed as an insulating spacer layer 208 on the substrate shown in FIG. 5.
  • a third via 600 that passes through the insulating spacer layer 208 and the gate insulating layer 205 to the pattern of the active layer 203 of the switching thin film transistor should be formed in a region of the source of the switching thin film transistor to be formed; corresponding to the switch to be formed
  • a drain-connected region of the thin film transistor forms a fourth via 700 through the insulating spacer layer 208 and the gate insulating layer 205 to reach a pattern of the active layer 203 of the switching thin film transistor; in a region corresponding to
  • Step S5 forming a pattern of the source 209, the drain 209' of the driving thin film transistor, and a pattern of the source 210 and the drain 210' of the switching thin film transistor.
  • the drain 209' of the driving thin film transistor is connected, for example, to the pixel electrode 204, and the drain of the switching thin film transistor is connected, for example, to the source of the driving thin film transistor.
  • a source/drain metal film is formed, and a pattern of the source 209 and the drain 209' of the driving thin film transistor, and a pattern of the source 210 and the drain 210' of the switching thin film transistor are formed by a patterning process, and driven.
  • a drain electrode 209' of the thin film transistor is formed to be connected to the pixel electrode 204.
  • Step S6 forming a pattern including the pixel electrode defining layer 211.
  • This step is performed, for example, as an insulating film forming a resin material, and as shown in FIG. 8, a pattern of the pixel electrode defining layer 211 is formed by a patterning process so as to cover the pattern area A of the pixel electrode 204 except the exposed above the substrate substrate. All other areas except.
  • the exposed pixel electrode 204 can serve as the anode of the subsequently formed OLED.
  • the pixel electrode is formed at the same level as the active layer of the driving thin film crystal and the switching thin film transistor, thereby reducing the number of mask processes required, for example, only 8 times.
  • Mask process the pixel electrode can be made of the same material as the active layer of the switching thin film transistor and can be simultaneously fabricated, which can further reduce the number of mask processes required, for example, only 7 mask processes are required. This reduces the Mask process in the manufacturing process, saving process and manufacturing costs.
  • the present application employs an oxide thin film transistor for switching a thin film transistor without using low-temperature polysilicon technology, the Tact Time can be reduced during crystallization, and the life of the laser tube can be prolonged. It has the effect of reducing manufacturing costs.
  • a gate drive shift register (GOA), and a thin film transistor in a peripheral region can utilize low temperature polysilicon (LTPS).
  • LTPS low temperature polysilicon
  • the driving thin film transistor formed by the LTPS process exists only in the peripheral region. Therefore, the laser annealing process used to prepare the driving thin film transistor only needs to crystallize the gate drive shift register (GOA) region and the peripheral region instead of the entire region of the array substrate, thereby reducing crystallization.
  • the process tact time can extend the life of the laser tube, thereby reducing the manufacturing cost.
  • An embodiment of the present invention further provides an array substrate fabricated by the above method.
  • the bottom to top includes: a substrate 201, a driving thin film transistor active layer 202, a switching thin film transistor active layer 203, and a pixel electrode. 204, a gate insulating layer 205, a gate (a gate 206 of the driving thin film transistor and a gate 207 of the switching thin film transistor), an insulating spacer layer 208 (including a via hole thereon), and a source/drain electrode (a source of the driving thin film transistor) 209, the drain 209' and the source 210 of the switching thin film transistor, the drain 210') and the pixel electrode defining layer 211.
  • the drain 210' of the switching thin film transistor is connected to the source 209 of the driving thin film transistor, and the drain 209' of the driving thin film transistor is connected to the pixel electrode 204.
  • the pixel electrode 204 is located in the same layer as the active layer 202 of the driving thin film transistor and the active layer 203 of the switching thin film transistor.
  • the driving thin film transistor is, for example, an LTPS thin film transistor
  • the switching thin film transistor is, for example, an oxide thin film transistor.
  • the pixel electrode 204 and the active layer of the oxide thin film transistor are made of, for example, the same material.
  • An embodiment of the present invention also provides a display device comprising the array substrate of any of the above.
  • An example of the display device is a liquid crystal display device in which a TFT array substrate and an opposite substrate are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, a color filter substrate.
  • the pixel electrode of each pixel unit of the TFT array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display further includes a backlight that provides backlighting for the array substrate.
  • Another example of the display device is an organic electroluminescence display device in which a TFT array is subjected to a display operation.
  • the display device can be, for example, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any product or component having a display function.

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Abstract

提供一种阵列基板制作方法、阵列基板和显示装置。该阵列基板的制造方法包括在衬底基板上形成处于同一层级的开关薄膜晶体管的有源层的图形及对应的像素电极的图形。

Description

阵列基板及其制作方法， 显示装置 技术领域
本发明的实施例涉及阵列基板及其制作方法， 显示装置。 背景技术
互补金属氧化物半导体 ( CMOS , Complementary Metal Oxide Semiconductor )由 P型沟道金属氧化物半导体（ PMOS, Positive channel Metal Oxide Semiconductor ) 和 N 型沟道金属氧化物半导体（NMOS , Negative channel-Metal-Oxide-Semiconductor )共同构成。
目前一般都采用低温多晶硅（LTPS, Low Temperature Poly-silicon )技 术制备 CMOS电路中 PMOS区域和 NMOS区域的半导体层， 如图 1所示， 为了形成 PMOS和 NMOS电路的阵列基板， 该阵列基板由下至上依次包括： 基板 101、 有源层（PMOS管有源层 102和 NMOS管有源层 102' ) 、 栅绝 缘层 103、 栅极 ( PMOS管的栅极 104和 NMOS管的栅极 104' ) 、 绝缘间 隔层 105 (包括其上的过孔 ) 、 源漏电极（ PMOS管的源漏极 106和 NMOS 管的源漏极 106' ) , 钝化层 107、 平坦层 108、 像素电极 109及像素电极定 义层 110。 利用低温多晶硅工艺制作该阵列基板需要使用 5次以上的涂布工 序及 11个光掩膜板（Mask ) , 11个光掩膜板的工序如下：
1)有源层 Mask;
2)栅极 (栅线） Mask;
3) P+掺杂 Mask;
4) N+掺杂 Mask;
5) LDD ( Lightly dopped drain )掺杂 Mask;
6)过孔 Mask;
7)源漏电极 Mask;
8)钝化层 Mask;
9)平坦层 Mask;
10)像素电极（阳极） Mask; 11)像素定义层（ Pixel Define Layer, PDL ) Mask;
上述制作过程存在工序复杂， 设备投资费用及制造费用高的缺点。 发明内容
本发明实施例提供一种阵列基板制作方法， 包括步骤 S1: 在衬底基板上 形成处于同一层级的开关薄膜晶体管的有源层的图形及对应的像素电极的图 形。
在一个示例中， 所述步骤 S1执行为包括： 形成金属氧化物半导体薄膜， 图案化该金属氧化物半导体薄膜形成所述开关薄膜晶体管的有源层及像素电 极的图形。
在一个示例中， 所述步骤 S1 执行为包括： 形成透明导电薄膜， 并图案 化该透明导电薄膜形成所述像素电极的图形； 以及形成金属氧化物半导体薄 膜， 并图案化该金属氧化物半导体薄膜晶体管形成所述开关薄膜晶体管的有 源层的图形。
在一个示例中， 所述步骤 S1 还包括在所述同一层级上形成驱动薄膜晶 体管的有源层的图形。
在一个示例中， 所述在所述同一层级上形成驱动薄膜晶体管的有源层的 图形包括形成非晶硅薄膜， 并对所述非晶硅薄膜进行结晶化， 使形成多晶硅 薄膜； 以及对所述多晶硅薄膜通过构图工艺形成所述驱动薄膜晶体管的有源 层的图形；
在一个示例中， 所述金属氧化物半导体薄膜为 IGZO、 ZnO、 IZO、 ITZO 或 ΗΙΖΟ薄膜。
在一个示例中， 所述阵列基板制作方法还包括：
步骤 S2: 在完成步骤 S1的衬底基板上形成栅绝缘层的图形、 驱动薄膜 晶体管的栅极的图形及开关薄膜晶体管的栅极的图形；
步骤 S3: 在完成 S2步骤的衬底基板上对驱动薄膜晶体管的有源层进行 掺杂；
步骤 S4: 在完成 S3步骤的衬底基板上形成包括绝缘间隔层、 位于所述 绝缘间隔层上的过孔及像素电极凹槽的图形， 所述像素电极凹槽使像素电极 图形的一部分暴露出来； 步骤 S5:在完成步骤 S4的衬底基板上形成包括驱动薄膜晶体管的源极、 漏极的图形， 及开关薄膜晶体管的源极、 漏极的图形， 使驱动薄膜晶体管的 漏极连接所述像素电极；
步骤 S6:在完成步骤 S5的衬底基板上形成包括像素电极定义层的图形。 在一个示例中， 所述步骤 S2包括：
形成第一绝缘薄膜作为所述栅绝缘层；
在所述栅绝缘层上形成第一金属薄膜， 图案化该第一金属薄膜使得在对 应驱动薄膜晶体管的有源层图形和开关薄膜晶体管的有源层图形的区域分别 形成所述驱动薄膜晶体管的栅极的图形及开关薄膜晶体管的栅极的图形。
在一个示例中， 所述步骤 S3包括：
涂覆光刻胶， 通过掩膜板对所述光刻胶曝光显影， 使保留开关薄膜晶体 管的有源层图形区域和像素电极图形区域的光刻胶， 显影掉驱动薄膜晶体管 的有源层图形区域的光刻胶， 暴露出驱动薄膜晶体管的有源层图形； 以及 对驱动薄膜晶体管的有源层进行掺杂处理， 掺杂完成后剥离保留的光刻 胶。
在一个示例中， 所述步骤 S4 包括： 形成第二绝缘薄膜作为所述绝缘间 隔层； 以及通过构图工艺形成穿过所述绝缘间隔层和栅绝缘层到达驱动薄膜 晶体管的有源层图形的第一过孔和第二过孔、 穿过所述绝缘间隔层和栅绝缘 层到开关动薄膜晶体管的有源层图形的第三过孔和第四过孔、 以及穿过所述 绝缘间隔层和栅绝缘层到达所述像素电极的图形的像素电极凹槽， 其中所述 第一过孔和第二过孔对应于待形成的驱动薄膜晶体管的源级和漏极区域； 所 述第三过孔和第四过孔对应于待形成的开关薄膜晶体管的源级和漏极区域。
在一个示例中， 所述步骤 S5 包括： 形成第二金属薄膜， 图案化该第二 金属薄膜形成驱动薄膜晶体管的源极、 漏极的图形， 及开关薄膜晶体管的源 极、 漏极的图形， 且使驱动薄膜晶体管的漏极连接所述像素电极。
在一个示例中， 所述步骤 S6 包括： 形成第三绝缘薄膜， 图案化该第三 绝缘薄膜使得仅保留其下方的像素电极图形的一部分， 以形成像素电极定义 层的图形。
本发明另一实施例提供一种阵列基板， 包括： 位于基板上的驱动薄膜晶 体管、 开关薄膜晶体管及像素电极， 所述开关薄膜晶体管的漏极连接所述驱 动薄膜晶体管的源极，所述驱动薄膜晶体管的漏极连接所述像素电极，其中， 所述像素电极与开关薄膜晶体管的有源层均位于同一层级。
在一个示例中， 所述驱动薄膜晶体管的有源层位于该同一层级。
在一个示例中， 所述驱动薄膜晶体管为多晶硅薄膜晶体管。
在一个示例中， 所述开关薄膜晶体管为金属氧化物薄膜晶体管。
在一个示例中， 所述像素电极与所述开关薄膜晶体管的有源层为同种材 料制成。
本发明的又一实施例提供一种显示装置， 包括如以上任一项所述的阵列 基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例或现有技 术描述中所需要使用的附图作筒单地介绍， 显而易见地， 下面描述中的附图 仅仅涉及本发明的一些实施例， 并非对本发明的限制。
图 1是现有技术中的一种阵列基板的结构示意图；
图 2是本发明实施例的阵列基板制作方法中在衬底基板上形成驱动薄膜 晶体管的有源层的结构示意图；
图 3是本发明实施例的阵列基板制作方法中在衬底基板上形成驱动薄膜 晶体管的有源层、 开关薄膜晶体管的有源层及像素电极图形的结构示意图； 图 4是本发明实施例的阵列基板制作方法中在衬底基板上形成栅绝缘层 及栅极图形的结构示意图；
图 5是本发明实施例的阵列基板制作方法中对驱动薄膜晶体管的有源层 进行掺杂的示意图；
图 6是本发明实施例的阵列基板制作方法中在衬底基板上形成绝缘间隔 层、 过孔及像素电极凹槽的图形的结构示意图；
图 7是本发明实施例的阵列基板制作方法中在衬底基板上形成驱动薄膜 晶体管的源漏极和开关薄膜晶体管的源漏极的图形的结构示意图；
图 8 是本发明实施例的阵列基板制作方法制作的阵列基板的结构示意 图。 具体实施方式
下面将结合附图，对本发明实施例中的技术方案进行清楚、完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有做出创造性劳动前提下 所获得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例要解决的技术问题之一是如何以筒单的工艺形成阵列基 板。
根据本发明的实施例的阵列基板的制作方法例如包括如下的步骤 S1 至 步骤 S6。
步骤 S1 :在衬底基板 201上同一层级形成包括驱动薄膜晶体管的有源层
102、 开关薄膜晶体管的有源层及像素电极的图形。
该步骤 S1例如如下执行： 如图 2所示， 在衬底基板 201上形成非晶硅 ( a-Si )薄膜并对该 a-Si薄膜进行结晶化使之形成多晶硅薄膜。 该非晶硅薄 膜可采用沉积、 涂敷、 溅射等多种方式形成。 该结晶化工艺可并采用 u-结晶 4匕 ( u-crystallization ) 、 激光退火 ( Laser Annealing ) 、 金属诱导晶 4匕 ( metal inducedcrystallization, MIC )、 金属诱导横向结晶或连续粒状结晶硅等方式。 对多晶硅薄膜通过构图工艺形成驱动薄膜晶体管的有源层 202的图形。 所述 构图工艺例如包括光刻胶涂敷、 曝光、 显影、 刻蚀、 光刻胶剥离等工艺。 如 此形成的驱动薄膜晶体管有源层 202为多晶硅材料。 在一个示例中， 驱动薄 膜晶体管可以是 PMOS管。
如图 3所示， 接下来在驱动薄膜晶体管的有源层 202的同一层级形成对 应的开关薄膜晶体管的有源层 203和对应的像素电极 204。 形成开关薄膜晶 体管的有源层 203和像素电极 204可以有两种方式：
方式 1、 形成透明导电薄膜， 通过构图工艺形成像素电极 204的图形。 形成金属氧化物半导体薄膜， 通过构图工艺形成开关薄膜晶体管的有源层 203的图形，且使得驱动薄膜晶体管的有源层 202、开关薄膜晶体管的有源层 203及像素电极 204位于同一层级。
方式 2、 形成金属氧化物半导体薄膜（例如： IGZO、 ZnO、 IZO、 ITZO 及 ΗΙΖΟ薄膜） ， 通过构图工艺形成开关薄膜晶体管的有源层 203及像素电 极 204的图形， 即像素电极 204和开关薄膜晶体管的有源层 203采用同种材 料制作。且使得驱动薄膜晶体管的有源层 202、开关薄膜晶体管的有源层 203 及像素电极 204位于同一层级。 方式 2相对于方式 1可减少一次 Mask的使 用， 更加节省工序。 在一个示例中， 开关薄膜晶体管可以是 NMOS管。
步骤 S2:如图 4所示，在图 3所示的衬底基板上形成包括栅绝缘层 205、 驱动薄膜晶体管的栅极 206及开关薄膜晶体管的栅极 207的图形。
该步骤 S2例如可如下执行：
形成栅绝缘薄膜作为所述栅绝缘层 205。 在栅绝缘层 205上形成栅金属 薄膜， 通过构图工艺在对应驱动薄膜晶体管的有源层 202图形和开关薄膜晶 体管的有源层 203图形的区域分别形成驱动薄膜晶体管的栅极 206及开关薄 膜晶体管的栅极 207的图形。
步骤 S3: 对图 4所示驱动薄膜晶体管的有源层 202进行掺杂。 该步骤 S3例如如下执行：
涂覆光刻胶 300, 通过掩膜板对光刻胶 300曝光显影， 保留开关薄膜晶 体管的有源层 203的图形区域和像素电极 204的图形区域的光刻胶 300, 显 影掉驱动薄膜晶体管的有源层 202的图形区域的光刻胶 300, 暴露出驱动薄 膜晶体管的有源层 202的图形。 如图 5所示， 掺杂时， 采用光刻胶 300遮挡 开关薄膜晶体管的有源层 203图形区域和像素电极 204的图形区域， 且有源 层 202上方的栅极 206遮挡一部分有源层 202的区域， 对驱动薄膜晶体管的 有源层 202未被栅极 206遮挡的区域进行掺杂处理。 掺杂完成后剥离保留的 光刻胶 300。 形成掺杂后的驱动薄膜晶体管的有源层 202。在一个示例中， 驱 动薄膜晶体管例如为 PMOS管。 则在此情况下上述掺杂工艺例如为 P+掺杂 工艺。
步骤 S4: 形成包括绝缘间隔层 208、 位于该绝缘间隔层 208上的过孔及 像素电极凹槽 800的图形， 像素电极凹槽 800使像素电极 204的图形的一部 分暴露出来。 该步骤处理完成后的基板如图 6所示， 步骤 S4例如如下执行： 在图 5所示的基板上形成绝缘薄膜作为绝缘间隔层 208。 通过构图工艺 对应于待形成的驱动薄膜晶体管的源极的区域形成穿过绝缘间隔层 208和栅 绝缘层 205到达驱动薄膜晶体管的有源层 202的图形的第一过孔 400; 在对 应于待形成的驱动薄膜晶体管的漏极的区域形成穿过绝缘间隔层 208和栅绝 缘层 205到达驱动薄膜晶体管的有源层 202的图形与的第二过孔 500; 在对 应于待形成的开关薄膜晶体管的源极的区域形成穿过绝缘间隔层 208和栅绝 缘层 205到达开关薄膜晶体管的有源层 203的图形的第三过孔 600; 在对应 于待形成的开关薄膜晶体管的漏极连接的区域形成穿过所述绝缘间隔层 208 和栅绝缘层 205到达开关薄膜晶体管的有源层 203的图形的第四过孔 700; 在对应于像素电极 204 的图形的区域形成穿过绝缘间隔层 208 和栅绝缘层 205到达该像素电极 204的图形的像素电极凹槽 800。上述第一至第四过孔以 及像素电极凹槽 800可通过同一掩模同时形成。
步骤 S5: 形成驱动薄膜晶体管的源极 209、 漏极 209' 的图形， 及开关 薄膜晶体管的源极 210、 漏极 210' 的图形。 驱动薄膜晶体管的漏极 209' 例 如连接到像素电极 204, 开关薄膜晶体管的漏极例如连接到驱动薄膜晶体管 的源极。 如图 7所示， 形成源漏金属薄膜， 并且通过构图工艺形成驱动薄膜 晶体管的源极 209、 漏极 209' 的图形， 及开关薄膜晶体管的源极 210、 漏极 210' 的图形， 且驱动薄膜晶体管的漏极 209' 形成为连接到像素电极 204。
步骤 S6: 形成包括像素电极定义层 211的图形。 该步骤例如执行为形成 树脂材料的绝缘薄膜， ， 并且如图 8所示， 通过构图工艺形成像素电极定义 层 211的图形， 使其覆盖衬底基板上方除暴露出的像素电极 204的图形区域 A以外的所有其他区域。暴露出的像素电极 204可作为后续形成的 OLED的 阳极。
在上述实施例提供的阵列基板的制作方法中， 将像素电极制作在与驱动 薄膜晶体和开关薄膜晶体管的有源层的同一层级， 因此减少了所需要的掩模 工艺数量， 例如只需要 8次 Mask工艺。 进一步地， 像素电极可以和开关薄 膜晶体管的有源层可采用同种材料且同时制作， 可进一步减少所需要的掩模 工艺数量， 例如仅需要 7次 Mask工艺。 从而减少了制作过程的中的 Mask 工序， 节省了工艺流程和制作成本。 此外， 由于本申请采用无需采用低温多 晶硅技术形成用于开关薄膜晶体管的氧化物薄膜晶体管， 因此能够减少结晶 化时的工艺节拍时间 （Tact Time ) , 能够延长激光管（Laser Tube )的寿命， 从而具有减少制造费用的效果。
另外， 在制造 CMOS 阵列的显示面板时， 例如在阵列基板的显示区域 例如形成氧化物薄膜晶体管作为开关薄膜晶体管， 栅极驱动移位寄存器 ( GOA ) 以及周边区域的薄膜晶体管可利用低温多晶硅（ LTPS )工艺形成， 因此利用 LTPS工艺形成的驱动薄膜晶体管仅仅存在于周边区域。 因此， 用 于制备驱动薄膜晶体管而使用的激光退火（ Laser annealing )工艺仅需要结晶 化栅极驱动移位寄存器（ GOA ) 区域以及周边区域， 而非阵列基板的全部区 域， 因此能够减少结晶化时的工艺节拍时间， 能够延长激光管的寿命， 从而 具有减少制造费用的效果。
本发明的实施例还提供了一种采用上述方法制作的阵列基板， 如图 8所 示， 由下至上包括： 基板 201、 驱动薄膜晶体管有源层 202、 开关薄膜晶体管 有源层 203、像素电极 204、栅绝缘层 205、栅极（驱动薄膜晶体管的栅极 206 和开关薄膜晶体管的栅极 207 )、 绝缘间隔层 208 (包括其上的过孔）、 源漏 电极（驱动薄膜晶体管的源极 209、漏极 209'和开关薄膜晶体管的源极 210、 漏极 210' )及像素电极定义层 211。 开关薄膜晶体管的漏极 210' 连接驱动 薄膜晶体管的源极 209, 驱动薄膜晶体管的漏极 209' 连接像素电极 204。 像 素电极 204与驱动薄膜晶体管的有源层 202及开关薄膜晶体管的有源层 203 均位于同一层。
在上述阵列基板中， 驱动薄膜晶体管例如为 LTPS薄膜晶体管， 开关薄 膜晶体管例如为氧化物薄膜晶体管。 像素电极 204与氧化物薄膜晶体管的有 源层例如为同种材料制成。
本发明的实施例还提供了一种显示装置， 包括上述任一项所述的阵列基 板。
该显示装置的一个示例为液晶显示装置， 其中， TFT阵列基板与对置基 板彼此对置以形成液晶盒， 在液晶盒中填充有液晶材料。 该对置基板例如为 彩膜基板。 TFT阵列基板的每个像素单元的像素电极用于施加电场对液晶材 料的旋转的程度进行控制从而进行显示操作。 在一些示例中， 该液晶显示器 还包括为阵列基板提供背光的背光源。
该显示装置的另一个示例为有机电致发光显示装置， 其中， TFT阵列基 进行显示操作。
该显示装置例如可以为： 电子纸、 手机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能的产品或部件。
虽然上文中已经用一般性说明及具体实施方式， 对本发明作了详尽的描 述， 但在本发明基础上， 可以对之作一些修改或改进， 这对本领域技术人员 而言是显而易见的。 因此， 在不偏离本发明精神的基础上所做的这些修改或 改进， 均属于本发明要求保护的范围。

Claims

权利要求书
1、 一种阵列基板制作方法， 包括步骤 S1: 在衬底基板上形成处于同一 层级的开关薄膜晶体管的有源层的图形及对应的像素电极的图形。
2、 如权利要求 1所述的阵列基板制作方法， 其中， 所述步骤 S1执行为 包括： 形成金属氧化物半导体薄膜， 图案化该金属氧化物半导体薄膜形成所 述开关薄膜晶体管的有源层及像素电极的图形。
3、 如权利要求 1所述的阵列基板制作方法， 其中， 所述步骤 S1执行为 包括： 形成透明导电薄膜， 并图案化该透明导电薄膜形成所述像素电极的图 形； 以及形成金属氧化物半导体薄膜， 并图案化该金属氧化物半导体薄膜晶 体管形成所述开关薄膜晶体管的有源层的图形。
4、如权利要求 1至 3中任一项所述的阵列基板制作方法， 其中， 所述步 骤 S1还包括在所述同一层级上形成驱动薄膜晶体管的有源层的图形。
5、如权利要求 4所述的阵列基板制作方法， 其中， 所述在所述同一层级 上形成驱动薄膜晶体管的有源层的图形包括形成非晶硅薄膜， 并对所述非晶 硅薄膜进行结晶化， 使形成多晶硅薄膜； 以及对所述多晶硅薄膜通过构图工 艺形成所述驱动薄膜晶体管的有源层的图形。
6、如权利要求 2至 5中任一项所述的阵列基板制作方法， 其中， 所述金 属氧化物半导体薄膜为 IGZO、 ZnO、 IZO、 ITZO或 HIZO薄膜。
7、 如权利要求 1至 6中任一项所述的阵列基板制作方法， 还包括： 步骤 S2: 在完成步骤 S1的衬底基板上形成栅绝缘层的图形、 驱动薄膜 晶体管的栅极的图形及开关薄膜晶体管的栅极的图形；
步骤 S3: 在完成 S2步骤的衬底基板上对驱动薄膜晶体管的有源层进行 掺杂；
步骤 S4: 在完成 S3步骤的衬底基板上形成包括绝缘间隔层、 位于所述 绝缘间隔层上的过孔及像素电极凹槽的图形， 所述像素电极凹槽使像素电极 图形的一部分暴露出来；
步骤 S5: 在完成步骤 S4的衬底衬底基板上形成包括驱动薄膜晶体管的 源极、 漏极的图形， 及开关薄膜晶体管的源极、 漏极的图形， 使驱动薄膜晶 体管的漏极连接所述像素电极； 步骤 S6:在完成步骤 S5的衬底基板上形成包括像素电极定义层的图形。
8、 如权利要求 7所述的阵列基板制作方法， 其中， 所述步骤 S2包括： 形成第一绝缘薄膜作为所述栅绝缘层；
在所述栅绝缘层上形成第一金属薄膜， 图案化该第一金属薄膜使得在对 应驱动薄膜晶体管的有源层图形和开关薄膜晶体管的有源层图形的区域分别 形成所述驱动薄膜晶体管的栅极的图形及开关薄膜晶体管的栅极的图形。
9、 如权利要求 7或 8所述的阵列基板制作方法， 其中， 所述步骤 S3包 括：
涂覆光刻胶， 通过掩膜板对所述光刻胶曝光显影， 使保留开关薄膜晶体 管的有源层图形区域和像素电极图形区域的光刻胶， 显影掉驱动薄膜晶体管 的有源层图形区域的光刻胶， 暴露出驱动薄膜晶体管的有源层图形； 以及 对驱动薄膜晶体管的有源层进行掺杂处理， 掺杂完成后剥离保留的光刻 胶。
10、 如权利要求 7至 9中任一项所述的阵列基板制作方法， 其中， 所述 步骤 S4包括：
形成第二绝缘薄膜作为所述绝缘间隔层； 以及
通过构图工艺形成穿过所述绝缘间隔层和栅绝缘层到达驱动薄膜晶体管 的有源层图形的第一过孔和第二过孔、 穿过所述绝缘间隔层和栅绝缘层到开 关动薄膜晶体管的有源层图形的第三过孔和第四过孔、 以及穿过所述绝缘间 隔层和栅绝缘层到达所述像素电极的图形的像素电极凹槽， 其中所述第一过 孔和第二过孔对应于待形成的驱动薄膜晶体管的源级和漏极区域； 所述第三 过孔和第四过孔对应于待形成的开关薄膜晶体管的源级和漏极区域。
11、如权利要求 7至 10中任一项所述的阵列基板制作方法， 其中， 所述 步骤 S5包括：
形成第二金属薄膜，图案化该第二金属薄膜形成驱动薄膜晶体管的源极、 漏极的图形， 及开关薄膜晶体管的源极、 漏极的图形， 且使驱动薄膜晶体管 的漏极连接所述像素电极。
12、如权利要求 7至 1 1中任一项所述的阵列基板制作方法， 其中， 所述 步骤 S6包括：
形成第三绝缘薄膜， 图案化该第三绝缘薄膜使得仅保留其下方的像素电 极图形的一部分， 以形成像素电极定义层的图形。
13、 一种阵列基板， 包括： 位于基板上的驱动薄膜晶体管、 开关薄膜晶 体管及像素电极， 所述开关薄膜晶体管的漏极连接所述驱动薄膜晶体管的源 极， 所述驱动薄膜晶体管的漏极连接所述像素电极， 其中， 所述像素电极与 开关薄膜晶体管的有源层均位于同一层级。
14、如权利要求 13所述的阵列基板， 其中， 所述驱动薄膜晶体管的有源 层位于该同一层级。
15、 如权利要求 13或 14所述的阵列基板， 其中， 所述驱动薄膜晶体管 为多晶硅薄膜晶体管。
16、 如权利要求 13至 15中任一项所述的阵列基板， 其中， 所述开关薄 膜晶体管为金属氧化物薄膜晶体管。
17、 如权利要求 13至 16中任一项所述的阵列基板， 其中， 所述像素电 极与所述开关薄膜晶体管的有源层为同种材料制成。
18、一种显示装置， 包括如权利要求 13至 17中任一项所述的阵列基板。
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