WO2018077239A1 - 显示基板及其制造方法、显示装置 - Google Patents

显示基板及其制造方法、显示装置 Download PDF

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Publication number
WO2018077239A1
WO2018077239A1 PCT/CN2017/108059 CN2017108059W WO2018077239A1 WO 2018077239 A1 WO2018077239 A1 WO 2018077239A1 CN 2017108059 W CN2017108059 W CN 2017108059W WO 2018077239 A1 WO2018077239 A1 WO 2018077239A1
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pattern
active layer
doped region
forming
semiconductor pattern
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PCT/CN2017/108059
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English (en)
French (fr)
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孙双
彭宽军
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京东方科技集团股份有限公司
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Priority to US15/779,694 priority Critical patent/US11043515B2/en
Publication of WO2018077239A1 publication Critical patent/WO2018077239A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/467—Chemical or electrical treatment, e.g. electrolytic etching using masks

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display substrate, a method of manufacturing the same, and a display device.
  • the industry related to display panels is the basic industry of the electronics industry, and its technology is constantly evolving and innovating.
  • oxide technology and low temperature polysilicon technology are widely used due to their own advantages. More specifically, the low temperature polysilicon transistor has an advantage in that it has a high electron mobility. At the same time, low-temperature polysilicon transistors also have the disadvantage of large leakage current. An advantage of an oxide transistor is that it has a small leakage current. However, oxide transistors have a problem of low electron mobility.
  • a top gate structure is often employed, with the gate being used as a mask for a doped region in the low temperature polysilicon transistor.
  • a low-temperature polysilicon transistor with a bottom gate structure it is necessary to design a mask, which undoubtedly increases the complexity of the manufacturing process and the manufacturing cost.
  • a display substrate capable of reducing process complexity and manufacturing cost, a method of manufacturing the same, and a display device.
  • a method of fabricating a display substrate comprising: providing a substrate; and forming a first thin film transistor including a first active layer and a second thin film including a second active layer on the substrate Transistor.
  • the second active layer includes a central area and is located separately a doped region on both sides of the central region, and forming a first thin film transistor including a first active layer and a second thin film transistor including a second active layer on the substrate include: forming by one patterning process The first active layer and the doped region.
  • the method of manufacturing the display substrate further includes: forming a first semiconductor pattern before forming the doped regions of the first active layer and the second active layer by one patterning process, and second The doped region of the source layer is formed by doping the first semiconductor pattern.
  • the doped region includes a first doped region and a second doped region, the first doped region is located between the second doped region and the central region, and passes through a patterning process Forming the first active layer and the doped region includes:
  • the performing the first doping process on the first semiconductor pattern to form the second doped region comprises:
  • the exposed portion of the first semiconductor pattern is doped to form the second doped region.
  • performing a second doping process on the first semiconductor pattern including the second doped region to form the first doped region comprises:
  • the method of manufacturing the display substrate further includes removing the third photoresist pattern after forming the first doped region.
  • forming the doped regions of the first active layer and the second active layer by one patterning process includes:
  • Forming a second semiconductor film the second semiconductor film covers the first semiconductor pattern; forming a photoresist layer on the second semiconductor film; exposing and developing the photoresist layer to form a first a photoresist pattern corresponding to a position where the first active layer is located, and a second photoresist pattern corresponding to a position where the central region is located
  • the method of manufacturing the display substrate further includes:
  • first active layer and the doped region After forming the first active layer and the doped region by one patterning process, forming a first source drain pattern over the first active layer and forming a second source over the second doped region a drain pattern; depositing a first insulating layer and a resin layer on the first source drain pattern and the second source drain pattern; and performing a patterning process on the first insulating layer and the resin layer to a first through hole corresponding to a position corresponding to the first source/drain pattern in the first insulating layer and the resin layer, and corresponding to the second semiconductor pattern in the first insulating layer and the resin layer
  • the location forms a second via to expose the second semiconductor pattern.
  • the method of manufacturing the display substrate further includes forming the common electrode and removing the second semiconductor pattern by one patterning process after forming the first via and the second via.
  • forming the common electrode by one patterning process and removing the second semiconductor pattern includes depositing a common electrode material on the resin layer, and the common electrode material and the central region and the first A second semiconductor pattern on a doped region is patterned to form the common electrode and remove the second semiconductor pattern.
  • the method of manufacturing the display substrate further includes: after forming the doped regions of the first active layer and the second active layer by one patterning process, Forming a first source/drain pattern on the first active layer, and forming a second source/drain pattern on the doped region; depositing a first insulating layer on the first source drain pattern and the second source drain pattern And a resin layer; and performing a patterning process on the first insulating layer and the resin layer to form a first position in the first insulating layer and the resin layer corresponding to the first source/drain pattern a via hole, and a second via hole is formed at a position corresponding to the second semiconductor pattern in the first insulating layer and the resin layer to expose the second semiconductor pattern.
  • the method of manufacturing the display substrate further includes forming the common electrode and removing the second semiconductor pattern by one patterning process after forming the first via and the second via.
  • forming the common electrode by one patterning process and removing the second semiconductor pattern includes depositing a common electrode material on the resin layer, and applying the common electrode material and the second on the central region The semiconductor pattern is subjected to a patterning process to form the common electrode and remove the second semiconductor pattern.
  • the method of manufacturing the display substrate further includes: forming a first gate and the second thin film of the first thin film transistor by one patterning process on the substrate before forming the first semiconductor pattern a second gate of the transistor; and a gate insulating layer formed on the first gate and the second gate, the first semiconductor pattern being formed on the gate insulating layer.
  • the material of the first active layer comprises a metal oxide and the material of the second active layer comprises polysilicon.
  • a further embodiment of the present invention provides a display substrate comprising: a substrate; and a first thin film transistor and a second thin film transistor on the substrate, the first thin film transistor including a first active layer,
  • the second thin film transistor includes a second active layer including a central region and doped regions respectively located on both sides of the central region.
  • the first active layer and the doped regions are formed by a single patterning process.
  • the first active layer is a metal oxide active layer and the second active layer is a polysilicon active layer.
  • the doped region includes a first doped region and a second doped region, the first doped region being located between the second doped region and the central region.
  • the second thin film transistor further includes a second source drain pattern, the second source drain pattern covering the second doped region.
  • the second thin film transistor further includes a second source drain pattern, the second source drain pattern covering the doped region.
  • the display substrate includes a display area and a peripheral area located around the display area, the first thin film transistor is located within the display area, and the second thin film transistor is located within the peripheral area.
  • a further example of the present invention also provides a display device that can include a display substrate as described in any of the preceding embodiments.
  • FIG. 1 is a flow chart showing a method of manufacturing a display substrate according to an embodiment of the present invention
  • step S1 is a schematic structural view of step S1 in a manufacturing method according to an embodiment of the present invention
  • step S2 in a manufacturing method according to an embodiment of the present invention
  • step S3 is a schematic structural view of step S3 in a manufacturing method according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of step S41 in a manufacturing method according to an embodiment of the present invention.
  • step S43 is a schematic structural view of step S43 in a manufacturing method according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural view of step S44 in a manufacturing method according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of step S45 in a manufacturing method according to an embodiment of the present invention.
  • step S46 is a schematic structural view of step S46 in a manufacturing method according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of step S47 in a manufacturing method according to an embodiment of the present invention.
  • step S48 is a schematic structural view of step S48 in a manufacturing method according to an embodiment of the present invention.
  • step S5 is a schematic structural view of step S5 in a manufacturing method according to an embodiment of the present invention.
  • FIG. 13 is a schematic structural diagram of step S6 in a manufacturing method according to an embodiment of the present invention.
  • FIG. 14 is a schematic structural diagram of step S7 in a manufacturing method according to an embodiment of the present invention.
  • step S8 is a schematic structural view of step S8 in a manufacturing method according to an embodiment of the present invention.
  • step S9 is a schematic structural view of step S9 in a manufacturing method according to an embodiment of the present invention.
  • Figure 17 is a block diagram showing the structure of step S10 in the manufacturing method according to an embodiment of the present invention.
  • a method of fabricating a display substrate includes: providing a substrate; and forming a first thin film transistor including a first active layer and a second thin film transistor including a second active layer on the substrate.
  • the second active layer includes a central region and doped regions respectively located on both sides of the central region.
  • forming the first thin film transistor including the first active layer and the second thin film transistor including the second active layer on the substrate may include: forming the first active layer and the second active layer by one patterning process Doped area.
  • the display substrate may include a substrate 1, and a first thin film transistor and a second thin film transistor on the substrate 1.
  • the first thin film transistor includes a first active layer 3, and the second thin film transistor includes a second active layer 6.
  • the second active layer 6 includes a central region 61 and doped regions respectively located on both sides of the central region 61.
  • the display substrate may be provided with a display area A and a peripheral area B located around the display area A.
  • the first thin film transistor is located in the display area A, and the second thin film transistor is located in the peripheral area B.
  • the first active layer 3 may be, for example, a metal oxide active layer.
  • the second active layer 6 may be, for example, a polysilicon active layer.
  • One example of a method of manufacturing a display substrate according to an embodiment of the present invention may include the following steps.
  • step S1 the first gate electrode 2 and the second gate electrode 5 are formed on the substrate 1 by one patterning process.
  • the first gate 2 is located in the display area A
  • the second gate 5 is located in the peripheral area B.
  • the one-time patterning process in the embodiment of the present invention means that the photoresist is exposed and developed using only one mask, and a corresponding pattern is formed by etching.
  • step S2 a gate insulating layer 8 is formed on the first gate 2 and the second gate 5.
  • step S3 a first semiconductor pattern 9 is formed.
  • step S3 may include, for example, the steps of: depositing an amorphous silicon material layer on the gate insulating layer 8; performing a dehydrogenation process and an excimer laser annealing process on the amorphous silicon material layer to form a low temperature polysilicon material layer; Depositing a photoresist layer on the low temperature polysilicon material layer; exposing and developing the photoresist layer; etching the exposed low temperature polysilicon material layer; removing the remaining position corresponding to the second gate 5 a photoresist layer to form a first semiconductor pattern 9.
  • Step S4 forming a doped region of the first active layer of the first thin film transistor and the second active layer of the second thin film transistor by one patterning process.
  • the doped region of the second active layer may include a first doped region and a second doped region.
  • the first doped region is located between the second doped region and the central region.
  • the doped region of the second active layer is formed by doping the first semiconductor pattern 9. Therefore, forming the first active layer and the doped region by one patterning process may include: performing a first doping process on the first semiconductor pattern to form the second doped region; and including the second doping
  • the first semiconductor pattern of the impurity region is subjected to a second doping process to form the first doped region.
  • step S4 may specifically include the following steps.
  • Step S41 referring to FIG. 5, a second semiconductor film 10 is formed, and the second semiconductor film 10 covers the first semiconductor pattern 9. As shown in FIG. 5, the second semiconductor film 10 covers the gate insulating layer 8 and the first semiconductor pattern 9 on the gate insulating layer 8, and the second active layer 6 may be formed based on the first semiconductor pattern.
  • step S42 a photoresist layer is formed on the second semiconductor film 10.
  • Step S43 referring to FIG. 6, the photoresist layer is exposed and developed to form a first photoresist pattern 11 and a second photoresist pattern 12.
  • the first photoresist pattern 11 corresponds to a position where the first active layer is located
  • the second photoresist pattern 12 corresponds to a position where the central region and the first doped region are located.
  • a portion of the second semiconductor thin film 10 is exposed after development of the photoresist layer.
  • the first photoresist pattern 11 is located in the display area A
  • the second photoresist pattern 12 is located in the peripheral area B.
  • the projection of the second photoresist pattern 12 on the substrate 1 is located within the projection of the first semiconductor pattern 9 on the substrate 1.
  • Step S44 referring to FIG. 7, etching the second semiconductor film 10 to form the first active layer pattern 31 and the second semiconductor pattern 101, and exposing a portion of the first semiconductor pattern Case 9.
  • the second semiconductor pattern 101 corresponds to a position where the central region and the first doped region are located.
  • the exposed second semiconductor film 10 is etched. Since the projection of the second photoresist pattern 12 on the substrate 1 is located within the projection of the first semiconductor pattern 9 on the substrate 1, the edge portion of the first semiconductor pattern 9 is exposed.
  • the edge portion of the first semiconductor pattern 9 can be regarded as the first region to be doped 13.
  • Step S45 referring to FIG. 8, the exposed portion of the first semiconductor pattern 9 is doped to form a second doped region 622.
  • a portion of the exposed first semiconductor pattern 9 ie, the first region to be doped 13
  • step S46 the second photoresist pattern 12 is subjected to ashing treatment to form a third photoresist pattern 121.
  • the third photoresist pattern 121 corresponds to a position where the central region is located.
  • the second photoresist pattern 12 is subjected to ashing treatment to reduce the coverage area of the second photoresist pattern 12, thereby forming the third photoresist pattern 121.
  • the projection of the third photoresist pattern 121 on the substrate 1 is located within the projection of the doped region on the substrate 1.
  • the projection of the doped region on the substrate 1 comprises a projection of the second doped region 622 on the substrate 1 and a projection of the second region to be doped 14 of the first semiconductor pattern 9 on the substrate 1.
  • Step S47 referring to FIG. 10, the first semiconductor pattern 9 is doped a second time to form a first doped region 621.
  • the second region to be doped 14 may be lightly doped to form a first doped region 621. It can be understood that the doped region of the second active layer includes a first doped region 621 and a second doped region 622.
  • Step S48 referring to FIG. 11, the first photoresist pattern 11 and the third photoresist pattern 121 are removed. As shown in FIG. 11, the first photoresist pattern 11 and the third photoresist pattern 121 are removed to form the first active layer 3, and the second semiconductor pattern 101 on the first semiconductor pattern 9 is exposed. It can be understood that the first photoresist pattern 11 and the third photoresist pattern 121 may not be simultaneously removed. For example, the first photoresist pattern 11 may be removed before the step S48.
  • the first active layer 3 is made of, for example, indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the material of the first active layer 3 is not limited thereto. Other types of materials may also be used to form the first active layer 3, which will not be described herein.
  • Step S5 referring to FIG. 12, a first source/drain pattern 4 is formed on the first active layer 3, and a second source/drain pattern 7 is formed on the second doped region 622.
  • the first source drain pattern 4 includes a first source 41 and a first drain 42. a portion of the first source 41 is located on the first active layer 3, and a portion of the first drain 42 is located at the first On the source layer 3.
  • the second source drain pattern 7 includes a second source 71 and a second drain 72. A portion of the second source 71 is located on the second doped region 622, and a portion of the second drain 72 is located on the second doped region 622. It should be noted that, since the first semiconductor pattern 9 is further covered with the second semiconductor pattern 101, the second semiconductor pattern 101 can avoid the first semiconductor pattern 9 and the first source drain pattern 4 and the second source drain pattern.
  • the etching material of 7 is in contact, so that the first semiconductor pattern 9 can be protected when the source and the drain are formed by etching.
  • Step S6 referring to FIG. 13, a first insulating layer 15 and a resin layer 16 are deposited on the first source drain pattern 4 and the second source drain pattern 7.
  • the first insulating layer 15 may be, for example, an interlayer dielectric layer.
  • Step S7 referring to FIG. 14, a first patterning process is performed on the first insulating layer 15 and the resin layer 16 to form a first via hole at a position corresponding to the first source/drain pattern 4 in the first insulating layer 15 and the resin layer 16. 17, and a second via hole 18 is formed at a position corresponding to the second semiconductor pattern 101 in the first insulating layer 15 and the resin layer 16, thereby exposing the second semiconductor pattern 101.
  • performing a patterning process on the first insulating layer 15 and the resin layer 16 may include: depositing a photoresist layer on the resin layer 16; and exposing the photoresist layer by using a mask. And developing; then etching the first insulating layer 15 and the resin layer 16 to form the first via hole 17 and the second via hole 18 in the first insulating layer 15 and the resin layer 16.
  • the first via hole 17 exposes a portion of the first drain electrode 42
  • the second via hole 18 exposes the second semiconductor pattern 101 on the first semiconductor pattern 9.
  • Step S8 referring to FIG. 15, the common electrode 19 is formed by one patterning process and the second semiconductor pattern 101 is removed.
  • step S8 may include depositing a common electrode material (eg, ITO) on the resin layer 16, and patterning the common electrode material and the second semiconductor pattern 101 on the central region 61 and the first doped region 621 to form The common electrode 19 removes the second semiconductor pattern 101.
  • a common electrode material eg, ITO
  • the second semiconductor pattern 101 located on the central region 61 of the second active layer and the first doped region 621 may be etched away to form a common electrode. 19, and exposing the central region 61 of the second active layer 6 and the first doped region 621.
  • the common electrode and the second semiconductor pattern 101 may be made of the same material (for example, metal oxide), or may be made of different materials.
  • the common electrode material and the second semiconductor pattern can be simultaneously engraved by the selection of the etching material Etched.
  • Step S9 referring to FIG. 16, a passivation layer material is deposited on the common electrode 19 and the resin layer 16, and a passivation layer material is patterned to form a passivation layer 20.
  • a first through hole 17 is provided in the passivation layer 20.
  • Step S10 referring to FIG. 17, a pixel electrode material is deposited on the passivation layer 20 and in the first via hole 17, and a pixel electrode material is patterned to form the pixel electrode 21.
  • the pixel electrode 21 is located on the passivation layer 20 and in the first via hole 17 to be connected to the first drain electrode 42 through the first via hole 17.
  • the doping regions of the first active layer 3 and the second active layer 6 are formed by one patterning process.
  • the second semiconductor pattern 101 on the second active layer 6 can be used as a mask for forming a doped region of the second active layer 6 on the one hand, and can also prevent formation of a second source and drain on the other hand.
  • the pattern 7 etches the contact of the substance with the second active layer 6.
  • the second semiconductor patterns 101 on the second active layer 6 may be removed together when the common electrode 19 is formed, thereby reducing process complexity and manufacturing cost.
  • a display substrate includes a substrate 1, and a first thin film transistor and a second thin film transistor on the substrate 1.
  • the first thin film transistor includes a first active layer 3, and the second thin film transistor includes a second active layer 6.
  • the second active layer 6 includes a central region 61 and doped regions respectively located on both sides of the central region 61.
  • the first thin film transistor and the second thin film transistor may both be thin film transistors of a bottom gate structure.
  • the first thin film transistor and the second thin film transistor may also be thin film transistors of a top gate structure.
  • one of the first thin film transistor and the second thin film transistor is a thin film transistor of a top gate structure, and the other is a thin film transistor of a bottom gate structure.
  • the doped regions of the first active layer 3 and the second active layer 6 may be formed by one patterning process.
  • the first active layer 3 may be a metal oxide active layer
  • the second active layer 6 may be a polysilicon active layer.
  • the doped region may include a first doped region 621 and a second doped region 622.
  • the first doped region 621 is located between the second doped region 622 and the central region 61.
  • the second thin film transistor further includes a second source drain pattern 7 covering the second doped region 622.
  • the display substrate may be provided with a display area A and a peripheral area B located around the display area A.
  • the first thin film transistor is located in the display area A, and the second thin film transistor is located in the peripheral area B.
  • the display substrate of this embodiment can be manufactured by using the above-described manufacturing method of the display substrate, and details are not described herein again.
  • another method of fabricating a display substrate is provided.
  • the difference from the manufacturing method of the display substrate provided by the above embodiment is that the doped region of the formed second thin film transistor does not include the first doped region and the second doped region, but includes only one type of doping. Miscellaneous area. Accordingly, in the manufacturing method of the other display substrate, the specific flow of steps S4 and S5 is different.
  • step S4 may include the following steps.
  • step S41 a second semiconductor film is formed, and the second semiconductor film covers the first semiconductor pattern.
  • Step S42 forming a photoresist layer on the second semiconductor film.
  • step S43 the photoresist layer is exposed and developed to form a first photoresist pattern and a second photoresist pattern.
  • the first photoresist pattern corresponds to a position where the first active layer is located
  • the second photoresist pattern corresponds to a position where the central region is located.
  • Step S44 etching the second semiconductor film to form a first active layer pattern and a second semiconductor pattern, and exposing a portion of the first semiconductor pattern.
  • the second semiconductor pattern corresponds to a location where the central region is located.
  • Step S45 doping the exposed portion of the first semiconductor pattern to form a doped region.
  • Step S46 removing the first photoresist pattern and the second photoresist pattern.
  • the second photolithography is not required.
  • the glue pattern is ashed and the second semiconductor pattern does not need to be doped a second time. That is, the doping region is formed only once by doping.
  • step S5 specifically, a first source/drain pattern is formed on the first active layer, and a second source/drain pattern is formed on the doped region. That is, the second source drain pattern is formed on the doped region instead of the second doped region as compared with step S5 in the previously described method of manufacturing the display substrate.
  • the doped regions of the first active layer and the second active layer are formed by one patterning process.
  • the second semiconductor pattern on the second active layer can be used as a mask for forming a doped region of the second active layer on the one hand, and can also prevent etching when forming the second source/drain pattern on the other hand. Contact of the substance with the second active layer.
  • the second semiconductor patterns on the second active layer may be removed together when forming the common electrode, thereby reducing process complexity and manufacturing cost.
  • a display substrate having a structure similar to that of the previously described display substrate, except that the doped region of the second thin film transistor does not include the first doped region and the Two doped regions, but only one type of doped region. Therefore, the second source drain pattern included in the second thin film transistor covers the doped region instead of covering the second doped region.
  • the display substrate of this embodiment can be manufactured by using the above-described other manufacturing method of the display substrate, and details are not described herein again.
  • a display panel may include the above display substrate. It can be understood that the display panel of the embodiment may further include a pair of cassette substrates disposed opposite to the display substrate.
  • a display device may include the above display substrate.
  • the display device can be any display product, electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator and the like with any display product or component.

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Abstract

一种显示基板及其制造方法，以及显示装置。显示基板的制造方法包括：提供衬底（1）；以及，在衬底（1）上形成包括第一有源层（3）的第一薄膜晶体管和包括第二有源层（6）的第二薄膜晶体管。第二有源层（6）包括中心区域（61）和分别位于中心区域（61）两侧的掺杂区域。在衬底上形成包括第一有源层（3）的第一薄膜晶体管和包括第二有源层（6）的第二薄膜晶体管包括：通过一次构图工艺形成第一有源层（3）和第二有源层（6）的掺杂区域。

Description

显示基板及其制造方法、显示装置
相关引用
本申请要求于2016年10月31日递交的中国专利申请No.201610930682.5的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本发明涉及显示技术领域，尤其涉及一种显示基板及其制造方法，以及显示装置。
背景技术
当前，与显示面板相关的产业作为电子行业的基础产业，其技术在不断的演变和革新。其中，氧化物技术和低温多晶硅技术因其自身的优点而被广泛应用。更具体而言，低温多晶硅晶体管的优点在于其具有较高的电子迁移率。但同时，低温多晶硅晶体管也具有漏电流大的缺点。而氧化物晶体管的优点在于其具有较小的漏电流。但氧化物晶体管存在电子迁移率低的问题。
由于氧化物晶体管和低温多晶硅晶体管各自的缺点，二者在实际的应用中都受到了限制。更具体而言，低温多晶硅晶体管的漏电流过大，不适用于显示区域。
在现有的制造包括低温多晶硅晶体管和氧化物晶体管的显示基板的工艺中，多采用顶栅结构，以栅极作为低温多晶硅晶体管中掺杂区域的掩膜。但对于底栅结构的低温多晶硅晶体管而言，则需要多设计一个掩膜板，这无疑增加了制造工艺的复杂性和制造成本。
发明内容
因此，所期望的是提供能够降低工艺复杂性和制造成本的显示基板及其制造方法、以及显示装置。
根据一个方面，提供了一种显示基板的制造方法，包括：提供衬底；以及在所述衬底上形成包括第一有源层的第一薄膜晶体管和包括第二有源层的第二薄膜晶体管。第二有源层包括中心区域和分别位于 所述中心区域两侧的掺杂区域，并且，在所述衬底上形成包括第一有源层的第一薄膜晶体管和包括第二有源层的第二薄膜晶体管包括：通过一次构图工艺形成所述第一有源层和所述掺杂区域。
在一些实施例中，显示基板的制造方法还包括：在通过一次构图工艺形成所述第一有源层和所述第二有源层的掺杂区域之前，形成第一半导体图案，第二有源层的掺杂区域是通过对所述第一半导体图案进行掺杂形成的。
在一些实施例中，掺杂区域包括第一掺杂区域和第二掺杂区域，所述第一掺杂区域位于所述第二掺杂区域和所述中心区域之间，并且通过一次构图工艺形成所述第一有源层和所述掺杂区域包括：
在所述第一半导体图案进行第一掺杂工艺处理形成所述第二掺杂区域；以及对包含有所述第二掺杂区域的第一半导体图案进行第二次掺杂工艺处理形成所述第一掺杂区域。
在一些实施例中，所述对所述第一半导体图案进行第一掺杂工艺处理形成所述第二掺杂区域包括：
形成第二半导体薄膜，所述第二半导体薄膜覆盖所述第一半导体图案；
在所述第二半导体薄膜上形成光刻胶层；
对所述光刻胶层进行曝光、显影，以形成第一光刻胶图案和第二光刻胶图案，所述第一光刻胶图案对应于所述第一有源层所在的位置，所述第二光刻胶图案对应于所述中心区域和所述第一掺杂区域所在的位置；
对所述第二半导体薄膜进行刻蚀，以形成第一有源层和第二半导体图案，并露出部分所述第一半导体图案，所述第二半导体图案对应于所述中心区域和所述第一掺杂区域所在的位置；
对露出的部分所述第一半导体图案进行掺杂，以形成所述第二掺杂区域。
进一步地，在一些实施例中，对包含有所述第二掺杂区域的第一半导体图案进行第二次掺杂工艺处理形成所述第一掺杂区域包括：
对所述第二光刻胶图案进行灰化处理，以形成第三光刻胶图案，所述第三光刻胶图案对应于所述中心区域所在的位置；
对所述第一半导体图案进行第二次掺杂，以形成所述第一掺杂区 域。
进一步地，在一些实施例中，显示基板的制造方法还包括：在形成所述第一掺杂区域之后，去除所述第三光刻胶图案。
在一些实施例中，通过一次构图工艺形成所述第一有源层和所述第二有源层的掺杂区域包括：
形成第二半导体薄膜，所述第二半导体薄膜覆盖所述第一半导体图案；在所述第二半导体薄膜上形成光刻胶层；对所述光刻胶层进行曝光、显影，以形成第一光刻胶图案和第二光刻胶图案，所述第一光刻胶图案对应于所述第一有源层所在的位置，所述第二光刻胶图案对应于所述中心区域所在的位置；对所述第二半导体薄膜进行刻蚀，以形成第一有源层和第二半导体图案，并露出部分所述第一半导体图案，所述第二半导体图案对应于所述中心区域所在的位置；对露出的部分所述第一半导体图案进行掺杂，以形成所述掺杂区域；以及去除所述第一光刻胶图案和所述第二光刻胶图案。
在一些实施例中，显示基板的制造方法还包括：
在通过一次构图工艺形成所述第一有源层和所述掺杂区域之后，在所述第一有源层上方形成第一源漏图形，在所述第二掺杂区域上方形成第二源漏图形；在所述第一源漏图形和所述第二源漏图形上沉积第一绝缘层和树脂层；以及对所述第一绝缘层和所述树脂层进行一次构图工艺，以在所述第一绝缘层和所述树脂层中与所述第一源漏图形对应的位置形成第一通孔，并且在所述第一绝缘层和所述树脂层中与所述第二半导体图案对应的位置形成第二通孔以露出所述第二半导体图案。
在一些实施例中，显示基板的制造方法还包括：在形成所述第一通孔和所述第二通孔之后，通过一次构图工艺形成公共电极并去除所述第二半导体图案。
在一些实施例中，通过一次构图工艺形成公共电极并去除所述第二半导体图案包括：在所述树脂层上沉积公共电极材料，并对所述公共电极材料以及所述中心区域和所述第一掺杂区域上的第二半导体图案进行构图工艺，以形成所述公共电极并去除所述第二半导体图案。
在一些实施例中，显示基板的制造方法还包括：在通过一次构图工艺形成所述第一有源层和所述第二有源层的掺杂区域之后，在所述 第一有源层上形成第一源漏图形，并且在所述掺杂区域上形成第二源漏图形；在所述第一源漏图形和所述第二源漏图形上沉积第一绝缘层和树脂层；以及对所述第一绝缘层和所述树脂层进行一次构图工艺，以在所述第一绝缘层和所述树脂层中与所述第一源漏图形对应的位置形成第一通孔，并且在所述第一绝缘层和所述树脂层中与所述第二半导体图案对应的位置形成第二通孔以露出所述第二半导体图案。
在一些实施例中，显示基板的制造方法还包括：在形成所述第一通孔和所述第二通孔之后，通过一次构图工艺形成公共电极并去除所述第二半导体图案。
在一些实施例中，通过一次构图工艺形成公共电极并去除所述第二半导体图案包括：在所述树脂层上沉积公共电极材料，并对所述公共电极材料以及所述中心区域上的第二半导体图案进行构图工艺，以形成所述公共电极并去除所述第二半导体图案。
在一些实施例中，显示基板的制造方法还包括：在形成第一半导体图案之前，在所述衬底上通过一次构图工艺形成所述第一薄膜晶体管的第一栅极和所述第二薄膜晶体管的第二栅极；以及在所述第一栅极和所述第二栅极上形成栅绝缘层，所述第一半导体图案形成在所述栅绝缘层上。
在一些实施例中，第一有源层的材料包括金属氧化物，第二有源层的材料包括多晶硅。
本发明的另外的实施例提供了一种显示基板，包括：衬底；以及位于所述衬底上的第一薄膜晶体管和第二薄膜晶体管，所述第一薄膜晶体管包括第一有源层，所述第二薄膜晶体管包括第二有源层，所述第二有源层包括中心区域和分别位于所述中心区域两侧的掺杂区域。
在一些实施例中，第一有源层和掺杂区域是通过一次构图工艺形成的。
在一些实施例中，第一有源层为金属氧化物有源层，第二有源层为多晶硅有源层。
在一些实施例中，掺杂区域包括第一掺杂区域和第二掺杂区域，第一掺杂区域位于第二掺杂区域和中心区域之间。
在一些实施例中，第二薄膜晶体管还包括第二源漏图形，第二源漏图形覆盖所述第二掺杂区域。
在一些实施例中，第二薄膜晶体管还包括第二源漏图形，第二源漏图形覆盖所述掺杂区域。
在一些实施例中，显示基板包括显示区域和位于所述显示区域周围的周边区域，所述第一薄膜晶体管位于所述显示区域内，所述第二薄膜晶体管位于所述周边区域内。
本发明的另外的示例还提供功率一种显示装置，其可包括如前述实施例中任一实施例所述的显示基板。
附图说明
图1为根据本发明实施例的显示基板的制造方法的流程示意图；
图2为根据本发明实施例的制造方法中步骤S1的结构示意图；
图3为根据本发明实施例的制造方法中步骤S2的结构示意图；
图4为根据本发明实施例的制造方法中步骤S3的结构示意图；
图5为根据本发明实施例的制造方法中步骤S41的结构示意图；
图6为根据本发明实施例的制造方法中步骤S43的结构示意图；
图7为根据本发明实施例的制造方法中步骤S44的结构示意图；
图8为根据本发明实施例的制造方法中步骤S45的结构示意图；
图9为根据本发明实施例的制造方法中步骤S46的结构示意图；
图10为根据本发明实施例的制造方法中步骤S47的结构示意图；
图11为根据本发明实施例的制造方法中步骤S48的结构示意图；
图12为根据本发明实施例的制造方法中步骤S5的结构示意图；
图13为根据本发明实施例的制造方法中步骤S6的结构示意图；
图14为根据本发明实施例的制造方法中步骤S7的结构示意图；
图15为根据本发明实施例的制造方法中步骤S8的结构示意图；
图16为根据本发明实施例的制造方法中步骤S9的结构示意图；
图17为根据本发明实施例的制造方法中步骤S10的结构示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明的实施例作进一步地详细描述。
在下面的描述中，将用到以下附图标记：
A、显示区域；B、周边区域；1、衬底；2、第一栅极；3、第一有 源层；31、第一有源层图形；4、第一源漏图形；41、第一源极；42、第一漏极；5、第二栅极；6、第二有源层；61、中心区域；621、第一掺杂区域；622、第二掺杂区域；7、第二源漏图形；71、第二源极；72、第二漏极；8、栅绝缘层；9、第一半导体图案；10、第二半导体薄膜；101、第二半导体图案；11、第一光刻胶图案；12、第二光刻胶图案；121、第三光刻胶图案；13、第一待掺杂区域；14、第二待掺杂区域；15、第一绝缘层；16、树脂层；17、第一通孔；18、第二通孔；19、公共电极；20、钝化层；21、像素电极。
根据本发明的一个实施例，提供了一种显示基板的制造方法。该方法包括：提供衬底；以及，在衬底上形成包括第一有源层的第一薄膜晶体管和包括第二有源层的第二薄膜晶体管。第二有源层包括中心区域和分别位于中心区域两侧的掺杂区域。并且，在衬底上形成包括第一有源层的第一薄膜晶体管和包括第二有源层的第二薄膜晶体管可以包括：通过一次构图工艺形成第一有源层和第二有源层的掺杂区域。
更具体而言，请参照图1至图17。图1至图17示出了根据本发明实施例的显示基板的制造方法的一个实例。如图17所示，显示基板可以包括衬底1，以及位于衬底1上的第一薄膜晶体管和第二薄膜晶体管。第一薄膜晶体管包括第一有源层3，第二薄膜晶体管包括第二有源层6。第二有源层6包括中心区域61和分别位于中心区域61两侧的掺杂区域。显示基板可以设置有显示区域A和位于显示区域A周围的周边区域B。第一薄膜晶体管位于显示区域A内，第二薄膜晶体管位于周边区域B内。第一有源层3例如可以为金属氧化物有源层。第二有源层6例如可以为多晶硅有源层。
根据本发明实施例的显示基板的制造方法的一个实例可以包括以下步骤。
请参照图2，步骤S1，在衬底1上通过一次构图工艺形成第一栅极2和第二栅极5。第一栅极2位于显示区域A内，第二栅极5位于周边区域B内。
需要说明的是，本发明实施例中所说的一次构图工艺是指，只使用一个掩膜板对光刻胶进行曝光、显影，并通过刻蚀形成相应的图案。
请参照图3，步骤S2，在第一栅极2和第二栅极5上形成栅绝缘层8。
请参照图4，步骤S3，形成第一半导体图案9。
如图4所示，第一半导体图案9位于栅绝缘层8上。可以理解的是，步骤S3例如可以包括以下步骤：在栅绝缘层8上沉积非晶硅材料层；对非晶硅材料层进行去氢工艺和准分子激光退火工艺，以形成低温多晶硅材料层；在低温多晶硅材料层上沉积光刻胶层；对光刻胶层进行曝光、显影工艺；对露出的低温多晶硅材料层进行刻蚀工艺；去除剩余的、位于与第二栅极5相对应的位置的光刻胶层，以形成第一半导体图案9。
步骤S4，通过一次构图工艺形成第一薄膜晶体管的第一有源层和第二薄膜晶体管的第二有源层的掺杂区域。第二有源层的掺杂区域可以包括第一掺杂区域和第二掺杂区域。第一掺杂区域位于第二掺杂区域和中心区域之间。第二有源层的掺杂区域是通过对第一半导体图案9进行掺杂而形成的。因此，通过一次构图工艺形成第一有源层和掺杂区域可包括：对所述第一半导体图案进行第一掺杂工艺处理形成所述第二掺杂区域；对包含有所述第二掺杂区域的第一半导体图案进行第二次掺杂工艺处理形成所述第一掺杂区域。
例如，步骤S4具体可以包括以下步骤。
步骤S41，请参照图5，形成第二半导体薄膜10，第二半导体薄膜10覆盖第一半导体图案9。如图5所示，第二半导体薄膜10覆盖栅绝缘层8和位于栅绝缘层8上的第一半导体图案9，可以基于第一半导体图案形成第二有源层6。
步骤S42，在第二半导体薄膜10上形成光刻胶层。
步骤S43，请参照图6，对光刻胶层进行曝光、显影，以形成第一光刻胶图案11和第二光刻胶图案12。第一光刻胶图案11对应于第一有源层所在的位置，第二光刻胶图案12对应于中心区域和第一掺杂区域所在的位置。
如图6所示，部分第二半导体薄膜10在光刻胶层显影后露出。第一光刻胶图案11位于显示区域A内，第二光刻胶图案12位于周边区域B内。第二光刻胶图案12在衬底1上的投影位于第一半导体图案9在衬底1上的投影之内。
步骤S44，请参照图7，对第二半导体薄膜10进行刻蚀，以形成第一有源层图形31和第二半导体图案101，并露出部分第一半导体图 案9。第二半导体图案101对应于中心区域和第一掺杂区域所在的位置。
如图7所示，对露出的第二半导体薄膜10进行刻蚀。由于第二光刻胶图案12在衬底1上的投影位于第一半导体图案9在衬底1上的投影之内，因此，第一半导体图案9的边缘部分露出。可以将第一半导体图案9的边缘部分视为第一待掺杂区域13。
步骤S45，请参照图8，对露出的部分第一半导体图案9进行掺杂，以形成第二掺杂区域622。如图8所示，可以对露出的部分第一半导体图案9(即第一待掺杂区域13)进行重掺杂，以形成第二掺杂区域622。
步骤S46，对第二光刻胶图案12进行灰化处理，以形成第三光刻胶图案121。第三光刻胶图案121对应于中心区域所在的位置。
如图9所示，对第二光刻胶图案12进行灰化处理，以减小第二光刻胶图案12的覆盖面积，从而形成第三光刻胶图案121。第三光刻胶图案121在衬底1上的投影位于掺杂区域在衬底1上的投影之内。该掺杂区域在衬底1上的投影包括第二掺杂区域622在衬底1上的投影和第一半导体图案9的第二待掺杂区域14在衬底1上的投影。
步骤S47，请参照图10，对第一半导体图案9进行第二次掺杂，以形成第一掺杂区域621。如图10所示，可以对第二待掺杂区域14进行轻掺杂，以形成第一掺杂区域621。可以理解的是，第二有源层的掺杂区域包括第一掺杂区域621和第二掺杂区域622。
步骤S48，请参照图11，去除第一光刻胶图案11和第三光刻胶图案121。如图11所示，去除第一光刻胶图案11和第三光刻胶图案121，以形成第一有源层3，并使位于第一半导体图案9上的第二半导体图案101露出。能够理解到的是，第一光刻胶图案11和第三光刻胶图案121可以不是同时被去除，例如，第一光刻胶图案11可以在该步骤S48之前被去除。
第一有源层3例如采用铟镓锌氧化物(IGZO)制成。当然，第一有源层3的材料并不局限于此。还可以采用其他类型的材料来形成第一有源层3，在此不再赘述。
步骤S5，请参照图12，在第一有源层3上形成第一源漏图形4，并且在第二掺杂区域622上形成第二源漏图形7。
如图12所示，第一源漏图形4包括第一源极41和第一漏极42。部分第一源极41位于第一有源层3上，部分第一漏极42位于第一有 源层3上。第二源漏图形7包括第二源极71和第二漏极72。部分第二源极71位于第二掺杂区域622上，部分第二漏极72位于第二掺杂区域622上。需要说明的是，由于第一半导体图案9上还覆盖有第二半导体图案101，因此，该第二半导体图案101能够避免第一半导体图案9与形成第一源漏图形4和第二源漏图形7的刻蚀物质接触，从而能够在通过刻蚀形成源极和漏极时保护第一半导体图案9。
步骤S6，请参照图13，在第一源漏图形4和第二源漏图形7上沉积第一绝缘层15和树脂层16。第一绝缘层15例如可以为层间电介质层。
步骤S7，请参照图14，对第一绝缘层15和树脂层16进行一次构图工艺，以在第一绝缘层15和树脂层16中与第一源漏图形4对应的位置形成第一通孔17，并且在第一绝缘层15和树脂层16中与第二半导体图案101对应的位置形成第二通孔18，从而露出第二半导体图案101。
如图14所示，可以理解的是，对第一绝缘层15和树脂层16进行一次构图工艺可以包括：在树脂层16上沉积光刻胶层；采用掩膜板对光刻胶层进行曝光、显影；然后对第一绝缘层15和树脂层16进行刻蚀，从而在第一绝缘层15和树脂层16中形成第一通孔17和第二通孔18。第一通孔17使部分第一漏极42露出，第二通孔18使位于第一半导体图案9上的第二半导体图案101露出。
步骤S8，请参照图15，通过一次构图工艺形成公共电极19并去除第二半导体图案101。
例如，步骤S8可以包括：在树脂层16上沉积公共电极材料(例如ITO)，并对公共电极材料以及中心区域61和第一掺杂区域621上的第二半导体图案101进行构图工艺，以形成公共电极19并去除第二半导体图案101。
请参照图15，在对公共电极材料进行刻蚀时，还可以将位于第二有源层的中心区域61和第一掺杂区域621上的第二半导体图案101刻蚀掉，从而形成公共电极19，并露出第二有源层6的中心区域61和第一掺杂区域621。需要说明的是，公共电极和第二半导体图案101可以采用同类材料(例如金属氧化物)制成，也可以采用不同的材料制成。可以通过刻蚀材料的选取，将公共电极材料和第二半导体图案同时刻 蚀掉。
步骤S9，请参照图16，在公共电极19和树脂层16上沉积钝化层材料，并对钝化层材料进行构图工艺，以形成钝化层20。在钝化层20中设置有第一通孔17。
步骤S10，请参照图17，在钝化层20上以及第一通孔17中沉积像素电极材料，并对像素电极材料进行构图工艺，以形成像素电极21。如图17所示，像素电极21位于钝化层20上和第一通孔17中，以通过第一通孔17与第一漏极42连接。
在根据本实施例的显示基板的制造方法中，通过一次构图工艺形成第一有源层3和第二有源层6的掺杂区域。而位于第二有源层6上的第二半导体图案101，一方面能够作为用于形成第二有源层6的掺杂区域的掩膜板，另一方面还能够防止在形成第二源漏图形7时刻蚀物质与第二有源层6的接触。位于第二有源层6上的第二半导体图案101可以在形成公共电极19时被一起去除，从而降低工艺复杂性和制造成本。
根据本发明的另一实施例，提供了一种显示基板。例如，如图17所示，该显示基板包括衬底1，以及位于衬底1上的第一薄膜晶体管和第二薄膜晶体管。第一薄膜晶体管包括第一有源层3，第二薄膜晶体管包括第二有源层6。第二有源层6包括中心区域61和分别位于中心区域61两侧的掺杂区域。第一薄膜晶体管和第二薄膜晶体管可以都为底栅结构的薄膜晶体管。当然，第一薄膜晶体管和第二薄膜晶体管也可以都为顶栅结构的薄膜晶体管。或者，第一薄膜晶体管和第二薄膜晶体管中的一个为顶栅结构的薄膜晶体管，另一个为底栅结构的薄膜晶体管。
第一有源层3和第二有源层6的掺杂区域可以通过一次构图工艺形成。
第一有源层3可以为金属氧化物有源层，第二有源层6可以为多晶硅有源层。
掺杂区域可以包括第一掺杂区域621和第二掺杂区域622。第一掺杂区域621位于第二掺杂区域622和中心区域61之间。
第二薄膜晶体管还包括第二源漏图形7，第二源漏图形7覆盖第二掺杂区域622。
显示基板可以设置有显示区域A和位于显示区域A周围的周边区域B。第一薄膜晶体管位于显示区域A内，第二薄膜晶体管位于周边区域B内。
本实施例的显示基板可以采用上述显示基板的制造方法制造而成，在此不再赘述。
根据本发明的另一实施例，提供了另一种显示基板的制造方法。其与上述实施例提供的显示基板的制造方法的区别在于，所形成的第二薄膜晶体管的掺杂区域并不包括第一掺杂区域和第二掺杂区域，而仅仅包括一种类型的掺杂区域。相应地，在该另一种显示基板的制造方法中，步骤S4、S5的具体流程不同。
具体地，步骤S4可以包括如下步骤。
步骤S41，形成第二半导体薄膜，第二半导体薄膜覆盖第一半导体图案。
步骤S42，在第二半导体薄膜上形成光刻胶层。
步骤S43，对光刻胶层进行曝光、显影，以形成第一光刻胶图案和第二光刻胶图案。第一光刻胶图案对应于第一有源层所在的位置，第二光刻胶图案对应于中心区域所在的位置。
步骤S44，对第二半导体薄膜进行刻蚀，以形成第一有源层图形和第二半导体图案，并露出部分第一半导体图案。第二半导体图案对应于中心区域所在的位置。
步骤S45，对露出的部分第一半导体图案进行掺杂，以形成掺杂区域。
步骤S46，去除第一光刻胶图案和第二光刻胶图案。
可见，在该另一种显示基板的制造方法的步骤S4中，由于不需要形成两种类型的掺杂区域(第一掺杂区域和第二掺杂区域)，因此，无需对第二光刻胶图案进行灰化，且无需对第一半导体图案进行第二次掺杂。即，只进行一次掺杂即形成掺杂区域。
关于步骤S5，具体可以为：在第一有源层上形成第一源漏图形，并且在掺杂区域上形成第二源漏图形。即，与之前描述的显示基板的制造方法中的步骤S5相比，第二源漏图形形成在掺杂区域上，而不是形成在第二掺杂区域上。
关于其他步骤，可参照之前描述的显示基板的制造方法，在此不 再赘述。
在根据本实施例的显示基板的制造方法中，通过一次构图工艺形成第一有源层和第二有源层的掺杂区域。而位于第二有源层上的第二半导体图案，一方面能够作为用于形成第二有源层的掺杂区域的掩膜板，另一方面还能够防止在形成第二源漏图形时刻蚀物质与第二有源层的接触。位于第二有源层上的第二半导体图案可以在形成公共电极时被一起去除，从而降低工艺复杂性和制造成本。
根据本发明的又一实施例，提供了一种显示基板，其具有与之前描述的显示基板相似的结构，区别仅在于，第二薄膜晶体管的掺杂区域并不包括第一掺杂区域和第二掺杂区域，而仅仅包括一种类型的掺杂区域。因此，第二薄膜晶体管所包括的第二源漏图形覆盖该掺杂区域，而不是覆盖第二掺杂区域。
本实施例的显示基板可以采用上述另一种显示基板的制造方法来制造，在此不再赘述。
根据本发明的又一实施例，提供了一种显示面板。该显示面板可以包括上述显示基板。可以理解的是，本实施例的显示面板还可以包括与显示基板相对设置的对盒基板。
根据本发明的又一实施例，提供了一种显示装置。该显示装置可以包括上述显示基板。显示装置可以为：显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为涵盖在本发明的保护范围内。

Claims (23)

  1. 一种显示基板的制造方法，包括：
    提供衬底；以及
    在所述衬底上形成包括第一有源层的第一薄膜晶体管和包括第二有源层的第二薄膜晶体管，
    其中，所述第二有源层包括中心区域和分别位于所述中心区域两侧的掺杂区域，并且
    其中，在所述衬底上形成包括第一有源层的第一薄膜晶体管和包括第二有源层的第二薄膜晶体管包括：通过一次构图工艺形成所述第一有源层和所述掺杂区域。
  2. 根据权利要求1所述的制造方法，还包括：在通过一次构图工艺形成所述第一有源层和所述第二有源层的掺杂区域之前，形成第一半导体图案，
    其中，所述第二有源层的掺杂区域是通过对所述第一半导体图案进行掺杂形成的。
  3. 根据权利要求2所述的制造方法，其中，所述掺杂区域包括第一掺杂区域和第二掺杂区域，所述第一掺杂区域位于所述第二掺杂区域和所述中心区域之间，并且
    其中，通过一次构图工艺形成所述第一有源层和所述掺杂区域包括：
    对所述第一半导体图案进行第一掺杂工艺处理形成所述第二掺杂区域；
    对包含有所述第二掺杂区域的第一半导体图案进行第二次掺杂工艺处理形成所述第一掺杂区域。
  4. 根据权利要求3所述的制造方法，其中对所述第一半导体图案进行第一掺杂工艺处理形成所述第二掺杂区域包括：
    形成第二半导体薄膜，所述第二半导体薄膜覆盖所述第一半导体图案；
    在所述第二半导体薄膜上形成光刻胶层；
    对所述光刻胶层进行曝光、显影，以形成第一光刻胶图案和第二光刻胶图案，所述第一光刻胶图案对应于所述第一有源层所在的位置， 所述第二光刻胶图案对应于所述中心区域和所述第一掺杂区域所在的位置；
    对所述第二半导体薄膜进行刻蚀，以形成第一有源层和第二半导体图案，并露出部分所述第一半导体图案，所述第二半导体图案对应于所述中心区域和所述第一掺杂区域所在的位置；
    对露出的部分所述第一半导体图案进行掺杂，以形成所述第二掺杂区域。
  5. 根据权利要求4所述的制造方法，其中对包含有所述第二掺杂区域的第一半导体图案进行第二次掺杂工艺处理形成所述第一掺杂区域包括：
    对所述第二光刻胶图案进行灰化处理，以形成第三光刻胶图案，所述第三光刻胶图案对应于所述中心区域所在的位置；
    对所述第一半导体图案进行第二次掺杂，以形成所述第一掺杂区域。
  6. 根据权利要求5所述的制造方法，还包括：
    在形成所述第一掺杂区域之后，去除所述第三光刻胶图案。
  7. 根据权利要求2所述的制造方法，其中，通过一次构图工艺形成所述第一有源层和所述第二有源层的掺杂区域包括：
    形成第二半导体薄膜，所述第二半导体薄膜覆盖所述第一半导体图案；
    在所述第二半导体薄膜上形成光刻胶层；
    对所述光刻胶层进行曝光、显影，以形成第一光刻胶图案和第二光刻胶图案，所述第一光刻胶图案对应于所述第一有源层所在的位置，所述第二光刻胶图案对应于所述中心区域所在的位置；
    对所述第二半导体薄膜进行刻蚀，以形成第一有源层和第二半导体图案，并露出部分所述第一半导体图案，所述第二半导体图案对应于所述中心区域所在的位置；
    对露出的部分所述第一半导体图案进行掺杂，以形成所述掺杂区域；以及
    去除所述第一光刻胶图案和所述第二光刻胶图案。
  8. 根据权利要求3所述的制造方法，还包括：
    在通过一次构图工艺形成所述第一有源层和所述掺杂区域之后， 在所述第一有源层上方形成第一源漏图形，在所述第二掺杂区域上方形成第二源漏图形；
    在所述第一源漏图形和所述第二源漏图形上沉积第一绝缘层和树脂层；以及
    对所述第一绝缘层和所述树脂层进行一次构图工艺，以在所述第一绝缘层和所述树脂层中与所述第一源漏图形对应的位置形成第一通孔，并且在所述第一绝缘层和所述树脂层中与所述第二半导体图案对应的位置形成第二通孔以露出所述第二半导体图案。
  9. 根据权利要求8所述的制造方法，还包括：在形成所述第一通孔和所述第二通孔之后，通过一次构图工艺形成公共电极并去除所述第二半导体图案。
  10. 根据权利要求6所述的制造方法，其中，通过一次构图工艺形成公共电极并去除所述第二半导体图案包括：
    在所述树脂层上沉积公共电极材料，并对所述公共电极材料以及所述中心区域和所述第一掺杂区域上的第二半导体图案进行构图工艺，以形成所述公共电极并去除所述第二半导体图案。
  11. 根据权利要求7所述的制造方法，还包括：
    在通过一次构图工艺形成所述第一有源层和所述第二有源层的掺杂区域之后，在所述第一有源层上形成第一源漏图形，并且在所述掺杂区域上形成第二源漏图形；
    在所述第一源漏图形和所述第二源漏图形上沉积第一绝缘层和树脂层；以及
    对所述第一绝缘层和所述树脂层进行一次构图工艺，以在所述第一绝缘层和所述树脂层中与所述第一源漏图形对应的位置形成第一通孔，并且在所述第一绝缘层和所述树脂层中与所述第二半导体图案对应的位置形成第二通孔以露出所述第二半导体图案。
  12. 根据权利要求11所述的制造方法，还包括：在形成所述第一通孔和所述第二通孔之后，通过一次构图工艺形成公共电极并去除所述第二半导体图案。
  13. 根据权利要求12所述的制造方法，其中，通过一次构图工艺形成公共电极并去除所述第二半导体图案包括：
    在所述树脂层上沉积公共电极材料，并对所述公共电极材料以及 所述中心区域上的第二半导体图案进行构图工艺，以形成所述公共电极并去除所述第二半导体图案。
  14. 根据权利要求2所述的制造方法，还包括：
    在形成第一半导体图案之前，在所述衬底上通过一次构图工艺形成所述第一薄膜晶体管的第一栅极和所述第二薄膜晶体管的第二栅极；以及
    在所述第一栅极和所述第二栅极上形成栅绝缘层，所述第一半导体图案形成在所述栅绝缘层上。
  15. 根据权利要求1所述的方法，其中所述第一有源层的材料包括金属氧化物，所述第二有源层的材料包括多晶硅。
  16. 一种显示基板，包括：
    衬底；以及
    位于所述衬底上的第一薄膜晶体管和第二薄膜晶体管，所述第一薄膜晶体管包括第一有源层，所述第二薄膜晶体管包括第二有源层，
    其中，所述第二有源层包括中心区域和分别位于所述中心区域两侧的掺杂区域。
  17. 根据权利要求16所述的显示基板，其中，所述第一有源层和所述掺杂区域是通过一次构图工艺形成的。
  18. 根据权利要求17所述的显示基板，其中，所述第一有源层为金属氧化物有源层，所述第二有源层为多晶硅有源层。
  19. 根据权利要求16所述的显示基板，其中，所述掺杂区域包括第一掺杂区域和第二掺杂区域，所述第一掺杂区域位于所述第二掺杂区域和所述中心区域之间。
  20. 根据权利要求16所述的显示基板，其中所述第二薄膜晶体管还包括第二源漏图形，所述第二源漏图形覆盖所述第二掺杂区域。
  21. 根据权利要求16所述的显示基板，其中，所述第二薄膜晶体管还包括第二源漏图形，所述第二源漏图形覆盖所述掺杂区域。
  22. 根据权利要求16所述的显示基板，其中，所述显示基板包括显示区域和位于所述显示区域周围的周边区域，所述第一薄膜晶体管位于所述显示区域内，所述第二薄膜晶体管位于所述周边区域内。
  23. 一种显示装置，包括如权利要求16至22中任意一项所述的显示基板。
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