WO2013149477A1 - 薄膜晶体管、制备该薄膜晶体管的掩模板、阵列基板及显示装置 - Google Patents

薄膜晶体管、制备该薄膜晶体管的掩模板、阵列基板及显示装置 Download PDF

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Publication number
WO2013149477A1
WO2013149477A1 PCT/CN2012/086066 CN2012086066W WO2013149477A1 WO 2013149477 A1 WO2013149477 A1 WO 2013149477A1 CN 2012086066 W CN2012086066 W CN 2012086066W WO 2013149477 A1 WO2013149477 A1 WO 2013149477A1
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Prior art keywords
thin film
film transistor
channel
mask
bent portion
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PCT/CN2012/086066
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English (en)
French (fr)
Inventor
崔承镇
刘圣烈
宋泳锡
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2015503729A priority Critical patent/JP2015514321A/ja
Priority to US13/883,858 priority patent/US8952384B2/en
Priority to KR1020137012242A priority patent/KR101530460B1/ko
Priority to EP12842681.4A priority patent/EP2677543B1/en
Publication of WO2013149477A1 publication Critical patent/WO2013149477A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/22—Masks or mask blanks for imaging by radiation of 100nm or shorter wavelength, e.g. X-ray masks, extreme ultraviolet [EUV] masks; Preparation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure

Definitions

  • Embodiments of the present invention relate to a Thin Film Transistor (TFT), a mask, an array substrate, and a display device for preparing the thin film transistor.
  • TFT Thin Film Transistor
  • Fig. 1 is a schematic view showing the structure of a TFT channel fabricated by using SSM in the conventional art. As shown in Fig. 1, the TFT channel is located between the source 1 and the drain 2 and has a U-shaped structure including a bent portion ⁇ and an extension portion ⁇ on both sides of the bent portion ⁇ .
  • the width of the channel in the bend ⁇ and the extension ⁇ is L.
  • the transmittance of the bent portion ⁇ is reduced as compared with the extension portion , so that the channel bending portion B is likely to have a decrease in transmittance during exposure.
  • the photoresist cannot be completely removed, so that the source and drain of the bent portion B after the patterning process are short-circuited.
  • a thin film transistor is provided.
  • the channel of the thin film transistor is formed by a single-gap gray scale mask, the channel of the thin film transistor has a bent portion and an extension portion on both sides of the bent portion, and the channel width of the bent portion is larger than the groove of the extended portion Road width.
  • a mask for preparing a thin film transistor has a single slit corresponding to the channel of the thin film transistor, the single slit having a bent portion and an extension portion on both sides of the bent portion, and the slit width of the bent portion is larger than the slit width of the extended portion.
  • an array substrate is provided.
  • the array substrate includes the thin film transistor as described above.
  • a display device includes the thin film transistor as described above.
  • FIGS. 2-4 are schematic structural views of a mask for fabricating a TFT according to an embodiment of the present invention. detailed description
  • This embodiment provides a mask for preparing a thin film transistor.
  • the mask has a single slit corresponding to the channel of the thin film transistor, and the single slit has a bent portion B and an extending portion A on both sides of the bent portion B, and a slit width of the bent portion B It is larger than the slit width of the extension A.
  • the slit is formed in a U shape.
  • the width of the above slit is formed at ⁇ ! ⁇ 5 ⁇ between.
  • the mask further has a first region 1 corresponding to the source of the TFT and a second region 2 corresponding to the drain of the TFT.
  • a slit corresponding to the channel of the thin film transistor is located between the first region 1 and the second region 2.
  • the first area 1 and the second area 2 are opaque areas.
  • the first region 1 is formed to be recessed in the opposite direction toward the second region 2.
  • the recessed portion has a rectangular shape.
  • the shape of the recessed portion is semicircular.
  • the shape of the recessed portion may also be a semi-elliptical shape.
  • the shape of the concave portion is not limited to a rectangular shape, a semicircular shape, or a semi-elliptical shape.
  • the slit width of the bent portion B is formed between 2.5 ⁇ m and 5 ⁇ m. This size is larger than the size currently used, whereby the light transmittance of the bent portion can be improved when the thin film transistor is fabricated, and the problem of channel defects easily occurring in the bent portion can be avoided. More preferably, the bent portion The slit width is 4 ⁇ m or less because the characteristics of the thin film transistor are better when the channel width is 4 ⁇ m or less.
  • the slit width of the extension portion is formed between 1 ⁇ and 4 ⁇ .
  • the gap width of this part can be selected according to the needs of the product performance.
  • the channel of the obtained thin film transistor can be minimized while preventing the occurrence of channel defects. Therefore, it is possible to improve the yield of the product while improving the performance of the TFT.
  • This embodiment provides a mask for preparing a thin film transistor.
  • the mask has a single slit corresponding to the channel of the thin film transistor, and the single slit has a bent portion ⁇ and an extension portion ⁇ on both sides of the bent portion, and a slit width of the bent portion ⁇ Greater than the gap width of the extension ⁇ .
  • the slit is formed in a U shape.
  • the width of the above slit is formed at ⁇ ! ⁇ 5 ⁇ between.
  • the mask further has a first region 1 corresponding to the source of the TFT and a second region 2 corresponding to the drain of the TFT.
  • a slit corresponding to the channel of the thin film transistor is located between the first region 1 and the second region 2.
  • the first area 1 and the second area 2 are opaque areas.
  • the second region 2 is formed to be recessed in the opposite direction toward the first region 1 at the bent portion B of the slit.
  • the shape of the depressed portion may be formed into a rectangular shape, a semicircular shape, a semi-elliptical shape or the like. As shown in Fig. 4, the slit width of the bent portion B is larger than the slit width of the extending portion A, so that the light transmittance of the bent portion B can be improved.
  • the slit width of the bent portion B is formed between 2.5 ⁇ m and 5 ⁇ m. This size is larger than the size currently used, whereby the light transmittance of the bent portion can be improved when the thin film transistor is fabricated, and the problem of channel defects easily occurring in the bent portion can be avoided. More preferably, the slit width of the bent portion ⁇ is 4 ⁇ m or less because the characteristics of the thin film transistor are better when the channel width is 4 ⁇ m or less.
  • the slit width of the extension portion is formed between 1 ⁇ and 4 ⁇ .
  • the gap width of this part can be selected according to the needs of the product performance.
  • the channel of the obtained thin film transistor can be minimized while preventing the occurrence of channel defects. Therefore, it is possible to improve the yield of the product while improving the performance of the TFT.
  • the embodiment provides a thin film transistor, wherein a channel of the thin film transistor is masked by a single slit gray scale The template is obtained, and the width of the channel of the thin film transistor is between 2 ⁇ m and 6 ⁇ m.
  • the channel of the thin film transistor according to the present embodiment has a bent portion ⁇ and an extending portion ⁇ located on both sides of the bent portion ⁇ , and the channel width of the bent portion ⁇ is larger than the channel width of the extended portion ⁇ .
  • the channel of the thin film transistor of the present embodiment is formed in a U shape.
  • the thin film transistor according to the present embodiment further has a source portion and a drain portion, and the channel is located between the source portion and the drain portion.
  • the source portion is formed to be recessed in the opposite direction to the drain direction, so that the channel width of the bent portion B can be made large.
  • the shape of the depressed portion may be a rectangle, a semicircle, a semi-ellipse or the like, but is not limited thereto.
  • a channel having a recessed portion which is rectangular may be formed by the mask shown in Fig. 2, and a channel having a recessed portion having a semicircular shape may be formed by the mask shown in Fig. 3.
  • the channel width of the bent portion B is formed between 3 ⁇ and 6 ⁇ .
  • the channel width of the extension portion is formed between 2 ⁇ m and 2.5 ⁇ m.
  • the channel width of this part can be selected according to the needs of the product performance.
  • the occurrence of channel defects can be prevented while the channel is the shortest. Therefore, it is possible to improve the yield of the product while improving the performance of the TFT.
  • the present embodiment provides a thin film transistor whose channel is formed by a single slit gray scale mask having a channel width of between 2 ⁇ m and 6 ⁇ m.
  • the channel of the thin film transistor according to the present embodiment has a bent portion ⁇ and an extending portion ⁇ located on both sides of the bent portion ⁇ , and the channel width of the bent portion ⁇ is larger than the channel width of the extended portion ⁇ .
  • the channel of the thin film transistor of the present embodiment is formed in a U shape.
  • the thin film transistor according to the present embodiment further has a source portion and a drain portion, and the channel is located between the source portion and the drain portion.
  • the drain portion is formed to be recessed in the opposite direction to the source direction, so that the channel width of the bent portion B can be made large.
  • the shape of the depressed portion may be a rectangle, a semicircle, a semi-ellipse or the like, but is not limited thereto.
  • the groove having a semi-elliptical portion may be formed by the mask shown in Fig. 4.
  • the channel width of the bent portion B is formed between 3 ⁇ and 6 ⁇ .
  • the channel width of the extension portion is formed between 2 ⁇ m and 2.5 ⁇ m.
  • the channel width of this part can be selected according to the needs of the product performance.
  • the channel can be prevented while reaching the shortest channel Bad appearance. Therefore, it is possible to improve the yield of the product while improving the performance of the TFT.
  • the present embodiment provides a method for preparing a thin film transistor of Embodiment 3 by using the mask of Embodiment 1, the method comprising the following steps:
  • Step S1 forming a conductive gate metal layer on the substrate, forming a gate on the substrate by a first patterning process; then forming a gate insulating layer over the gate; forming a semiconductor layer and a source drain on the gate insulating layer Extreme metal layer.
  • Step S2 performing a second patterning process by using the single-gap gray mask provided in Embodiment 1 above, patterning the source/drain metal layer and the semiconductor layer to form an active layer, a source, and a drain. Pole and channel.
  • the gap size of the mask may not completely match the channel size of the finally formed thin film transistor due to the process margin of the exposure, development, and etching processes, which is reasonable. Process error.
  • the width of the slit of the mask is between 1 ⁇ m and 5 ⁇ m, and the width of the channel of the thin film transistor is 2 ⁇ ! ⁇ 6 ⁇ between.
  • each of the layered structures may be formed by a process such as spin coating, deposition, sputtering, or the like, and a patterning process may be performed by conventional photolithography, printing, or the like.
  • the present embodiment provides a method for preparing a thin film transistor of Embodiment 4 by using the mask of Embodiment 2, the method comprising the following steps:
  • Step S1 forming a conductive gate metal layer on the substrate, forming a gate on the substrate by a first patterning process; then forming a gate insulating layer over the gate; forming a semiconductor layer and a source drain on the gate insulating layer Extreme metal layer.
  • Step S2 performing the second composition by using the single slit gray mask provided in Embodiment 2 above.
  • the gap size of the mask may not completely match the channel size of the finally formed thin film transistor due to the process margin of the exposure, development, and etching processes, which is reasonable. Process error.
  • the width of the slit of the mask is between 1 ⁇ m and 5 ⁇ m, and the width of the channel of the thin film transistor is 2 ⁇ ! ⁇ 6 ⁇ between.
  • each of the layered structures may be formed by a process such as spin coating, deposition, sputtering, or the like, and a patterning process may be performed by conventional photolithography, printing, or the like.
  • the present invention also provides an array substrate comprising any of the thin film transistors of the above embodiments.
  • the present invention also provides a display device comprising any of the thin film transistors of the above embodiments.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

提供一种薄膜晶体管、制备该薄膜晶体管的掩模板、阵列基板以及显示装置。该薄膜晶体管的沟道通过单缝隙灰度掩模板制得，该薄膜晶体管的沟道具有弯折部（B）和位于弯折部（B）两侧的延伸部（A），并且弯折部（B）的沟道宽度大于延伸部（A）的沟道宽度。

Description

薄膜晶体管、 制备该薄膜晶体管的掩模板、 阵列基板及显示装置 技术领域
本发明的实施例涉及薄膜晶体管（ Thin Film Transistor, 简称 TFT ) , 制 备该薄膜晶体管的掩模板、 阵列基板及显示装置。 背景技术
在平板显示领域， 薄膜晶体管是制作显示器件的关键器件。 需要不断地 改善薄膜晶体管的特性来实现更好的显示品质。减小 TFT的沟道宽度以实现 更好的器件特性是研究的趋势之一。 目前， 常使用 SSM ( Single Slit Mask, 单缝隙掩模板）来制造宽度为 4μπι以下的 TFT沟道。 图 1为传统技术中利 用 SSM所制造的 TFT沟道的结构示意图。 如图 1所示， TFT沟道位于源极 1和漏极 2之间并具有 U型结构，该 U型结构包括弯折部 Β和位于弯折部 Β 两侧的延伸部 Α。 弯折部 Β和延伸部 Α中的沟道宽度均为 L。 当形成宽度 L 为 3~3.5μπι的沟道时， 弯折部 Β的透过率相较于延伸部 Α会有所降低， 这 样沟道弯折部 B在曝光时容易发生透过率下降,导致光刻胶不能被完全去除， 使得构图工艺后弯折部 B的源漏极产生短路不良。 发明内容
根据本发明的一个实施例， 提供一种薄膜晶体管。 该薄膜晶体管的沟道 通过单缝隙灰度掩模板制得， 该薄膜晶体管的沟道具有弯折部和位于弯折部 两侧的延伸部， 并且弯折部的沟道宽度大于延伸部的沟道宽度。
根据本发明的另一个实施例， 提供一种制备薄膜晶体管的掩模板。 该掩 模板具有与薄膜晶体管的沟道相对应的单缝隙， 该单缝隙具有弯折部和位于 弯折部两侧的延伸部， 并且弯折部的缝隙宽度大于延伸部的缝隙宽度。
根据本发明的另一个实施例， 提供一种阵列基板。 该阵列基板包括如上 所述的薄膜晶体管。
根据本发明的再一个实施例， 提供一种显示装置。 该显示装置包括如上 所述的薄膜晶体管。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为传统技术中利用 SSM所制造的 TFT沟道的结构示意图； 图 2-4为根据本发明实施例的制备 TFT的掩模板的结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
实施例 1
本实施例提供一种用于制备薄膜晶体管的掩模板。 如图 2所示， 该掩模 板具有与薄膜晶体管的沟道相对应的单缝隙， 该单缝隙具有弯折部 B和位于 弯折部 B两侧的延伸部 A, 弯折部 B的缝隙宽度大于延伸部 A的缝隙宽度。
例如， 如图 2所示， 上述缝隙形成为 U形。
例如， 上述缝隙的宽度形成为在 Ιμπ！〜 5μπι之间。
该掩模板还具有与 TFT的源极相对应的第一区域 1和与 TFT的漏极相 对应的第二区域 2。 与薄膜晶体管的沟道相对应的缝隙位于该第一区域 1和 第二区域 2之间。 第一区域 1和第二区域 2为不透光区域。 为了使弯折部 Β 的缝隙宽度大于延伸部 Α的缝隙宽度， 在缝隙的弯折部 B处， 第一区域 1 形成为沿着朝第二区域 2方向的相反方向凹陷进去。 如图 2所示， 凹陷部分 的形状为矩形。 如图 3所示， 凹陷部分的形状为半圓形。 此外， 凹陷部分的 形状还可以是半椭圓形。 然而， 凹陷部分的形状并不局限于矩形、 半圓形、 半椭圓形。
优选地， 弯折部 B的缝隙宽度形成在 2.5μπι~5μπι之间。 该尺寸比目前 通常釆用的尺寸大，由此在制作薄膜晶体管时，可以提高弯折部 Β的透光率， 从而可以避免弯折部 Β处容易出现沟道不良的问题。 更优选地， 弯折部 Β的 缝隙宽度在 4μπι以下， 这是因为当薄膜晶体管的沟道宽度在 4μπι以下时特 性会更好。
优选地， 延伸部 Α的缝隙宽度形成在 1 μπι~4μπι之间。 该部分的缝隙宽 度可以根据产品性能的需要来选择。
利用上述掩模板， 在制得的薄膜晶体管的沟道达到最短的同时能够防止 沟道不良的出现。 因此， 能够在提高 TFT的性能的同时提高产品的良率。
实施例 2
本实施例提供一种用于制备薄膜晶体管的掩模板。 如图 4所示， 该掩模 板具有与薄膜晶体管的沟道相对应的单缝隙， 该单缝隙具有弯折部 Β和位于 弯折部 Β两侧的延伸部 Α, 弯折部 Β的缝隙宽度大于延伸部 Α的缝隙宽度。
例如， 如图 2所示， 上述缝隙形成为 U形。
例如， 上述缝隙的宽度形成为在 Ιμπ！〜 5μπι之间。
该掩模板还具有与 TFT的源极相对应的第一区域 1和与 TFT的漏极相 对应的第二区域 2。 与薄膜晶体管的沟道相对应的缝隙位于该第一区域 1和 第二区域 2之间。 第一区域 1和第二区域 2为不透光区域。 为了使弯折部 Β 的缝隙宽度大于延伸部 Α的缝隙宽度， 在缝隙的弯折部 B, 第二区域 2形成 为沿着朝第一区域 1方向的相反方向凹陷进去。 凹陷部分的形状可以形成为 矩形、 半圓形、 半椭圓形等。 如图 4所示， 弯折部 B的缝隙宽度比延伸部 A 的缝隙宽度要大， 这样可以提高弯折部 B的光透过率。
优选地， 弯折部 B的缝隙宽度形成在 2.5μπι~5μπι之间。 该尺寸比目前 通常釆用的尺寸大，由此在制作薄膜晶体管时，可以提高弯折部 Β的透光率， 从而可以避免弯折部 Β处容易出现沟道不良的问题。 更优选地， 弯折部 Β的 缝隙宽度在 4μπι以下， 这是因为当薄膜晶体管的沟道宽度在 4μπι以下时特 性会更好。
优选地， 延伸部 Α的缝隙宽度形成在 1 μπι~4μπι之间。 该部分的缝隙宽 度可以根据产品性能的需要来选择。
利用上述掩模板， 在制得的薄膜晶体管的沟道达到最短的同时能够防止 沟道不良的出现。 因此， 能够在提高 TFT的性能的同时提高产品的良率。
实施例 3
本实施例提供一种薄膜晶体管， 该薄膜晶体管的沟道通过单缝隙灰度掩 模板制得， 该薄膜晶体管的沟道的宽度在 2μπι~6μπι之间。
根据本实施例的薄膜晶体管的沟道具有弯折部 Β和位于弯折部 Β两侧的 延伸部 Α, 弯折部 Β的沟道宽度大于延伸部 Α的沟道宽度。
例如， 本实施例的薄膜晶体管的沟道形成为 U形。
根据本实施例的薄膜晶体管还具有源极部分和漏极部分， 沟道位于源极 部分和漏极部分之间。 在沟道的弯折部 B, 源极部分形成为沿着朝漏极方向 的相反方向凹陷进去， 从而弯折部 B的沟道宽度可以变大。 凹陷部分的形状 可以为矩形、 半圓形、 半椭圓形等， 但不限于此。 凹陷部分为矩形的沟道可 以通过图 2所示的掩模板制得， 凹陷部分为半圓形的沟道可以通过图 3所示 的掩模板制得。
优选地， 弯折部 B的沟道宽度形成在 3 μπι~6μπι之间。
优选地， 延伸部 Α的沟道宽度形成在 2μπι~2.5μπι之间。 该部分的沟道 宽度可以根据产品性能的需要来选择。
在根据本实施例的薄膜晶体管中， 在达到沟道最短的同时能够防止沟道 不良的出现。 因此， 能够在提高 TFT的性能的同时提高产品的良率。
实施例 4
本实施例提供一种薄膜晶体管， 该薄膜晶体管的沟道通过单缝隙灰度掩 模板制得， 该薄膜晶体管的沟道的宽度在 2μπι~6μπι之间。
根据本实施例的薄膜晶体管的沟道具有弯折部 Β和位于弯折部 Β两侧的 延伸部 Α, 弯折部 Β的沟道宽度大于延伸部 Α的沟道宽度。
例如， 本实施例的薄膜晶体管的沟道形成为 U形。
根据本实施例的薄膜晶体管还具有源极部分和漏极部分， 沟道位于源极 部分和漏极部分之间。 在沟道的弯折部 B, 漏极部分形成为沿着朝源极方向 的相反方向凹陷进去， 从而弯折部 B的沟道宽度可以变大。 凹陷部分的形状 可以为矩形、 半圓形、 半椭圓形等， 但不限于此。 凹陷部分为半椭圓形的沟 道可以通过图 4所示的掩模板制得。
优选地， 弯折部 B的沟道宽度形成在 3 μπι~6μπι之间。
优选地， 延伸部 Α的沟道宽度形成在 2μπι~2.5μπι之间。 该部分的沟道 宽度可以根据产品性能的需要来选择。
在根据本实施例的薄膜晶体管中， 在达到沟道最短的同时能够防止沟道 不良的出现。 因此， 能够在提高 TFT的性能的同时提高产品的良率。
实施例 5
本实施例提供一种利用实施例 1的掩模板来制备实施例 3的薄膜晶体管 的制备方法， 该方法包括如下步骤：
步骤 S1 : 在基板上形成导电的栅极金属层， 通过第一次构图工艺在基板 上形成栅极； 然后在栅极上方形成栅绝缘层； 接下来在栅绝缘层上形成半导 体层和源漏极金属层。
步骤 S2:利用上述实施例 1所提供的单缝隙灰度掩模板进行第二次构图 工艺，对所述源漏极金属层和所述半导体层进行图案化以形成有源层、源极、 漏极和沟道。
在源漏极金属层上涂覆一层光刻胶， 利用实施例 1所提供的单缝隙灰度 掩模板进行曝光， 形成对应源极和漏极的光刻胶完全保留区域， 对应薄膜晶 体管沟道区域的光刻胶部分保留区域， 以及对应其他区域的光刻胶完全除去 区域。刻蚀掉光刻胶完全除去区域的源漏极金属层和半导体层，形成有源层。 通过灰化工艺去除薄膜晶体管沟道区域的光刻胶。 刻蚀掉薄膜晶体管沟道区 域的源漏极金属层， 以形成源极、 漏极和薄膜晶体管沟道。 去除剩余的光刻 胶， 得到薄膜晶体管。
在该步骤中， 由于受曝光、 显影及刻蚀工艺的工艺裕度 ( margin ) 的影 响， 所述掩模板的缝隙尺寸与最终形成的薄膜晶体管的沟道尺寸可能不会完 全一致，这属于合理的工艺误差。例如，所述掩模板的缝隙的宽度在 1 μπι~5μπι 之间， 所述薄膜晶体管的沟道的宽度在 2μπ！〜 6μπι之间。
在本实施例中， 各层状结构可以通过旋涂、 沉积、 溅镀等工艺形成， 且 可以釆用常规的光刻、 印刷等进行构图工艺。
实施例 6
本实施例提供一种利用实施例 2的掩模板来制备实施例 4的薄膜晶体管 的制备方法， 该方法包括如下步骤：
步骤 S1 : 在基板上形成导电的栅极金属层， 通过第一次构图工艺在基板 上形成栅极； 然后在栅极上方形成栅绝缘层； 接下来在栅绝缘层上形成半导 体层和源漏极金属层。
步骤 S2:利用上述实施例 2所提供的单缝隙灰度掩模板进行第二次构图 工艺，对所述源漏极金属层和所述半导体层进行图案化以形成有源层、源极、 漏极和沟道。
在源漏极金属层上涂覆一层光刻胶， 利用实施例 2所提供的单缝隙灰度 掩模板进行曝光， 形成对应源极和漏极的光刻胶完全保留区域， 对应薄膜晶 体管沟道的光刻胶部分保留区域，以及对应其他区域的光刻胶完全除去区域。 刻蚀掉光刻胶完全除去区域的源漏极金属层和半导体有源层， 形成有源层。 通过灰化工艺去除薄膜晶体管沟道区域的光刻胶。 刻蚀掉薄膜晶体管沟道区 域的源漏极金属层， 以形成源极、 漏极和薄膜晶体管沟道。 去除剩余的光刻 胶， 得到薄膜晶体管。
在该步骤中， 由于受曝光、 显影及刻蚀工艺的工艺裕度（margin ) 的影 响， 所述掩模板的缝隙尺寸与最终形成的薄膜晶体管的沟道尺寸可能不会完 全一致，这属于合理的工艺误差。例如，所述掩模板的缝隙的宽度在 1 μπι~5μπι 之间， 所述薄膜晶体管的沟道的宽度在 2μπ！〜 6μπι之间。
在本实施例中， 各层状结构可以通过旋涂、 沉积、 溅镀等工艺形成， 且 可以釆用常规的光刻、 印刷等进行构图工艺。
同时， 本发明还提供一种阵列基板， 该阵列基板包括上述实施例中的任 一种薄膜晶体管。
此外， 本发明还提供一种显示装置， 所述显示装置包括上述实施例中的 任一种薄膜晶体管。 所述显示装置可以为液晶面板、 电子纸、 OLED面板、 液晶电视、 液晶显示器、 数码相框、 手机、 平板电脑等任何具有显示功能的 产品或部件。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种薄膜晶体管，所述薄膜晶体管的沟道通过单缝隙灰度掩模板制得， 其中所述薄膜晶体管的沟道具有弯折部和位于弯折部两侧的延伸部， 并且所 述弯折部的沟道宽度大于所述延伸部的沟道宽度。
2、根据权利要求 1所述的薄膜晶体管，其中所述薄膜晶体管还具有源极 和漏极， 所述沟道位于所述源极和所述漏极之间， 并且在所述弯折部处所述 源极形成为沿着朝漏极方向的相反方向凹陷进去。
3、根据权利要求 1所述的薄膜晶体管，其中所述薄膜晶体管还具有源极 和漏极， 所述沟道位于所述源极和所述漏极之间， 并且在所述弯折部处所述 漏极形成为沿着朝源极方向的相反方向凹陷进去。
4、根据权利要求 2或 3所述的薄膜晶体管， 所述凹陷部分为矩形、半圓 形或半椭圓形。
5、根据权利要求 1所述的薄膜晶体管，其中所述沟道的宽度在 2μπι ~6μπι 之间
6、 根据权利要求 1 所述的薄膜晶体管， 其中所述弯折部的沟道宽度在 3μπι~6μπι之间。
7、 根据权利要求 1 所述的薄膜晶体管， 其中所述延伸部的沟道宽度在 2μπι~3.5μπι之间。
8、一种制备薄膜晶体管的掩模板，所述掩模板具有与薄膜晶体管的沟道 相对应的单缝隙， 所述单缝隙具有弯折部和位于弯折部两侧的延伸部， 并且 所述弯折部的缝隙宽度大于延伸部的缝隙宽度。
9、根据权利要求 8所述的用于制备薄膜晶体管的掩模板，其中所述掩模 板还具有与薄膜晶体管的源极相对应的第一区域和与薄膜晶体管的漏极相对 应的第二区域， 与薄膜晶体管的沟道相对应的所述缝隙位于所述第一区域和 第二区域之间， 并且在所述弯折部处所述第一区域形成为沿着朝第二区域方 向的相反方向凹陷进去。
10、 根据权利要求 8所述的用于制备薄膜晶体管的掩模板， 其中所述掩 模板还具有与薄膜晶体管的源极相对应的第一区域和与薄膜晶体管的漏极相 对应的第二区域， 与薄膜晶体管的沟道相对应的所述缝隙位于所述第一区域 和第二区域之间， 并且在所述弯折部处所述第二区域形成为沿着朝第一区域 方向的相反方向凹陷进去。
11、根据权利要求 9或 10所述的用于制备薄膜晶体管的掩模板，其中所 述凹陷部分为矩形、 半圓形或半椭圓形。
12、根据权利要求 9或 10所述的用于制备薄膜晶体管的掩模板，其中所 述第一区域和所述第二区域为不透光区域。
13、 根据权利要求 8所述的用于制备薄膜晶体管的掩模板， 其中所述缝 隙的宽度在 1 μπ！〜 5 μπι之间。
14、 根据权利要求 8所述的用于制备薄膜晶体管的掩模板， 其中所述弯 折部的缝隙宽度在 2.5μπ！〜 5μπι之间。
15、 根据权利要求 8所述的用于制备薄膜晶体管的掩模板， 其中所述延 伸部的缝隙宽度在 Ιμπ！〜 4μπι之间。
16、 一种阵列基板， 该阵列基板包括如权利要求 1所述薄膜晶体管。
17、 一种显示装置， 该显示装置包括如权利要求 1所述的薄膜晶体管。
PCT/CN2012/086066 2012-04-06 2012-12-06 薄膜晶体管、制备该薄膜晶体管的掩模板、阵列基板及显示装置 WO2013149477A1 (zh)

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US8952384B2 (en) 2015-02-10
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