WO2015096392A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2015096392A1
WO2015096392A1 PCT/CN2014/078848 CN2014078848W WO2015096392A1 WO 2015096392 A1 WO2015096392 A1 WO 2015096392A1 CN 2014078848 W CN2014078848 W CN 2014078848W WO 2015096392 A1 WO2015096392 A1 WO 2015096392A1
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Prior art keywords
tft
insulating layer
electrode
gate
array substrate
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PCT/CN2014/078848
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English (en)
French (fr)
Inventor
金熙哲
宋泳锡
刘圣烈
崔承镇
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP14856805.8A priority Critical patent/EP3089213B1/en
Priority to US14/429,501 priority patent/US10403651B2/en
Publication of WO2015096392A1 publication Critical patent/WO2015096392A1/zh

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Definitions

  • the present disclosure relates to an array substrate, a method of manufacturing the same, and a display device. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • oxide TFT backplane technology is a backplane technology similar to the conventional a-Si TFT process, which replaces the silicon semiconductor material originally applied to the a-Si TFT with an oxide semiconductor material, which is the most widely used.
  • An IGZO (Indmm Gallium Zinc Oxide, Indium Gallium Zinc Oxide) material is used to form a semiconductor active layer of the TFT.
  • An array structure of a typical oxide TFT array structure is known as shown in Fig. 1, and includes a gate electrode 11 of a TFT which is sequentially formed on the surface of the transparent substrate 10, a gate insulating layer 12, and a semiconductor active layer 13 formed of IGZO.
  • a gate electrode 11 of a TFT which is sequentially formed on the surface of the transparent substrate 10, a gate insulating layer 12, and a semiconductor active layer 13 formed of IGZO.
  • an etching stopper layer 14 having via holes A, B is formed by a patterning process, and via holes A, B are respectively penetrated through the etching stopper layer 14 to expose the semiconductor active layer 13.
  • the source 151 and the drain 152 of the TFT are electrically connected to the semiconductor active layer 13 through the via holes A, B, respectively. Summary of the invention
  • the present disclosure provides an array substrate, a method of manufacturing the same, and a display device.
  • an array substrate comprising: a gate electrode of a TFT sequentially formed on a surface of a base substrate; and a gate insulating layer; wherein the gate insulating layer is sequentially on a surface corresponding to a gate of the TFT A semiconductor active layer, an etch stop layer, and a source and a drain of the TFT are formed, and a source and a drain of the TFT are respectively in contact with the semiconductor active layer through via holes.
  • the array substrate further includes: a first insulating layer formed between a gate of the TFT and the gate insulating layer, the first insulating layer corresponding to a source of the TFT and a drain of the TFT At least one; And the gate is in contact with the gate insulating layer at a channel region of the TFT corresponding to a source and a drain of the TFT.
  • a display device including the array substrate as described above is provided.
  • a method for fabricating an array substrate including: forming a gate of a TFT on a surface of a substrate;
  • first insulating layer Forming a first insulating layer on the substrate on which the gate is formed, the first insulating layer corresponding to at least one of a source of the TFT and a drain of the TFT;
  • a gate insulating layer is formed on a surface of the substrate on which the first insulating layer is formed, the gate being in contact with the gate insulating layer at a region corresponding to a channel of the TFT.
  • Figure 1 is a schematic view showing the structure of a known array
  • FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural view of a substrate after forming a second insulating layer according to an embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a substrate after forming a TFT gate according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a substrate after forming a first insulating layer according to an embodiment of the present invention
  • FIG. 6 is a schematic structural view of a substrate after forming a first insulating layer according to an embodiment of the present invention
  • FIG. 7 is a schematic structural view of a substrate after forming a gate insulating layer according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural view of a substrate after forming a semiconductor active layer according to an embodiment of the present invention
  • FIG. 9 is a schematic structural view of a substrate after forming an etch barrier layer according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural view of a substrate after forming a source and a drain of a TFT according to an embodiment of the present invention
  • FIG. 11 is a schematic structural view of a substrate after forming a first transparent electrode according to an embodiment of the present invention
  • FIG. 12 is a schematic diagram of forming a passivation layer according to an embodiment of the present invention
  • Rear schematic structure of the substrate Rear schematic structure of the substrate.
  • the source 151 and the drain of the TFT are shown.
  • a parasitic capacitance Cgs is generated between the source 151 and the gate 11, and a parasitic capacitance Cgd is generated between the drain 152 and the gate 11.
  • a change in the voltage signal on the gate line 11 from a high value to a low value when the TFT is turned off causes the drain 152 to output a trip voltage, thereby This causes a sudden drop in the liquid crystal voltage in the pixel, which will seriously affect the accuracy of the pixel electrode voltage, causing the display to flicker.
  • An array substrate provided by an embodiment of the present invention, as shown in FIG. 2, includes:
  • a gate electrode 21 of the TFT formed on the surface of the base substrate 20 and a gate insulating layer 22; a layer 23, an etch barrier layer 24, and a source 251 and a drain 252 of the TFT, a source 251 of the TFT and
  • the drain electrode 252 is in contact with the semiconductor active layer 23 through a via hole (shown by a broken line in FIG. 2), respectively.
  • a corresponds to B in the present disclosure means that A, B are opposed to each other or at least partially overlap in the vertical direction. Therefore, “the surface of the gate insulating layer 22 corresponding to the gate electrode 21 of the TFT” is understood to be the surface of the portion where the gate insulating layer 22 and the gate electrode 21 are opposed or overlap in the vertical direction.
  • the array substrate further includes:
  • a first insulating layer 26 is formed between the gate electrode 21 of the TFT and the gate insulating layer 22, the first insulating layer 26 corresponding to at least one of the source 251 of the TFT and the drain 252 of the TFT.
  • the gate electrode 21 and the gate insulating layer 22 are in contact at a channel region of the TFT between the source 215 and the drain 252 of the TFT. Since it is necessary to ensure a small distance between the gate material and the semiconductor active layer at the corresponding TFT channel region, it is not necessary to provide the insulating layer 26.
  • the distance between the source 251 or the drain 252 and the gate 21 of the TFT in the array substrate shown in FIG. 2 is much larger than The spacing between the source 151 or the drain 152 of the TFT in FIG. 1 and the gate 11 respectively.
  • corresponding A region of the source of the TFT and/or a region of the drain of the TFT form a first insulating layer having a certain thickness.
  • the structure significantly increases the spacing between the gate and the source/drain of the TFT, so that the capacitance between the two electrodes of the parallel plate capacitor is increased, so that the capacitance is significantly reduced, thereby effectively reducing the source and gate of the TFT.
  • the parasitic capacitance Cgs existing between the TFTs or the parasitic capacitance Cgd existing between the drain and the gate of the TFT is reduced, thereby preventing the output jump voltage from being excessive due to excessive parasitic capacitances Cgd and Cgs, thereby effectively improving display flicker and improving The quality of the display device.
  • the first insulating layer 26 corresponds to at least one of the source 251 of the TFT or the drain 252 of the TFT.
  • the description is made by taking the first insulating layer 26 simultaneously corresponding to the source 251 of the TFT and the drain 252 of the TFT.
  • the spacing between the gate 21 of the TFT and the source and drain electrodes 251, 252 is significantly increased, thereby effectively reducing the source 252 and the gate 21 of the TFT.
  • the parasitic capacitance Cgs present and the parasitic capacitance Cgd existing between the drain 252 and the gate 21 of the TFT are reduced.
  • the first insulating layer 26 corresponds only to the source 251 of the TFT; at this time, since the electrode spacing between the gate 21 and the source 251 of the TFT which is the two electrodes of the parallel plate capacitor is increased, thereby The parasitic capacitance Cgs between the source 251 and the gate 21 is effectively reduced.
  • the first insulating layer 26 only corresponds to the drain 252 of the TFT, and the parasitic capacitance Cgd between the drain 252 and the gate 21 is effectively reduced.
  • the source 251 of the TFT and the drain 252 of the TFT respectively correspond to the first insulating layer 26 of the TFT
  • the thicknesses of the portions are equal (i.e., the thicknesses of the left and right portions of the first insulating layer 26 in FIG. 2 are equal).
  • the thickness D of the first insulating layer 26 is 1 ⁇ -3 ⁇ m.
  • the design of such a thickness of the first insulating layer 26 is easily achieved by a known patterning process while reducing the capacitance between the electrodes, thereby effectively reducing the production difficulty of the product.
  • the capacitance is reduced by increasing the spacing between the two electrodes. Since the spacing between the two electrodes (one electrode is the source 251 or the drain 252 and the other electrode is the gate 21) in FIG. 2 is increased, the capacitance is reduced, so that the jump generated by the parasitic capacitance can be effectively reduced. The effect of the variable voltage on the display screen.
  • the array substrate of this embodiment further includes: Forming a second insulating layer 27 between the base substrate 20 and the gate 21 of the TFT, the second insulating layer 27 corresponding to the channel of the TFT (C region in FIG. 2); the second insulating layer 27 and the gate of the TFT
  • the sum D of the thicknesses of 21 is greater than or equal to the thickness D of the first insulating layer 26.
  • the first insulating layer 26 and the second insulating layer 27 are made of a material having good insulating properties such as an organic resin material, which is not limited in the present invention.
  • the gate 21 of the TFT located in the region is raised so that the upper surface of the gate 21 and the upper surface of the first insulating layer 26 are raised.
  • the thickness of the first insulating layer and the second insulating layer the sum D of the thicknesses of the two insulating layers 27 and the gate 21 of the TFT is greater than or equal to the thickness D of the first insulating layer 26, thereby ensuring at least the exposure.
  • the surface of the gate electrode 21 is used to ensure the formation of a channel of the TFT.
  • TFT-LCD array substrate provided by the above embodiments can be applied to FFS (Fringe Field Switching) type, AD-SDS (Advanced-Super Dmiensional Switching, referred to as ADS, advanced super-dimensional field switch).
  • FFS Flexible Field Switching
  • AD-SDS Advanced-Super Dmiensional Switching
  • ADS advanced super-dimensional field switch
  • Type IPS (In Plane Switch) type
  • TN Transist Nematic
  • the color filter substrate and the array substrate of the pair are included.
  • the common electrode is disposed on the color filter substrate, and the pixel electrode is disposed on the array substrate;
  • the common electrode and the pixel electrode are both disposed On the array substrate.
  • the array substrate according to the above embodiment further includes:
  • first transparent electrode 281 Forming a first transparent electrode 281 on the surface of the etch stop layer 24, the first transparent electrode 281 being in contact with the drain 252 of the TFT;
  • a passivation layer 29 formed on a surface of the first transparent electrode 281, the passivation layer 29 covering the TFT;
  • a second transparent electrode 282 is formed on the surface of the passivation layer 29.
  • the “overlay TFT” herein refers to an area covering at least the gate, the drain, and the source of the TFT.
  • the first transparent electrode 281 is a pixel electrode
  • the second transparent electrode 282 is The common electrode
  • the first transparent electrode 281 is a plate electrode
  • the second transparent electrode 282 is a strip electrode including a plurality of metal strips arranged at intervals.
  • the electrode located in the upper layer is a strip electrode
  • the electrode located in the lower layer is a strip electrode or a plate electrode.
  • the description was made by taking the electrode located in the lower layer as a flat electrode as an example.
  • the common electrode and the pixel electrode are disposed in different layers.
  • the "different layer setting" herein means that at least two films are respectively formed into at least two patterns by a patterning process, and the at least two patterns are disposed in layers different from each other.
  • the array substrate of such a structure provided in this embodiment can also be applied to an IPS type display device.
  • the common electrode and the pixel electrode are disposed in the same layer, and the common electrode includes a plurality of first strip electrodes, and the pixel electrode includes a plurality of And a second strip electrode, wherein the first strip electrode and the second strip electrode are spaced apart.
  • “same layer setting" means that at least two patterns are formed by the same film through a patterning process.
  • the common electrode and the pixel electrode are disposed in the same layer means that the pixel electrode and the common electrode are formed by the patterning process from the same transparent conductive film.
  • the pixel electrode refers to an electrode electrically connected to a data line through a switching unit (for example, a thin film transistor), and the common electrode refers to an electrode electrically connected to the common electrode line.
  • the semiconductor active layer 23 is made of a transparent metal oxide material having semiconductor characteristics.
  • the transparent metal oxide material includes at least one of: IGZO indium gallium zinc oxide, IGO (indium gallium oxide), ITZO (indium tin zinc oxide), and AlZnO (aluminum zinc oxide).
  • IGZO indium gallium zinc oxide IGO (indium gallium oxide), ITZO (indium tin zinc oxide), and AlZnO (aluminum zinc oxide).
  • a transparent metal oxide material in place of a-Si (amorphous silicon) or LTPS (low-temperature polysilicon) to form a semiconductor active layer of a TFT has advantages such as low preparation temperature requirement and high mobility, and the technique can be applied to high Frequency display and high-resolution display products, and have the advantages of low equipment cost and low operating cost compared to LTPS TFT technology.
  • the present invention also provides a display device comprising the array substrate as described above.
  • the array substrate includes a first insulating layer formed between a gate of the TFT and the gate insulating layer, the first insulating layer corresponding to at least one of a source of the TFT and a drain of the TFT, Further, the gate of the TFT is in contact with the gate insulating layer in the channel region of the corresponding TFT.
  • the display device provided in this embodiment may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • the array substrate is formed with a certain thickness by a gate region between the TFT and the gate insulating layer, a source region corresponding to the TFT, and/or a drain region of the TFT.
  • An insulating layer is formed.
  • the parasitic capacitance Cgs or the parasitic capacitance Cgd existing between the drain and the gate of the TFT is reduced, thereby avoiding the output jump voltage defect caused by the excessive parasitic capacitance, effectively improving the flicker of the display screen, and improving the quality of the display device.
  • a further embodiment of the present invention further provides a method for fabricating an array substrate, comprising:
  • the first insulating layer corresponds to at least one of a source of the TFT or a drain of the TFT.
  • the description is made by taking the first insulating layer 26 simultaneously corresponding to the source 251 of the TFT and the drain 252 of the TFT.
  • the spacing between the gate 21 of the TFT and the source and drain electrodes 251, 252 is significantly increased, thereby effectively reducing the source 252 and the gate 21 of the TFT.
  • the parasitic capacitance Cgs present and the parasitic capacitance Cgd existing between the drain 252 and the gate 21 of the TFT are reduced.
  • the first insulating layer 26 corresponds only to the source 251 of the TFT; at this time, since the electrode spacing between the gate 21 and the source 251 of the TFT which is the two electrodes of the parallel plate capacitor is increased, thereby The parasitic capacitance Cgs between the source 251 and the gate 21 is effectively reduced.
  • the first insulating layer 26 only corresponds to the drain 252 of the TFT, and the parasitic capacitance Cgd between the drain 252 and the gate 21 is effectively reduced.
  • the source 251 of the TFT and the drain 252 of the TFT respectively correspond to the first insulating layer 26 of the TFT
  • the thicknesses of the portions are equal (i.e., the thicknesses of the left and right portions of the first insulating layer 26 in FIG. 2 are equal).
  • the thickness D of the first insulating layer 26 is 1 ⁇ -3 ⁇ m. The design of such a thickness of the first insulating layer 26 is passed while reducing the capacitance between the electrodes The known patterning process is easily produced and implemented, thereby effectively reducing the production difficulty of the product.
  • the capacitance is reduced by increasing the spacing between the two electrodes when other conditions are constant.
  • the capacitance between the two electrodes in the present embodiment is reduced as compared with the capacitance of the capacitor in the known array substrate, so that the influence of the trip voltage generated by the parasitic capacitance on the display screen can be effectively reduced.
  • the array substrate forms a first insulation having a certain thickness by a source region of the TFT and/or a drain region of the TFT between the gate of the TFT and the gate insulating layer.
  • the spacing between the gate and the source and drain of the TFT is significantly increased, so that the capacitance between the two electrodes of the parallel plate capacitor is increased, so that the capacitance is significantly reduced, thereby effectively reducing the source and the gate of the TFT.
  • the parasitic capacitance Cgs existing between the TFTs reduces the parasitic capacitance Cgd existing between the drain and the gate of the TFT, thereby avoiding the output jump voltage defect caused by the excessive parasitic capacitance, effectively improving the flicker of the display screen, and improving the quality of the display device. .
  • a method for fabricating an array substrate according to still another embodiment of the present invention includes:
  • the base substrate is made of, for example, a transparent material having a certain hardness such as glass or a transparent resin, and then a second insulating layer is formed on the base substrate by using a patterning process.
  • a layer of an organic resin material having a certain thickness is first applied to the surface of the base substrate to form a second insulating film.
  • Exposure development by a mask having a specific pattern finally forms the second insulating layer 27 as shown in FIG.
  • a gate of the TFT by a patterning process on the substrate on which the second insulating layer is formed.
  • a metal layer is formed on a substrate on which a second insulating layer is formed by plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering, thermal evaporation, or other film forming method.
  • PECVD plasma enhanced chemical vapor deposition
  • the metal layer may be a single-layer film formed of a metal or an alloy such as a 4-mesh, aluminum, aluminum-bismuth alloy, tungsten, chromium, or copper, or a multilayer film formed of the above metal or alloy.
  • a photoresist is formed on the surface of the metal layer, and is exposed and developed by a mask having a specific pattern to expose a part of the metal layer, and the film is peeled off.
  • the exposed metal layer finally forms the gate 21 of the TFT on the surface of the second insulating layer, as shown in FIG. S403, forming a first insulating layer on a surface of the gate of the TFT.
  • a layer of an organic resin material is coated on the surface of the substrate on which the gate of the TFT is formed, as shown in
  • the first insulating layer 260 will completely cover the gate of the TFT.
  • the first insulating layer is processed by an ashing process to expose at least a gate of the TFT.
  • the first insulating layer 260 is processed by an ashing process, and its thickness is reduced as a whole until the surface of the gate of the TFT is exposed, and finally the patterned first insulating layer 26 is formed.
  • an ashing process is taken as an example. It should be understood that in order to expose the surface of the gate of the TFT, various other known patterning processes may be employed, which are not limited by the present invention. .
  • the sum D of the thicknesses of the second insulating layer 27 and the gate 21 of the TFT is greater than or equal to the thickness D' of the first insulating layer 26.
  • the first insulating layer 26 and the second insulating layer 27 are made of a material such as an organic resin material having good insulating properties, which is not limited in the present invention.
  • the gate 21 of the TFT located in the region is raised, so that the gate 21 corresponds to the upper surface of the channel of the TFT and the first insulating layer. There is no significant step difference between the upper surfaces of 26, ie the two are flush or substantially flush. Further, by controlling the thicknesses of the first insulating layer and the second insulating layer, the sum D of the thicknesses of the gate layers 21 of the two insulating layers 27 and the TFTs is greater than or equal to the thickness D of the first insulating layer 26, thereby ensuring at least the exposure. A surface of the gate electrode 21 corresponding to the channel of the TFT to ensure formation of a channel of the TFT.
  • a gate insulating layer 22 having a uniform thickness is formed on the surface of the substrate on which the first insulating layer 26 is formed.
  • a semiconductor active layer film having semiconductor characteristics is formed on the surface of the substrate on which the above structure is formed, and exposed and developed by a mask to form a semiconductor active layer 23 as shown in Fig. 8.
  • the semiconductor active layer 23 is transparent in semiconductor characteristics.
  • the transparent metal oxide material includes at least one of IGZO, IGO, ITZO, and AlZnO.
  • IGZO IGZO
  • IGO amorphous silicon
  • ITZO amorphous silicon
  • AlZnO aluminum oxide
  • the use of such a transparent metal oxide material instead of a-Si (amorphous silicon) or LTPS (low temperature polysilicon) to form a semiconductor active layer of a TFT has advantages such as low preparation temperature requirement and high mobility, and the technique can be applied to high Frequency display and high-resolution display products, and have the advantages of low equipment cost and low operating cost compared to LTPS TFT technology.
  • the etch stop layer 24 is shown in FIG.
  • a via hole is finally formed at a position of a source and a drain of the corresponding TFT, respectively ( In the dotted line region in Fig. 9, the bottom of the via exposes the semiconductor active layer 23, thereby obtaining the etch stop layer 24.
  • S408 forming a source and a drain of the TFT by a patterning process on a surface of the etch barrier layer, wherein the source and the drain of the TFT are respectively in contact with the semiconductor active layer through the via hole.
  • the substrate structure in which the source 251 and the drain 252 of the TFT are formed is as shown in FIG.
  • the structure of the substrate on which the first transparent electrode 281 is formed is as shown in FIG.
  • the structure of the substrate on which the passivation layer 29 is formed is as shown in FIG.
  • the first transparent electrode 281 is a pixel electrode
  • the second transparent electrode 282 is a common electrode
  • the first transparent electrode 281 is a plate electrode
  • the second transparent electrode 282 is a strip electrode including a plurality of spaced metal strips.
  • the array substrate of such a configuration provided in this embodiment can also be applied to various display device array substrates such as an ADS type display device, an IPS type display device, or a TN type display device.
  • various display device array substrates such as an ADS type display device, an IPS type display device, or a TN type display device.
  • the specific arrangement and shape of the common electrode and the pixel electrode are described with reference to the embodiments in the foregoing. It is conceivable that when the position or shape of the pixel electrode or the common electrode changes due to different types of display devices, The steps or processes of forming the pixel electrode or the common electrode can also be performed to achieve the production of various array substrates, which is not listed in the present disclosure.
  • the above array substrate manufacturing method significantly increases the spacing between the gate and the source and drain of the TFT, so that the capacitance between the two electrodes of the parallel plate capacitor is increased, so that the capacitance value is significantly reduced, thereby effectively reducing the TFT.
  • the parasitic capacitance Cgs existing between the source and the gate reduces the parasitic capacitance Cgd existing between the drain and the gate of the TFT, thereby avoiding the output jump voltage defect caused by the excessive parasitic capacitance, effectively improving the display flicker. , improve the quality of the display device.

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Abstract

公布一种阵列基板及其制造方法和显示装置。该阵列基板包括：依次形成在衬底基板表面上的TFT的栅极以及栅绝缘层；在所述栅绝缘层对应所述TFT的栅极的表面上依次形成的半导体有源层、刻蚀阻挡层以及所述TFT的源极和漏极，所述TFT的源极和漏极分别通过过孔与所述半导体有源层相接触；该阵列基板还包括：形成在所述TFT的栅极和所述栅绝缘层之间的第一绝缘层，所述第一绝缘层对应所述TFT的源极和所述TFT的漏极中的至少一个；以及所述栅极在对应所述TFT的源极和漏极之间的TFT的沟道区域与所述栅绝缘层接触该阵列基板降低了TFT的源、漏电极与栅极之间的寄生电容，提高了显示装置的质量。

Description

阵列基板及其制造方法、 显示装置 技术领域
本公开涉及一种阵列基板及其制造方法、 显示装置。 背景技术
随着 TFT-LCD ( Thin Film Transistor Liquid Crystal Display, 薄膜晶体管 液晶显示器）显示技术的不断发展， 各种新型半导体元件及其在显示装置中 的应用技术也随之得到了飞跃性的进步。
在已知的 TFT-LCD 的制造过程当中， 越来越多的厂商开始尝试采用氧 化物 TFT (即 Oxide TFT )取代 a-Si (非晶硅） TFT或 LTPS (低温多晶硅） TFT, 以期获得具有更高质量的显示产品。 氧化物 TFT背板技术， 是与传统 的 a-Si TFT制程相近的一种背板技术，该技术将原本应用于 a-Si TFT的硅半 导体材料置换成氧化物半导体材料， 如现在应用最为广泛的 IGZO(Indmm Gallium Zinc Oxide, 铟镓锌氧化物)材料， 来形成 TFT 的半导体有源层。 已 知一种典型的氧化物 TFT的阵列基板结构如图 1所示， 包括依次形成在透明 基板 10表面的 TFT的栅极 11、栅绝缘层 12以及由 IGZO形成的半导体有源 层 13。 半导体有源层 13的表面上通过构图工艺形成有具有过孔 A、 B的刻 蚀阻挡层 14，过孔 A、 B分别贯穿刻蚀阻挡层 14,以暴露出半导体有源层 13。 TFT的源极 151和漏极 152分别通过过孔 A、 B与半导体有源层 13电连接。 发明内容
本公开提供一种阵列基板及其制造方法、 显示装置。
根据本发明的一个实施例， 提供一种阵列基板， 包括依次形成在衬底基 板表面上的 TFT的栅极以及栅绝缘层； 在所述栅绝缘层对应所述 TFT的栅 极的表面上依次形成的半导体有源层、刻蚀阻挡层以及所述 TFT的源极和漏 极， 所述 TFT的源极和漏极分别通过过孔与所述半导体有源层相接触。 该阵 列基板还包括： 形成在所述 TFT的栅极和所述栅绝缘层之间的第一绝缘层， 所述第一绝缘层对应所述 TFT的源极和所述 TFT的漏极中的至少一个； 以 及所述栅极在对应所述 TFT的源极和漏极之间的 TFT的沟道区域与所述栅 绝缘层接触。
根据本发明的另一个实施例， 提供一种包括如上所述的阵列基板的显示 装置。
根据本发明再一实施例， 还提供了一种阵列基板制造方法， 包括： 在衬底基板的表面上形成 TFT的栅极；
在形成有所述栅极的基板上形成第一绝缘层， 所述第一绝缘层对应 TFT 的源极和 TFT的漏极中的至少一个； 以及
在形成有所述第一绝缘层的基板的表面上形成栅绝缘层， 所述栅极在对 应所述 TFT的沟道的区域处与所述栅绝缘层接触。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为一种已知阵列 反的结构示意图；
图 2为本发明实施例提供的一种阵列基板的结构示意图；
图 3为本发明实施例形成第二绝缘层后的基板结构示意图；
图 4为本发明实施例形成 TFT栅极后的基板结构示意图；
图 5为本发明实施例形成第一绝缘层后的基板结构示意图；
图 6为本发明实施例形成第一绝缘层后的基板结构示意图；
图 7为本发明实施例形成栅绝缘层后的基板结构示意图；
图 8为本发明实施例形成半导体有源层后的基板结构示意图； 图 9为本发明实施例形成刻蚀阻挡层后的基板结构示意图；
图 10为本发明实施例形成 TFT的源极和漏极后的基板结构示意图； 图 11为本发明实施例形成第一透明电极后的基板结构示意图； 图 12为本发明实施例形成钝化层后的基板结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例中的附图， 对本发明实施例中的技术方案进行清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有做出创造性劳动前提下 所获得的所有其他实施例， 都属于本发明保护的范围。
在如图 1所示的已知氧化物 TFT阵列 反中， TFT的源极 151和漏极
152分别与栅极 11具有较大的重叠区域。 在 TFT通电的情况下， 源极 151 与栅极 11之间产生寄生电容 Cgs， 同理漏极 152与栅极 11之间产生寄生电 容 Cgd。在栅线 11通过电压控制 TFT开关的瞬间，由于寄生电容 Cgs和 Cgd 的存在， TFT关闭时栅线 11上的电压信号由高值到低值的变化会使得漏极 152输出跳变电压， 从而引起像素中液晶电压的突然降低， 这将严重影响像 素电极电压的准确性， 导致显示画面闪烁。
本发明一个实施例提供的阵列基板， 如图 2所示， 包括：
依次形成在衬底基板 20表面上的 TFT的栅极 21以及栅绝缘层 22; 层 23、 刻蚀阻挡层 24以及所述 TFT的源极 251和漏极 252， 所述 TFT的源 极 251和漏极 252分别通过过孔（图 2中虚线框所示）与半导体有源层 23 相接触。
本公开中的 "A对应 B" 指的是 A、 B在竖直方向上彼此相对或至少部 分重叠。 因此， "栅绝缘层 22对应所述 TFT的栅极 21的表面 " 应理解为栅 绝缘层 22与栅极 21在竖直方向上相对或相重叠的那部分的表面。
该阵列基板还包括：
形成在 TFT的栅极 21和栅绝缘层 22之间的第一绝缘层 26, 该第一绝 缘层 26对应该 TFT的源极 251和该 TFT的漏极 252中的至少一个。
此外，栅极 21与栅绝缘层 22在对应所述 TFT的源极 215和漏极 252之 间 TFT的沟道区域处接触。 由于对应 TFT沟道区域处需要保证栅极材料与 半导体有源层之间具有一个较小的距离， 因此无需设置绝缘层 26。
与图 1的已知采用氧化物 TFT的阵列基板相比， 可以明显的看出， 图 2 所示的阵列基板中 TFT的源极 251或漏极 252与栅极 21之间的间距远远大 于图 1中 TFT的源极 151或漏极 152各自与栅极 11之间的间距。
在上述实施例提供的阵列基板中， 在 TFT的栅极和栅绝缘层之间， 对应 TFT的源极的区域和 /或 TFT的漏极的区域形成具有一定厚度的第一绝缘层。 该结构显著增加了 TFT 的栅极与源 /漏极之间的间距， 这样由于平行板电容 器的两电极之间的间距增大， 使得电容明显降低， 从而有效降低了 TFT的源 极与栅极之间存在的寄生电容 Cgs或降低 TFT的漏极与栅极之间存在的寄生 电容 Cgd， 进而避免由于寄生电容 Cgd、 Cgs过大而产生的输出跳变电压不 良， 有效改善显示画面闪烁， 提高显示装置的质量。
在一个实施例中， 第一绝缘层 26与 TFT的源极 251或 TFT的漏极 252 中的至少一个相对应。在如图 2所示的阵列基板中，是以第一绝缘层 26同时 对应 TFT的源极 251和 TFT的漏极 252为例进行的说明。 当采用这样一种 如图 2所示的阵列基板时， 显著增加了 TFT的栅极 21与源漏极 251、 252之 间的间距， 从而有效降低了 TFT的源极 252与栅极 21之间存在的寄生电容 Cgs以及降低 TFT的漏极 252与栅极 21之间存在的寄生电容 Cgd。 在一个 实施例中， 第一绝缘层 26仅对应 TFT的源极 251 ; 此时， 由于作为平行板 电容器的两个电极的 TFT的栅极 21和源极 251之间的电极间距增大， 从而 有效降低了源极 251与栅极 21之间寄生电容 Cgs。同理，在另一个实施例中， 第一绝缘层 26仅对应 TFT的漏极 252, 此时有效降低了漏极 252与栅极 21 之间寄生电容 Cgd。
在一个实施例中， 当第一绝缘层 26同时对应该 TFT的源极 251和 TFT 的漏极 252时， 该 TFT的源极 251和 TFT的漏极 252分别对应的第一绝缘 层 26的两个部分的厚度相等（即图 2中第一绝缘层 26的左、 右部分的厚度 相等）。
如图 2所示， 在一个实施例中， 第一绝缘层 26的厚度 D， 为 1 μ ηι-3 μ m。这样一种厚度的第一绝缘层 26的设计在降低电极之间电容的同时通过已 知的构图工艺轻松制作实现， 从而有效降低了产品的生产难度。
根据平行板电容公式 C= s S/d可知， 为了减小平行电极之间的电容， 当 其他条件不变时， 通过增大两电极之间的间距实现电容的减小。 由于图 2中 的两电极（一个电极为源极 251或漏极 252， 另一个电极为栅极 21 )之间的 间距增大了， 因此电容减小， 从而能够有效降低寄生电容所产生的跳变电压 对显示画面的影响。
如图 2所示， 本实施例的阵列基板还包括： 形成在衬底基板 20和 TFT的栅极 21之间的第二绝缘层 27， 该第二绝 缘层 27对应 TFT的沟道（图 2中 C区域）； 第二绝缘层 27与 TFT的栅极 21 的厚度之和 D大于等于第一绝缘层 26的厚度 D，。 在一个实施例中， 第一 绝缘层 26和第二绝缘层 27采用诸如有机树脂材料等的具有良好绝缘性的材 料制成， 本发明对此并不做限制。
这样， 通过在对应 TFT的沟道的区域制作第二绝缘层 27, 抬高了位于 该区域的 TFT的栅极 21 , 以使得栅极 21的上表面与第一绝缘层 26的上表 面之间没有明显的段差。 进一步地， 通过控制笫一绝缘层以及笫二绝缘层的 厚度， 以使得二绝缘层 27与 TFT的栅极 21的厚度之和 D大于等于第一绝 缘层 26的厚度 D，， 从而保证至少露出栅极 21的表面， 以确保形成 TFT的 沟道。
需要说明的是， 根据以上实施例提供的 TFT-LCD 阵列基板可以应用于 FFS ( Fringe Field Switching, 边缘场开关）型、 AD-SDS ( Advanced- Super Dmiensional Switching, 简称为 ADS , 高级超维场开关）型、 IPS ( In Plane Switch, 面内电场效应）型、 TN ( Twist Nematic, 扭曲向列）型等类型的液 晶显示装置。
无论上述哪种液晶显示装置都包括对盒的彩膜基板和阵列基板。 然而， 在 TN型显示装置中， 公共电极设置在彩膜基板上， 像素电极设置在阵列基 板上； 在 FFS型显示装置、 ADS型显示装置以及 IPS型显示装置中， 公共电 极和像素电极均设置在阵列基板上。
下面以应用到 FFS型显示装置的阵列基板为例进行说明。 如图 2所示， 根据上述实施例的阵列基板还包括：
形成在刻蚀阻挡层 24表面上的第一透明电极 281， 该第一透明电极 281 与 TFT的漏极 252相接触；
形成在第一透明电极 281表面上的钝化层 29， 该钝化层 29覆盖 TFT; 以及
形成在该钝化层 29表面上的第二透明电极 282。
本文中的 "覆盖 TFT"指的是至少覆盖该 TFT的栅极、 漏极、 源极所在 的区域。
在一个实施例中， 第一透明电极 281为像素电极， 第二透明电极 282为 公共电极， 且该第一透明电极 281为板状电极， 第二透明电极 282为包括多 个间隔排列的金属条的条状电极。
可选的， 位于上层的电极为条状电极， 位于下层的电极为条状电极或为 板状电极。 在上述实施例中， 是以位于下层的电极为平状电极为例进行的说 明。 在所述 FFS型显示装置的阵列基板中， 所述公共电极和所述像素电极为 异层设置。 本文中的 "异层设置" 是指， 分别将至少两层薄膜通过构图工艺 形成至少两种图案，且该至少两种图案设置在彼此不同的层中。例如， "公共 电极和像素电极为异层设置" 是指， 由笫一层透明导电薄膜通过构图工艺形 成下层电极， 由第二层透明导电薄膜通过构图工艺形成上层电极， 下层电极 为公共电极（或像素电极）， 上层电极为像素电极（或公共电极）。
本实施例提供的这样一种结构的阵列基板同样可以应用于 IPS型显示装 置。 与 FFS型显示装置不同的是， 在 IPS型显示装置中， 所述公共电极和所 述像素电极为同层设置， 并且所述公共电极包含多个第一条形电极， 所述像 素电极包含多个第二条形电极， 所述第一条形电极和所述第二条形电极间隔 设置。 本文中的 "同层设置" 是指， 将同一薄膜通过构图工艺形成至少两种 图案。 例如， "公共电极和像素电极同层设置"是指， 由同一透明导电薄膜通 过构图工艺形成像素电极和公共电极。 像素电极是指通过开关单元（例如， 薄膜晶体管）与数据线电连接的电极， 公共电极是指和公共电极线电连接的 电极。
在本发明至少一个实施例中，半导体有源层 23采用呈半导体特性的透明 金属氧化物材料制成。 例如， 所述透明金属氧化物材料包括： IGZO 铟镓锌 氧化物 )、 IGO (铟镓氧化物）、 ITZO (铟锡锌氧化物）、 AlZnO (铝锌氧化物） 中的至少一种。采用这样一种透明金属氧化物材料取代 a-Si(非晶硅）或 LTPS (低温多晶硅）来形成 TFT 的半导体有源层， 具有制备温度要求低， 迁移 率高等优势，该技术可应用于高频显示和高分辨率显示产品，且相对于 LTPS TFT技术具有设备成本低、 运营成本低等优点。
本发明的另一实施例还提供一种显示装置， 包括如上所述的阵列基板。 在一个实施例中，该阵列基板包括形成在 TFT的栅极和所述栅绝缘层之 间的第一绝缘层， 该第一绝缘层对应 TFT的源极和 TFT的漏极中的至少一 个， 并且， 在对应 TFT的沟道区域， 该 TFT的栅极与栅绝缘层接触。 本实施例所提供的显示装置可以为： 液晶面板、 电子纸、 OLED面板、 液晶电视、 液晶显示器、 数码相框、 手机、 平板电脑等任何具有显示功能的 产品或部件。
在上述实施例提供的包括阵列基板的显示装置中， 该阵列基板通过在 TFT的栅极和栅绝缘层之间， 对应 TFT的源极区域和 /或 TFT的漏极区域形 成具有一定厚度的第一绝缘层。 这样， 显著增加了 TFT的栅极与源漏极之间 的间距， 由于平行板电容器的两电极之间的间距增大， 使得电容明显降低， 从而有效降低 TFT的源极与栅极之间存在的寄生电容 Cgs或降低 TFT的漏 极与栅极之间存在的寄生电容 Cgd， 进而避免由于寄生电容过大而产生的输 出跳变电压不良， 有效改善显示画面闪烁， 提高显示装置的质量。
本发明的又一实施例还提供一种阵列基板制造方法， 包括：
5301、 在村底基板的表面上形成 TFT的栅极。
5302、 在形成有所述栅极的基板上形成第一绝缘层， 该第一绝缘层对应 TFT的源极和 TFT的漏极中的至少一个。
在一个实施例中， 第一绝缘层与 TFT的源极或 TFT的漏极中的至少一 个相对应。 在如图 2所示的阵列基板中， 是以第一绝缘层 26同时对应 TFT 的源极 251和 TFT的漏极 252为例进行的说明。 当采用这样一种如图 2所示 的阵列基板时， 显著增加了 TFT的栅极 21与源漏极 251、 252之间的间距， 从而有效降低了 TFT的源极 252与栅极 21之间存在的寄生电容 Cgs以及降 低 TFT的漏极 252与栅极 21之间存在的寄生电容 Cgd。 在一个实施例中， 第一绝缘层 26仅对应 TFT的源极 251 ; 此时， 由于作为平行板电容器的两 个电极的 TFT的栅极 21和源极 251之间的电极间距增大， 从而有效降低了 源极 251与栅极 21之间寄生电容 Cgs。 同理， 在另一个实施例中， 第一绝缘 层 26仅对应 TFT的漏极 252， 此时有效降低了漏极 252与栅极 21之间寄生 电容 Cgd。
在一个实施例中， 当第一绝缘层 26同时对应该 TFT的源极 251和 TFT 的漏极 252时， 该 TFT的源极 251和 TFT的漏极 252分别对应的第一绝缘 层 26的两个部分的厚度相等（即图 2中第一绝缘层 26的左、 右部分的厚度 相等）。 如图 2所示， 在一个实施例中， 第一绝缘层 26的厚度 D， 为 1 μ πι-3 μ m。这样一种厚度的第一绝缘层 26的设计在降低电极之间电容的同时通过 已知的构图工艺轻松制作实现， 从而有效降低了产品的生产难度。
根据平行板电容公式 C= ε S/d可知， 为了减小平行电极之间的电容， 当 其他条件不变时， 通过增大两电极之间的间距实现电容的减小。 这样， 与已 知阵列基板中电容器的电容相比， 本实施例中的两电极之间的电容减小， 从 而能够有效降低了寄生电容所产生的跳变电压对显示画面的影响。
S303、 在形成有第一绝缘层的基板的表面上形成栅绝缘层， 其中所述栅 极与所述栅绝缘层在对应 TFT沟道的区域接触。
由于对应 TFT 沟道的区域处需要保证栅极材料与半导体有源层之间具 有一个较小的距离， 因此无需设置绝缘层。
在上述实施例提供的阵列基板制造方法中，该阵列基板通过在 TFT的栅 极和栅绝缘层之间， 对应 TFT的源极区域和 /或 TFT的漏极区域形成具有一 定厚度的第一绝缘层。 这样， 显著增加了 TFT的栅极与源漏极之间的间距， 这样由于平行板电容器的两电极之间的间距增大， 使得电容明显降低， 从而 有效降低了 TFT的源极与栅极之间存在的寄生电容 Cgs或降低 TFT的漏极 与栅极之间存在的寄生电容 Cgd, 进而避免由于寄生电容过大而产生的输出 跳变电压不良， 有效改善显示画面闪烁， 提高显示装置的质量。
进一步地， 本发明再一实施例提供的阵列基板制造方法， 包括：
S401、 在衬底基板的表面上通过构图工艺形成第二绝缘层， 该第二绝缘 层对应 TFT的沟道。
在阵列基板的实际生产过程当中， 衬底基板例如采用玻璃或透明树脂等 具有一定硬度的透明材料制成， 然后通过釆用一次构图工艺在衬底基板上形 成第二绝缘层。 例如， 首先在衬底基板的表面涂覆一层具有一定厚度的有机 树脂材料， 形成第二绝缘薄膜。 通过具有特定图案的掩模板进行曝光显影最 终形成如图 3所示的第二绝缘层 27。
S402、 在形成有第二绝缘层的基板上通过构图工艺形成 TFT的栅极。 例如， 在形成有第二绝缘层的基板上采用等离子增强化学气相沉积 ( PECVD )、 磁控溅射、 热蒸发或其它成膜方法， 形成金属层。 该金属层可 以是 4目、 铝、 铝铷合金、 钨、 铬、 铜等金属或合金形成的单层薄膜， 也可以 是以上金属或合金形成的多层薄膜。然后，在该金属层的表面形成有光刻胶， 通过具有特定图案的掩模板进行曝光显影以使一部分金属层暴露， 剥离掉暴 露的金属层， 最终在第二绝缘层的表面形成 TFT的栅极 21 , 如图 4所示。 S403、 在 TFT的栅极的表面上形成形成第一绝缘层。
例如， 在形成有 TFT的栅极的基板的表面涂覆一层有机树脂材料， 如图
5所示， 以形成第一绝缘层 260。 该第一绝缘层 260将完全覆盖 TFT的栅极。
S404、 采用灰化工艺处理第一绝缘层， 以至少暴露出 TFT 的栅极的与
TFT沟道相对应的表面。
如图 6所示， 该第一绝缘层 260通过灰化工艺的处理， 其厚度将整体降 低， 直至暴露出 TFT的栅极的表面为止， 最终形成图案化的第一绝缘层 26。 在本发明实施例中是以采用灰化工艺为例进行的说明， 应当理解， 为了暴露 出 TFT的栅极的表面，还可以采用其他各种已知的构图工艺， 本发明对此并 不作限制。
在一个实施例中， 第二绝缘层 27与 TFT的栅极 21的厚度之和 D大于 等于第一绝缘层 26的厚度 D'。在一个实施例中，第一绝缘层 26和第二绝缘 层 27均采用具有良好绝缘性的有机树脂材料等材料制成，本发明对此并不做 限制。
这样， 通过在对应 TFT的沟道区域制作第二绝缘层 27, 抬高了位于该 区域的 TFT的栅极 21，以使得柵极 21对应所述 TFT的沟道的上表面与第一 绝缘层 26的上表面之间没有明显的段差，即二者齐平或基本齐平。进一步地， 通过控制第一绝缘层以及第二绝缘层的厚度， 以使得二绝缘层 27与 TFT的 栅极 21的厚度之和 D大于等于第一绝缘层 26的厚度 D，， 从而保证至少露 出柵极 21的与所述 TFT的沟道相对应的表面， 以确保形成 TFT的沟道。
5405、 在形成有第一绝缘层的基板的表面形成栅绝缘层， 所述栅极在对 应 TFT的沟道区域处与栅绝缘层接触。
如图 7所示，在形成有第一绝缘层 26的基板的表面上形成有厚度均一的 栅绝缘层 22。
5406、在栅绝缘层对应 TFT的栅极区域的表面上通过构图工艺形成半导 体有源层。
例如， 在形成有上述结构的基板表面形成具有半导体特性的半导体有源 层薄膜， 通过掩模板曝光、 显影， 形成如图 8所示的半导体有源层 23。
在本发明至少一个实施例中，半导体有源层 23采用呈半导体特性的透明 金属氧化物材料制成。 例如， 所述透明金属氧化物材料包括： IGZO、 IGO、 ITZO、 AlZnO 中的至少一种。 采用这样一种透明金属氧化物材料取代 a-Si (非晶硅）或 LTPS (低温多晶硅）来形成 TFT 的半导体有源层， 具有制备 温度要求低， 迁移率高等优势， 该技术可应用于高频显示和高分辨率显示产 品， 且相对于 LTPS TFT技术具有设备成本低、 运营成本低等优点。
S407、 在半导体有源层的表面通过构图工艺形成具有过孔的刻蚀阻挡 层。
刻蚀阻挡层 24如图 9所示。例如，通过在形成有上述结构的基板上涂覆 或沉积刻蚀阻挡层薄膜， 然后通过具有特定图案的掩模板曝光、 显影， 最终 在对应 TFT的源极和漏极的位置分别形成过孔（图 9中虚线区域）， 过孔的 底部暴露出半导体有源层 23 , 从而得到刻蚀阻挡层 24。
S408、在刻蚀阻挡层的表面上通过构图工艺形成 TFT的源极和漏极，该 TFT的源极和漏极分别通过过孔与半导体有源层相接触。
形成有 TFT的源极 251和漏极 252的基板结构如图 10所示。
S409、在形成有 TFT的源极和漏极的基板的表面通过构图工艺形成第一 透明电极， 该第一透明电极与 TFT的漏极相接触。
形成有第一透明电极 281的基板结构如图 11所示。
5410、 在第一透明电极的表面上通过构图工艺形成钝化层， 该飩化层覆 盖 TFT。
形成有钝化层 29的基板结构如图 12所示。
5411、 在钝化层的表面上通过构图工艺形成第二透明电极。 最终形成如 图 2所示的阵列基板。
需要说明的是，在本发明实施例中是以 FFS型显示装置为例进行的说明。 第一透明电极 281为像素电极， 第二透明电极 282为公共电极， 且该第一透 明电极 281为板状电极， 第二透明电极 282为包括多个间隔排列的金属条的 条状电极。
本实施例提供的这样一种结构的阵列基板同样可以适用于 ADS 型显示 装置、 IPS型显示装置或 TN型显示装置等各种显示装置阵列基板。 公共电 极与像素电极的具体设置和形状参考前文中实施例的描述。 可以想到， 当像 素电极或公共电极的位置或形状因显示装置的不同类型而发生变化时， 通过 改变形成像素电极或公共电极的步骤或工艺， 同样能实现各种阵列基板的生 产， 本公开对此并不——列举。
釆用上述阵列基板制造方法，显著增加了 TFT的柵极与源漏极之间的间 距， 这样由于平行板电容两电极之间的间距增大， 使得电容值明显降低， 从 而有效降低了 TFT的源极与栅极之间存在的寄生电容 Cgs或降低 TFT的漏 极与栅极之间存在的寄生电容 Cgd， 进而避免由于寄生电容过大而产生的输 出跳变电压不良， 有效改善显示画面闪烁， 提高显示装置的质量。
本申请基于并且要求于 2013 年 12 月 26 曰递交的中国专利申请笫 201310739761.4号的优先权， 在此全文引用上述中国专利申请公开的内容。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板， 包括：
依次形成在村底基板表面上的 TFT的栅极以及栅绝缘层；
在所述栅绝缘层对应所述 TFT 的栅极的表面上依次形成的半导体有源 层， 刻蚀阻挡层以及所述 TFT的源极和漏极， 所述 TFT的源极和漏极分别 通过过孔与所述半导体有源层相接触；
该阵列基板还包括：
形成在所述 TFT的栅极和所述栅绝缘层之间的第一绝缘层，所述第一绝 缘层对应所述 TFT的源极和所述 TFT的漏极中的至少一个； 以及
所述栅极在对应所述 TFT的源极和漏极之间的 TFT的沟道区域与所述 栅绝缘层接触。
2、 根据权利要求 1所述的阵列基板， 还包括：
形成在所述村底基板和所述 TFT的栅极之间的第二绝缘层，所述第二绝 缘层对应所述 TFT的沟道， 并且所述第二绝缘层与所述 TFT的栅极的厚度 之和大于等于所述第一绝缘层的厚度。
3、 根据权利要求 1或 2所述的阵列基板， 还包括：
形成在所述刻蚀阻挡层表面上的第一透明电极， 所述第一透明电极与所 述 TFT的漏极相接触；
形成在所述第一透明电极表面上的钝化层， 所述钝化层覆盖所述 TFT; 以及
形成在所述钝化层表面上的第二透明电极。
4、根据权利要求 3所述的阵列基板，其中所述第一透明电极为像素电极， 所述第二透明电极为公共电极； 且所述第一透明电极为板状电极， 所述第二 透明电极为条状电极。
5、根据权利要求 2所述的阵列基板，其中所述第一绝缘层和所述第二绝 缘层均釆用有机树脂材料制成。
6、根据权利要求 1-5任一所述的阵列基板， 其中所述第一绝缘层同时对 应所述 TFT的源极和所述 TFT的漏极。
7、 根据权利要求 6所述的阵列基板， 其中所述 TFT的源极和所述 TFT 的漏极分别对应的所述笫一绝缘层的两个部分的厚度相等，该厚度为 1 μ ηι-3 μ πι。
8、根据权利要求 1-7任一所述的阵列基板， 其中所述半导体有源层釆用 呈半导体特性的透明金属氧化物材料制成。
9、根据权利要求 1-8任一所述的阵列基板， 其中所述栅极对应所述 TFT 的沟道的表面与所述第一绝缘层的表面齐平。
10、 一种显示装置， 包括如权利要求 1-9任一所述的阵列基板。
11、 一种阵列基板制造方法， 包括：
在衬底基板的表面上形成 TFT的栅极；
在形成有所述栅极的基板上形成第一绝缘层， 所述第一绝缘层对应 TFT 的源极和 TFT的漏极中的至少一个； 以及
在形成有所述第一绝缘层的基板的表面上形成栅绝缘层， 所述栅极在对 应所述 TFT的沟道的区域处与所述栅绝缘层接触。
12、根据权利要求 11所述的阵列基板制造方法， 其中， 所述在村底基板 的表面上形成 TFT的栅极包括：
在所述衬底基板的表面上形成第二绝缘层， 所述第二绝缘层对应所述 TFT的沟道区域； 以及
在形成有所述第二绝缘层的基板上形成所述 TFT的栅极。
13、 根据权利要求 11或 12所述的阵列基板制造方法， 其中所述在形成 有所述栅极的基板上形成第一绝缘层包括：
在所述 TFT的栅极的表面沉积所述第一绝缘层；
采用灰化工艺处理所述第一绝缘层，以至少暴露出所述 TFT的栅极的与 TFT沟道相对应的表面。
14、 根据权利要求 11-13任一所述的阵列基板制造方法， 还包括:
在所述栅绝缘层对应所述 TFT的栅极的表面上形成半导体有源层； 在所述半导体有源层的表面上形成具有过孔的刻蚀阻挡层；
在所述刻蚀阻挡层的表面上形成所述 TFT的源极和漏极， 所述 TFT的 源极和漏极分别通过过孔与所述半导体有源层相接触；
在形成有所述 TFT的源极和漏极的基板的表面上形成第一透明电极，所 述第一透明电极与所述 TFT的漏极相接触； 在所述第一透明电极的表面上形成钝化层， 所述钝化层覆盖所述 TFT; 以及
在所述钝化层的表面通过构图工艺处理形成第二透明电极。
15、根据权利要求 14所述的阵列基板制造方法，其中所述第一透明电极 为像素电极， 所述第二透明电极为公共电极； 且所述第一透明电极为板状结 构， 所述第二透明电极为条状电极。
16、根据权利要求 12所述的阵列基板制造方法，其中所述第一绝缘层和 所述笫二绝缘层均采用有机树脂材料制成。
17、 根据权利要求 11-16任一所述的阵列基板制造方法， 其中所述第一 绝缘层同时对应所述 TFT的源极和所述 TFT的漏极。
18、 根据权利要求 17所述的阵列基板制造方法， 其中， 所述 TFT的源 极和所述 TFT的漏极分別对应的所述第一绝缘层的两个部分的厚度相等，该 厚度为 1 μ πι-3 μ ηΐο
19、 根据权利要求 11-18任一所述的阵列基板制造方法， 其中所述半导 体有源层采用呈半导体特性的透明金属氧化物材料制成。
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