CN103730475A - 一种阵列基板及其制造方法、显示装置 - Google Patents

一种阵列基板及其制造方法、显示装置 Download PDF

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CN103730475A
CN103730475A CN201310739761.4A CN201310739761A CN103730475A CN 103730475 A CN103730475 A CN 103730475A CN 201310739761 A CN201310739761 A CN 201310739761A CN 103730475 A CN103730475 A CN 103730475A
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tft
pattern
insulating barrier
electrode
grid
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CN103730475B (zh
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金熙哲
宋泳锡
刘圣烈
崔承镇
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to EP14856805.8A priority patent/EP3089213B1/en
Priority to PCT/CN2014/078848 priority patent/WO2015096392A1/zh
Priority to US14/429,501 priority patent/US10403651B2/en
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    • H01L2924/13069—Thin film transistor [TFT]

Abstract

本发明实施例提供一种阵列基板及其制造方法、显示装置，涉及显示技术领域。包括依次形成在透明基板表面的TFT的栅极以及栅绝缘层，在所述栅绝缘层对应所述TFT的栅极区域的表面依次形成有半导体有源层的图案、刻蚀阻挡层的图案以及所述TFT的源极和漏极，所述TFT的源极和漏极分别通过过孔与所述半导体有源层的图案相接触；以及形成在所述TFT的栅极和所述栅绝缘层之间的第一绝缘层的图案，所述第一绝缘层的图案对应所述TFT的源极区域和/或所述TFT的漏极区域；在对应所述TFT的沟道区域，所述栅极与所述栅绝缘层接触。这样一种阵列基板可以降低TFT的源、漏电极与栅极之间的寄生电容，提高显示装置的质量。

Description

一种阵列基板及其制造方法、显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制造方法、显示装置。
背景技术
随着TFT-LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器）显示技术的不断发展，各种新型半导体元件及其在显示装置中的应用技术也随之得到了飞跃性的进步。
在现有的显示面板TFT的制造过程当中，越来越多的厂商开始尝试采用氧化物TFT取代a-Si（非晶硅）TFT或LTPS（低温多晶硅）TFT，以期获得具有更高质量的显示产品。氧化物TFT（即Oxide TFT）背板技术，是与传统的a-Si TFT制程相近的一种背板技术，该技术将原本应用于a-Si TFT的硅半导体材料部分置换成氧化物半导体材料，如现在应用最为广泛的IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)材料，来形成TFT的半导体有源层。现有技术中一种典型的氧化物TFT的阵列基板结构如图1所示，包括依次形成在透明基板10表面的TFT的栅极11、栅绝缘层12以及由IGZO形成的氧化物半导体有源层13，半导体有源层13的表面通过构图工艺形成有具有过孔的刻蚀阻挡层14，过孔A、B分别贯穿刻蚀阻挡层14,以暴露出底部的半导体有源层13，TFT的源极151和漏极152分别通过过孔A、B与半导体有源层13导通。
采用氧化物TFT相对于a-Si TFT具有制备温度要求低，迁移率高等优势，该技术可应用于高频显示和高分辨率显示产品，且相对于LTPS TFT技术具有设备投资成本低、运营保障成本低等优点。但其不足之处在于，在如图1所示的氧化物TFT阵列基板中，TFT的源极151和漏极152分别与栅极11具有较长的一段交叠区域，这样一来，在通电的情况下，由于层级差异TFT的源极151与栅极11之间将产生寄生电容Cgs，同理TFT的漏极152与栅极11之间也将产生寄生电容Cgd，在栅线11通过电压控制TFT开关的瞬间，由于寄生电容的存在，TFT关闭时栅线11上的电压信号由高到低的变化会使得漏极152相应输出跳变电压，从而引起像素中液晶电压的突然降低，这将严重影响像素电极电压的准确性，使得显示画面闪烁。
发明内容
本发明的实施例提供一种阵列基板及其制造方法、显示装置，可以降低TFT的源、漏电极与栅极之间的寄生电容，提高显示装置的质量。
本发明实施例的一方面，提供一种阵列基板，包括：依次形成在透明基板表面的TFT的栅极以及栅绝缘层，在所述栅绝缘层对应所述TFT的栅极区域的表面依次形成有半导体有源层的图案、刻蚀阻挡层的图案以及所述TFT的源极和漏极，所述TFT的源极和漏极分别通过过孔与所述半导体有源层的图案相接触；其中，还包括：
形成在所述TFT的栅极和所述栅绝缘层之间的第一绝缘层的图案，所述第一绝缘层的图案对应所述TFT的源极区域和/或所述TFT的漏极区域。
在对应所述TFT的沟道区域，所述栅极与所述栅绝缘层接触。
另一方面，本发明实施例还提供一种显示装置，所述显示装置可以包括如上所述的阵列基板。
此外，本发明实施例还提供了一种阵列基板制造方法，所述方法具体包括：
在透明基板的表面形成TFT的栅极；
在形成有所述栅极的基板上形成第一绝缘层的图案，所述第一绝缘层的图案对应所述TFT的源极区域和/或所述TFT的漏极区域；
在形成有所述第一绝缘层的图案的基板的表面形成栅绝缘层，在对应所述TFT的沟道区域，所述栅极与所述栅绝缘层接触。
本发明实施例提供的这样一种阵列基板及其制造方法、显示装置，通过在TFT的栅极和栅绝缘层之间，对应TFT的源极区域和/或TFT的漏极区域形成具有一定厚度的第一绝缘层。这样一来，可以显著增加TFT的栅极与源漏极之间的间距，这样由于平行板电容两电极之间的间距增大，使得电容值明显降低，从而可以有效降低TFT的源极与栅极之间存在的寄生电容Cgs或降低TFT的漏极与栅极之间存在的寄生电容Cgd，进而避免由于寄生电容过大而产生的输出跳变电压不良，有效改善显示画面闪烁，提高显示装置的质量。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中一种阵列基板的结构示意图；
图2为本发明实施例提供的一种阵列基板的结构示意图；
图3为本发明实施例提供的一种阵列基板制造方法的流程示意图；
图4为本发明实施例提供的另一阵列基板制造方法的流程示意图；
图5为形成第二绝缘层的图案后的基板结构示意图；
图6为形成TFT的栅极后的基板结构示意图；
图7为形成第一绝缘层的结构示意图；
图8为形成第一绝缘层的图案后的基板结构示意图；
图9为形成栅绝缘层后的基板结构示意图；
图10为形成半导体有源层后的基板结构示意图；
图11为形成刻蚀阻挡层后的基板结构示意图；
图12为形成TFT的源极和漏极后的基板结构示意图；
图13为形成第一透明电极后的基板结构示意图；
图14为形成钝化层后的基板结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供的阵列基板，如图2所示，包括：依次形成在透明基板20表面的TFT的栅极21以及栅绝缘层22，在栅绝缘层22对应所述TFT的栅极21区域的表面依次形成有半导体有源层的图案23、刻蚀阻挡层的图案24以及所述TFT的源极251和漏极252，所述TFT的源极251和漏极252分别通过过孔（图2中虚线框所示）与半导体有源层的图案23相接触。进一步地，还包括：
形成在TFT的栅极21和栅绝缘层22之间的第一绝缘层的图案26，该第一绝缘层的图案26对应该TFT的源极251区域和/或该TFT的漏极252区域。
此外，在对应TFT的沟道区域，栅极21与栅绝缘层22接触。由于对应TFT沟道区域处需要保证栅极材料与半导体有源层之间具有一个较小的距离，因此无需设置绝缘层的图案。
这样一种结构的阵列基板与现有技术中采用氧化物TFT的阵列基板相比，可以明显的看出图2所示的阵列基板中TFT的源漏极与栅极之间的间距远远大于图1中TFT的源漏极与栅极之间的间距。
本发明实施例提供的这样一种阵列基板，通过在TFT的栅极和栅绝缘层之间，对应TFT的源极区域和/或TFT的漏极区域形成具有一定厚度的第一绝缘层。这样一来，可以显著增加TFT的栅极与源漏极之间的间距，这样由于平行板电容两电极之间的间距增大，使得电容值明显降低，从而可以有效降低TFT的源极与栅极之间存在的寄生电容Cgs或降低TFT的漏极与栅极之间存在的寄生电容Cgd，进而避免由于寄生电容过大而产生的输出跳变电压不良，有效改善显示画面闪烁，提高显示装置的质量。
需要说明的是，第一绝缘层的图案26覆盖区域可以与TFT的源极区域或TFT的漏极区域中的至少一个区域相对应，在如图2所示的阵列基板中，是以第一绝缘层的图案26覆盖区域同时对应TFT的源极区域和TFT的漏极区域为例进行的说明。当采用这样一种如图2所示的阵列基板时，可以显著增加TFT的栅极与源漏极之间的间距，从而可以有效降低TFT的源极与栅极之间存在的寄生电容Cgs以及降低TFT的漏极与栅极之间存在的寄生电容Cgd。可以想到，当第一绝缘层的图案26覆盖区域仅对应TFT的源极区域时，由于TFT的栅极和源极之间作为平行板电容器的电极间距增大，从而可以有效降低源极与栅极之间寄生电容Cgs的影响，同理，当第一绝缘层的图案26覆盖区域仅对应TFT的漏极区域时，可以有效降低漏极与栅极之间寄生电容Cgd的影响。
当第一绝缘层的图案26同时对应该TFT的源极251区域和TFT的漏极252区域时，该TFT的源极251区域和TFT的漏极252区域分别对应的第一绝缘层的图案26的厚度可以相等。
如图2所示，在本发明实施例中，第一绝缘层的图案26的厚度D’可以为1μm－3μm。这样一种厚度的第一绝缘层的图案26的设计在降低电极之间电容值的同时可以通过现有的构图工艺轻松制作实现，从而有效降低了产品的生产难度。
根据平行板电容公式C=εS/d可知，为了减小平行电极之间的电容值，当其他条件不变时，可以通过增大两电极之间的间距实现电容的减小。这样一来，与现有技术中两电极之间的间距相比，两电极之间的电容值减小，从而能够有效降低寄生电容所产生的跳变电压的影响。
进一步地，如图2所示，该阵列基板还可以包括：
形成在透明基板20和TFT的栅极21之间的第二绝缘层的图案27，该第二绝缘层的图案27对应TFT的沟道区域（图2中A区域）。
其中，第二绝缘层的图案27与TFT的栅极21的厚度之和D大于等于第一绝缘层的图案26的厚度D’。进一步地，第一绝缘层的图案26和第二绝缘层的图案27均可以采用具有良好绝缘性的有机树脂材料等材料制成，本发明对此并不做限制。
这样一来，通过在TFT的沟道区域制作第二绝缘层的图案27，可以抬高位于该区域的TFT的栅极21，以使得栅极21的上表面与第一绝缘层的图案26的上表面之间没有明显的段差。进一步地，通过控制第一绝缘层以及第二绝缘层的厚度，以使得二绝缘层的图案27与TFT的栅极21的厚度之和D大于等于第一绝缘层的图案26的厚度D’，从而可以保证至少露出栅极21的表面，以确保形成TFT的沟道区域。
需要说明的是，本发明实施例提供的TFT-LCD阵列基板可以适用于FFS（Fringe Field Switching，边缘场开关）型、AD-SDS（Advanced-Super Dimensional Switching，简称为ADS，高级超维场开关）型、IPS（In Plane Switch，横向电场效应）型、TN（Twist Nematic，扭曲向列）型等类型的液晶显示装置的生产。其中，ADS技术是通过同一平面内像素电极边缘所产生的平行电场以及像素电极层与公共电极层间产生的纵向电场形成多维电场，使液晶盒内像素电极间、电极正上方所有取向液晶分子都能够产生旋转转换，从而提高了平面取向系液晶工作效率并增大了透光效率。
无论上述哪种液晶显示装置都包括对盒成形的彩膜基板和阵列基板。不同的是，TN型显示装置的公共电极设置在彩膜基板上，像素电极设置在阵列基板上；FFS型显示装置、ADS型显示装置以及IPS型显示装置的公共电极和像素电极均设置在阵列基板上。
具体的，如图2所示，在本发明实施例中是以FFS型显示装置为例进行的说明。其中，阵列基板还可以包括：
形成在刻蚀阻挡层的图案24表面的第一透明电极281，该第一透明电极281与TFT的漏极252相接触。
形成在第一透明电极281表面的钝化层的图案29，该钝化层的图案29覆盖TFT区域。
以及形成在该钝化层表面的第二透明电极282。
其中，第一透明电极281可以为像素电极，第二透明电极282可以为公共电极，且该第一透明电极281可以为面状结构，第二透明电极282可以为间隔排列的条状结构。
在所述FFS型显示装置的阵列基板中，所述公共电极和所述像素电极异层设置，可选的，位于上层的电极包含多个条形电极，位于下层的电极可以包含多个条形电极或为平板形。在本发明实施例中，是以位于下层的电极为平板形的面状结构为例进行的说明。其中，异层设置是针对至少两种图案而言的，至少两种图案异层设置是指，分别将至少两层薄膜通过构图工艺形成至少两种图案。对于两种图案异层设置是指，通过构图工艺，由两层薄膜各形成一种图案。例如，公共电极和像素电极异层设置是指：由第一层透明导电薄膜通过构图工艺形成下层电极，由第二层透明导电薄膜通过构图工艺形成上层电极，其中，下层电极为公共电极（或像素电极），上层电极为像素电极（或公共电极）。
本发明实施例提供的这样一种结构的阵列基板同样可以适用于IPS型显示装置，与FFS型显示装置不同的是，所述公共电极和所述像素电极同层设置，所述公共电极包含多个第一条形电极，所述像素电极包含多个第二条形电极，所述第一条形电极和所述第二条形电极间隔设置。其中，同层设置是针对至少两种图案而言的；至少两种图案同层设置是指：将同一薄膜通过构图工艺形成至少两种图案。例如，公共电极和像素电极同层设置是指：由同一透明导电薄膜通过构图工艺形成像素电极和公共电极。其中，像素电极是指通过开关单元（例如，可以是薄膜晶体管）与数据线电连接的电极，公共电极是指和公共电极线电连接的电极。
需要说明的是，在本发明实施例中，半导体有源层的图案23可以采用呈半导体特性的透明金属氧化物材料制成。例如，金属氧化物薄膜可以包括：IGZO（铟镓锌氧化物）、IGO（铟镓氧化物）、ITZO（铟锡锌氧化物）、AlZnO（铝锌氧化物）中的至少一种。采用这样一种透明金属氧化物材料取代a-Si（非晶硅）或LTPS（低温多晶硅）来形成TFT的半导体有源层，相对于a-Si TFT或LTPS TFT具有制备温度要求低，迁移率高等优势，该技术可应用于高频显示和高分辨率显示产品，且相对于LTPS TFT技术具有设备投资成本低、运营保障成本低等优点。
本发明实施例提供的显示装置，包括如上所述的阵列基板。
该阵列基板具体包括形成在TFT的栅极和所述栅绝缘层之间的第一绝缘层的图案，该第一绝缘层的图案对应TFT的源极区域和/或TFT的漏极区域。其中，在对应TFT的沟道区域，该TFT的栅极与栅绝缘层接触。
需要说明的是本发明所提供的显示装置可以为：液晶面板、电子纸、OLED面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
本发明实施例提供的这样一种显示装置，包括阵列基板，该阵列基板通过在TFT的栅极和栅绝缘层之间，对应TFT的源极区域和/或TFT的漏极区域形成具有一定厚度的第一绝缘层。这样一来，可以显著增加TFT的栅极与源漏极之间的间距，这样由于平行板电容两电极之间的间距增大，使得电容值明显降低，从而可以有效降低TFT的源极与栅极之间存在的寄生电容Cgs或降低TFT的漏极与栅极之间存在的寄生电容Cgd，进而避免由于寄生电容过大而产生的输出跳变电压不良，有效改善显示画面闪烁，提高显示装置的质量。
本发明实施例还提供一种阵列基板制造方法，该方法如图3所示，包括：
S301、在透明基板的表面形成TFT的栅极。
S302、在形成有栅极的基板上形成第一绝缘层的图案，该第一绝缘层的图案对应TFT的源极区域和/或TFT的漏极区域。
需要说明的是，第一绝缘层的图案覆盖区域可以与TFT的源极区域或TFT的漏极区域中的至少一个区域相对应，在如图2所示的阵列基板中，是以第一绝缘层的图案26覆盖区域同时对应TFT的源极区域和TFT的漏极区域为例进行的说明。当采用这样一种如图2所示的阵列基板时，可以显著增加TFT的栅极与源漏极之间的间距，从而可以有效降低TFT的源极与栅极之间存在的寄生电容Cgs以及降低TFT的漏极与栅极之间存在的寄生电容Cgd。可以想到，当第一绝缘层的图案26覆盖区域仅对应TFT的源极区域时，由于TFT的栅极和源极之间作为平行板电容器的电极间距增大，从而可以有效降低源极与栅极之间寄生电容Cgs的影响，同理，当第一绝缘层的图案26覆盖区域仅对应TFT的漏极区域时，可以有效降低漏极与栅极之间寄生电容Cgd的影响。
当第一绝缘层的图案同时对应该TFT的源极区域和TFT的漏极区域时，该TFT的源极区域和TFT的漏极区域分别对应的第一绝缘层的图案的厚度可以相等。
如图2所示，在本发明实施例中，第一绝缘层的图案26的厚度D’可以为1μm－3μm。这样一种厚度的第一绝缘层的图案26的设计在降低电极之间电容值的同时可以通过现有的构图工艺轻松制作实现，从而有效降低了产品的生产难度。
根据平行板电容公式C=εS/d可知，为了减小平行电极之间的电容值，当其他条件不变时，可以通过增大两电极之间的间距实现电容的减小。这样一来，与现有技术中两电极之间的间距相比，两电极之间的电容值减小，从而能够有效降低寄生电容所产生的跳变电压的影响。
S303、在形成有第一绝缘层的图案的基板的表面形成栅绝缘层，在对应TFT的沟道区域，栅极与栅绝缘层接触。
由于对应TFT沟道区域处需要保证栅极材料与半导体有源层之间具有一个较小的距离，因此无需设置绝缘层的图案。
本发明实施例提供的这样一种阵列基板制造方法，该阵列基板通过在TFT的栅极和栅绝缘层之间，对应TFT的源极区域和/或TFT的漏极区域形成具有一定厚度的第一绝缘层。这样一来，可以显著增加TFT的栅极与源漏极之间的间距，这样由于平行板电容两电极之间的间距增大，使得电容值明显降低，从而可以有效降低TFT的源极与栅极之间存在的寄生电容Cgs或降低TFT的漏极与栅极之间存在的寄生电容Cgd，进而避免由于寄生电容过大而产生的输出跳变电压不良，有效改善显示画面闪烁，提高显示装置的质量。
进一步地，本发明实施例提供的阵列基板制造方法，如图4所示，具体包括：
S401、在透明基板的表面通过构图工艺形成第二绝缘层的图案，该第二绝缘层的图案对应TFT的沟道区域。
在阵列基板的实际生产过程当中，透明基板具体可以是采用玻璃或透明树脂等具有一定坚固性的透明材料制成。在透明基板上需要采用一次构图工艺以形成第二绝缘层的图案。
例如，可以首先在透明基板的表面涂覆一层具有一定厚度的有机树脂材料，形成第二绝缘层。通过具有特定图案的掩膜进行曝光显影最终形成如图5所示的第二绝缘层的图案27。
S402、在形成有第二绝缘层的图案的基板上通过构图工艺形成TFT的栅极。
例如，在形成有第二绝缘层的图案的基板上可以采用等离子增强化学气相沉积（PECVD）、磁控溅射、热蒸发或其它成膜方法，形成金属层。其中，该金属层可以是钼、铝、铝铷合金、钨、铬、铜等金属形成的单层薄膜，也可以是以上金属多层形成的多层薄膜。在该金属层的表面形成有光刻胶，通过具有特定图案的掩膜板进行曝光显影以使光刻胶产生图案，剥离掉未覆盖光刻胶处的金属层，最终在第二绝缘层的图案的表面形成TFT的栅极21，其结构可以如图6所示。
S403、在TFT的栅极的表面沉积形成第一绝缘层。
例如，可以在形成有TFT的栅极的基板的表面涂覆一层具有一定厚度的有机树脂材料，如图7所示，以形成第一绝缘层260。该第一绝缘层260将完全覆盖TFT的栅极。
S404、采用灰化工艺处理第一绝缘层，以至少暴露出TFT的栅极的表面，形成第一绝缘层的图案。
如图8所示，该第一绝缘层260通过灰化工艺的处理，其厚度将整体降低，直至暴露出TFT的栅极的表面为止，最终形成图案化的第一绝缘层的图案26。在本发明实施例中是以采用灰化工艺为例进行的说明，应当理解，为了暴露出TFT的栅极的表面，还可以采用其他各种已知的构图工艺，本发明对此并不作限制。
其中，第二绝缘层的图案27与TFT的栅极21的厚度之和D大于等于第一绝缘层的图案26的厚度D’。进一步地，第一绝缘层的图案26和第二绝缘层的图案27均可以采用具有良好绝缘性的有机树脂材料等材料制成，本发明对此并不做限制。
这样一来，通过在TFT的沟道区域制作第二绝缘层的图案27，可以抬高位于该区域的TFT的栅极21，以使得栅极21的上表面与第一绝缘层的图案26的上表面之间没有明显的段差。进一步地，通过控制第一绝缘层以及第二绝缘层的厚度，以使得二绝缘层的图案27与TFT的栅极21的厚度之和D大于等于第一绝缘层的图案26的厚度D’，从而可以保证至少露出栅极21的表面，以确保形成TFT的沟道区域。
S405、在形成有第一绝缘层的图案的基板的表面形成栅绝缘层，在对应TFT的沟道区域，栅极与栅绝缘层接触。
如图9所示，可见，在形成有第一绝缘层的图案26的基板的表面上形成有厚度均一的栅绝缘层22。
S406、在栅绝缘层对应TFT的栅极区域的表面通过构图工艺处理形成半导体有源层的图案。
例如，可以在形成有上述结构的基板表面形成具有半导体特性的半导体有源层，通过掩膜曝光形成如图10所示的半导体有源层的图案23。
需要说明的是，在本发明实施例中，半导体有源层的图案23可以采用呈半导体特性的透明金属氧化物材料制成。例如，金属氧化物薄膜可以包括：IGZO、IGO、ITZO、AlZnO中的至少一种。采用这样一种透明金属氧化物材料取代a-Si（非晶硅）或LTPS（低温多晶硅）来形成TFT的半导体有源层，相对于a-Si TFT或LTPS TFT具有制备温度要求低，迁移率高等优势，该技术可应用于高频显示和高分辨率显示产品，且相对于LTPS TFT技术具有设备投资成本低、运营保障成本低等优点。
S407、在半导体有源层的图案的表面通过构图工艺处理形成具有过孔的刻蚀阻挡层的图案。
刻蚀阻挡层的图案24可以如图11所示，具体的，可以通过在形成有上述结构的基板上涂覆或沉积刻蚀阻挡层，通过具有特定图案的掩膜曝光最终在对应TFT的源极和漏极的位置分别形成过孔（图11中虚线区域），过孔的底部为半导体有源层的图案23，从而得到刻蚀阻挡层的图案24。
S408、在刻蚀阻挡层的图案的表面通过构图工艺处理形成TFT的源极和漏极，该TFT的源极和漏极分别通过过孔与半导体有源层的图案相接触。
形成有TFT的源极251和漏极252的基板结构可以如图12所示。
S409、在形成有TFT的源极和漏极的基板的表面通过构图工艺处理形成第一透明电极，该第一透明电极与TFT的漏极相接触。
形成有第一透明电极281的基板结构可以如图13所示。
S410、在第一透明电极的表面通过构图工艺处理形成钝化层的图案，该钝化层的图案覆盖TFT区域。
形成有钝化层的图案29的基板结构可以如图14所示。
S411、在钝化层的表面通过构图工艺处理形成第二透明电极。从而最终形成如图2所示的阵列基板。
需要说明的是，在本发明实施例中是以FFS型显示装置为例进行的说明。其中，第一透明电极281可以为像素电极，第二透明电极282可以为公共电极，且该第一透明电极281可以为面状结构，第二透明电极282可以为间隔排列的条状结构。
在所述FFS型显示装置的阵列基板中，所述公共电极和所述像素电极异层设置，可选的，位于上层的电极包含多个条形电极，位于下层的电极可以包含多个条形电极或为平板形。在本发明实施例中，是以位于下层的电极为平板形的面状结构为例进行的说明。其中，异层设置是针对至少两种图案而言的，至少两种图案异层设置是指，分别将至少两层薄膜通过构图工艺形成至少两种图案。对于两种图案异层设置是指，通过构图工艺，由两层薄膜各形成一种图案。例如，公共电极和像素电极异层设置是指：由第一层透明导电薄膜通过构图工艺形成下层电极，由第二层透明导电薄膜通过构图工艺形成上层电极，其中，下层电极为公共电极（或像素电极），上层电极为像素电极（或公共电极）。
本发明实施例提供的这样一种结构的阵列基板同样可以适用于ADS型显示装置、IPS型显示装置或TN型显示装置等各种显示装置阵列基板的生产。可以想到，当像素电极或公共电极的位置或形状结构发生变化时，通过改变上述工序中的相关步骤，同样可以实现各种结构阵列基板的生产，本发明实施例中对此并不一一列举。
采用上述阵列基板制造方法，可以显著增加TFT的栅极与源漏极之间的间距，这样由于平行板电容两电极之间的间距增大，使得电容值明显降低，从而可以有效降低TFT的源极与栅极之间存在的寄生电容Cgs或降低TFT的漏极与栅极之间存在的寄生电容Cgd，进而避免由于寄生电容过大而产生的输出跳变电压不良，有效改善显示画面闪烁，提高显示装置的质量。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (16)

1.一种阵列基板，包括：依次形成在透明基板表面的TFT的栅极以及栅绝缘层，在所述栅绝缘层对应所述TFT的栅极区域的表面依次形成有半导体有源层的图案、刻蚀阻挡层的图案以及所述TFT的源极和漏极，所述TFT的源极和漏极分别通过过孔与所述半导体有源层的图案相接触；其特征在于，还包括：
形成在所述TFT的栅极和所述栅绝缘层之间的第一绝缘层的图案，所述第一绝缘层的图案对应所述TFT的源极区域和/或所述TFT的漏极区域；
在对应所述TFT的沟道区域，所述栅极与所述栅绝缘层接触。
2.根据权利要求1所述的阵列基板，其特征在于，所述阵列基板还包括：
形成在所述透明基板和所述TFT的栅极之间的第二绝缘层的图案，所述第二绝缘层的图案对应所述TFT的沟道区域；
所述第二绝缘层的图案与所述TFT的栅极的厚度之和大于等于所述第一绝缘层的图案的厚度。
3.根据权利要求1所述的阵列基板，其特征在于，所述阵列基板还包括：
形成在所述刻蚀阻挡层的图案表面的第一透明电极，所述第一透明电极与所述TFT的漏极相接触；
形成在所述第一透明电极表面的钝化层的图案，所述钝化层的图案覆盖所述TFT区域；
形成在所述钝化层表面的第二透明电极。
4.根据权利要求3所述的阵列基板，其特征在于，所述第一透明电极为像素电极，所述第二透明电极为公共电极；
且所述第一透明电极为面状结构，所述第二透明电极为间隔排列的条状结构。
5.根据权利要求2所述的阵列基板，其特征在于，所述第一绝缘层的图案和所述第二绝缘层的图案均采用有机树脂材料制成。
6.根据权利要求1-5任一所述的阵列基板，其特征在于，当所述第一绝缘层的图案同时对应所述TFT的源极区域和所述TFT的漏极区域时，所述TFT的源极区域和所述TFT的漏极区域分别对应的所述第一绝缘层的图案的厚度相等；
所述第一绝缘层的图案的厚度为1μm－3μm。
7.根据权利要求1-5任一所述的阵列基板，其特征在于，所述半导体有源层的图案采用呈半导体特性的透明金属氧化物材料制成。
8.一种显示装置，其特征在于，所述显示装置包括如权利要求1-7任一所述的阵列基板。
9.一种阵列基板制造方法，其特征在于，包括：
在透明基板的表面形成TFT的栅极；
在形成有所述栅极的基板上形成第一绝缘层的图案，所述第一绝缘层的图案对应所述TFT的源极区域和/或所述TFT的漏极区域；
在形成有所述第一绝缘层的图案的基板的表面形成栅绝缘层，在对应所述TFT的沟道区域，所述栅极与所述栅绝缘层接触。
10.根据权利要求9所述的阵列基板制造方法，其特征在于，所述在透明基板的表面形成TFT的栅极包括：
在所述透明基板的表面通过构图工艺形成第二绝缘层的图案，所述第二绝缘层的图案对应所述TFT的沟道区域；
在形成有所述第二绝缘层的图案的基板上通过构图工艺形成所述TFT的栅极。
11.根据权利要求10所述的阵列基板制造方法，其特征在于，所述在形成有所述栅极的基板上形成第一绝缘层的图案包括：
在所述TFT的栅极的表面沉积形成所述第一绝缘层；
采用灰化工艺处理所述第一绝缘层，以至少暴露出所述TFT的栅极的表面，形成第一绝缘层的图案。
12.根据权利要求11所述的阵列基板制造方法，其特征在于，所述方法还包括：
在所述栅绝缘层对应所述TFT的栅极区域的表面通过构图工艺处理形成半导体有源层的图案；
在所述半导体有源层的图案的表面通过构图工艺处理形成具有过孔的刻蚀阻挡层的图案；
在所述刻蚀阻挡层的图案的表面通过构图工艺处理形成所述TFT的源极和漏极，所述TFT的源极和漏极分别通过过孔与所述半导体有源层的图案相接触；
在形成有所述TFT的源极和漏极的基板的表面通过构图工艺处理形成第一透明电极，所述第一透明电极与所述TFT的漏极相接触；
在所述第一透明电极的表面通过构图工艺处理形成钝化层的图案，所述钝化层的图案覆盖所述TFT区域；
在所述钝化层的表面通过构图工艺处理形成第二透明电极。
13.根据权利要求12所述的阵列基板制造方法，其特征在于，所述第一透明电极为像素电极，所述第二透明电极为公共电极；
且所述第一透明电极为面状结构，所述第二透明电极为间隔排列的条状结构。
14.根据权利要求10所述的阵列基板制造方法，其特征在于，所述第一绝缘层和所述第二绝缘层均采用有机树脂材料制成。
15.根据权利要求9-14任一所述的阵列基板制造方法，其特征在于，当所述第一绝缘层的图案同时对应所述TFT的源极区域和所述TFT的漏极区域时，所述TFT的源极区域和所述TFT的漏极区域分别对应的所述第一绝缘层的图案的厚度相等；
所述第一绝缘层的图案的厚度为1μm－3μm。
16.根据权利要求9-14任一所述的阵列基板制造方法，其特征在于，所述半导体有源层的图案采用呈半导体特性的透明金属氧化物材料制成。
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