WO2015096309A1 - 薄膜晶体管及其制造方法、阵列基板、显示装置 - Google Patents

薄膜晶体管及其制造方法、阵列基板、显示装置 Download PDF

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Publication number
WO2015096309A1
WO2015096309A1 PCT/CN2014/075670 CN2014075670W WO2015096309A1 WO 2015096309 A1 WO2015096309 A1 WO 2015096309A1 CN 2014075670 W CN2014075670 W CN 2014075670W WO 2015096309 A1 WO2015096309 A1 WO 2015096309A1
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Prior art keywords
film transistor
active layer
thin film
layer
gate
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PCT/CN2014/075670
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English (en)
French (fr)
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崔承镇
金熙哲
宋泳锡
刘圣烈
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京东方科技集团股份有限公司
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Priority to US14/406,667 priority Critical patent/US9502576B2/en
Publication of WO2015096309A1 publication Critical patent/WO2015096309A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support

Definitions

  • Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, an array substrate, and a display device. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the thin film transistor generally includes a gate electrode, an active layer, a source and a drain, and a gate insulating layer is spaced apart from the active layer.
  • a driving signal is input to the gate, the drain can be turned on to the source through the active layer.
  • an oxide (Oxide) semiconductor material is used as an active layer.
  • an etch stop layer (ESL) is usually overlaid on the active layer to protect the active layer, and via holes, source and drain are formed on the etch stop layer. Connected to the active layer through vias.
  • the present inventors have found in the process of implementing the present invention that the prior art has at least the following problems:
  • the gate and the source In the scheme of using an oxide semiconductor material as an active layer, in particular, after etching the barrier layer, the gate and the source The overlap area between the gate and the drain is large, which results in a capacitance Cgs formed between the gate and the source, and a capacitance Cgd formed between the gate and the drain is large, which affects the conductivity of the thin film transistor.
  • Embodiments of the present invention provide a thin film transistor and a method of fabricating the same, the array substrate provided with the thin film transistor, and a display device provided with the array substrate, which solves the technology of large Cgs and Cgd in the existing thin film transistor problem.
  • the present invention provides a thin film transistor including a gate, an active layer, a source and a drain, and the thin film transistor is formed on a base substrate, the gate including a first portion, a second portion, and a third portion
  • the first portion and the third portion are respectively located at two sides of the second portion, the first portion corresponds to a position of the source, and the third portion is opposite to a position of the drain Corresponding;
  • two recesses are formed on the base substrate, and the first portion and the third portion are respectively located in the two recesses;
  • the first portion and the third portion are covered with a filling layer
  • the filling layer and the second portion are covered with a gate insulating layer
  • the active layer is disposed on the gate insulating layer
  • the source and the drain are located above the active layer and are both connected to the active layer.
  • the depression has a thickness of 0.3 to 1.0 ⁇ m, for example, 0.5 ⁇ m.
  • the material of the active layer is an oxide semiconductor.
  • the active layer is covered with an etch barrier layer, the etch stop layer is provided with a via hole, and the source and the drain pass through the via hole and the active layer Connected.
  • the material of the filling layer is a transparent resin, in particular a polyacrylamide resin.
  • the active layer includes a channel region at an intermediate portion and source and drain regions at both sides of the channel region, the source region, the channel region, and the The drain regions are opposite the first portion, the second portion, and the third portion of the gate, respectively.
  • the source and the drain are respectively connected to a source region and a drain region of the active layer.
  • the present invention also provides a method of manufacturing the above thin film transistor, comprising:
  • the gate including a first portion, a second portion, and a third portion, the first portion and the third portion being respectively located in the second portion On both sides, the first portion and the third portion are respectively located in the two recesses;
  • a pattern of a source and a drain is formed by a patterning process, the source is corresponding to a position of the first portion, and the drain corresponds to a position of the third portion.
  • the material of the active layer is an oxide semiconductor.
  • the method further includes: forming a pattern of the etch barrier layer by a patterning process, wherein the etch barrier layer is provided with a via hole; the source formed subsequently A pole and the drain are connected to the active layer through the via.
  • the present invention also provides an array substrate, wherein the array substrate is provided with a plurality of the above thin film transistors arranged in an array.
  • the present invention also provides a display device comprising the above array substrate.
  • the above technical solution provided by the present invention has the following advantages: forming two recesses on the base substrate such that the first portion of the gate corresponding to the source and the third portion corresponding to the drain are located in the recess, and The filling layer is added above the first part and the third part, so the spacing between the first part and the source is increased, and the spacing between the third part and the drain is increased, thereby reducing the size of Cgs and Cgd, and improving Conductive properties of thin film transistors.
  • FIG. 1 is a schematic view of a thin film transistor according to an embodiment of the present invention.
  • FIG. 2a to 2h are schematic views showing a manufacturing process of a thin film transistor according to an embodiment of the present invention.
  • FIG. 3 is a schematic view of an array substrate according to an embodiment of the present invention. detailed description
  • a thin film transistor provided by an embodiment of the present invention includes a gate 1, an active layer 2, a source 31, and a drain 32, and the thin film transistor is formed on a base substrate 4.
  • the gate 1 includes a first portion 11, a second portion 12 and a third portion 13, respectively, the first portion 11 and the third portion 13 are respectively located on both sides of the second portion 12, and the first portion 11 corresponds to the position of the source 31, and the third portion Part 13 with The position of the drain 32 corresponds.
  • the first portion 11 is at least partially opposite the source 31, and the third portion 13 is at least partially opposite the drain 32.
  • Two recesses 40 are formed on the base substrate 4, and the first portion 11 and the third portion 13 are respectively located in the two recesses 40.
  • the depth of the recess 40 is, for example, 0.3 to 1.0 ⁇ m, preferably 0.5 ⁇ m.
  • the size of the recess 40 (e.g., the dimension parallel to the substrate direction in the cross-sectional view of Fig. 1) corresponds to the size of the source 31 and the drain 32.
  • the first portion 11 and the third portion 13 are covered with a filling layer 5, and the filling layer 5 and the second portion 12 are covered with a gate insulating layer 6.
  • the material of the filling layer 5 is, for example, a transparent resin, and in the present embodiment, a polyacrylamide resin is used.
  • the active layer 2 is disposed on the gate insulating layer 6, and the source 31 and the drain 32 are located above the active layer 2, and are both connected to the active layer 2.
  • the material of the active layer 2 is an oxide semiconductor. In other embodiments, the material of the active layer 2 may also be other kinds of semiconductors.
  • the active layer 2 is further covered with an etch barrier layer 7 for protecting the active layer 2 of the oxide semiconductor material.
  • a via 70 is formed in the etch stop layer 7, and the source 31 and the drain 32 are connected to the active layer 2 through the via 70.
  • two recesses 40 are formed on the base substrate 4, so that the first portion 11 of the gate 1 corresponding to the source 31 and the third portion 13 corresponding to the drain 32 are located.
  • the spacing between the first portion 11 and the source 31 is increased, and the spacing between the third portion 13 and the drain 32 is increased. , thereby reducing the size of Cgs and Cgd, and improving the conductivity of the thin film transistor.
  • the present invention also provides a method of manufacturing the above thin film transistor, comprising:
  • the base substrate 4 can usually be a glass substrate.
  • the base substrate 4 may be etched by a conventional method of etching glass.
  • the base substrate 4 may be etched by irradiating a laser.
  • the patterning process may be used. In the processes of exposure, development, etching, etc., two recesses 40 are formed on the base substrate 4.
  • a pattern of a gate electrode is formed on the base substrate by a patterning process.
  • the gate electrode 1 can be formed by a conventional patterning process through exposure, development, etching, and the like.
  • the formed gate 1 includes a first portion 11, a second portion 12 and a third portion 13, respectively, the first portion 11 and the third portion 13 are respectively located on both sides of the second portion 12, and the first portion 11 and the third portion 13 are respectively located at two In the depression 40.
  • S3 As shown in FIG. 2c, on the basis of completing the above steps, the filling layer 5 is covered on the gate 1.
  • the material of the filling layer 5 is, for example, a transparent resin, and a polyacrylamide resin is used in the present embodiment. In other embodiments, a material other than the resin may be used as the filling layer 5.
  • the thickness of the filled filling layer 5 may be generally between 0.5 and 3.0 ⁇ m, and the thickness of the filling layer 5 can be appropriately adjusted. After the filling layer 5 is over, the first part can be made
  • the height of the filling layer 5 above the second portion 12 and the third portion 13 is uniform.
  • the filling layer 5 located above the second portion 12 of the gate 1 is removed.
  • the entire filling layer 5 may be subjected to an ashing process to remove the filling layer 5 of the transparent resin material above the second portion 12, and after the filling layer 5 above the second portion 12 is removed, the second portion 12 may also be Forming a plane with the remaining filling layer 5, that is, the remaining filling layer
  • the surface of the surface 5 is flush with the surface of the second portion 12.
  • the gate insulating layer 6 forms a certain pattern in other regions of the base substrate 4, for example, a via hole is formed in the non-display area for transmitting the gate driving signal to the gate line, and thus in the drawings of the embodiments of the present invention None of the via holes on the gate insulating layer 6 are shown.
  • the material of the active layer 2 is an oxide semiconductor. In other embodiments, the material of the active layer 2 may also be other types of semiconductors.
  • the active layer 2 includes a channel region 22 at an intermediate portion and a source region 21 and a drain region 23 on both sides of the channel region 22, the source region 21, the channel region 22, and The drain region 23 is opposed to the first portion 11, the second portion 12, and the third portion 13 of the gate 1, respectively.
  • a pattern of the etch barrier layer 7 is formed by a patterning process, and a via hole 70 is formed in the etch barrier layer 7.
  • the patterns of the source 31 and the drain 32 are formed by a patterning process.
  • the source 31 corresponds to the position of the first portion 11 of the gate 1
  • the drain 32 corresponds to the position of the third portion 13 of the gate 1
  • the source 31 and the drain 32 are blocked by etching.
  • a via 70 on layer 7 is connected to active layer 2.
  • the source 31 and the drain 32 are connected to the source region 21 and the drain region 23 of the active layer 2, respectively.
  • the above steps S5 to S8 can all be performed by a conventional patterning process, and will not be described in detail herein. After the above steps are completed, the thin film transistor provided by the embodiment of the present invention can be fabricated.
  • the active layer in this embodiment is an oxide semiconductor material
  • the etch stop layer formed in step S7 is used to protect the active layer of the oxide semiconductor material.
  • step S7 may be omitted and step S8 may be directly performed.
  • the embodiment of the invention further provides an array substrate, wherein the array substrate is provided with a plurality of thin film transistors provided in an array arrangement.
  • the array substrate provided in this embodiment is an Advanced Super Dimension Switch (ADSDS) type array substrate.
  • ADSDS Advanced Super Dimension Switch
  • FIG. 3 in addition to the thin film transistor provided in the above embodiment, a pixel electrode 81 connected to the drain 32, a protective layer 9 covering the thin film transistor and the pixel electrode 81, and A common electrode 82 is formed on the protective layer 9.
  • TN type array substrate in addition to forming the thin film transistor, a drain electrode connected to the drain electrode may be formed, and a protective layer may be formed.
  • the embodiment of the invention further provides a display device, which comprises the array substrate provided by the above embodiments.
  • the display device may be any product or component having a display function such as a liquid crystal panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • the array substrate and the display device provided by the embodiments of the present invention have the same technical features as the thin film transistor provided by the above embodiments of the present invention, the same technical effects can be produced and the same technical problem can be solved.

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

　提供了一种薄膜晶体管及其制造方法、阵列基板、显示装置。该薄膜晶体管形成于衬底基板（4）上，包括栅极（1）、有源层（2）、源极（31）和漏极（32），栅极（1）包括第一部分（11）、第二部分（12）和第三部分（13），第一部分（11）和第三部分（13）分别与源极（31）与漏极（32）的位置相对应；衬底基板（4）上形成有两个凹陷（40），第一部分（11）和第三部分（13）分别位于两个凹陷（40）中；第一部分（11）和第三部分（13）上方覆盖有填充层（5）；填充层（5）和第二部分（12）上方依次覆盖有栅绝缘层（6）、有源层（2）、源极（31）和漏极（32）。解决了现有的薄膜晶体管中的Cgs和Cgd较大的技术问题。

Description

薄膜晶体管及其制造方法、 阵列基板、 显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管及其制造方法、 阵列基板、 显示装 置。 背景技术
随着显示技术的不断发展， 薄膜晶体管液晶显示器（Thin Film Transistor Liquid Crystal Display, TFT-LCD )由于具有体积小、功耗低、无辐射等优点， 在平板显示领域中占据了主导地位。
薄膜晶体管通常包括栅极、 有源层、 源极和漏极， 栅极与有源层之间隔 有栅绝缘层。 对栅极输入驱动信号时， 漏极就可以通过有源层与源极导通。 目前， 越来越多的薄膜晶体管中， 釆用氧化物（Oxide )半导体材料作为有源 层。 在这种情况下， 通常还会在有源层上覆盖刻蚀阻挡层（Etch Stop Layer, 简称 ESL ) ， 以保护有源层， 并且刻蚀阻挡层上形成有过孔， 源极和漏极通 过过孔与有源层相连。
本发明人在实现本发明的过程中发现， 现有技术至少存在以下问题： 釆 用氧化物半导体材料作为有源层的方案中， 特别是釆用了刻蚀阻挡层之后， 栅极与源极、 栅极与漏极之间的重叠面积较大， 导致栅极与源极之间形成的 电容 Cgs， 以及栅极与漏极之间形成的电容 Cgd较大， 影响了薄膜晶体管的 导电性能。 发明内容
本发明实施例提供了一种薄膜晶体管及其制造方法， 设有该薄膜晶体管 的阵列基板， 以及设有该阵列基板的显示装置， 解决了现有的薄膜晶体管中 的 Cgs和 Cgd较大的技术问题。
为达到上述目的， 本发明的实施例釆用如下技术方案：
本发明提供一种薄膜晶体管， 包括栅极、 有源层、 源极和漏极， 且所述 薄膜晶体管形成于衬底基板上， 所述栅极包括第一部分、 第二部分和第三部 分， 所述第一部分和所述第三部分分别位于所述第二部分的两侧， 所述第一 部分与所述源极的位置相对应， 所述第三部分与所述漏极的位置相对应； 所述衬底基板上形成有两个凹陷， 所述第一部分和所述第三部分分别位 于所述两个凹陷中；
所述第一部分和所述第三部分上方覆盖有填充层；
所述填充层和所述第二部分上方覆盖有栅绝缘层；
所述有源层设置于所述栅绝缘层上；
所述源极和所述漏极位于所述有源层上方， 且均与所述有源层相连。 在一个示例中， 所述凹陷的厚度为 0.3~1.0μπι， 例如是 0.5μπι。
在一个示例中， 所述有源层的材料为氧化物半导体。
在一个示例中， 所述有源层上方覆盖有刻蚀阻挡层， 所述刻蚀阻挡层上 开设有过孔， 所述源极和所述漏极通过所述过孔与所述有源层相连。
在一个示例中，所述填充层的材料为透明树脂，特别是聚丙烯酰胺树脂。 在一个示例中， 所述有源层包括位于中间部分的沟道区域和位于所述沟 道区域两侧的源极区域和漏极区域， 所述源极区域、 所述沟道区域和所述漏 极区域分别与所述栅极的所述第一部分、所述第二部分和所述第三部分相对。
在一个示例中， 所述源极和所述漏极分别与所述有源层的源极区域和漏 极区域连接。
本发明还提供了上述薄膜晶体管的制造方法， 包括：
对衬底基板进行刻蚀， 形成两个凹陷；
通过构图工艺在所述衬底基板上形成栅极的图形， 所述栅极包括第一部 分、 第二部分和第三部分， 所述第一部分和所述第三部分分别位于所述第二 部分的两侧， 所述第一部分和所述第三部分分别位于所述两个凹陷中；
在所述栅极上覆盖填充层；
去除掉位于所述第二部分上方的填充层；
通过构图工艺形成栅绝缘层的图形；
通过构图工艺形成有源层的图形；
通过构图工艺形成源极和漏极的图形， 所述源极与所述第一部分的位置 相对应， 所述漏极与所述第三部分的位置相对应。
在一个示例中， 所述有源层的材料为氧化物半导体。 在一个示例中， 所述通过构图工艺形成有源层的图形之后， 还包括： 通过构图工艺形成刻蚀阻挡层的图形， 所述刻蚀阻挡层上开设有过孔； 后续形成的所述源极和所述漏极通过所述过孔与所述有源层相连。
本发明还提供一种阵列基板， 所述阵列基板上设置有呈阵列式排布的若 干个上述的薄膜晶体管。
本发明还提供一种显示装置， 包括上述的阵列基板。
本发明所提供的上述技术方案具有如下优点： 在衬底基板上形成两个凹 陷， 使栅极中与源极对应的第一部分， 以及与漏极对应的第三部分均位于凹 陷中， 并且在第一部分和第三部分上方增加了填充层， 所以增大了第一部分 与源极之间的间距，以及第三部分与漏极之间的间距，从而减小了 Cgs和 Cgd 的大小， 提高了薄膜晶体管的导电性能。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明的实施例所提供的薄膜晶体管的示意图；
图 2a至图 2h为本发明的实施例所提供的薄膜晶体管制造过程的示意图； 图 3为本发明的实施例所提供的阵列基板的示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图， 对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
如图 1所示， 本发明实施例所提供的薄膜晶体管包括栅极 1、 有源层 2、 源极 31和漏极 32， 且该薄膜晶体管形成于衬底基板 4上。 栅极 1包括第一 部分 11、 第二部分 12和第三部分 13， 第一部分 11和第三部分 13分别位于 第二部分 12的两侧， 第一部分 11与源极 31的位置相对应， 第三部分 13与 漏极 32的位置相对应。 例如， 第一部分 11与源极 31至少部分地相对， 第三 部分 13与漏极 32至少部分地相对。
衬底基板 4上形成有两个凹陷 40，第一部分 11和第三部分 13分别位于 两个凹陷 40中。 凹陷 40的深度例如为 0.3~1.0μπι， 优选为 0.5μπι。 凹陷 40 的尺寸（例如， 在图 1的截面图中平行于基板方向的尺寸）与源极 31和漏极 32的尺寸相对应。 第一部分 11和第三部分 13上方覆盖有填充层 5， 填充层 5和第二部分 12上方覆盖有栅绝缘层 6。 填充层 5的材料例如为透明树脂， 本实施例中釆用的是聚丙烯酰胺树脂。 有源层 2设置于栅绝缘层 6上， 源极 31和漏极 32位于有源层 2上方， 且均与有源层 2相连。
作为一个实施例，有源层 2的材料为氧化物半导体。在其他实施方式中， 有源层 2的材料也可以是其他种类的半导体。
进一步， 有源层 2上方还覆盖有刻蚀阻挡层 7， 用于保护氧化物半导体 材料的有源层 2。 刻蚀阻挡层 7上开设有过孔 70， 源极 31和漏极 32通过过 孔 70与有源层 2相连。
本发明实施例提供的薄膜晶体管中， 在衬底基板 4上形成两个凹陷 40， 使栅极 1中与源极 31对应的第一部分 11，以及与漏极 32对应的第三部分 13 均位于凹陷 40中， 并且在第一部分 11和第三部分 13上方增加了填充层 5， 所以增大了第一部分 11与源极 31之间的间距， 以及第三部分 13与漏极 32 之间的间距，从而减小了 Cgs和 Cgd的大小，提高了薄膜晶体管的导电性能。
本发明还提供了上述薄膜晶体管的制造方法， 包括：
S1 : 如图 2a所示， 对衬底基板 4进行刻蚀， 形成两个凹陷 40。
衬底基板 4通常可釆用玻璃基板。 本步骤中， 可以釆用常规的刻蚀玻璃 的方法对衬底基板 4进行刻蚀， 例如， 釆用照射激光的方法对衬底基板 4进 行刻蚀； 或者， 也可以釆用构图工艺， 经曝光、 显影、 刻蚀等过程， 在衬底 基板 4上刻蚀形成两个凹陷 40。
S2: 通过构图工艺在衬底基板上形成栅极的图形。
如图 2b所示， 具体可以釆用常规的构图工艺， 经曝光、 显影、 刻蚀等过 程即可形成栅极 1。所形成的栅极 1包括第一部分 11、第二部分 12和第三部 分 13， 第一部分 11和第三部分 13分别位于第二部分 12的两侧， 第一部分 11和第三部分 13分别位于两个凹陷 40中。 S3:如图 2c所示，在完成上述步骤的基础上，在栅极 1上覆盖填充层 5。 填充层 5的材料例如为透明树脂，本实施例中釆用的是聚丙烯酰胺树脂。 在其他实施方式中， 也可以釆用树脂以外的其他材料作为填充层 5。
因为栅极 1的第一部分 11和第三部分 13位于凹陷 40中，所以会比第二 部分 12低一些。 所覆盖的填充层 5的厚度通常可以在 0.5至 3.0μπι之间， 并 且可以适当调整填充层 5的厚度。 填充层 5覆盖完毕之后， 可以使第一部分
11、 第二部分 12和第三部分 13上方的填充层 5的高度一致。
S4: 如图 2d所示， 去除掉位于栅极 1的第二部分 12上方的填充层 5。 具体的，可以对整个填充层 5进行灰化工艺，去除掉第二部分 12上方的 透明树脂材料的填充层 5， 并且第二部分 12上方的填充层 5去除之后， 还可 以使第二部分 12与剩余的填充层 5形成一个平面，也就是说，剩余的填充层
5的表面与第二部分 12的表面齐平。
S5: 如图 2e所示， 在完成上述步骤的基础上，通过构图工艺形成栅绝缘 层 6的图形。
栅绝缘层 6有可能会在衬底基板 4的其他区域形成一定的图形， 例如在 非显示区形成过孔， 用于将栅驱动信号传输至栅线， 因此本发明实施例的各 附图中均未示出栅绝缘层 6上的过孔。
S6: 如图 2f所示， 在完成上述步骤的基础上， 通过构图工艺形成有源层 2的图形。
本实施例中， 有源层 2的材料为氧化物半导体。 在其他实施方式中， 有 源层 2的材料也可以是其他种类的半导体。
例如， 有源层 2包括位于中间部分的沟道区域 22和位于所述沟道区域 22两侧的源极区域 21和漏极区域 23， 所述源极区域 21、 所述沟道区域 22 和所述漏极区域 23分别与所述栅极 1的所述第一部分 11、 所述第二部分 12 和所述第三部分 13相对。
S7: 如图 2g所示， 在完成上述步骤的基础上， 通过构图工艺形成刻蚀 阻挡层 7的图形， 且刻蚀阻挡层 7上开设有过孔 70。
S8: 如图 2h所示， 在完成上述步骤的基础上， 通过构图工艺形成源极 31和漏极 32的图形。 源极 31与栅极 1的第一部分 11的位置相对应， 漏极 32与栅极 1的第三部分 13的位置相对应， 源极 31和漏极 32通过刻蚀阻挡 层 7上的过孔 70与有源层 2相连。
例如， 所述源极 31和所述漏极 32分别与所述有源层 2的源极区域 21 和漏极区域 23连接。
上述步骤 S5至 S8均可以通过常规的构图工艺进行，此处不再详细描述。 完成以上步骤， 即可制成本发明实施例提供的薄膜晶体管。
还需要说明的是， 本实施例中的有源层为氧化物半导体材料， 而步骤 S7 中形成的刻蚀阻挡层用于保护该氧化物半导体材料的有源层。 在其他实施方 式中， 如果有源层的材料为氧化物半导体之外的其他材料， 则可以省略步骤 S7, 直接进行步骤 S8。
本发明实施例还提供一种阵列基板， 阵列基板上设置有呈阵列式排布的 若干个上述实施例提供的薄膜晶体管。
作为一个示例， 本实施例提供的阵列基板为高级超维场转换 ( Advanced super Dimension Switch, ADSDS )型阵列基板。 如图 3所示该阵列基板上除 了形成有上述实施例提供的薄膜晶体管之外，还形成有与漏极 32相连的像素 电极 81，覆盖在薄膜晶体管和像素电极 81上的保护层 9， 以及形成于保护层 9上的公共电极 82。
当然， 在其他实施方式中， 也可以是扭曲向列 （ Twisted Nematic, 简称 TN )型阵列基板，或其他类型的阵列基板。在 TN型阵列基板的实施方式中， 在形成上述薄膜晶体管的基础上， 形成漏极相连的像素电极， 在形成保护层 即可。
本发明实施例还提供一种显示装置， 包括上述实施例提供的阵列基板。 该显示装置可以是液晶面板、 液晶电视、 液晶显示器、 数码相框、 手机、 平 板电脑等任何具有显示功能的产品或部件。
由于本发明实施例提供的阵列基板及显示装置与上述本发明实施例所提 供的薄膜晶体管具有相同的技术特征， 所以也能产生相同的技术效果， 解决 相同的技术问题。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种薄膜晶体管， 包括栅极、 有源层、 源极和漏极， 且所述薄膜晶体 管形成于衬底基板上， 其中：
所述栅极包括第一部分、 第二部分和第三部分， 所述第一部分和所述第 三部分分别位于所述第二部分的两侧， 所述第一部分与所述源极的位置相对 应， 所述第三部分与所述漏极的位置相对应；
所述衬底基板上形成有两个凹陷， 所述第一部分和所述第三部分分别位 于所述两个凹陷中；
所述第一部分和所述第三部分上方覆盖有填充层；
所述填充层和所述第二部分上方覆盖有栅绝缘层；
所述有源层设置于所述栅绝缘层上；
所述源极和所述漏极位于所述有源层上方， 且均与所述有源层相连。
2、 根据权利要求 1 所述的薄膜晶体管， 其中： 所述凹陷的深度为 0.3~1.0μπι。
3、根据权利要求 2所述的薄膜晶体管，其中：所述凹陷的深度为 0.5μπι。
4、根据权利要求 1至 3中任一项所述的薄膜晶体管， 其中： 所述有源层 的材料为氧化物半导体。
5、根据权利要求 4所述的薄膜晶体管， 其中： 所述有源层上方覆盖有刻 蚀阻挡层， 所述刻蚀阻挡层上开设有过孔， 所述源极和所述漏极通过所述过 孔与所述有源层相连。
6、根据权利要求 1至 5中任一项所述的薄膜晶体管， 其中： 所述填充层 的材料为透明树脂。
7、根据权利要求 6所述的薄膜晶体管， 其中： 所述填充层的材料为聚丙 烯酰胺树脂。
8、根据权利要求 1至 7中任一项所述的薄膜晶体管， 其中： 所述有源层 包括位于中间部分的沟道区域和位于所述沟道区域两侧的源极区域和漏极区 域， 所述源极区域、 所述沟道区域和所述漏极区域分别与所述栅极的所述第 一部分、 所述第二部分和所述第三部分相对。
9、根据权利要求 8所述的薄膜晶体管， 其中： 所述源极和所述漏极分别 与所述有源层的源极区域和漏极区域连接。
10、 一种薄膜晶体管的制造方法， 包括：
对衬底基板进行刻蚀， 形成两个凹陷；
通过构图工艺在所述衬底基板上形成栅极的图形， 所述栅极包括第一部 分、 第二部分和第三部分， 所述第一部分和所述第三部分分别位于所述第二 部分的两侧， 所述第一部分和所述第三部分分别位于所述两个凹陷中；
在所述栅极上覆盖填充层；
去除掉位于所述第二部分上方的填充层；
通过构图工艺形成栅绝缘层的图形；
通过构图工艺形成有源层的图形；
通过构图工艺形成源极和漏极的图形， 所述源极与所述第一部分的位置 相对应， 所述漏极与所述第三部分的位置相对应。
11、根据权利要求 10所述的制造方法， 其中： 所述有源层的材料为氧化 物半导体。
12、根据权利要求 11所述的制造方法， 其中： 所述通过构图工艺形成有 源层的图形之后， 还包括：
通过构图工艺形成刻蚀阻挡层的图形， 所述刻蚀阻挡层上开设有过孔； 后续形成的所述源极和所述漏极通过所述过孔与所述有源层相连。
13、 一种阵列基板， 其上设置有呈阵列式排布的若干个权利要求 1至 9 任一项所述的薄膜晶体管。
14、 一种显示装置， 包括权利要求 13所述的阵列基板。
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