WO2015090000A1 - 阵列基板及其制作方法，显示装置 - Google Patents

阵列基板及其制作方法，显示装置 Download PDF

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Publication number
WO2015090000A1
WO2015090000A1 PCT/CN2014/078456 CN2014078456W WO2015090000A1 WO 2015090000 A1 WO2015090000 A1 WO 2015090000A1 CN 2014078456 W CN2014078456 W CN 2014078456W WO 2015090000 A1 WO2015090000 A1 WO 2015090000A1
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Prior art keywords
array substrate
spacer layer
insulating spacer
data line
thickness
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PCT/CN2014/078456
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English (en)
French (fr)
Inventor
王凯
Original Assignee
京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/429,928 priority Critical patent/US9570473B2/en
Publication of WO2015090000A1 publication Critical patent/WO2015090000A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers

Definitions

  • Embodiments of the present invention relate to an array substrate and a method of fabricating the same, and a display device. Background technique
  • Embodiments of the present invention provide an array substrate and a method of fabricating the same, to prevent display from being insufficient in contact after deposition of a second layer of transparent electrodes, and to avoid occurrence of orientation abnormalities.
  • At least one embodiment of the present invention provides a method of fabricating an array substrate, comprising: forming a pattern including a thin film transistor, a gate lead, and a data line lead on a base substrate, wherein the gate lead and the data line lead are located on the array substrate a display peripheral region (PAD region); forming an insulating spacer layer, a pattern of the first transparent electrode and the passivation layer, and forming a first via hole and a second via hole respectively in regions corresponding to the gate lead and the data line lead, And exposing the gate lead and the data line lead, wherein a thickness of the insulating spacer layer of the PAD region of the array substrate is smaller than a thickness of the insulating spacer layer of the other region; forming the second transparent electrode, the first connecting electrode, and a second connection electrode pattern, the first The connection electrode connects the gate lead through the first via, and the second connection electrode connects the data line lead through the second via.
  • a display peripheral region PAD region
  • the pattern of forming the insulating spacer layer, the first transparent electrode and the passivation layer comprises: forming a thin film of insulating material, and removing a connection region connecting the drain of the first transparent electrode and the thin film transistor by a patterning process And an insulating material film corresponding to the region of the gate lead and the region corresponding to the data line lead to form a pattern of a connection via, the first sub via, and the second sub via, respectively, and The thickness of the insulating material film of the PAD region is smaller than the thickness of the insulating material film of the other regions to form the insulating spacer layer; the pattern of the first transparent electrode is formed in the non-PAD region of the array substrate by a patterning process, the first a transparent electrode is connected to the drain of the thin film transistor through the connection via; a passivation layer is formed, and etching is continued in a region corresponding to the first sub via and the second sub via, respectively, by a patterning process until respectively exposed
  • the gate is wired to
  • the thickness of the insulating spacer layer of the PAD region of the array substrate is half of the thickness of the insulating spacer layer of the other regions.
  • the thickness of the insulating spacer layer of the non-PAD region of the array substrate is
  • the insulating spacer layer is made of an organic material.
  • Another embodiment of the present invention further provides an array substrate, comprising: a thin film transistor, a gate lead and a data line lead formed on a base substrate, wherein the gate lead and the data line lead are located in a PAD of the thin film transistor An insulating spacer layer over the thin film transistor, the gate lead and the data line lead; a first transparent electrode located in the non-PAD region above the spacer spacer and connected to the drain of the thin film transistor; a second transparent electrode over the transparent electrode; a passivation layer between the first transparent electrode and the second transparent electrode; a first via and a second formed in a region of the insulating spacer corresponding to the PAD region a via hole; and a first connection electrode and a second connection electrode formed over the insulating spacer layer and in the same layer as the second transparent electrode.
  • the thickness of the insulating spacer layer in the PAD region is smaller than the thickness of the insulating spacer layer in other regions, and the first connection electrode and the second connection electrode are respectively connected through the first via hole and the second via hole.
  • the gate lead and the data line lead are respectively connected through the first via hole and the second via hole.
  • the thickness of the insulating spacer layer of the PAD region is half of the thickness of the insulating spacer layer of the other regions.
  • the first transparent electrode is connected to a drain of the thin film transistor.
  • the first transparent electrode is a pixel electrode.
  • the second transparent electrode is a common electrode.
  • Another embodiment of the present invention also provides a display device comprising the array substrate of any of the above embodiments.
  • 1 is a schematic view showing an etched pixel electrode of a PAD region of an array substrate
  • FIG. 2 is a schematic view of the first connection electrode formed in the PAD region of the array substrate
  • FIG. 3 is a schematic view showing a method of forming an insulating spacer layer according to an embodiment of the present invention
  • FIG. 4 is a schematic view showing a pixel electrode formed on the array substrate shown in FIG.
  • FIG. 5 is a schematic view showing a passivation layer formed on the array substrate shown in FIG. 4;
  • FIG. 6 is a schematic view showing a common electrode, a first connection electrode, and a second connection electrode formed on the array substrate shown in FIG. 5;
  • Figure 7 is an enlarged schematic view of the first via hole of Figure 6. detailed description
  • FIG. 1 and 2 are schematic diagrams showing the hierarchical structure of a wiring area (PAD area) on the periphery of a display area of an array substrate.
  • the structure in FIG. 1 is from bottom to top: substrate substrate 1, gate lead 2, gate insulating layer 3, passivation layer 71, organic insulating layer 8 and its via holes, pixel electrode 9 (electrode material is ITO) And a photoresist 11. Since the thickness of the organic insulating layer is 10 times the thickness of the other layers, a deeper hole is formed at the via of the peripheral PAD region.
  • the thicker organic insulating layer causes the photoresist of the first transparent electrode to undergo insufficient illumination when subjected to vertical illumination, and thus is at the bottom of the hole (the area shown by the dotted oval frame in FIG. 1) ) There is some photoresist residue. Further, a portion of the ITO remains in the holes due to the residual photoresist during the subsequent wet etching process.
  • a second passivation layer 72 is deposited after etching the pixel electrode 9, and then the second passivation layer 72 and the gate insulating layer 3 at the via are etched.
  • the ITO remaining at the time of etching the pixel electrode 9 causes the gate insulating layer region which is not covered by the remaining ITO in the via hole to be etched later when the gate insulating layer 3 is etched. Therefore, after depositing the first connection electrode 12, the actual contact area of the first connection electrode 12 with the gate lead 2 is greatly reduced compared to the design contact area of the first connection electrode 12 and the gate lead 2.
  • the connection electrodes connecting the gate metal layers are formed simultaneously with the common electrodes, and the material forming these electrodes is ITO.
  • the method for fabricating an array substrate according to at least one embodiment of the present invention includes the following steps.
  • a pattern including a thin film transistor (TFT), a gate lead 21, and a data line lead 61 is formed on the base substrate 1, and the gate lead 21 and the data line lead 61 are located in the PAD region of the array substrate.
  • TFT thin film transistor
  • the TFT is formed in a non-PAD region (i.e., display region) of the array substrate and includes: a gate electrode 2, a gate insulating layer 3, an active layer 4, and a source 5 and a drain electrode 6.
  • the gate lead 21 is formed in the same layer as the gate 2
  • the data line lead 61 is formed in the same layer as the source 5 and the drain 6.
  • the display area is located in the middle of the array substrate for the liquid crystal display, for example, surrounded by the non-display area.
  • the display area includes a plurality of sub-pixel units arranged in an array, and each sub-pixel unit includes a TFT as a switching element.
  • Step 2 forming a pattern of the insulating spacer layer 8, the first transparent electrode and the passivation layer 72, such that the thickness of the insulating spacer layer of the PAD region of the array substrate 1 is smaller than the thickness of the insulating spacer layer of other regions, and corresponds to the gate
  • the areas of the lead 21 and the data line lead 61 form a first via 15' and a second via 16, respectively, to expose the gate lead 21 and the data line lead 61.
  • an example of the second step is as follows. Forming an insulating material
  • the film is removed by a patterning process including photoresist coating, exposure, development, etching, photoresist stripping, etc. (for example, a Half Tone mask can be used to remove the first transparent layer) a connection region of the electrode and the drain of the thin film transistor, a region corresponding to the gate lead 21, and a region of the insulating material corresponding to the region of the data line lead 61 to form a connection via 14, a first sub via 15, And a pattern of the second sub via 16, and such that the thickness of the insulating material film of the PAD region is smaller than the thickness of the insulating material film of the other regions to form the insulating spacer layer 8.
  • the insulating spacer layer can increase the distance between the pixel electrode and the source and drain, thereby reducing parasitic capacitance and reducing power consumption.
  • a passivation layer 71 is formed on the substrate before the film of the insulating material is formed, that is, a film of an insulating material is formed over the passivation layer 71 to be patterned later.
  • the insulating material film and the passivation layer 71 are patterned and removed, and the insulating material film and the passivation layer 71 in the corresponding regions are removed to form the connection via 14, the first sub via 15, and the second sub.
  • the pattern of the vias 16, and the thickness of the insulating material film of the PAD region is smaller than the thickness of the insulating material film of the other regions, and accordingly, the sum of the thicknesses of the insulating material film and the passivation layer 71 of the PAD region is smaller than that of other regions.
  • Fig. 3 shows a pattern after the formation of the insulating spacer 8, and the thickness h2 of the insulating spacer 8 of the PAD region A is smaller than the thickness hl of the insulating spacer 8 of the other regions.
  • the thickness h2 can be half of hi.
  • the thickness of the insulating spacer layer 8 of the non-PAD region is, for example, 20,000A to 30000A.
  • the insulating spacer layer 8 may be composed of an organic insulating material.
  • the pattern of the first transparent electrode is formed in the non-PAD region by a patterning process.
  • the first transparent electrode is a pixel electrode 9, and the pixel electrode 9 is connected to the drain electrode 6 of the thin film transistor through a connection via 14.
  • forming the pixel electrode 9 includes the following process.
  • An ITO film is deposited on the surface of the substrate after the insulating spacer layer 8 is formed, and correspondingly, the first sub via 15 and the second sub via 16 are also deposited with ITO.
  • a pattern of the pixel electrode 9 in Fig. 4 is formed by a patterning process. In the patterning process, since the insulating spacer layer 8 of the PAD region has a small thickness, the first sub via 15 and the second sub via 16 have a shallow depth, and the photoresist in the holes can be sufficiently exposed. And removed, so that the ITO in the first sub via 15 and the second sub via 16 is not left as a part of ITO as in FIG.
  • the thickness h2 is half of the thickness hi, which allows the photoresist to be sufficiently exposed, the ITO is not easily left in the via holes, and the patterning by using the halftone mask is also facilitated.
  • the process achieves patterning while improving the poor orientation (if the thickness difference is too large (eg, 2 ⁇ or more), the orientation is likely to be poor).
  • a passivation layer 72 of a certain thickness is formed thereon.
  • the passivation layer 72 may have a thickness of 2000 ⁇ to 4000 ⁇ . Etching is continued in a region corresponding to the first sub via 15 and the second sub via 16' by a patterning process until the gate lead 21 and the data line lead 61 are respectively exposed to form the first Via 15 and second via 16.
  • Step 3 forming a pattern including the second transparent electrode, the first connection electrode 12, and the second connection electrode 13, and connecting the first connection electrode 12 to the gate lead 21 through the first via hole 15,
  • the second connection electrode 13 is connected to the data line lead 61 through the second via hole 16.
  • an example of the third step includes the following process.
  • a tantalum film is formed on the passivation layer 72, and the second transparent electrode, the first connection electrode 12, and the second connection electrode 13 shown in Fig. 6 are formed by a patterning process.
  • the second transparent electrode is the common electrode 10.
  • the common electrode 10 is connected to a common electrode line (not shown), and the common electrode line is formed simultaneously with the gate 2 and the gate lead 21.
  • the first connection electrode 12 is connected to the gate lead 21 through the first via 15, and the second connection electrode 13 is connected to the data line lead 61 through the second via 16, thereby finally forming the array substrate as shown in FIG.
  • the first connection electrode 12 and the second connection electrode 13 has sufficient contact area with the gate lead 21 and the data line lead 61, respectively, which reduces defects such as high brightness of the display device and abnormal lighting.
  • At least one embodiment of the present invention also provides an array substrate, as shown in FIG.
  • the array substrate includes a thin film transistor, a first transparent electrode, a second transparent electrode, a gate lead 21, and a data line lead 61 formed on the base substrate 1.
  • the gate lead 21 and the data line lead 61 are located in the PAD area of the array substrate.
  • the thin film transistor is located in a sub-pixel unit in the display area.
  • the array of sub-pixel units is defined, for example, by gate lines and data lines that intersect each other.
  • the array substrate further includes an insulating spacer layer 8 over the thin film transistor, the gate lead 21, and the data line lead 61.
  • a passivation layer 71 is also formed between the thin film transistor, the gate lead 21, and the data line lead 61 and the insulating spacer layer 8.
  • the first transparent electrode is located
  • the non-PAD region of the array substrate above the insulating spacer layer 8 may be a pixel electrode 9 and connected to the drain electrode 6 of the thin film transistor.
  • the second transparent electrode may be a common electrode 10 located above the pixel electrode 9.
  • a passivation layer 72 is interposed between the first transparent electrode and the second transparent electrode.
  • the thickness of the insulating spacer layer 8 in the PAD region is smaller than the thickness of the insulating spacer layer 8 in other regions.
  • the array substrate further includes a first via 15 and a second via 16 formed in a region of the insulating spacer 8 corresponding to the PAD region; and is formed over the insulating spacer 8 and in the same layer as the common electrode 10.
  • the first connection electrode 12 and the second connection electrode 13 connect the gate lead 21 and the data line lead 61 through the first via 15 and the second via 16, respectively.
  • the thickness of the insulating spacer layer 8 of the PAD region may be half the thickness of the insulating spacer layer 8 of other regions.
  • Embodiments of the present invention also provide a display device including the above array substrate.
  • the display device can be: any product or component having a display function such as a liquid crystal panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the array substrate manufacturing method of the embodiment of the present invention is such that a thin insulating spacer layer is formed in the display peripheral region (PAD region), so that the connection electrode formed in the PAD region can be sufficiently contacted with the corresponding signal lead without causing In the subsequent rubbing, rubbing mura is generated to improve the product detection rate.

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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

　一种阵列基板制作方法，阵列基板及显示装置。该阵列基板制作方法包括：在衬底基板（1）上形成包括薄膜晶体管、栅极引线（21）及数据线引线（61）的图形，栅极引线（21）和数据线引线（61）位于PAD区；形成绝缘间隔层（8）、第一透明电极（9）及钝化层（72）的图形，并在对应于栅极引线（21）和数据线引线（61）的区域分别形成第一过孔（15）和第二过孔（16），以暴露出栅极引线（21）和数据线引线（61），阵列基板的PAD区的绝缘间隔层（8）的厚度小于其它区域的绝缘间隔层（8）的厚度。由此使得在PAD区形成的连接电极（12，13）能够与相应的信号引线（21，61）充分接触，以及避免产生取向不良。

Description

阵列基板及其制作方法， 显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制作方法， 显示装置。 背景技术
近年来随着人们对显示效果的要求提高， 液晶显示器的 PPI ( Pixels per inch, 每英寸像素数目 )不断提高， 这就要求显示屏内部单位面积上排布更 多的像素， 相应地有更多的布线。 这样在各层金属间的电容及电阻会成倍增 加， 因此时间延迟及功耗增加就变得更为明显， 严重影响客户使用。 而且， 这也同现在提倡的节能环保相悖。 为了降低金属层间的电容需要釆用更低介 电常数、 更厚的绝缘材料。 若要增加釆用化学气相沉积 （Chemical Vapor Deposition, CVD )方式制备的无机绝缘材料的厚度， 对生产成本及工艺的要 求会非常高， 特别是在刻蚀时带来的技术难题是很难克服的， 同时工艺的时 间会大大增加， 这样对产量会有很大影响， 降低了企业的竟争力。相比之下， 选用有机绝缘材料具有生产工艺简单， 成本较低， 易于调整厚度， 对降低功 耗有很明显的效果， 同时还降低公共电极的负载， 对改善 greenish (显示偏 绿现象）不良有很明显的效果。 发明内容
本发明的实施例提供了一种阵列基板及其制作方法， 显示装置， 以避免 在第二层透明电极沉积后产生接触不充分， 且避免产生取向异常。
本发明的至少一个实施例提供了一种阵列基板制作方法， 包括： 在衬底 基板上形成包括薄膜晶体管、 栅极引线及数据线引线的图形， 所述栅极引线 和数据线引线位于阵列基板的显示外围区 (PAD区)； 形成绝缘间隔层， 第一 透明电极及钝化层的图形， 并在对应于栅极引线和数据线引线的区域分别形 成第一过孔和第二过孔， 以暴露出所述栅极引线和数据线引线， 其中， 所述 阵列基板的 PAD区的绝缘间隔层的厚度小于其它区域的绝缘间隔层的厚度； 形成包括第二透明电极、 第一连接电极和第二连接电极的图形， 使所述第一 连接电极通过所述第一过孔连接所述栅极引线， 所述第二连接电极通过所述 第二过孔连接所述数据线引线。
在一个实施例中， 所述形成绝缘间隔层， 第一透明电极及钝化层的图形 包括： 形成绝缘材料薄膜， 通过构图工艺去除连接所述第一透明电极与薄膜 晶体管的漏极的连接区域、 对应于所述栅极引线的区域及对应于数据线引线 的区域的绝缘材料薄膜， 以分别形成连接过孔、 所述第一子过孔和所述第二 子过孔的图形， 且使得 PAD 区的绝缘材料薄膜的厚度小于其它区域的绝缘 材料薄膜的厚度， 以形成所述绝缘间隔层； 通过构图工艺在阵列基板的非 PAD区形成所述第一透明电极的图形，所述第一透明电极通过所述连接过孔 连接薄膜晶体管的漏极； 形成钝化层， 通过构图工艺分别在与所述第一子过 孔和第二子过孔对应的区域继续刻蚀， 直到分别暴露出所述栅极弓 I线和数据 线引线， 以形成所述第一过孔和第二过孔。
在一个实施例中， 所述阵列基板的 PAD 区的绝缘间隔层厚度为其它区 域的绝缘间隔层厚度的一半。
在一个实施例中， 所述阵列基板的非 PAD 区的绝缘间隔层厚度为
20000Λ〜 30000A。
在一个实施例中， 所述绝缘间隔层由有机材料制成。
本发明的另一个实施例还提供了一种阵列基板， 其包括： 形成在衬底基 板上的薄膜晶体管、 栅极引线及数据线引线， 所述栅极引线及数据线引线位 于薄膜晶体管的 PAD 区； 位于薄膜晶体管、 栅极引线及数据线引线上方的 绝缘间隔层； 位于所述绝缘件间隔层之上的非 PAD 区且连接所述薄膜晶体 管的漏极的第一透明电极； 位于第一透明电极上方的第二透明电极； 在所述 第一透明电极和第二透明电极之间的钝化层； 形成在所述绝缘间隔层对应于 PAD区的区域中的第一过孔和第二过孔； 以及形成在绝缘间隔层上方且与所 述第二透明电极位于同一层的第一连接电极和第二连接电极。 在该阵列基板 中， 在所述 PAD区的绝缘间隔层的厚度小于其它区域的绝缘间隔层的厚度， 所述第一连接电极和第二连接电极分别通过第一过孔和第二过孔连接所述栅 极引线和数据线引线。
在一个实施例中， 所述 PAD 区的绝缘间隔层厚度为其它区域的绝缘间 隔层厚度的一半。 在一个实施例中， 所述第一透明电极连接所述薄膜晶体管的漏极。
在一个实施例中， 所述第一透明电极为像素电极。
在一个实施例中， 所述第二透明电极为公共电极。
本发明的另一个实施例还提供了一种显示装置， 包括上述任一实施例的 阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1是一种阵列基板的 PAD区刻蚀像素电极的示意图；
图 2是在阵列基板的 PAD区形成第一连接电极后的示意图；
图 3是根据本发明实施例的制作方法形成绝缘间隔层后的示意图； 图 4是在图 3所示的阵列基板上形成像素电极后的示意图；
图 5是在图 4所示的阵列基板上形成钝化层后的示意图；
图 6是在图 5所示的阵列基板上形成公共电极、 第一连接电极和第二连 接电极后的示意图；
图 7是图 6中第一过孔的放大示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图， 对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
图 1和图 2为一种阵列基板的显示区域外围的布线区域（PAD区）的层 次结构示意图。 图 1中的结构由下至上依次为： 衬底基板 1、栅极引线 2、栅 绝缘层 3， 钝化层 71、 有机绝缘层 8及其上过孔、 像素电极 9 (电极材料为 ITO )以及光刻胶 11。 由于有机绝缘层的厚度是其它层厚度的 10倍， 在外围 PAD区走线的过孔处产生一个较深的孔。这样在随后曝光制作像素电极 9的 图形时， 该较厚的有机绝缘层导致第一层透明电极的光刻胶在受垂直光照时 经历照射不充分， 因此在孔的底部（如图 1所示中虚线椭圓框所示的区域） 有部分光刻胶残留。 进而， 在后续湿刻过程中由于该残留的光刻胶而导致在 孔内有部分 ITO残留。
如图 2所示， 刻蚀像素电极 9后沉积第二钝化层 72， 然后刻蚀过孔处的 第二钝化层 72和栅绝缘层 3。在刻蚀像素电极 9时残留的 ITO导致后面在刻 蚀栅绝缘层 3时只有过孔中未被残留的 ITO覆盖的栅绝缘层区被刻透。 因此 在沉积第一连接电极 12后， 第一连接电极 12与栅极引线 2的实际接触面积 比第一连接电极 12与栅极引线 2的设计接触面积大大减小。这里，连接栅金 属层的连接电极， 与公共电极同时形成， 且形成这些电极的材料为 ITO。 这 种减小的接触面积导致接触不充分， 从而会带来屏的亮线高发及异常点灯等 不良， 不利于产品的不良检测及良率的提高。 此外， 若在外围布线处去除有 机绝缘层， 则由于膜层段差过大导致后面成盒工序配向膜取向 （rubbing )时 产生异常， 造成产品后面画面显示不均。
如图 3~6所示， 本发明的至少一个实施例的阵列基板制作方法包括以下 步骤。
步骤一， 在衬底基板 1上形成包括薄膜晶体管（TFT )、 栅极引线 21及 数据线引线 61的图形， 所述栅极引线 21和数据线引线 61位于阵列基板的 PAD区。
在本发明的一个实施例中， TFT形成在阵列基板的非 PAD区 （即显示 区）且包括： 栅极 2、 栅绝缘层 3、 有源层 4， 以及源极 5和漏极 6。 在本发 明的一个实施例中， 栅极引线 21与栅极 2同层形成， 数据线引线 61与源极 5和漏极 6同层形成。 显示区位于用于液晶显示器的阵列基板的中部， 例如 被非显示区围绕。 显示区包括按阵列排列的多个亚像素单元， 每个亚像素单 元包括 TFT作为开关元件。
步骤二， 形成绝缘间隔层 8， 第一透明电极及钝化层 72的图形， 使阵列 基板 1 的 PAD区的绝缘间隔层的厚度小于其它区域的绝缘间隔层的厚度， 并在对应于栅极引线 21和数据线引线 61的区域分别形成第一过孔 15' 和第 二过孔 16， ， 以暴露出栅极引线 21和数据线引线 61。
在本发明的一个实施例中， 该步骤二的一个示例如下所述。 形成绝缘材 料薄膜， 通过包括光刻胶涂敷、 曝光、 显影、 刻蚀、 光刻胶剥离等的构图工 艺（例如， 可以釆用半色调掩膜板（Half Tone mask ) )去除连接所述第一透 明电极与薄膜晶体管的漏极的连接区域、对应于所述栅极引线 21的区域及对 应于数据线引线 61的区域的绝缘材料薄膜， 以分别形成连接过孔 14、 第一 子过孔 15， 和第二子过孔 16， 的图形， 且使得 PAD区的绝缘材料薄膜的厚 度小于其它区域的绝缘材料薄膜的厚度， 以形成所述绝缘间隔层 8。 所述绝 缘间隔层能够增加像素电极和源漏极之间的距离， 进而减少寄生电容， 降低 功耗。
在另一个示例中， 与上一个示例相比， 在形成绝缘材料薄膜之前， 在基 板上还形成有一层钝化层 71， 即绝缘材料薄膜形成在钝化层 71之上， 从而 在之后进行构图工艺时，将所述绝缘材料薄膜和钝化层 71—并构图，去除相 应区域中的绝缘材料薄膜和钝化层 71， 以形成连接过孔 14、 第一子过孔 15， 和第二子过孔 16， 的图形， 且使得 PAD区的绝缘材料薄膜的厚度小于其它 区域的绝缘材料薄膜的厚度， 相应地使得 PAD 区的绝缘材料薄膜和钝化层 71的厚度之和小于其它区域的绝缘材料薄膜和钝化层 71的厚度之和。
图 3示出形成绝缘间隔层 8后的图形， PAD区 A的绝缘间隔层 8的厚度 h2小于其它区域的绝缘间隔层 8的厚度 hl。 在一个示例中， 厚度 h2可为 hi 的一半。 在一个示例中， 为了减小高 PPI阵列基板中各层导电层的电容及电 阻， 非 PAD区的绝缘间隔层 8的厚度例如为 20000A ~ 30000A。 例如， 绝缘 间隔层 8可由有机绝缘材料构成。
形成绝缘间隔层 8之后， 通过构图工艺在非 PAD区形成所述第一透明 电极的图形。 如图 4所示， 在本发明的一个实施例中， 第一透明电极为像素 电极 9， 该像素电极 9通过连接过孔 14连接薄膜晶体管的漏极 6。 在本发明 的一个实施例中， 形成像素电极 9包括以下过程。
在形成有绝缘间隔层 8之后的基板表面上沉积一层 ITO薄膜，相应地第 一子过孔 15， 和第二子过孔 16， 中也沉积有 ITO。 通过构图工艺形成图 4 中像素电极 9的图形。 在该构图工艺中， 由于 PAD区的绝缘间隔层 8厚度 较小， 第一子过孔 15， 和第二子过孔 16， 的深度较浅， 在这些孔中的光刻胶 能够得到充分曝光而被去除， 因此在刻蚀第一子过孔 15， 和第二子过孔 16， 中的 ITO是不会像图 2中那样残留一部分 ITO。 在一个示例中， 在形成绝缘间隔层 8时， 厚度 h2为厚度 hi的一半， 这 样能使光刻胶充分曝光， 过孔中不容易残留 ITO， 也便于通过釆用半色调掩 膜板的构图工艺实现构图， 同时改善取向不良 (若厚度差异过大（如： 2μπι以 上） ， 则容易产生取向不良)。
如图 5所示， 形成像素电极 9之后， 在其上形成一定厚度的钝化层 72， 例如， 钝化层 72的厚度可为 2000Α ~ 4000Α。 通过构图工艺分别在与所述第 一子过孔 15， 和第二子过孔 16' 对应的区域继续刻蚀， 直到分别暴露出栅极 引线 21和数据线引线 61， 以形成所述第一过孔 15和第二过孔 16。
步骤三， 形成包括第二透明电极、 第一连接电极 12和第二连接电极 13 的图形，使所述第一连接电极 12通过所述第一过孔 15连接所述栅极引线 21， 所述第二连接电极 13通过所述第二过孔 16连接所述数据线引线 61。
如图 6所示， 该步骤三的一个示例包括以下过程。
在钝化层 72上形成 ΙΤΟ薄膜， 通过构图工艺形成图 6中所示的第二透 明电极、 第一连接电极 12和第二连接电极 13。 在本发明的一个实施例中， 第二透明电极为公共电极 10。 例如， 公共电极 10连接公共电极线（图中未 示出） ， 公共电极线与栅极 2及栅极引线 21同时形成。 第一连接电极 12通 过第一过孔 15连接栅极引线 21， 第二连接电极 13通过第二过孔 16连接数 据线引线 61， 最终形成如图 6所示的阵列基板。
由于在步骤二中第一子过孔 15， 和第二子过孔 16， 中不会残留制作像素 电极 9时使用的 ΙΤΟ， 如图 7所示， 因此第一连接电极 12和第二连接电极 13分别与栅极引线 21和数据线引线 61有足够的接触面积，这减少了显示装 置的亮线高发及异常点灯等不良。
本发明的至少一个实施例还提供了一种阵列基板， 如图 6所示。 该阵列 基板包括形成在衬底基板 1上的薄膜晶体管、第一透明电极、第二透明电极、 栅极引线 21及数据线引线 61， 栅极引线 21及数据线引线 61位于阵列基板 的 PAD 区。 薄膜晶体管位于显示区域中的亚像素单元之中。 亚像素单元的 阵列例如由彼此交叉的栅线和数据线界定。
该阵列基板还包括位于薄膜晶体管、 栅极引线 21及数据线引线 61上方 的绝缘间隔层 8。 例如， 在另一个示例中， 薄膜晶体管、 栅极引线 21及数据 线引线 61和绝缘间隔层 8之间还形成有钝化层 71。 所述第一透明电极位于 所述绝缘间隔层 8之上的阵列基板的非 PAD区， 第一透明电极可以为像素 电极 9且连接所述薄膜晶体管的漏极 6。 第二透明电极可以为公共电极 10， 位于像素电极 9上方。 第一透明电极和第二透明电极之间间隔有钝化层 72。 在所述 PAD区的绝缘间隔层 8的厚度小于其它区域的绝缘间隔层 8的厚度。
该阵列基板还包括形成在绝缘间隔层 8对应于 PAD区的区域中的第一 过孔 15和第二过孔 16; 以及形成在绝缘间隔层 8上方且与所述公共电极 10 位于同一层的第一连接电极 12和第二连接电极 13。第一连接电极 12和第二 连接电极 13分别通过第一过孔 15和第二过孔 16连接栅极引线 21和数据线 引线 61。
在一个实施例中， 所述 PAD区的绝缘间隔层 8的厚度可以为其它区域 的绝缘间隔层 8厚度的一半。
本发明的实施例还提供了一种显示装置， 包括上述的阵列基板。 该显示 装置可以为： 液晶面板、 手机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能的产品或部件。
本发明的实施例的阵列基板制作方法使得在显示外围区 (PAD区)形成厚 度较薄的绝缘间隔层， 使得在 PAD 区形成的连接电极能够与相应的信号引 线充分接触，且不会导致在后续摩擦 (rubbing)时产生取向不良 (rubbing mura), 提高产品检出率。
以上实施方式仅用于说明本发明， 而并非对本发明的限制， 有关技术领 域的普通技术人员， 在不脱离本发明的精神和范围的情况下， 还可以做出各 种变化和变型， 因此所有等同的技术方案也属于本发明的范畴， 本发明的专 利保护范围应由权利要求限定。
本申请要求于 2013年 12月 16日递交的中国专利申请第 201310689196.5 号的优先权， 在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims

权利要求书
1、 一种阵列基板制作方法， 包括：
在衬底基板上形成包括薄膜晶体管、 栅极引线及数据线引线的图形， 所 述栅极引线和数据线引线位于显示外围区；
形成绝缘间隔层、 第一透明电极及钝化层的图形， 并在对应于栅极引线 和数据线引线的区域分别形成第一过孔和第二过孔， 以暴露出所述栅极引线 和数据线引线， 其中， 所述阵列基板的显示外围区的绝缘间隔层的厚度小于 其它区域的绝缘间隔层的厚度；
形成包括第二透明电极、 第一连接电极和第二连接电极的图形， 其中， 所述第一连接电极通过所述第一过孔连接所述栅极引线， 所述第二连接电极 通过所述第二过孔连接所述数据线引线。
2、如权利要求 1所述的阵列基板制作方法，其中，所述形成绝缘间隔层， 第一透明电极及钝化层的图形包括：
形成绝缘材料薄膜， 通过构图工艺去除连接所述第一透明电极与薄膜晶 体管的漏极的连接区域、 对应于所述栅极引线的区域及对应于所述数据线弓 I 线的区域的绝缘材料薄膜， 以分别形成连接过孔、 所述第一子过孔和所述第 二子过孔的图形， 且使得所述显示外围区的绝缘材料薄膜的厚度小于其它区 域的绝缘材料薄膜的厚度， 以形成所述绝缘间隔层；
通过构图工艺在所述阵列基板的非显示外围区形成所述第一透明电极的 图形， 且所述第一透明电极通过所述连接过孔连接所述薄膜晶体管的漏极； 形成钝化层， 通过构图工艺分别在对应于所述第一子过孔和第二子过孔 的区域继续刻蚀， 直到分别暴露出所述栅极引线和数据线引线， 以形成所述 第一过孔和第二过孔。
3、如权利要求 2所述的阵列基板制作方法，还包括： 在形成所述绝缘材 料薄膜之前在所述薄膜晶体管、 所述栅极引线及所述数据线引线的图形上形 成第一钝化层。
4、如权利要求 2或 3所述的阵列基板制作方法， 其中， 所述阵列基板的 显示外围区的绝缘间隔层厚度为其它区域的绝缘间隔层厚度的一半。
5、 如权利要求 2-4任一所述的阵列基板制作方法， 其中， 所述非显示外 围区的绝缘间隔层厚度为 20000A〜 30000A。
6、 如权利要求 1-5中任一项所述的阵列基板制作方法， 其中， 所述绝缘 间隔层由有机材料制成。
7、 一种阵列基板， 包括：
形成在衬底基板上的薄膜晶体管、 栅极引线及数据线引线， 其中所述栅 极引线及数据线引线位于所述阵列基板的显示外围区；
位于薄膜晶体管、 栅极引线及数据线引线上方的绝缘间隔层； 位于所述绝缘间隔层之上且位于所述阵列基板的非显示外围区的第一透 明电极；
位于所述第一透明电极上方的第二透明电极；
位于所述第一透明电极和所述第二透明电极之间的钝化层；
形成在所述绝缘间隔层对应于所述显示外围区的区域中的第一过孔和第 二过孔； 以及
形成在绝缘间隔层上方且与所述第二透明电极位于同一层的第一连接电 极和第二连接电极；
其中， 所述显示外围区的绝缘间隔层的厚度小于其它区域的绝缘间隔层 的厚度， 所述第一连接电极通过所述第一过孔连接所述栅极引线， 以及所述 第二连接电极通过所述第二过孔连接所述数据线引线。
8、如权利要求 7所述的阵列基板， 其中， 所述显示外围区的绝缘间隔层 厚度为其它区域的绝缘间隔层厚度的一半。
9、如权利要求 7或 8所述的阵列基板， 其中， 所述第一透明电极连接所 述薄膜晶体管的漏极。
10、 一种显示装置， 包括如权利要求 7-9中任一项所述的阵列基板。
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