JP6521534B2 - 薄膜トランジスタとその作製方法、アレイ基板及び表示装置 - Google Patents
薄膜トランジスタとその作製方法、アレイ基板及び表示装置 Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims description 73
- 239000000758 substrate Substances 0.000 title claims description 48
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 229920002120 photoresistant polymer Polymers 0.000 claims description 29
- 238000000059 patterning Methods 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 16
- 230000008569 process Effects 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 230000014759 maintenance of location Effects 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 170
- 230000009194 climbing Effects 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 229910052779 Neodymium Inorganic materials 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 229910052748 manganese Inorganic materials 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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Description
本発明は、半導体デバイス製造の技術分野に関し、特に薄膜トランジスタとその作製方法、アレイ基板及び表示装置に関する。
本発明の実施例や従来技術における技術案をより明確に説明するために、以下、実施例や従来技術の記載に必要とされる図面を簡単に説明する。明らかに、以下の記載に関する図面は、単に本発明の一部の実施例である。当業者にとって、創造性のある作業をしない前提で、これらの図面から他の図面を得ることもできる。
Claims (13)
- 全体が同一平面に位置する活性層と、
活性層上に位置し、上記活性層に接触するように設置されたソース電極と、
ソース電極上に位置し、第1ホールを含む第1絶縁層と、
上記第1絶縁層上に位置し、第1ホールを介して活性層に接触するドレイン電極と、
ドレイン電極を被覆する第2絶縁層と、
ソース電極とドレイン電極の間の領域に対応する部分を有し上記第2絶縁層上に位置する第1部分を含むゲート電極と
を含み、
上記ゲート電極は、ゲート電極の第1部分と電気接続する第2部分を更に含み、
上記ドレイン電極と上記ゲート電極の第2部分とは同一層に位置し、
上記第2絶縁層は、上記ゲート電極の第2部分とドレイン電極を被覆することを特徴とする薄膜トランジスタ。 - 上記ゲート電極の第2部分は、ソース電極のドレイン電極から離れた側に位置することを特徴とする請求項1に記載の薄膜トランジスタ。
- 上記第2絶縁層は、第2ホールを含み、
上記ゲート電極の第1部分は、上記第2ホールを介してゲート電極の第2部分と電気接触することを特徴とする請求項1に記載の薄膜トランジスタ。 - 上記ゲート電極の第2部分とドレイン電極の材料は、ゲート金属であることを特徴とする請求項1に記載の薄膜トランジスタ。
- 上記ゲート電極の第1部分は、透明導電材料であることを特徴とする請求項1に記載の薄膜トランジスタ。
- 上記ソース電極は、薄膜トランジスタの活性層が存在する領域上に位置し、且つ全体が上記活性層と接触するように設置されることを特徴とする請求項1〜5のいずれか一項に記載の薄膜トランジスタ。
- 全体が同一平面に位置する活性層を形成し、
上記活性層と接触するように設置されたソース電極を上記活性層上に形成し、
上記ソース電極上に第1絶縁層を形成し、上記第1絶縁層に第1ホールを形成し、
第1ホールを介して活性層に接触するドレイン電極を上記第1絶縁層上に形成し、
ドレイン電極を被覆する第2絶縁層を形成し、
ソース電極とドレイン電極の間の領域に対応する部分を有し上記第2絶縁層上に位置する第1部分を含むゲート電極を形成し、
上記第2絶縁層に第2ホールを形成することを含み、
ゲート電極とドレイン電極の形成において、
上記第1絶縁層上にゲート金属層を形成し、上記ゲート金属層にパターニング工程を行うことにより、ゲート電極の第2部分と、第1絶縁層の第1ホールを介して活性層に接触するドレイン電極とを形成し、
上記第2絶縁層上に導電層を形成し、上記導電層にパターニング工程を行うことにより、ソース電極とドレイン電極の間の領域に対応する部分を有し第2絶縁層の第2ホールを介してゲート電極の第2部分と電気接触するゲート電極の第1部分を形成することを含むことを特徴とする薄膜トランジスタの作製方法。 - 活性層とソース電極の形成において、
活性層薄膜を形成し、
上記活性層薄膜上にソース金属層を形成し、
上記ソース金属層上にフォトレジストを塗布し、フォトレジストに対して露光、現像を行うことにより、薄膜トランジスタのソース電極が存在する領域に対応するフォトレジスト完全保留領域と、薄膜トランジスタの活性層がソース電極の位置に対応しない領域に対応するフォトレジスト半分保留領域と、及び、他の領域に対応するフォトレジスト未保留領域とを形成し、
フォトレジスト未保留領域のソース金属層と活性層薄膜をエッチングして除去し、活性層のパターンを形成し、
フォトレジスト半分保留領域のフォトレジストを除去し、
フォトレジスト半分保留領域のソース金属層をエッチングして除去し、
残りのフォトレジストを剥離し、薄膜トランジスタの活性層とソース電極を形成することを含むことを特徴とする請求項7に記載の作製方法。 - 請求項1〜6のいずれか一項に記載の薄膜トランジスタと、
薄膜トランジスタのドレイン電極を被覆し、第3ホールを有する第2絶縁層と、
上記第2絶縁層上に位置し、上記第3ホールを介して薄膜トランジスタのドレイン電極と電気接触する画素電極と
を含むことを特徴とするアレイ基板。 - 上記第2絶縁層上に位置する第1部分を含むゲート電極を更に含み、
上記第1部分は、ソース電極とドレイン電極の間の領域に対応する部分を有し、画素電極と同一層に位置することを特徴とする請求項9に記載のアレイ基板。 - 請求項9又は10に記載のアレイ基板を含む表示装置。
- 全体が同一平面に位置する活性層を形成し、
上記活性層と接触するように設置されたソース電極を上記活性層上に形成し、
上記ソース電極上に第1絶縁層を形成し、上記第1絶縁層に第1ホールを形成し、
上記第1絶縁層上にゲート金属層を形成し、上記ゲート金属層にパターニング工程を行うことにより、ゲート電極の第2部分と、第1絶縁層の第1ホールを介して活性層と接触するドレイン電極とを形成し、
ドレイン電極を被覆する第2絶縁層を形成し、上記第2絶縁層に第2ホールと第3ホールを形成し、
ソース電極とドレイン電極の間の領域に対応する部分を有し、第2絶縁層の第2ホールを介してゲート電極の第2部分と電気接触するゲート電極の第1部分を上記第2絶縁層上に形成し、
ゲート電極の第1部分の形成と同時に、第3ホールを介してドレイン電極と電気接触するアレイ基板の画素電極を形成することを含むことを特徴とするアレイ基板の作製方法。 - ゲート電極の第1部分と画素電極の形成において、
上記第2絶縁層上に導電層を形成し、上記導電層にパターニング工程を行うことにより、ゲート電極の第1部分と画素電極を形成することを特徴とする請求項12に記載の作製方法。
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