WO2017049824A1 - Tft阵列基板的制造方法、tft阵列基板及显示装置 - Google Patents

Tft阵列基板的制造方法、tft阵列基板及显示装置 Download PDF

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WO2017049824A1
WO2017049824A1 PCT/CN2016/072292 CN2016072292W WO2017049824A1 WO 2017049824 A1 WO2017049824 A1 WO 2017049824A1 CN 2016072292 W CN2016072292 W CN 2016072292W WO 2017049824 A1 WO2017049824 A1 WO 2017049824A1
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source
array substrate
layer
tft array
pixel electrode
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PCT/CN2016/072292
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English (en)
French (fr)
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陈磊
彭志龙
代伍坤
张磊
仇淼
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US15/324,641 priority Critical patent/US10020325B2/en
Publication of WO2017049824A1 publication Critical patent/WO2017049824A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT (Thin Film Transistor) array substrate manufacturing method, a TFT array substrate, and a display device.
  • TFT Thin Film Transistor
  • the TFT array substrate is an important component of the display device.
  • the TFT array substrate generally includes a base substrate, and a gate, a gate protection layer, an active layer, a pixel electrode, a source, a drain, a source signal line, and a source/drain protection layer disposed on the base substrate, wherein
  • the pixel electrode is formed by a patterning process of the transparent conductive layer
  • the source, drain and source signal lines are formed by a patterning process of the source/drain metal layer
  • the transparent conductive layer is located under the source and drain metal layer.
  • the source signal line is prone to breakage, resulting in the signal being unable to be transmitted.
  • the pixel electrode line 3 is formed in synchronization with the pixel electrode 3 ′.
  • the pixel electrode line 3 is located at a position where the source signal line is to be formed, thereby causing the subsequently formed source signal line 4 to overlap the pixel electrode line 3.
  • the signal can be conducted through the pixel electrode line 3 below the broken source signal line 4.
  • the above improved technical solution may cause an increase in the coupling capacitance of the TFT array substrate, resulting in an increase in power consumption of the TFT array substrate.
  • the present invention provides a method for fabricating a TFT array substrate, a TFT array substrate, and a display device, without increasing the coupling capacitance of the TFT array substrate. Solve the problem that the signal caused by the break of the source signal line cannot be transmitted.
  • a first aspect of the present invention provides a method of fabricating a TFT array substrate, the method comprising: sequentially forming a transparent conductive layer and a source/drain metal layer on a base substrate; and the source/drain metal layer and the transparent The conductive layer performs a patterning process to form overlapping source signal lines and pixel electrode lines.
  • the overlapping source signal lines and the pixel electrode lines are formed, When the source signal line is broken, the signal can be conducted through the pixel electrode line below the broken source signal line. Moreover, the source signal line and the pixel electrode line are formed by one patterning process, so there is no problem of alignment deviation between the two, the two can just overlap, there is no misalignment, and the width of the source signal line is still The original width is such that the distance between the source signal line and the pixel electrode does not increase, and the coupling capacitance generated between the two does not increase.
  • a second aspect of the present invention provides a TFT array substrate including overlapping pixel electrode lines and source signal lines, the pixel electrode lines and the source signal lines being under the same patterning process form.
  • the TFT array substrate can solve the problem that the source signal line breaks without increasing the coupling capacitance. The problem caused by the signal cannot be transmitted.
  • a third aspect of the invention provides a display device comprising the TFT array substrate provided by the second aspect of the invention.
  • the above display device includes the TFT array substrate provided by the second aspect of the present invention, the above display device has the same advantageous effects as the TFT array substrate, and details are not described herein again.
  • FIG. 1 is a cross-sectional structural view of a TFT array substrate in the prior art
  • 3'-pixel electrode 30-transparent conductive layer; 4-source signal line;
  • 5-source drain protection layer 60-photoresist; 61-first photoresist layer;
  • the prior art in which the pixel electrode line 3 is disposed under the source signal line 4 cannot solve the problem that the signal caused by the breakage of the source signal line 4 cannot be transmitted.
  • the main reason for the above problems is that the pixel electrode line 3 and the source signal line 4 are respectively formed in two patterning processes. In the patterning process of the source/drain metal layer, the mask needs to be combined with the pixel. The electrode line 3 is aligned.
  • the alignment is prone to deviation, and the formed source signal line 4 cannot overlap with the pixel electrode line 3, and there is a misalignment between the two, which is equivalent to The width of the source signal line 4 is increased, causing the spacing between the source signal line 4 and the pixel electrode 3' to decrease. Since the size of the capacitor is inversely proportional to the spacing between the two plates, the spacing between the source signal line 4 and the pixel electrode 3' is reduced, resulting in coupling between the source signal line 4 and the pixel electrode 3'. The capacitance increases, which in turn causes an increase in power consumption of the TFT array substrate.
  • Step S1 sequentially forming a transparent conductive layer and a source/drain metal layer on the base substrate;
  • Step S2 performing a patterning process on the source/drain metal layer and the transparent conductive layer to form overlapping source signal lines and pixel electrode lines.
  • the source signal lines and the pixel electrode lines that overlap each other are formed, and when the source signal lines are broken, the signals can be conducted through the pixel electrode lines 3 under the broken source signal lines.
  • the source signal line and the pixel electrode line are formed by one patterning process, so there is no problem of alignment deviation between the source signal line and the pixel electrode line, and the two can just overlap, there is no misalignment, and thus no increase
  • the width of the large source signal line does not reduce the distance between the source signal line and the pixel electrode, and the coupling capacitance generated between the two does not increase, and the power consumption of the TFT array substrate does not increase.
  • step S1 is to sequentially form a transparent conductive layer 30 and a source/drain metal layer 40 on the base substrate 1.
  • the material of the transparent conductive layer 30 may be a metal oxide transparent conductive material such as ITO (Indium Tin Oxide). Tin), the formation of the transparent conductive layer 30 and the source/drain metal layer 40 may employ a sputtering process.
  • the manufacturing method of the TFT array substrate provided in this embodiment is further before step S1.
  • the method may include the steps of forming a gate electrode, a gate protection layer, and an active layer.
  • the steps may be: forming a gate metal layer on the substrate substrate, patterning the gate metal layer to form a gate;
  • a gate protective layer 2 is formed on the base substrate (as shown in FIG. 2);
  • a semiconductor layer is formed on the gate protective layer 2, and a semiconductor layer is patterned to form an active layer.
  • step S2 may include the following steps:
  • Step S21 As shown in FIG. 3, a photoresist 60 is coated on the source/drain metal layer 40.
  • the photoresist 60 can be applied by a spin coating process, and the photoresist 60 is preferably a photoresist having high viscosity, good uniformity, and high sensitivity to light.
  • the photoresist 60 may be a positive photoresist, which forms a soluble substance after exposure, or may be a negative photoresist, and forms an insoluble substance after exposure. This embodiment is described by taking the photoresist 60 as a negative photoresist as an example.
  • Step S22 As shown in FIG. 4, the applied photoresist 60 is exposed by using a mask 70 having a full light transmission pattern 71, a partial light transmission pattern 72, and a light shielding pattern 73 to form a first photoresist layer 61. And the second photoresist layer 62, the first photoresist layer 61 covers the region where the source signal line is to be formed, and the second photoresist layer 62 covers the region where the pixel electrode is to be formed, and the thickness of the first photoresist layer 61 It is larger than the thickness of the second photoresist layer 62.
  • the fully transparent pattern 71 of the mask 70 should be aligned with the region where the source signal line is to be formed, and in addition, the source to be formed should be aligned.
  • the area and the area where the drain is to be formed, the partial light-transmissive pattern 72 should be aligned with the area where the pixel electrode is to be formed, and the light-shielding pattern 73 should be aligned with the area except the source signal line to be formed, the area where the source is to be formed, and the drain to be formed.
  • the glue layer 61 covers a region where the source signal line is to be formed, a region where the source is to be formed, and a region where the drain is to be formed; the photoresist in the region where the pixel electrode is to be formed becomes partially soluble, thereby being partially retained, forming a second photoresist layer 62; all of the photoresist in the region except the region where the source signal line is to be formed, the region where the source is to be formed, the region where the drain is to be formed, and the region where the pixel electrode is to be formed become all Dissolved and thus completely removed.
  • the partial light transmissive pattern 72 described above may be a semi-transmissive pattern.
  • Step S23 As shown in FIG. 5, using the first photoresist layer 61 and the second photoresist layer 62 as a mask, the source/drain metal layer and the transparent conductive layer not covered by the photoresist are removed, and the source is to be formed.
  • the overlapping source signal line 4 and the pixel electrode line 3 are formed in the region of the pole signal line, and the pixel electrode 3' is formed in the region where the pixel electrode is to be formed, and the pixel electrode 3' is covered by the source/drain metal layer, that is, FIG.
  • the source/drain metal layer and the transparent conductive layer not covered by the photoresist may be removed by a wet etching process.
  • the source signal line 4 and the pixel electrode line 3 overlap, when the source signal line 4 is broken, the source and the source are The pixel electrode line 3 in which the signal lines 4 are overlapped can electrically connect both ends of the source signal line 4 to be well connected to ensure smooth signal conduction. Moreover, since the source signal line 4 and the pixel electrode line 3 are formed under the same patterning process, the source signal line 4 and the pixel electrode line 3 can be just overlapped, and there is no misalignment between the two, and the width of the source signal line 4 is not The increase is such that the distance between the source signal line 4 and the pixel electrode 3' is not reduced, the coupling capacitance generated between the two is not increased, and the power consumption of the TFT array substrate is not increased.
  • step S23 the source and the drain are formed simultaneously with the source signal line 4, and the pixel electrode 3' is formed simultaneously with the pixel electrode line 3. It can be seen that the patterning process and the transparent of the source/drain metal layer in this embodiment are transparent. The patterning process of the conductive layer is combined into one, which saves the number of patterning, thereby simplifying the manufacturing steps and improving the performance of the TFT array substrate.
  • Step S24 As shown in FIG. 6, the second photoresist layer 62 is removed to expose the source/drain metal layer covering the pixel electrode 4'.
  • the second photoresist layer 62 may be removed by an ashing process. Since the thickness of the first photoresist layer 61 is greater than the thickness of the second photoresist layer 62, the first photoresist layer 61 still has a certain thickness when the second photoresist layer 62 is completely ashed.
  • Step S25 As shown in FIG. 7, the exposed source/drain metal layer 4' is removed by using the first photoresist layer 61 as a mask.
  • the exposed source/drain metal layer 4' may be removed by a wet etching process.
  • Step S26 As shown in FIG. 8, the first photoresist layer 61 is removed.
  • the first photoresist layer 61 may be removed by a lift-off process.
  • a source/drain protection layer 5 may be formed on the base substrate to protect the lower pixel electrode 3', the source metal line 4, the source and the drain, and make them The subsequently formed film or component is electrically insulated. Further, after the source/drain protective layer 5 is formed, a common electrode may be formed on the source/drain protective layer 5 to form an electric field with the pixel electrode 3'.
  • This embodiment further provides a TFT array substrate.
  • the TFT array substrate includes overlapping pixel electrode lines 3 and source signal lines 4, and the pixel electrode lines 3 and the source signal lines 4 are at the same time. Formed under the patterning process.
  • the pixel electrode line 3 located below it can electrically connect the two ends of the source signal line 4 to be broken, and the electrical connection is good. To ensure the smooth transmission of the signal. Moreover, since the pixel electrode line 3 and the source signal line 4 of the TFT array substrate are formed under the same patterning process, the formation of the pixel electrode line 3 and the source signal line 4 by using the two patterning processes separately is avoided.
  • the problem of the alignment error enables the pixel electrode line 3 and the source signal line 4 to be Good overlap, no misalignment, so that the width of the source signal line 4 does not increase, the distance between the source signal line 4 and the pixel electrode 3' does not decrease, and the coupling capacitance generated between the two does not Increasing, the power consumption of the TFT array substrate does not increase.
  • the TFT array substrate further includes a pixel electrode 3', and the pixel electrode 3', the pixel electrode line 3, and the source signal line 4 are formed under the same patterning process. Further, the pixel electrode 3', the pixel electrode line 3, and the source signal line 4 are formed under the same patterning process, and further include a source and a drain. It can be seen that, in this embodiment, the patterning process for forming the pixel electrode 3' and the pixel electrode line 3 and the patterning process for forming the source signal line 4, the source and the drain are combined into one, saving one patterning. Process, which is beneficial to improve the performance of the TFT array substrate.
  • the present embodiment also provides a display device including the above TFT array substrate.
  • the above-mentioned TFT array substrate can solve the problem that the signal caused by the breakage of the source signal line cannot be transmitted without increasing the coupling capacitance of the TFT array substrate, so that the display device provided by the embodiment can be displayed at the time of display. Affected by the breakage of the source signal line, it has a small coupling capacitance.
  • the display device provided in this embodiment may be of a liquid crystal type, an OLED (Organic Light-Emitting Diode) type or an electronic paper type, and is suitable for mobile phones, tablet computers, televisions, displays, and notebooks. Any product or component that has a display function, such as a computer, digital photo frame, and navigator.
  • OLED Organic Light-Emitting Diode

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Abstract

一种TFT阵列基板的制造方法、TFT阵列基板及显示装置，涉及显示技术领域，能够在不增加TFT阵列基板的耦合电容的前提下，解决源极信号线断裂所引起的信号无法传输的问题。TFT阵列基板的制造方法包括：在衬底基板上依次形成透明导电层和源漏金属层；对源漏金属层和透明导电层进行一次构图工艺，形成相重叠的源极信号线和像素电极线。

Description

TFT阵列基板的制造方法、TFT阵列基板及显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT(Thin Film Transistor，薄膜晶体管)阵列基板的制造方法、TFT阵列基板及显示装置。
背景技术
TFT阵列基板是显示装置的重要组成部件。TFT阵列基板通常包括衬底基板，及设置于衬底基板上的栅极、栅极保护层、有源层、像素电极、源极、漏极、源极信号线和源漏极保护层，其中，像素电极由透明导电层经构图工艺形成，源极、漏极和源极信号线由源漏金属层经构图工艺形成，透明导电层位于源漏金属层的下方。
由于受到源漏金属层的构图工艺的前道工艺和后道工艺，及源漏金属层的构图工艺中涂胶不均匀等因素的影响，源极信号线容易发生断裂，导致信号无法传输。如图1所示，现有技术中为解决源极信号线4断裂所引起的信号无法传输的问题，在透明导电层的构图工艺中，与像素电极3′同步形成了像素电极线3，该像素电极线3位于待形成源极信号线的位置，从而使后续形成的源极信号线4与该像素电极线3重叠。当源极信号线4发生断裂时，信号能够通过断裂的源极信号线4下方的像素电极线3进行传导。
但是，在上述改善的技术方案的实际应用过程中，上述改善的技术方案会引起TFT阵列基板的耦合电容增加，导致TFT阵列基板的功耗增加。
发明内容
为至少部分地克服上述现有技术中的缺陷和/或不足，本发明提供一种TFT阵列基板的制造方法、TFT阵列基板及显示装置，以在不增加TFT阵列基板的耦合电容的前提下，解决源极信号线断裂所引起的信号无法传输的问题。
为达到上述目的，本发明采用如下技术方案：
本发明的第一方面提供了一种TFT阵列基板的制造方法，所述制造方法包括：在衬底基板上依次形成透明导电层和源漏金属层；对所述源漏金属层和所述透明导电层进行一次构图工艺，形成相重叠的源极信号线和像素电极线。
上述TFT阵列基板的制造方法中，形成了相重叠源极信号线和像素电极线，在 源极信号线发生断裂时，信号能够通过断裂的源极信号线下方的像素电极线进行传导。并且，源极信号线和像素电极线利用一次构图工艺形成，因此二者之间不存在对位偏差的问题，二者能够刚好重叠，不存在错位，相当于源极信号线的宽度仍为其本身原有的宽度，从而源极信号线与像素电极之间的距离不会增大，二者之间所产生的耦合电容不会增加。
本发明的第二方面提供了一种TFT阵列基板，所述TFT阵列基板包括相重叠的像素电极线和源极信号线，所述像素电极线和所述源极信号线在同一次构图工艺下形成。
由于上述TFT阵列基板的像素电极线和源极信号线相重叠，并且二者在同一次构图工艺下形成，因此该TFT阵列基板实现了在不增加耦合电容的前提下，解决源极信号线断裂所引起的信号无法传输的问题。
本发明的第三方面提供了一种显示装置，所述显示装置包括本发明的第二方面所提供的TFT阵列基板。
由于上述显示装置包括本发明的第二方面所提供的TFT阵列基板，因此上述显示装置具有与该TFT阵列基板相同的有益效果，在此不再赘述。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为现有技术中的TFT阵列基板的截面结构图；
图2～图9为本发明实施例所提供的TFT阵列基板的制造方法的各步骤图。
附图标记说明：
1-衬底基板；           2-栅极保护层；           3-像素电极线；
3′-像素电极；         30-透明导电层；          4-源极信号线；
4′-覆盖像素电极的源漏金属层；40-源漏金属层；
5-源漏极保护层；       60-光刻胶；              61-第一光刻胶层；
62-第二光刻胶层；      70-掩膜版；              71-全透光图形；
72-部分透光图形；      73-遮光图形。
具体实施方式
如背景技术所述，现有技术中在源极信号线4的下方设置像素电极线3的技术方案不能很好地解决源极信号线4断裂所引起的信号无法传输的问题。经过大量的研究和实验发现，产生上述问题的主要原因是：像素电极线3和源极信号线4分别在两次构图工艺中形成，在源漏金属层的构图工艺中，掩膜需要与像素电极线3进行对位，由于构图工艺的局限性，因此对位时容易出现偏差，造成所形成的源极信号线4不能与像素电极线3刚好重叠，二者之间存在错位，这相当于增加了源极信号线4的宽度，造成源极信号线4与像素电极3′之间的间距减小。由于电容的大小与两极板之间的间距呈反比，因此源极信号线4与像素电极3′之间的间距减小，会导致源极信号线4与像素电极3′之间所产生的耦合电容增大，进而造成TFT阵列基板的功耗增加。
基于此，提出一种TFT阵列基板的制造方法，该制造方法包括以下步骤：
步骤S1：在衬底基板上依次形成透明导电层和源漏金属层；
步骤S2：对源漏金属层和透明导电层进行一次构图工艺，形成相重叠的源极信号线和像素电极线。
上述TFT阵列基板的制造方法中，形成了相重叠的源极信号线和像素电极线，在源极信号线发生断裂时，信号能够通过断裂的源极信号线下方的像素电极线3进行传导。并且，源极信号线和像素电极线利用一次构图工艺形成，因此源极信号线和像素电极线之间不存在对位偏差的问题，二者能够刚好重叠，不存在错位，也就不会增大源极信号线的宽度，从而不会减小源极信号线与像素电极之间的距离，二者之间所产生的耦合电容不会增加，进而TFT阵列基板的功耗不会增加。
为使本发明所提出的上述技术方案的目的、特征和优点能够更加明显易懂，下面将结合附图，对上述技术方案的实施例进行清楚、完整地描述。显然，所描述的实施例仅仅是上述技术方案的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本发明保护的范围。
参见图2，步骤S1为在衬底基板1上依次形成透明导电层30和源漏金属层40，透明导电层30的材料可为金属氧化物透明导电材料，如ITO(Indium Tin Oxide，氧化铟锡)，形成透明导电层30和源漏金属层40可采用溅射工艺。
需要说明的是，本实施例所提供的TFT阵列基板的制造方法，在步骤S1之前还 可包括形成栅极、栅极保护层和有源层的步骤，这些步骤具体可为：在衬底基板上形成栅极金属层，对栅极金属层进行构图工艺，形成栅极；在具有栅极的衬底基板上形成栅极保护层2(如图2所示)；在栅极保护层2上形成半导体层，对半导体层进行构图工艺，形成有源层。
参见图3～图8，步骤S2可包括以下步骤：
步骤S21：如图3所示，在源漏金属层40上涂覆光刻胶60。
涂覆光刻胶60可采用旋涂工艺，光刻胶60优选粘度高、均匀性好、对光的敏感度高的光刻胶。光刻胶60可为正性光刻胶，曝光后形成可溶物质，也可为负性光刻胶，曝光后形成不可溶物质。本实施例以光刻胶60为负性光刻胶为例进行说明。
步骤S22：如图4所示，采用具有全透光图形71、部分透光图形72和遮光图形73的掩膜版70对所涂覆的光刻胶60曝光，形成第一光刻胶层61和第二光刻胶层62，第一光刻胶层61覆盖待形成源极信号线的区域，第二光刻胶层62覆盖待形成像素电极的区域，第一光刻胶层61的厚度大于第二光刻胶层62的厚度。
对于光刻胶60为负性光刻胶的情况，进行曝光前，掩膜版70的全透光图形71应对准待形成源极信号线的区域，除此之外还应对准待形成源极的区域和待形成漏极的区域，部分透光图形72应对准待形成像素电极的区域，遮光图形73应对准除待形成源极信号线的区域、待形成源极的区域、待形成漏极的区域和待形成像素电极的区域外的区域。曝光后，待形成源极信号线的区域和待形成源极和漏极的区域内的光刻胶变得不可溶，从而被完全保留，形成第一光刻胶层61，因此第一光刻胶层61覆盖待形成源极信号线的区域、待形成源极的区域和待形成漏极的区域；待形成像素电极的区域内的光刻胶变得部分可溶，从而被部分保留，形成第二光刻胶层62；除待形成源极信号线的区域、待形成源极的区域、待形成漏极的区域和待形成像素电极的区域外的区域内的光刻胶全部变得可溶，从而被全部去除。
上述的部分透光图形72可为半透光图形。
步骤S23：如图5所示，以第一光刻胶层61和第二光刻胶层62为掩膜，去除未被光刻胶覆盖的源漏金属层和透明导电层，在待形成源极信号线的区域内形成相重叠的源极信号线4和像素电极线3，并在待形成像素电极的区域内形成像素电极3′，像素电极3′被源漏金属层覆盖，即图5中的覆盖像素电极3′的源漏金属层4′。
在上述步骤S23中，可采用采用湿法刻蚀工艺去除未被光刻胶覆盖的源漏金属层和透明导电层。
由于源极信号线4和像素电极线3重叠，因此在源极信号线4断裂时，与源极 信号线4重叠的像素电极线3能够将源极信号线4断裂的两端良好地电连接起来，保证信号顺利传导。并且，由于源极信号线4和像素电极线3在同一构图工艺下形成，因此源极信号线4和像素电极线3能够刚好重叠，二者之间没有错位，源极信号线4的宽度没有增大，从而源极信号线4与像素电极3′之间的距离没有减小，二者之间所产生的耦合电容没有增加，TFT阵列基板的功耗没有增加。
需要说明的是，在步骤S23中，源极和漏极与源极信号线4同时形成，像素电极3′与像素电极线3同时形成，可见本实施例将源漏金属层的构图工艺和透明导电层的构图工艺合二为一，节省了构图次数，从而简化了制造步骤，有利于提高TFT阵列基板的性能。
步骤S24：如图6所示，去除第二光刻胶层62，使覆盖像素电极的源漏金属层暴露4′。
在上述步骤S24中，可采用灰化工艺去除第二光刻胶层62。由于第一光刻胶层61的厚度大于第二光刻胶层62的厚度，因此当第二光刻胶层62被完全灰化去除时，第一光刻胶层61仍有一定的厚度。
步骤S25：如图7所示，以第一光刻胶层61为掩膜，去除暴露的源漏金属层4′。
在上述步骤S25中，可采用湿法刻蚀工艺去除暴露的源漏金属层4′。
步骤S26：如图8所示，去除第一光刻胶层61。
在上述步骤S26中，可采用剥离工艺去除第一光刻胶层61。
完成步骤S26后，如图9所示，可在衬底基板上形成源漏极保护层5，以保护下方的像素电极3′、源极金属线4、源极和漏极，并使它们与后续形成的膜层或元件电性绝缘。此外，在形成源漏极保护层5后，还可在源漏极保护层5上形成公共电极，以与像素电极3′形成电场。
本实施例还提供了一种TFT阵列基板，如图9所示，该TFT阵列基板包括相重叠的像素电极线3和源极信号线4，像素电极线3和源极信号线4在同一次构图工艺下形成。
由于源极信号线4和像素电极线3重叠，因此在源极信号线4断裂时，位于其下方的像素电极线3能够将源极信号线4断裂的两端电连接起来，且电连接良好，保证了信号的顺利传导。并且，由于该TFT阵列基板的像素电极线3和源极信号线4在同一次构图工艺下形成，因此避免了单独采用两次构图工艺分别形成像素电极线3和源极信号线4所引起的对位误差的问题，使得像素电极线3和源极信号线4能够刚 好重叠，不存在错位，从而源极信号线4的宽度不会增大，源极信号线4与像素电极3′之间的距离不会减小，二者之间所产生的耦合电容不会增加，TFT阵列基板的功耗不会增加。
上述TFT阵列基板还包括像素电极3′，该像素电极3′、像素电极线3和源极信号线4在同一次构图工艺下形成。此外，与像素电极3′、像素电极线3和源极信号线4在同一次构图工艺下形成的还包括源极和漏极。可见，本实施例中，将用于形成像素电极3′和像素电极线3的构图工艺和用于形成源极信号线4、源极和漏极的构图工艺合二为一，节省了一次构图工艺，这有利于提高TFT阵列基板的性能。
本实施还提供了一种显示装置，该显示装置包括上述TFT阵列基板。由于上述TFT阵列基板能够在不增加TFT阵列基板的耦合电容的前提下，解决源极信号线断裂所引起的信号无法传输的问题，因此使得本实施例所提供的显示装置既能够在显示时不受源极信号线断裂的影响，又具有较小的耦合电容。
需要说明的是，本实施例所提供的显示装置的类型可为液晶型、OLED(Organic Light-Emitting Diode，有机发光二极管)型或电子纸型，适用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种TFT阵列基板的制造方法，所述制造方法包括：
    在衬底基板上依次形成透明导电层和源漏金属层；
    对所述源漏金属层和所述透明导电层进行一次构图工艺，形成相重叠的源极信号线和像素电极线。
  2. 根据权利要求1所述的TFT阵列基板的制造方法，其中，所述对所述源漏金属层和所述透明导电层进行一次构图工艺，形成相重叠的源极信号线和像素电极线的步骤包括：
    在所述源漏金属层上涂覆光刻胶；
    采用具有全透光图形、部分透光图形和遮光图形的掩膜版对所涂覆的光刻胶曝光，形成第一光刻胶层和第二光刻胶层，所述第一光刻胶层覆盖待形成源极信号线的区域，所述第二光刻胶层覆盖待形成像素电极的区域，所述第一光刻胶层的厚度大于所述第二光刻胶层的厚度；
    以所述第一光刻胶层和所述第二光刻胶层为掩膜，去除未被光刻胶覆盖的源漏金属层和透明导电层，在所述待形成源极信号线的区域内形成相重叠的源极信号线和像素电极线，并在所述待形成像素电极的区域内形成像素电极，所述像素电极被源漏金属层覆盖；
    去除所述第二光刻胶层，使覆盖所述像素电极的源漏金属层暴露；
    以所述第一光刻胶层为掩膜，去除暴露的源漏金属层；
    去除所述第一光刻胶层。
  3. 根据权利要求1或2所述的TFT阵列基板的制造方法，其中，所述第一光刻胶层还覆盖待形成源极的区域和待形成漏极的区域。
  4. 根据权利要求2所述的TFT阵列基板的制造方法，其中，所述掩膜版所具有的部分透光图形为半透光图形。
  5. 根据权利要求2所述的TFT阵列基板的制造方法，其中，所述去除未被光刻胶覆盖的源漏金属层和透明导电层的步骤为：采用湿法刻蚀工艺去除未被光刻胶覆盖的源漏金属层和透明导电层。
  6. 根据权利要求5所述的TFT阵列基板的制造方法，其中，所述去除所述第二 光刻胶层的步骤为：采用灰化工艺去除所述第二光刻胶层。
  7. 根据权利要求6所述的TFT阵列基板的制造方法，其中，
    所述去除暴露的源漏金属层的步骤为：采用湿法刻蚀工艺去除暴露的源漏金属层。
  8. 根据权利要求7所述的TFT阵列基板的制造方法，其中，
    所述去除所述第一光刻胶层的步骤为：采用剥离工艺去除所述第一光刻胶层。
  9. 根据权利要求1-8中任一项所述的TFT阵列基板的制造方法，其中，形成所述透明导电层和所述源漏金属层采用溅射工艺。
  10. 根据权利要求1～9中任一项所述的TFT阵列基板的制造方法，其中，所述制造方法在形成所述透明导电层之前还包括：
    在衬底基板上形成栅极金属层，对所述栅极金属层进行构图工艺，形成栅极；
    在具有所述栅极的衬底基板上形成栅极保护层；
    在所述栅极保护层上形成半导体层，对所述半导体层进行构图工艺，形成有源层。
  11. 一种TFT阵列基板，所述TFT阵列基板是根据权利要求1-10中任一项所述的TFT阵列基板，其中所述TFT阵列基板包括相重叠的像素电极线和源极信号线，所述像素电极线和所述源极信号线在同一次构图工艺下形成。
  12. 根据权利要求11所述的TFT阵列基板，其中，所述TFT阵列基板还包括像素电极，所述像素电极、所述像素电极线和所述源极信号线在同一次构图工艺下形成。
  13. 一种显示装置，所述显示装置包括如权利要求11或12所述的TFT阵列基板。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040180480A1 (en) * 2003-03-14 2004-09-16 Fujitsu Display Technologies Corporation Thin film transistor substrate and method for fabricating the same
CN101350330A (zh) * 2008-09-05 2009-01-21 上海广电光电子有限公司 薄膜晶体管阵列基板及其制造方法
CN102709237A (zh) * 2012-03-05 2012-10-03 京东方科技集团股份有限公司 薄膜场效应晶体管阵列基板及其制造方法、电子器件
CN102779785A (zh) * 2012-07-25 2012-11-14 京东方科技集团股份有限公司 有机薄膜晶体管阵列基板及其制备方法和显示装置
CN105140181A (zh) * 2015-09-21 2015-12-09 京东方科技集团股份有限公司 Tft阵列基板的制造方法、tft阵列基板及显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3614684C1 (de) * 1986-04-30 1987-06-11 Du Pont Deutschland Photographische Masken fuer die Tonwertkorrektur
JPH02109341A (ja) * 1988-10-19 1990-04-23 Fuji Xerox Co Ltd 薄膜トランジスタの製造方法
JPH08313394A (ja) * 1995-05-23 1996-11-29 Fujikura Ltd 光スイッチ
KR101125254B1 (ko) * 2004-12-31 2012-03-21 엘지디스플레이 주식회사 프린지 필드 스위칭 타입의 박막 트랜지스터 기판 및 그제조 방법과, 그를 이용한 액정 패널 및 그 제조 방법
US7952099B2 (en) * 2006-04-21 2011-05-31 Beijing Boe Optoelectronics Technology Co., Ltd. Thin film transistor liquid crystal display array substrate
KR101183361B1 (ko) * 2006-06-29 2012-09-14 엘지디스플레이 주식회사 액정 표시 장치용 어레이 기판 및 그 제조 방법
TW202429692A (zh) * 2006-09-29 2024-07-16 日商半導體能源研究所股份有限公司 半導體裝置
KR20090075554A (ko) * 2008-01-04 2009-07-08 삼성전자주식회사 액정 표시 장치와 그 제조 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040180480A1 (en) * 2003-03-14 2004-09-16 Fujitsu Display Technologies Corporation Thin film transistor substrate and method for fabricating the same
CN101350330A (zh) * 2008-09-05 2009-01-21 上海广电光电子有限公司 薄膜晶体管阵列基板及其制造方法
CN102709237A (zh) * 2012-03-05 2012-10-03 京东方科技集团股份有限公司 薄膜场效应晶体管阵列基板及其制造方法、电子器件
CN102779785A (zh) * 2012-07-25 2012-11-14 京东方科技集团股份有限公司 有机薄膜晶体管阵列基板及其制备方法和显示装置
CN105140181A (zh) * 2015-09-21 2015-12-09 京东方科技集团股份有限公司 Tft阵列基板的制造方法、tft阵列基板及显示装置

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