WO2016197692A1 - 阵列基板、其制备方法及显示装置 - Google Patents

阵列基板、其制备方法及显示装置 Download PDF

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Publication number
WO2016197692A1
WO2016197692A1 PCT/CN2016/079035 CN2016079035W WO2016197692A1 WO 2016197692 A1 WO2016197692 A1 WO 2016197692A1 CN 2016079035 W CN2016079035 W CN 2016079035W WO 2016197692 A1 WO2016197692 A1 WO 2016197692A1
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common electrode
electrode
line
array substrate
substrate
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PCT/CN2016/079035
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English (en)
French (fr)
Inventor
严允晟
林允植
崔贤植
李会
田允允
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京东方科技集团股份有限公司
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Priority to US15/306,879 priority Critical patent/US10139685B2/en
Publication of WO2016197692A1 publication Critical patent/WO2016197692A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136218—Shield electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
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    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device.
  • the instantaneous electromagnetic signal caused by the change of the voltage of the data line with time generally affects the stability of the pixel electrode and the common electrode voltage, that is, the electric field generated by the data line causes crosstalk to the pixel electrode and the common electrode, which affects The voltage difference between the pixel electrode and the common electrode, thereby affecting the display quality of the array substrate.
  • Embodiments of the present invention provide an array substrate, a method for fabricating the same, and a display device, which can solve the problem that the common electrode is susceptible to crosstalk of the data line and the common electrode voltage is unstable, thereby affecting the image quality of the entire array substrate.
  • an array substrate comprising: a substrate substrate; a plurality of gate lines and a plurality of data lines on the substrate substrate and defining a plurality of pixel regions; a pixel electrode and a common electrode, each located at each The pixel electrode and the common electrode are disposed in different layers; and a shielding electrode is formed on the substrate substrate at least corresponding to the data line, the shielding electrode and the common The electrode is disposed in a different layer and is electrically connected to the pixel electrode and the common electrode.
  • a display device comprising the array substrate of any of the first aspects is provided.
  • a third aspect provides a method for fabricating an array substrate, comprising: forming a first conductive layer pattern on a substrate, the first conductive layer pattern including a common electrode located in a pixel region; forming a first conductive layer a patterned insulating layer; a second conductive layer pattern is formed on the insulating layer, the second conductive layer pattern includes a pixel electrode and a shield electrode electrically connected to each other, the pixel electrode being located in the pixel region, The shielding electrode is formed at least on a region of the substrate substrate corresponding to the data line, and is electrically connected to the common electrode.
  • 1 is a schematic cross-sectional structural view of an array substrate
  • FIG. 2 is a schematic cross-sectional structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional structural view of another array substrate according to an embodiment of the present invention.
  • FIG. 4 is a top plan view of a portion of an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a flowchart of a method for preparing an array substrate according to an embodiment of the present invention.
  • FIG. 6 is a flow chart of another method for fabricating an array substrate according to an embodiment of the present invention.
  • the same layer setting means that at least two patterns are located on the same bearing surface.
  • the heterogeneous setting means that the two patterns are on different bearing surfaces, and usually there are other layers spaced between the two patterns.
  • the shield electrodes provided corresponding to the data line regions are used to shield the crosstalk of the data lines.
  • the array substrate may include a base substrate 01, a data line 02 disposed on the base substrate 01, a thin film transistor 03, and a pixel electrode 04 connected to the drain electrode 03a of the thin film transistor 03, facing the pixel electrode 04.
  • the common electrode 05 is provided, and the shield electrode 06 is provided corresponding to the data line 02.
  • the shielding electrode 06 is disposed in the same layer as the common electrode 05, And electrically connected.
  • the electric field formed by the data line affects the voltage of the shield electrode such that the voltage of the shield electrode is unstable
  • the shield electrode since the shield electrode is electrically connected to the common electrode, the voltage of the common electrode is also As the shielding electrode changes together, the common electrode voltage of the entire array substrate is unstable, and thus the voltage difference between the pixel electrode and the common electrode changes, thereby affecting the image quality of the entire array substrate.
  • An embodiment of the present invention provides an array substrate, as shown in FIG. 2, comprising a substrate substrate 01, a plurality of gate lines and data lines 02 on the substrate substrate and defining a pixel region, and further comprising: pixels located in the pixel region
  • the electrode 04 and the common electrode 05, the pixel electrode 04 and the common electrode 05 are disposed in different layers; the shield electrode 06, the shield electrode 06 is formed at least on the area of the corresponding substrate 02 on the corresponding substrate 02, and the shield electrode 06 and the common electrode 05 are disposed in different layers. And electrically connected to the pixel electrode 04 and the common electrode 05.
  • the structure of the array substrate is not limited thereto.
  • the array substrate shown in FIG. 2 the array substrate may further include: a thin film transistor 03 and a gate insulating layer 07 disposed on the base substrate 01. And an insulating layer 08.
  • the thin film transistor 03 includes a drain electrode 03a, a source electrode 03b, a gate electrode 03c, and an active layer 03d which are provided on the base substrate 01.
  • the pixel electrode 04 is electrically connected to the drain electrode 03a through the via 09, the data line 02 is disposed in the same layer as the drain electrode 03a and the source electrode 03b, and is electrically connected to the source electrode 03b, and the common electrode 05 and the pixel electrode 04 are disposed opposite to each other.
  • a gate line (not shown in FIG. 2) is disposed in the same layer as the gate 03c and is electrically connected.
  • FIG. 2 the structure added in FIG. 2 is only for the purpose of more clearly describing the solution of the embodiment of the present invention, and is not limited by the scope of the claimed invention.
  • the array substrate may be an array substrate in an advanced super-dimensional field switching (ADS) type display device; in the ADS array substrate, the common electrode and the pixel electrode are disposed on the same substrate And one of the electrodes is a flat electrode and the other electrode is a comb or a pinned electrode.
  • ADS advanced super-dimensional field switching
  • a pixel electrode and a common electrode disposed in different layers may be included, which means that the pixel electrode and the common electrode are located on different bearing surfaces.
  • the common electrode 05 is located above the gate insulating layer 07, and the pixel electrode 04 is located above the insulating layer 08.
  • the pixel electrode 04 and the common electrode 05 are electrically connected.
  • the pixel electrode 04 and the common electrode 05 are separated by an insulating layer 08, and the insulating layer 08 may be made of an insulating material such as silicon oxide, silicon nitride or an organic material.
  • the insulating layer 08 can be referred to as a passivation layer.
  • the electrodes adjacent to the substrate in the pixel electrode 04 and the common electrode 05 are flat, and the electrodes away from the substrate are comb-shaped or electrodes with nips.
  • the common electrode located near the substrate substrate and above the gate insulating layer is a flat electrode, and the pixel electrode located away from the substrate substrate and above the insulating layer is a comb electrode.
  • the above non-electrical connection means that there is no electrical connection between at least two conductive patterns.
  • the above-mentioned shielding electrode is formed at least on the corresponding substrate on the substrate substrate, and the area where the positive projection of the data line on the substrate substrate is located overlaps with the area where the projection electrode is projected on the substrate.
  • the shield electrode formed in the region of the corresponding substrate on the substrate substrate is electrically connected to the common electrode, when the crosstalk of the data line to the shield electrode is such that the voltage of the shield electrode is unstable, The voltage of the common electrode does not change with the change of the voltage of the shield electrode. Therefore, the common electrode electrically connected to the shield electrode varies with the voltage of the shield electrode, and the common electrode can be easily interfered by the crosstalk of the data line to cause common The electrode voltage is unstable, which affects the image quality of the entire array substrate.
  • the shield electrode and the common electrode are disposed in the same layer on the basis of the non-electrical connection between the shield electrode and the common electrode, the spacing between the common electrode and the shield electrode is ensured in order to ensure the aperture ratio.
  • the common electrode and the shielding electrode are easily mis-contacted and electrically connected, so that the common electrode is easily interfered by the data line and the voltage is unstable, thereby affecting the image quality of the entire array substrate.
  • the non-electrically connected shielding electrode and the common electrode are disposed in different layers, which can avoid the problem of easy mis-contact during the same layer setting, thereby ensuring the stability of the common voltage and ensuring the display quality of the array substrate.
  • the shield electrode and the common electrode are electrically connected, in order to avoid light leakage, a voltage signal identical to the voltage of the common electrode is usually applied to the shield electrode.
  • the shielding electrode and the pixel electrode may be disposed in the same layer.
  • the meaning that the shielding electrode and the pixel electrode are disposed in the same layer means that the shielding electrode and the pixel electrode are located on the same bearing surface.
  • the shield electrode 06 and the pixel electrode 04 Both are located above the insulating layer 08. Since the shield electrode 06 and the pixel electrode 04 which are disposed in the same layer and are both electrodes can be made of the same material, for example, a transparent conductive material such as Indium Tin Oxide (ITO), they can be fabricated together by the same patterning process.
  • ITO Indium Tin Oxide
  • different patterns may be obtained by one patterning of the same transparent conductive film layer, the different patterns including the shield electrode and the pixel electrode, thereby simplifying the structure of the array substrate and the process of preparing the process.
  • the shielding electrode 06 and the pixel electrode 04 can also be disposed in the same layer and different materials, which are not limited herein.
  • the spacing between the shielding electrode and the pixel electrode should not be too large, so that the shielding electrode and the pixel electrode may also be electrically connected due to false contact. Case.
  • the voltage of the pixel electrode electrically connected to the shield electrode also changes with the change of the shield voltage, thereby affecting the image quality of the pixel unit.
  • the shielding electrode is disposed in the same layer as the pixel electrode, and the shielding electrode is in the same layer as the common electrode.
  • the setting is more to ensure the image quality of the array substrate, and thus is a more optimized structural design.
  • the common electrode and the data line may be disposed in the same layer.
  • the common electrode 05 and the data line 02 are both located on the gate insulating layer.
  • the data line is usually made of a metal material such as Al (aluminum), Mo (molybdenum), Cr (chromium), Cu (copper), or Ti (titanium)
  • the common electrode is usually made of ITO or the like, that is, a common electrode and a data line.
  • the materials used are usually different and cannot be fabricated together in the same patterning process.
  • the common electrode and the data line are disposed in the same layer to save the process of making the spacer insulating layer between the common electrode and the data line when the different layer is set.
  • the structure of the array substrate and the process of preparing the process can be simplified.
  • the arrangement of the insulating layer between the common electrode and the data line is reduced, the entire array substrate is thinner than the prior art, which is advantageous for thinning and thinning of the display device.
  • the shielding electrode is disposed in the same layer as the pixel electrode, and the common electrode and the data line are disposed in the same layer to increase the spacing between the pixel electrode and the data line, and reduce the coupling capacitance between the pixel electrode and the data line, thereby reducing The effect of a small coupling capacitor on the pixel electrode voltage and display quality.
  • the source and the drain may be disposed in the same layer as the data line and the common electrode.
  • the width of the shield electrode may be greater than the width of the data line. That is, the area where the orthographic projection of the shielding electrode on the substrate substrate is located may be larger than the area where the orthographic projection of the data line on the substrate substrate is located, so that the shielding electrode can better shield the electric field formed by the data line, thereby reducing the data line. Crosstalk.
  • the width of the shield electrode may also be equal to the width of the data line, or slightly smaller than the width of the data line, and only the shielding effect of the shield electrode on the electric field formed by the data line is slightly worse than the above case.
  • the shield electrode may also be formed on a region of the corresponding substrate line on the substrate substrate, that is, an area where the orthographic projection of the gate line on the substrate substrate is located and an orthographic projection of the shield electrode on the substrate substrate.
  • the regions have overlap; for example, the boundary of the orthographic projection of the gate lines on the substrate substrate is located inside the boundary of the orthographic projection of the shield electrodes on the substrate substrate, and of course there may be partial boundaries coincident.
  • the area where the positive projection of the shield electrode on the base substrate is located may be larger than the area where the data line and the gate line as a whole are orthographically projected on the base substrate, that is, the data line and the gate line as a whole are on the substrate.
  • the boundary of the orthographic projection on the substrate is located inside the boundary of the orthographic projection of the shield electrode on the substrate, or a partial boundary coincides, so that the data line and the electric field formed by the gate line can be simultaneously shielded from other wirings on the array substrate such as the common electrode. Crosstalk with the pixel electrode.
  • the embodiment of the present invention provides an array substrate. Since the shield electrode formed in at least the corresponding data line on the substrate substrate is electrically connected to the common electrode, the crosstalk of the data line to the shield electrode makes the shield electrode When the voltage is unstable, the voltage of the common electrode does not change with the change of the voltage of the shield electrode. Therefore, the common electrode electrically connected to the shield electrode varies with the voltage of the shield electrode, and the common electrode can be easily affected by the data line.
  • the crosstalk causes the common electrode voltage to be unstable, thereby affecting the image quality of the entire array substrate.
  • An embodiment of the present invention provides an array substrate, as shown in FIG. 3, comprising a substrate substrate 01, a plurality of gate lines and data lines 02 on the substrate substrate and defining pixel regions, and further comprising: pixels located in the pixel region
  • the electrode 04 and the common electrode 05, the pixel electrode 04 and the common electrode 05 are disposed in different layers; the shield electrode 06, the shield electrode 06 is formed at least on the area of the corresponding substrate 02 on the corresponding substrate 02, and the shield electrode 06 and the common electrode 05 are disposed in different layers. And electrically connected to the pixel electrode 04 and the common electrode 05.
  • the structure of the array substrate is not limited thereto.
  • the array substrate shown in FIG. 3 the array substrate can also be The thin film transistor 03, the gate insulating layer 07, and the insulating layer 08 are disposed on the base substrate 01.
  • the thin film transistor 03 includes a drain electrode 03a, a source electrode 03b, a gate electrode 03c, and a photo substrate 01.
  • the source layer 03d is electrically connected to the drain electrode 03a
  • the data line 02 is disposed in the same layer as the drain electrode 03a and the source electrode 03b, and is electrically connected to the source electrode 03b
  • the common electrode 05 and the pixel electrode 04 are disposed opposite to each other.
  • a gate line (not shown in FIG. 3) is disposed in the same layer as the gate 03c and is electrically connected.
  • FIG. 3 the structure added in FIG. 3 is only for the purpose of more clearly describing the solution of the embodiment of the present invention, and is not limited by the scope of the claimed invention.
  • the shielding electrode and the pixel electrode may be disposed in the same layer.
  • the array substrate provided by the embodiment of the present invention may further include a common electrode line (not shown in FIG. 3 ), the common electrode is disposed in the same layer as the common electrode line, and the common electrode line is electrically connected to the common electrode.
  • the common electrode and the common electrode line are disposed in the same layer, and the common electrode and the common electrode line are located on the same bearing surface.
  • the common electrode and the common electrode line may be located on the base substrate, and the lining The base substrate is in direct contact.
  • the common electrode needs to be supplied with a voltage required for normal operation through the common electrode line, and thus the common electrode must be electrically connected to the common electrode line.
  • the common electrode and the common electrode line need not be connected through the via hole, thereby saving the process flow for making the via hole and simplifying the process.
  • the structure of the array substrate by arranging the common electrode and the common electrode line in the same layer, the common electrode and the common electrode line need not be connected through the via hole, thereby saving the process flow for making the via hole and simplifying the process.
  • the common electrode and the common electrode line are disposed in the same layer, for example, since the common electrode is usually made of a material such as ITO, the common electrode line is usually Al (aluminum), Mo (molybdenum), Cr (chromium), or Cu (copper). Metal materials such as Ti (titanium), that is, the materials used for the common electrode and the common electrode line are usually different, and are usually not fabricated together in the same patterning process.
  • the common electrode and the data line are designed in the same layer, and the common electrode and the common electrode line are disposed in the same layer to simplify the structure and process preparation process of the array, and the display device is light and thin.
  • the common electrode and the common electrode line disposed in the same layer may be connected by a metal line, such that the metal line is disposed in the same layer as the common electrode and the common electrode line.
  • the metal lines can be made of the same material as the common electrode lines and fabricated together with the common electrode lines.
  • the common electrode and the common electrode disposed in the same layer may also be connected in other manners.
  • the metal wire connection is only an example.
  • array substrates also have large-sized and small-sized array substrates corresponding to large-sized display products (such as televisions) and small-sized display products (such as mobile phones).
  • the resistance of the large-sized array substrate is large, and connecting the common electrode in the array substrate to the common electrode line through the via hole cannot ensure the stability of the common electrode voltage, and the common electrode is usually through the metal line and the common The electrode wires are connected to ensure the stability of the common electrode voltage, and thus the large-sized array substrate is generally constructed as shown in FIG.
  • the common electrode, the common electrode line, the gate line and the gate may be disposed in the same layer.
  • the common electrode and the data line are arranged in the same layer, which simplifies the structure of the array and the process of preparing the process, and is advantageous for thinning and thinning of the display device.
  • the metal line when a metal line is included in the array substrate, the metal line may be disposed in the same layer as the common electrode, the common electrode line, the gate line, and the gate.
  • a partial structure top view of an array substrate provided by an embodiment of the present invention is used to indicate the relative positions of the gate electrode 03c, the gate line 10, the common electrode line 11, the metal line 12, and the common electrode 05.
  • the gate electrode 03c and the common electrode 05 in Figs. 2 and 3 are obtained by cross-sectional view in Fig. 4A-A.
  • other structures such as pixel electrodes are not shown in FIG.
  • the embodiment of the present invention provides an array substrate. Since the shield electrode formed in at least the corresponding data line on the substrate substrate is electrically connected to the common electrode, the crosstalk of the data line to the shield electrode makes the shield electrode When the voltage is unstable, the voltage of the common electrode does not change with the change of the voltage of the shield electrode. Therefore, the common electrode electrically connected to the shield electrode varies with the voltage of the shield electrode, and the common electrode can be easily affected by the data line.
  • the crosstalk causes the common electrode voltage to be unstable, thereby affecting the image quality of the entire array substrate.
  • the embodiment of the invention further provides a display device, which comprises the array substrate provided in the first embodiment and the second embodiment.
  • the display device may be a display device such as a liquid crystal display, an electronic paper, an Organic Light-Emitting Diode (OLED) display, or any display-enabled product such as a television, a digital camera, a mobile phone, a tablet computer, or the like including the display device.
  • a display device such as a liquid crystal display, an electronic paper, an Organic Light-Emitting Diode (OLED) display, or any display-enabled product such as a television, a digital camera, a mobile phone, a tablet computer, or the like including the display device.
  • OLED Organic Light-Emitting Diode
  • the shield electrode formed in the region of the substrate substrate corresponding to the data line is electrically connected to the common electrode, when the crosstalk of the data line to the shield electrode is such that the voltage of the shield electrode is unstable, The voltage of the common electrode does not change with the change of the voltage of the shield electrode. Therefore, the common electrode electrically connected to the shield electrode varies with the voltage of the shield electrode, and the common electrode can be easily interfered by the crosstalk of the data line to cause common The electrode voltage is unstable, which affects the image quality of the entire array substrate.
  • the embodiment of the invention provides a method for preparing an array substrate in the first embodiment.
  • the main steps may include:
  • first conductive layer pattern on the base substrate, the first conductive layer pattern including a common electrode located in the pixel region.
  • the base substrate may be made of Corning, Asahi Glass, quartz glass or the like.
  • the first conductive layer pattern is generally formed by a patterning process, and the so-called patterning process may include a process of film formation, exposure, development, and the like, and may of course further include etching, stripping, and the like.
  • the patterning process is not limited thereto, as long as the process of forming the first conductive layer pattern on the substrate substrate is within the protection scope of the embodiment of the present invention.
  • the first conductive layer pattern may further include a data line, a source, and a drain disposed in the same layer as the common electrode.
  • the common electrode is usually a transparent material
  • the data line, the source and the drain are usually the same metal material.
  • the first conductive layer includes a transparent conductive film and a metal thin film formed in sequence.
  • the first conductive layer comprises a transparent conductive film and a metal thin film formed in sequence.
  • a photoresist is formed on the first conductive layer, and the first conductive layer is exposed, developed, etched or the like by using a halftone or gray scale mask to obtain a first conductive layer pattern.
  • the data line, the source and the drain formed by this process may comprise two layers, one being a transparent conductive pattern close to the base substrate and the other being a metal pattern on the transparent conductive pattern.
  • the transparent conductive film can
  • the metal film may be Al, Mo, Cr, Cu, Ti or the like.
  • the second step and the step 101 may be performed by using two mask patterning processes, and may include: (1) forming a transparent conductive film on the substrate; and then obtaining a common electrode by a glue coating, a mask exposure, a development, and an etching process. The pattern retains an unremoved photoresist on the pattern of the common electrode. (2) Forming a metal thin film on the base substrate on which the common electrode is formed, and obtaining a pattern of the data line, the source, and the drain by a glue coating, a mask exposure, a development, and an etching process.
  • the pattern of the data line, the source and the drain, and the photoresist on the pattern of the common electrode are stripped by a lift-off process to obtain a common electrode, a data line, a source, and a drain including the same layer.
  • a conductive layer pattern is
  • the photoresist on the pattern of the common electrode in the step (1) is not removed, the photoresist can protect the common electrode from being not in the step (2). Etching.
  • the mask used may be a normal mask (ie, a mask including only a light-transmitting, opaque region).
  • a normal mask ie, a mask including only a light-transmitting, opaque region.
  • the third step and the step 101 may be performed by using two mask patterning processes, and may include: (1) forming a metal thin film on the substrate; and then obtaining a data line and a source by a glue coating, a mask exposure, a development, and an etching process. The pattern of the poles and the drains, the unremoved photoresist remains on the pattern of the data lines, the source and the drain. (2) A transparent conductive film is formed on the base substrate on which the patterns of the data lines, the source and the drain are formed, and a pattern of the common electrode is obtained by a glue coating, a mask exposure, a development, and an etching process.
  • the pattern of the common electrode and the photoresist on the pattern of the data line, the source and the drain are peeled off by a lift-off process, thereby obtaining a pattern of the common electrode, the data line, the source, and the drain including the same layer.
  • the first conductive layer pattern is
  • step (2) when the step (2) is performed, since the photoresist on the data line, the source and the drain in the step (1) is not removed, the photoresist can protect the data line and the source.
  • the pole and drain are not etched in step (2).
  • the formed first conductive layer pattern includes the common electrode, the data line, the source and the drain provided in the same layer, it is possible to save the need for setting the common electrode and the data line, the source and the drain.
  • the insulating layer simplifies the structure of the array substrate and the process of preparing the process, and is advantageous for thinning and thinning of the display device.
  • the insulating layer here may be an insulating material such as silicon oxide, silicon nitride or an organic material.
  • the second conductive layer pattern includes a pixel electrode and a shield electrode electrically connected to each other, the pixel electrode is located in the pixel region, and the shield electrode is formed on at least the corresponding data line on the base substrate The area is electrically connected to the common electrode.
  • the formed second conductive layer pattern includes pixel electrodes and shield electrodes that are electrically connected to each other, that is, the pixel electrodes are disposed in the same layer as the shield electrodes, and thus can be simplified compared with the pixel electrodes and the shield electrodes.
  • the insulating layer in step 102 may be the insulating layer 08 in FIG. 2, and the drain electrode 03a is connected to the pixel electrode 04 through the via 09 on the insulating layer 08.
  • the width of the shield electrode may be greater than the width of the data line, so that the crosstalk of the data line signal can be better shielded.
  • the shield electrode may also be formed on a region of the substrate substrate corresponding to the gate line to facilitate crosstalk of the shielded gate line signal.
  • the common electrode in the first conductive layer pattern and the shield electrode in the second conductive layer pattern are electrically connected, and thus the data line is shielded from the electrode.
  • the crosstalk causes the voltage of the shield electrode to be unstable, the voltage of the common electrode does not change with the change of the voltage of the shield electrode, and thus the common electrode electrically connected to the shield electrode varies with the voltage of the shield electrode, and can solve the common problem.
  • the electrodes are susceptible to crosstalk of the data lines, causing the common electrode voltage to be unstable, thereby affecting the image quality of the entire array substrate.
  • the embodiment of the invention provides a method for preparing an array substrate in the second embodiment.
  • the main steps may include:
  • first conductive layer pattern on the base substrate, the first conductive layer pattern including a common electrode located in the pixel region.
  • the first conductive layer pattern may further include a common electrode line disposed in the same layer as the common electrode, and/or a gate line, a gate, and/or a common electrode and a common electrode line.
  • the common electrode is usually a transparent conductive material, and the common electrode line, the gate line, the gate, and the metal line are usually the same metal material.
  • the first conductive layer pattern includes a common layer set
  • the electrode, the common electrode line, the gate line, the gate, and the metal line the step 201 can be implemented by using any one of the following solutions:
  • the first conductive layer includes a transparent conductive film and a metal thin film formed in sequence.
  • the first conductive layer comprises a transparent conductive film and a metal thin film formed in sequence.
  • a photoresist is formed on the first conductive layer, and the first conductive layer is exposed, developed, etched or the like by using a halftone or gray scale mask to obtain a first conductive layer pattern.
  • the common electrode lines, the gate lines, the gate electrodes and the metal lines formed by the process comprise two layers, one layer is a transparent conductive pattern close to the base substrate, and the other layer is located on the transparent conductive pattern.
  • the transparent conductive film may be a material such as ITO, and the metal film may be a material such as Al, Mo, Cr, Cu, or Ti.
  • the second step and the step 201 may be performed by using two mask patterning processes, and may include: (1) forming a transparent conductive film on the substrate; and then obtaining a common electrode by a glue coating, a mask exposure, a development, and an etching process. The pattern retains an unremoved photoresist on the pattern of the common electrode. (2) A metal thin film is formed on the base substrate on which the common electrode is formed, and patterns of the common electrode lines, the gate lines, the gate electrodes, and the metal lines are obtained by a glue coating, a mask exposure, a development, and an etching process.
  • the common electrode line, the gate line, the gate, the pattern of the metal line, and the photoresist on the pattern of the common electrode are stripped by a lift-off process, thereby obtaining a common electrode, a common electrode line, and a gate line including the same layer. a first conductive layer pattern of the gate and the metal line.
  • the photoresist on the pattern of the common electrode in the step (1) is not removed, the photoresist can protect the common electrode from being not in the step (2). Etching.
  • the mask used may be a normal mask (ie, a mask including only a light-transmitting, opaque region).
  • a normal mask ie, a mask including only a light-transmitting, opaque region.
  • the third step and the step 201 may be performed by using two mask patterning processes, and may include: (1) forming a metal thin film on the base substrate; and then obtaining a common electrode line by applying a glue, mask exposure, development, and etching process, A pattern of gate lines, gate lines, and metal lines, on which the unremoved photoresist remains on the pattern of the common electrode lines, the gate lines, the gate electrodes, and the metal lines. (2) A transparent conductive film is formed on the base substrate on which the patterns of the common electrode lines, the gate lines, the gate electrodes, and the metal lines are formed, and the pattern of the common electrode is obtained by a glue coating, a mask exposure, development, and an etching process. After that, it will be passed through the stripping process.
  • the photoresist of the common electrode line, the gate line, the gate electrode and the metal line in the step (1) is not removed, the photoresist can be protected.
  • the common electrode line, the gate line, the gate, and the metal line are not etched in the step (2).
  • the formed first conductive layer pattern includes a common electrode and a common electrode line disposed in the same layer, and/or a gate line, a gate, and/or a metal line for connecting the common electrode and the common electrode line.
  • the common electrode and the common electrode line are disposed in the same layer, so that the common electrode and the common electrode line disposed in the same layer do not need to be connected through the via hole, thereby simplifying the structure of the array substrate; and the common electrode and the common electrode line, and/ Or a gate line, a gate, and/or a metal line for connecting the common electrode and the common electrode line in the same layer, which can save the insulating layer required for the different layer arrangement, further simplify the structure and process flow, and facilitate display
  • the device is light and thin.
  • the first insulator layer herein can be mainly used to insulate the first conductive layer pattern from other conductive patterns, and an insulating material such as silicon oxide, silicon nitride or organic material can be used.
  • the data lines, the source and the drain of the same layer in the third conductive layer pattern may be the same material, and thus may be completed by the same patterning process.
  • the second insulator layer herein can be mainly used to insulate the third conductive layer pattern from the second conductive layer pattern, and an insulating material such as silicon oxide, silicon nitride or organic material can be used.
  • the second conductive layer pattern includes a pixel electrode and a shield electrode electrically connected to each other, the pixel electrode is located in the pixel region, and the shield electrode is formed on the substrate substrate at least The area of the data line and is electrically connected to the common electrode.
  • the common electrode and the shielding electrode disposed in the same layer in the second conductive layer pattern may be the same material, and thus may be completed by the same patterning process.
  • the structure of the array substrate obtained by the preparation method provided by the embodiment of the present invention can be seen in FIG. 3 , wherein the first insulating layer can be the gate insulating layer 07 in FIG. 3 , The second insulator layer may be the insulating layer 08 of FIG. 2, and the pixel electrode is connected to the drain electrode 03a through the via 09 on the second insulator layer.
  • the first insulating layer can be the gate insulating layer 07 in FIG. 3
  • the second insulator layer may be the insulating layer 08 of FIG. 2
  • the pixel electrode is connected to the drain electrode 03a through the via 09 on the second insulator layer.
  • the common electrode in the first conductive layer pattern and the shield electrode in the second conductive layer pattern are electrically connected, and thus the data line is shielded from the electrode.
  • the crosstalk causes the voltage of the shield electrode to be unstable, the voltage of the common electrode does not change with the change of the voltage of the shield electrode, and thus the common electrode electrically connected to the shield electrode varies with the voltage of the shield electrode, and can solve the common problem.
  • the electrodes are susceptible to crosstalk of the data lines, causing the common electrode voltage to be unstable, thereby affecting the image quality of the entire array substrate.

Abstract

一种阵列基板、其制备方法及显示装置。该阵列基板包括：衬底基板(01)；多条栅线(10)和多条数据线(02)，位于所述衬底基板(01)上且界定多个像素区域；像素电极(04)和公共电极(05)，位于每个所述像素区域内且所述像素电极(04)和所述公共电极(05)异层设置；以及屏蔽电极(06)，形成在所述衬底基板(01)上至少对应于所述数据线(02)的区域中，所述屏蔽电极(06)与所述公共电极(05)异层设置，且与所述像素电极(04)、所述公共电极(05)无电性连接。该方案能够解决公共电极容易受到数据线的串扰而导致公共电极电压不稳，从而影响整个阵列基板的画质的问题。

Description

阵列基板、其制备方法及显示装置 技术领域
本发明的实施例涉及一种阵列基板、其制备方法及显示装置。
背景技术
在阵列基板中，数据线的电压随时间的高低变化引起的瞬时电磁信号通常会影响像素电极和公共电极电压的稳定性，即数据线产生的电场对像素电极和公共电极产生了串扰，影响了像素电极与公共电极之间的电压差，从而影响了阵列基板的显示画质。
发明内容
本发明的实施例提供一种阵列基板、其制备方法及显示装置，能够解决公共电极容易受到数据线的串扰而导致公共电极电压不稳，从而影响整个阵列基板的画质的问题。
第一方面，提供了一种阵列基板，包括：衬底基板；多条栅线和多条数据线，位于所述衬底基板上且界定多个像素区域；像素电极和公共电极，位于每个所述像素区域内且所述像素电极和所述公共电极异层设置；以及屏蔽电极，形成在所述衬底基板上至少对应于所述数据线的区域中，所述屏蔽电极与所述公共电极异层设置，且与所述像素电极、所述公共电极无电性连接。
第二方面，提供一种显示装置，包括第一方面任一项所述的阵列基板。
第三方面，提供一种阵列基板的制备方法，包括：在衬底基板上形成第一导电层图案，所述第一导电层图案包括位于像素区域的公共电极；形成覆盖所述第一导电层图案的绝缘层；在所述绝缘层上形成第二导电层图案，所述第二导电层图案包括相互无电性连接的像素电极和屏蔽电极，所述像素电极位于所述像素区域内，所述屏蔽电极至少形成于所述衬底基板上对应数据线的区域，且与所述公共电极无电性连接。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种阵列基板的剖面结构示意图；
图2为本发明实施例提供的一种阵列基板的剖面结构示意图；
图3为本发明实施例提供的另一种阵列基板的剖面结构示意图；
图4为本发明实施例提供的一种阵列基板中部分结构俯视图；
图5为本发明实施例提供的一种阵列基板的制备方法流程图；
图6为本发明实施例提供的另一种阵列基板的制备方法流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明实施例的描述中，需要理解的是，术语“上”、“下”、“内”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明实施例和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明实施例的限制。
需要的说明的是，在本发明所有实施例中，同层设置是指：至少两个图案位于同一承载面上。异层设置是指：两个图案位于不同的承载面上，通常两个图案之间间隔有其他层。
为了尽量减小数据线的串扰引起的画质问题，采用对应数据线区域设置的屏蔽电极来屏蔽数据线的串扰。如图1所示，阵列基板可以包括衬底基板01、设置在衬底基板01上数据线02、薄膜晶体管03，与薄膜晶体管03的漏极03a连接的像素电极04，与像素电极04对向设置的公共电极05，与数据线02对应设置的屏蔽电极06。其中，屏蔽电极06与公共电极05同层设置， 且电性连接。
在图1所示结构的阵列基板中，当数据线形成的电场对屏蔽电极的电压造成影响使得屏蔽电极的电压不稳时，由于屏蔽电极与公共电极电性连接，因而公共电极的电压也会随着屏蔽电极的变化而一起变化，则整个阵列基板的公共电极电压不稳，进而使得像素电极与公共电极之间的电压差发生变化，从而影响了整个阵列基板的画质。
实施例一
本发明实施例提供一种阵列基板，如图2所示，包括衬底基板01，位于衬底基板上且界定像素区域的多条栅线和数据线02，还包括：位于像素区域内的像素电极04和公共电极05，像素电极04和公共电极05异层设置；屏蔽电极06，屏蔽电极06至少形成于衬底基板01上对应数据线02的区域，屏蔽电极06与公共电极05异层设置，且与像素电极04、公共电极05无电性连接。
需要说明的是，以上仅是描述了如何解决“公共电极容易受到数据线的串扰而导致公共电极电压不稳，从而影响整个阵列基板的画质”的结构。然而，本领域技术人员能够知晓，阵列基板的结构不局限于此，例如在图2所示阵列基板中，阵列基板还可以包括:设置于衬底基板01上的薄膜晶体管03、栅绝缘层07以及绝缘层08。其中，薄膜晶体管03包括设置于衬底基板01上的漏极03a、源极03b、栅极03c和有源层03d。像素电极04通过过孔09与漏极03a电性连接，数据线02与漏极03a、源极03b同层设置，且与源极03b电性连接，公共电极05与像素电极04对向设置，栅线(未在图2中标示)与栅极03c同层设置且电性连接。
当然，图2中所增设的结构也仅是为了更加清楚的描述本发明实施例的方案才绘制的，并不作为本发明实施例请求保护的范围限定。
本发明实施例所涉及到阵列基板可以是高级超维场转换(ADvanced Super Dimension Switch，ADS)型显示装置中的阵列基板；在ADS阵列基板中，公共电极与像素电极设置在同一衬底基板上，且其中一个电极为平板状电极，另一个电极为梳状或带有夹缝的电极。
对于ADS阵列基板而言，可以包括异层设置的像素电极和公共电极，其含义是指：像素电极和公共电极位于不同的承载面上。示例性地，如图2 所示，公共电极05位于栅绝缘层07之上，像素电极04位于绝缘层08之上。其中，像素电极04和公共电极05是无电性连接的，图2中像素电极04和公共电极05间隔有绝缘层08，绝缘层08可以采用氧化硅、氮化硅及有机材料等绝缘材料，通常，可以把该绝缘层08称为钝化层。
其中，像素电极04和公共电极05中靠近衬底基板的电极是平板状的，远离衬底基板的电极是梳状的，或带有夹缝的电极。如图2所示，靠近衬底基板且位于栅绝缘层之上的公共电极为平板状电极，而远离衬底基板且位于绝缘层之上的像素电极为梳状电极。
上述的无电性连接是指：至少两个导电图案之间没有电连接。
上述的屏蔽电极至少形成于衬底基板上对应数据线的区域是指，数据线在衬底基板上的正投影所在的区域与屏蔽电极在衬底基板上的正投影所在的区域具有重叠。
上述阵列基板中，由于阵列基板中至少形成于衬底基板上对应数据线的区域的屏蔽电极与公共电极无电性连接，因而当数据线对屏蔽电极的串扰使得屏蔽电极的电压不稳时，公共电极的电压不会随着屏蔽电极电压的变化而变化，因而与屏蔽电极电性连接的公共电极会随着屏蔽电极的电压一起变化不同，能够解决公共电极容易受到数据线的串扰而导致公共电极电压不稳，从而影响整个阵列基板的画质的问题。
需要说明的是，在屏蔽电极与公共电极无电性连接的基础上，若将无电性连接的屏蔽电极和公共电极同层设置，则为了保证开口率，公共电极与屏蔽电极之间的间距通常较小，从而导致公共电极与屏蔽电极容易误接触而电性连接，从而会使得公共电极容易受到数据线的串扰而电压不稳，从而影响整个阵列基板的画质。本发明实施例将无电性连接的屏蔽电极与公共电极异层设置，可以避免同层设置时容易误接触的问题，从而保证了公共电压的稳定性，保证了阵列基板的显示画质。
可选的，虽然屏蔽电极与公共电极是无电性连接的，但为了避免发生漏光现象，通常在屏蔽电极上施加与公共电极的电压相同的电压信号。
在本发明实施例提供的上述阵列基板中，屏蔽电极与像素电极可以同层设置。其中，屏蔽电极与像素电极同层设置的含义是指：屏蔽电极与像素电极位于同一承载面上。示例性地，如图2所示，屏蔽电极06和像素电极04 均位于绝缘层08之上。由于同层设置且均为电极的屏蔽电极06和像素电极04可以采用同一材料，例如可以是氧化铟锡(Indium Tin Oxide，ITO)等透明导电材料，因而可以通过同一次构图工艺一起制作完成。示例性地，可以是由同一透明导电膜层经一次构图得到不同图案，该不同图案包括屏蔽电极和像素电极，从而简化了阵列基板的结构以及工艺制备流程。当然，屏蔽电极06和像素电极04还可以同层设置且采用不同材料，在此不做限定。
需要说明的是，为了保证一定的像素电极的覆盖面积及开口率，屏蔽电极与像素电极之间的间距也不能太大，从而屏蔽电极与像素电极之间也可能出现由于误接触从而电性连接的情况。此时，由于受到数据线串扰的影响，与屏蔽电极电性连接的像素电极的电压也会随着屏蔽电压的变化而变化，从而影响该像素单元的画质。但是，与将无电性连接的屏蔽电极与公共电极同层设置且出现误接触时影响整个阵列基板的画质相比，将屏蔽电极与像素电极同层设置比将屏蔽电极与公共电极同层设置更能保证阵列基板的画质，因而是更为优化的结构设计。
在本发明实施例中，可选的，公共电极与数据线可以同层设置，示例性地，可以参见图2，公共电极05与数据线02均位于栅绝缘层上。这样虽然数据线通常采用Al(铝)、Mo(钼)、Cr(铬)、Cu(铜)、Ti(钛)等金属材料，而公共电极通常采用ITO等材料，即公共电极与数据线所采用的材料通常不同，不能在同一次构图工艺中一起制作完成，但将公共电极与数据线同层设置可以节省异层设置时制作位于公共电极与数据线之间的间隔绝缘层的工艺流程，从而可以简化阵列基板的结构及工艺制备流程。并且，由于减少了公共电极与数据线之间绝缘层的设置，整个阵列基板相对现有技术会变薄，有利于显示装置的轻薄化。当然，在上述阵列基板中，将公共电极与数据线异层设置，也在本发明实施例的保护范围之内。
另外，将屏蔽电极与像素电极同层设置并将公共电极与数据线同层设置还可以增大像素电极与数据线之间的间距，减小像素电极与数据线之间的耦合电容，从而减小耦合电容对像素电极电压以及显示画质的影响。
进一步地，在本发明实施例提供的阵列基板中，也可以将源极、漏极与数据线以及公共电极同层设置。
示例性地，上述阵列基板中，屏蔽电极的宽度可以大于数据线的宽度， 即屏蔽电极在衬底基板上的正投影所在的区域可以大于数据线在衬底基板上的正投影所在的区域，以便屏蔽电极可以更好地屏蔽数据线形成的电场，从而减小数据线的串扰。当然，屏蔽电极的宽度也可以等于数据线的宽度，或者略小于数据线的宽度，仅是屏蔽电极对数据线形成的电场的屏蔽效果比以上情况略差。
进一步地，上述阵列基板中，屏蔽电极还可以形成于衬底基板上对应栅线的区域，即栅线在衬底基板上的正投影所在的区域与屏蔽电极在衬底基板上的正投影所在的区域具有交叠；例如，栅线在衬底基板上的正投影的边界位于屏蔽电极在衬底基板上的正投影的边界内侧，当然可以有部分边界重合。当屏蔽电极形成于衬底基板上对应栅线的区域时，还可以屏蔽栅线的电压信号随时间变化引起的瞬时电磁信号对像素电极和公共电极电压的干扰。更进一步地，屏蔽电极在衬底基板上的正投影所在的区域可以大于数据线和栅线作为整体在衬底基板上的正投影所在区域，也即，数据线和栅线作为整体在衬底基板上的正投影的边界位于屏蔽电极在衬底基板上的正投影的边界内侧，或有部分边界重合，从而可以同时屏蔽数据线以及栅线形成的电场对阵列基板上的其他布线例如公共电极和像素电极的串扰。
本发明实施例提供一种阵列基板，由于阵列基板中至少形成于衬底基板上对应数据线的区域的屏蔽电极与公共电极无电性连接，因而当数据线对屏蔽电极的串扰使得屏蔽电极的电压不稳时，公共电极的电压不会随着屏蔽电极电压的变化而变化，因而与屏蔽电极电性连接的公共电极会随着屏蔽电极的电压一起变化不同，能够解决公共电极容易受到数据线的串扰而导致公共电极电压不稳，从而影响整个阵列基板的画质的问题。
实施例二
本发明实施例提供一种阵列基板，如图3所示，包括衬底基板01，位于衬底基板上且界定像素区域的多条栅线和数据线02，还包括：位于像素区域内的像素电极04和公共电极05，像素电极04和公共电极05异层设置；屏蔽电极06，屏蔽电极06至少形成于衬底基板01上对应数据线02的区域，屏蔽电极06与公共电极05异层设置，且与像素电极04、公共电极05无电性连接。
上述仅介绍了解决“公共电极容易受到数据线的串扰而导致公共电极电 压不稳，从而影响整个阵列基板的画质”的问题的结构。然而，本领域技术人员能够知晓，阵列基板的结构不局限于此，例如在图3所示阵列基板中，阵列基板还可以包括:设置于衬底基板01上的薄膜晶体管03、栅绝缘层07以及绝缘层08。其中，薄膜晶体管03包括设置于衬底基板01上的漏极03a、源极03b、栅极03c和有源层03d。像素电极04与漏极03a电性连接，数据线02与漏极03a、源极03b同层设置，且与源极03b电性连接，公共电极05与像素电极04对向设置，栅线(未在图3中标示)与栅极03c同层设置且电性连接。
当然，图3中所增设的结构也仅是为了更加清楚的描述本发明实施例的方案才绘制的，并不作为本发明实施例请求保护的范围限定。
可选地，在本发明实施例提供的阵列基板中，屏蔽电极与像素电极可以同层设置。
需要说明的是，本发明实施例重点对与实施例一中不相同的部分进行详细描述，对于与实施例一相同的部分的解释可以参见实施例一中的具体描述，这里不再赘述。
可选的，本发明实施例提供的阵列基板还可以包括公共电极线(未在图3中标示)，公共电极与公共电极线同层设置，且公共电极线与公共电极电性连接。在本发明实施例中，公共电极与公共电极线是同层设置的，公共电极与公共电极线位于同一承载面上，例如，公共电极与公共电极线可以均位于衬底基板上，且与衬底基板直接接触。公共电极需要通过公共电极线为其提供正常工作所需要的电压，因而公共电极必须与公共电极线电性连接。在本发明实施例中，通过将公共电极和公共电极线同层设置，可以使得公共电极与公共电极线之间不需要通过过孔进行连接，从而节省了制作过孔的工艺流程，同时简化了阵列基板的结构。
在同层设置公共电极和公共电极线时，示例性地，由于公共电极通常采用ITO等材料，而公共电极线通常采用Al(铝)、Mo(钼)、Cr(铬)、Cu(铜)、Ti(钛)等金属材料，可就是说，公共电极与公共电极线所采用的材料通常不同，通常不在同一次构图工艺中一起制作完成。但与实施例一中将公共电极与数据线同层设计类似，将公共电极与公共电极线同层设置同样可以简化制作阵列的结构及工艺制备流程，且有利于显示装置的轻薄化。 当然，在上述阵列基板中，将公共电极与公共电极线异层设置，也在本发明实施例的保护范围之内。
可选地，在本发明实施例中，同层设置的公共电极与公共电极线之间可以通过金属线连接，这样金属线就与公共电极以及公共电极线同层设置。示例性地，金属线可以与公共电极线采用同种材料，且与公共电极线一起制作完成。当然，同层设置的公共电极与公共电极之间也可以采用其它方式进行连接，这里通过金属线连接仅是举例说明。
需要说明的是，在实际生产应用中，对应于大尺寸显示产品(例如电视)和小尺寸显示产品(例如手机)，阵列基板也有大尺寸和小尺寸阵列基板。与小尺寸阵列基板相比，大尺寸阵列基板的电阻较大，通过过孔将阵列基板中的公共电极与公共电极线相连将不能保证公共电极电压的稳定性，公共电极通常通过金属线与公共电极线连接，以保证公共电极电压的稳定性，因而大尺寸阵列基板通常采用如图3所示的结构。
进一步地，在本发明实施例提供的阵列基板中，公共电极、公共电极线、栅线与栅极可以同层设置。与实施例一中将公共电极和数据线同层设置类似，可以简化制作阵列的结构及工艺制备流程，且有利于显示装置的轻薄化。
此外，当阵列基板中包括金属线时，还可以将金属线与公共电极、公共电极线、栅线以及栅极同层设置。
示例性的，本发明实施例提供的一种阵列基板中部分结构俯视图，以表明栅极03c、栅线10、公共电极线11、金属线12以及公共电极05的相对位置，示意图可以参见图4，且图2、图3中的栅极03c和公共电极05是沿图4A-A向剖视得到的。另外，其他例如像素电极等结构并未在图4中绘出。
本发明实施例提供一种阵列基板，由于阵列基板中至少形成于衬底基板上对应数据线的区域的屏蔽电极与公共电极无电性连接，因而当数据线对屏蔽电极的串扰使得屏蔽电极的电压不稳时，公共电极的电压不会随着屏蔽电极电压的变化而变化，因而与屏蔽电极电性连接的公共电极会随着屏蔽电极的电压一起变化不同，能够解决公共电极容易受到数据线的串扰而导致公共电极电压不稳，从而影响整个阵列基板的画质的问题。
本发明实施例还提供了一种显示装置，包括上述实施例一和实施例二提供的阵列基板。
该显示装置可以为液晶显示器、电子纸、有机发光二极管(Organic Light-Emitting Diode，OLED)显示器等显示器件，以及包括这些显示器件的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件，其中的阵列基板的具体实施可以参照上述对阵列基板的描述，这里不再赘述。
上述显示装置中，由于阵列基板中至少形成于衬底基板上对应数据线的区域的屏蔽电极与公共电极无电性连接，因而当数据线对屏蔽电极的串扰使得屏蔽电极的电压不稳时，公共电极的电压不会随着屏蔽电极电压的变化而变化，因而与屏蔽电极电性连接的公共电极会随着屏蔽电极的电压一起变化不同，能够解决公共电极容易受到数据线的串扰而导致公共电极电压不稳，从而影响整个阵列基板的画质的问题。
实施例三
本发明实施例提供一种实施例一中阵列基板的制备方法，参见图5，主要步骤可以包括：
101、在衬底基板上形成第一导电层图案，第一导电层图案包括位于像素区域的公共电极。
其中，衬底基板可以为康宁、旭硝子玻璃、石英玻璃等材质。第一导电层图案通常通过构图工艺形成，所谓的构图工艺可以包括：成膜、曝光、显影等工艺，当然可以进一步包括刻蚀、剥离等工艺。在本发明实施例中，构图工艺并不限于此，只要在衬底基板上能够形成第一导电层图案的工艺均应在本发明实施例的保护范围内。
可选地，在步骤101中，第一导电层图案还可以包括与公共电极同层设置的数据线、源极和漏极。其中，公共电极通常为透明材料，而数据线、源极和漏极通常为同一金属材料。此时，步骤101可以采用以下任一种方案实现。
方案一、步骤101可以采用一次掩模构图工艺完成，可以包括：在衬底基板上形成第一导电层，该第一导电层包括：依次形成的透明导电薄膜、金属薄膜。之后，在第一导电层上形成光刻胶、对第一导电层采用半色调或灰度掩模板进行曝光、显影、刻蚀等工艺，得到第一导电层图案。采用这种工艺形成的数据线、源极、漏极可以包含两层，一层是靠近衬底基板的透明导电图案，另一层是位于透明导电图案上的金属图案。其中，透明导电薄膜可 以是ITO等材料，金属薄膜可以是Al、Mo、Cr、Cu、Ti等材料。
方案二、步骤101可以采用两次掩模构图工艺完成，可以包括：(1)在衬底基板上形成透明导电薄膜；之后，通过涂胶、掩模曝光、显影、刻蚀工艺得到公共电极的图案，该公共电极的图案上保留有未去除的光刻胶。(2)在形成了公共电极的衬底基板上形成金属薄膜，并通过涂胶、掩模曝光、显影、刻蚀工艺得到数据线、源极、漏极的图案。之后，再通过剥离工艺将数据线、源极、漏极的图案，以及公共电极的图案上的光刻胶剥离，从而得到包含同层设置的公共电极、数据线、源极、漏极的第一导电层图案。
需要说明的是，在进行步骤(2)时，由于步骤(1)中公共电极的图案上的光刻胶并没有去除，因此，该光刻胶可以保护公共电极在步骤(2)中不被刻蚀。
另外，采用两次掩模构图工艺形成第一导电层图案的过程中，所使用的掩模板可以是普通掩模板(即仅包括透光、不透光区域的掩模板)。这种掩模板相对与半色调或灰度掩模版的造价相对较低，可以节约成本。
方案三、步骤101可以采用两次掩模构图工艺完成，可以包括：(1)在衬底基板上形成金属薄膜；之后，通过涂胶、掩模曝光、显影、刻蚀工艺得到数据线、源极、漏极的图案，该数据线、源极、漏极的图案上保留有未去除的光刻胶。(2)在形成了数据线、源极、漏极的图案的衬底基板上形成透明导电薄膜，并通过涂胶、掩模曝光、显影、刻蚀工艺得到公共电极的图案。之后，再通过剥离工艺将公共电极的图案，以及数据线、源极、漏极的图案上的光刻胶剥离，从而得到包含同层设置的公共电极、数据线、源极、漏极的图案的第一导电层图案。
与上述方案二同理，在进行步骤(2)时，由于步骤(1)中数据线、源极、漏极上的光刻胶并没有去除，因此，该光刻胶可以保护数据线、源极、漏极在步骤(2)中不被刻蚀。
在本步骤中，由于形成的第一导电层图案包括同层设置的公共电极、数据线、源极和漏极，因而可以节省将公共电极与数据线、源极和漏极异层设置时需要的绝缘层，从而简化了阵列基板的结构及工艺制备流程，且有利于显示装置的轻薄化。
102、形成覆盖第一导电层图案的绝缘层。
其中，这里的绝缘层可以采用氧化硅、氮化硅及有机材料等绝缘材料。
103、在绝缘层上形成第二导电层图案，第二导电层图案包括相互无电性连接的像素电极和屏蔽电极，像素电极位于像素区域内，屏蔽电极至少形成于衬底基板上对应数据线的区域，且与公共电极无电性连接。
在本步骤中，形成的第二导电层图案包括相互无电性连接的像素电极和屏蔽电极，即像素电极与屏蔽电极同层设置，因而与像素电极和屏蔽电极异层设置相比，可以简化阵列基板的结构及工艺制备流程。其中，在同层设置像素电极和屏蔽电极时，同为电极的像素电极与屏蔽电极可以为同一材料，因而可以通过同一次构图工艺一起制作完成。
示例性的，通过本发明实施例提供的方法制备获得的阵列基板的结构示意图可以参见图2。其中，步骤102中的绝缘层可以为图2中的绝缘层08，漏极03a与像素电极04通过绝缘层08上的过孔09相连。
进一步地，屏蔽电极的宽度可以大于数据线的宽度，从而能够更好地屏蔽数据线信号的串扰。屏蔽电极还可以形成于衬底基板上对应栅线的区域，以便于屏蔽栅线信号的串扰。
在本发明实施例提供的阵列基板的制备方法中，由于分别形成的第一导电层图案中的公共电极和第二导电层图案中的屏蔽电极无电性连接，因而当数据线对屏蔽电极的串扰使得屏蔽电极的电压不稳时，公共电极的电压不会随着屏蔽电极电压的变化而变化，因而与屏蔽电极电性连接的公共电极会随着屏蔽电极的电压一起变化不同，能够解决公共电极容易受到数据线的串扰而导致公共电极电压不稳，从而影响整个阵列基板的画质的问题。
实施例四
本发明实施例提供一种实施例二中阵列基板的制备方法，参见图6，主要步骤可以包括：
201、在衬底基板上形成第一导电层图案，第一导电层图案包括位于像素区域的公共电极。
可选地，在步骤201中，第一导电层图案还可以包括与公共电极同层设置的公共电极线，和/或栅线、栅极，和/或用以连接公共电极和公共电极线的金属线。其中，公共电极通常为透明导电材料，而公共电极线、栅线、栅极以及金属线通常为同一金属材料。以第一导电层图案包括同层设置的公共 电极、公共电极线、栅线、栅极以及金属线为例，步骤201可以采用以下任一种方案实现：
方案一、步骤201可以采用一次掩模构图工艺完成，可以包括：在衬底基板上形成第一导电层，该第一导电层包括：依次形成的透明导电薄膜、金属薄膜。之后，在第一导电层上形成光刻胶、对第一导电层采用半色调或灰度掩模板进行曝光、显影、刻蚀等工艺，得到第一导电层图案。需要强调的是，采用这种工艺形成的公共电极线、栅线、栅极以及金属线均包含两层，一层是靠近衬底基板的透明导电图案，另一层是位于透明导电图案上的金属图案。其中，透明导电薄膜可以是ITO等材料，金属薄膜可以是Al、Mo、Cr、Cu、Ti等材料。
方案二、步骤201可以采用两次掩模构图工艺完成，可以包括：(1)在衬底基板上形成透明导电薄膜；之后，通过涂胶、掩模曝光、显影、刻蚀工艺得到公共电极的图案，该公共电极的图案上保留有未去除的光刻胶。(2)在形成了公共电极的衬底基板上形成金属薄膜，并通过涂胶、掩模曝光、显影、刻蚀工艺得到公共电极线、栅线、栅极以及金属线的图案。之后，再通过剥离工艺将公共电极线、栅线、栅极、金属线的图案，以及公共电极的图案上的光刻胶剥离，从而得到包含同层设置的公共电极、公共电极线、栅线、栅极以及金属线的第一导电层图案。
需要说明的是，在进行步骤(2)时，由于步骤(1)中公共电极的图案上的光刻胶并没有去除，因此，该光刻胶可以保护公共电极在步骤(2)中不被刻蚀。
另外，采用两次掩模构图工艺形成第一导电层图案的过程中，所使用的掩模板可以是普通掩模板(即仅包括透光、不透光区域的掩模板)。这种掩模板相对与半色调或灰度掩模版的造价相对较低，可以节约成本。
方案三、步骤201可以采用两次掩模构图工艺完成，可以包括：(1)在衬底基板上形成金属薄膜；之后，通过涂胶、掩模曝光、显影、刻蚀工艺得到公共电极线、栅线、栅极以及金属线的图案，该公共电极线、栅线、栅极以及金属线的图案上保留有未去除的光刻胶。(2)在形成了公共电极线、栅线、栅极以及金属线的图案的衬底基板上形成透明导电薄膜，并通过涂胶、掩模曝光、显影、刻蚀工艺得到公共电极的图案。之后，再通过剥离工艺将 公共电极的图案，以及公共电极线、栅线、栅极以及金属线的图案上的光刻胶剥离，从而得到包含同层设置的公共电极、公共电极线、栅线、栅极以及金属线的图案的第一导电层图案。
与上述方案二同理，在进行步骤(2)时，由于步骤(1)中公共电极线、栅线、栅极以及金属线上的光刻胶并没有去除，因此，该光刻胶可以保护公共电极线、栅线、栅极以及金属线在步骤(2)中不被刻蚀。
在本步骤中，形成的第一导电层图案中包括同层设置的公共电极和公共电极线，和/或栅线、栅极，和/或用以连接公共电极和公共电极线的金属线，其中，公共电极与公共电极线同层设置可以使得同层设置的公共电极和公共电极线不需要通过过孔进行连接，从而简化了阵列基板的结构；而将公共电极和公共电极线，和/或栅线、栅极，和/或用以连接公共电极和公共电极线的金属线同层设置，可以节省异层设置时需要的绝缘层，进一步简化了结构和工艺制作流程，且有利于显示装置的轻薄化。
202、形成覆盖第一导电层图案的第一绝缘子层。
其中，这里的第一绝缘子层主要可以用于将第一导电层图案与其他导电图案绝缘，可以采用氧化硅、氮化硅及有机材料等绝缘材料。
203、在第一绝缘子层上形成第三导电层图案，第三导电层图案包括数据线、源极和漏极。
其中，第三导电层图案中同层设置的数据线、源极和漏极可以为同种材料，因而可以通过同一次构图工艺一起制作完成。
204、形成覆盖第三导电层图案的第二绝缘子层。
其中，这里的第二绝缘子层主要可以用于将第三导电层图案与第二导电层图案绝缘，可以采用氧化硅、氮化硅及有机材料等绝缘材料。
205、在第二绝缘子层上形成第二导电层图案，第二导电层图案包括相互无电性连接的像素电极和屏蔽电极，像素电极位于像素区域内，屏蔽电极至少形成于衬底基板上对应数据线的区域，且与公共电极无电性连接。
其中，第二导电层图案中同层设置的公共电极和屏蔽电极可以为同种材料，因而可以通过同一次构图工艺一起制作完成。
示例性的，根据本发明实施例提供的制备方法制备获得的阵列基板的结构示意图可以参见图3，其中，第一绝缘层可以为图3中的栅绝缘层07，第 二绝缘子层可以为图2中的绝缘层08，像素电极通过第二绝缘子层上的过孔09与漏极03a相连。
在本发明实施例提供的阵列基板的制备方法中，由于分别形成的第一导电层图案中的公共电极和第二导电层图案中的屏蔽电极无电性连接，因而当数据线对屏蔽电极的串扰使得屏蔽电极的电压不稳时，公共电极的电压不会随着屏蔽电极电压的变化而变化，因而与屏蔽电极电性连接的公共电极会随着屏蔽电极的电压一起变化不同，能够解决公共电极容易受到数据线的串扰而导致公共电极电压不稳，从而影响整个阵列基板的画质的问题。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
本申请要求于2015年6月11日递交的中国专利申请第201510320741.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (14)

  1. 一种阵列基板，包括：
    衬底基板；
    多条栅线和多条数据线，位于所述衬底基板上且界定多个像素区域；
    像素电极和公共电极，位于每个所述像素区域内且所述像素电极和所述公共电极异层设置；以及
    屏蔽电极，形成在所述衬底基板上至少对应于所述数据线的区域中，所述屏蔽电极与所述公共电极异层设置，且与所述像素电极、所述公共电极无电性连接。
  2. 根据权利要求1所述的阵列基板，其中所述屏蔽电极与所述像素电极同层设置。
  3. 根据权利要求2所述的阵列基板，其中所述公共电极与所述数据线同层设置。
  4. 根据权利要求2所述的阵列基板，还包括：公共电极线，所述公共电极与所述公共电极线同层设置，且所述公共电极线与所述公共电极电性连接。
  5. 根据权利要求4所述的阵列基板，其中所述公共电极线与所述公共电极电性连接包括：
    所述公共电极线与所述公共电极通过金属线电性连接。
  6. 根据权利要求4或5所述的阵列基板，其中所述公共电极、所述公共电极线、所述栅线与栅极同层设置。
  7. 根据权利要求1所述的阵列基板，其中所述屏蔽电极的宽度大于所述数据线的宽度。
  8. 根据权利要求1所述的阵列基板，其中所述屏蔽电极还形成于所述衬底基板上对应所述栅线的区域。
  9. 根据权利要求1所述的阵列基板，其中所述屏蔽电极的宽度等于或小于所述数据线的宽度。
  10. 一种显示装置，包括权利要求1-9中任一项所述的阵列基板。
  11. 一种阵列基板的制备方法，包括：
    在衬底基板上形成第一导电层图案，所述第一导电层图案包括位于像素 区域的公共电极；
    形成覆盖所述第一导电层图案的绝缘层；
    在所述绝缘层上形成第二导电层图案，所述第二导电层图案包括相互无电性连接的像素电极和屏蔽电极，所述像素电极位于所述像素区域内，所述屏蔽电极至少形成于所述衬底基板上对应数据线的区域，且与所述公共电极无电性连接。
  12. 根据权利要求11所述的制备方法，其中所述第一导电层图案还包括与所述公共电极同层设置的数据线、源极和漏极。
  13. 根据权利要求11所述的制备方法，其中所述第一导电层图案还包括与所述公共电极同层设置的公共电极线，和/或栅线、栅极，和/或用以连接所述公共电极和所述公共电极线的金属线。
  14. 根据权利要求13所述的制备方法，其中所述形成覆盖所述第一导电层图案的绝缘层包括：依次形成覆盖所述第一导电层图案的第一绝缘子层和第二绝缘子层；
    在形成所述第一绝缘子层之后，在形成所述第二绝缘子层之前，所述方法还包括：在所述第一绝缘子层上形成第三导电层图案，所述第三导电层图案包括数据线、源极和漏极。
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