WO2019091182A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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WO2019091182A1
WO2019091182A1 PCT/CN2018/101373 CN2018101373W WO2019091182A1 WO 2019091182 A1 WO2019091182 A1 WO 2019091182A1 CN 2018101373 W CN2018101373 W CN 2018101373W WO 2019091182 A1 WO2019091182 A1 WO 2019091182A1
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Prior art keywords
layer
photoresist
substrate
array substrate
forming
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PCT/CN2018/101373
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English (en)
French (fr)
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崔承镇
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京东方科技集团股份有限公司
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Priority to US16/335,085 priority Critical patent/US11437409B2/en
Priority to EP18855144.4A priority patent/EP3709355A4/en
Publication of WO2019091182A1 publication Critical patent/WO2019091182A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate

Definitions

  • At least one embodiment of the present disclosure is directed to an array substrate, a method of fabricating the same, and a display device.
  • HADS Advanced Advanced Super-Sensor Switching
  • organic film technology can significantly reduce the parasitic capacitance between the common electrode and the data line. This can reduce power consumption.
  • At least one embodiment of the present disclosure provides an array substrate, a method of fabricating the same, and a display device.
  • the array substrate includes: a base substrate including first and second surfaces opposite to each other; and a through hole penetrating the base substrate from the first surface to the second surface; a data line on the first surface of the substrate, the data line at least partially filling the via; a thin film transistor on the second surface of the base substrate, the thin film transistor including a source and a drain, The source is electrically connected to the data line.
  • the array substrate further includes: a common electrode on the second surface of the base substrate.
  • an orthographic projection of the data line on the substrate substrate at least partially overlaps an orthographic projection of the common electrode on the substrate substrate.
  • the source and drain include a first conductive layer sequentially stacked in a direction perpendicular to a second surface of the base substrate and away from the second surface toward the second surface a second conductive layer, the orthographic projection of the first conductive layer on the substrate substrate and the orthographic projection of the second conductive layer on the substrate substrate completely coincide.
  • the material of the first conductive layer is the same transparent material as the material of the common electrode, and the first conductive layer is disposed in the same layer as the common electrode.
  • the array substrate further includes: a first passivation layer on a side of the common electrode away from the base substrate; a pixel electrode on a side of the first passivation layer away from the common electrode .
  • the thin film transistor further includes a gate insulating layer, the gate insulating layer includes a via, and the source is electrically connected to the data line through the via.
  • the common electrode is disposed directly on the gate insulating layer.
  • the array substrate further includes: a second passivation layer on a side of the data line away from the substrate substrate.
  • At least one embodiment of the present disclosure provides a method of fabricating an array substrate, comprising: providing a substrate including a first surface and a second surface opposite to each other, and penetrating the first surface from the first surface a through hole reaching the second surface; a data line is formed on the first surface of the base substrate, the data line is at least partially filled in the through hole; A thin film transistor is formed on the two surfaces, and forming the thin film transistor includes forming a source and a drain, and the source is electrically connected to the data line.
  • the providing a substrate includes forming the via on the substrate.
  • the method of fabricating the array substrate further includes: forming a common electrode on the second surface of the base substrate, wherein the source, the drain, and the common electrode are formed by a one-step patterning process .
  • forming the thin film transistor further includes sequentially forming an insulating material layer and a semiconductor layer on the second surface of the base substrate; forming the insulating material layer and the semiconductor layer by a one-step patterning process a gate insulating layer and an active layer, wherein the gate insulating layer includes a via, and the source is electrically connected to the data line through the via.
  • the step of forming the gate insulating layer and the active layer by using the one-step patterning process on the insulating material layer and the semiconductor layer includes: forming a first photoresist layer on the semiconductor layer; The first photoresist layer is patterned to form a first photoresist complete retention region, a first photoresist partial removal region, and a first photoresist complete removal region, wherein the first photoresist complete retention region
  • the thickness of the medium photoresist is greater than the thickness of the photoresist in the first photoresist partial removal region;
  • the insulating material layer and the semiconductor layer located in the first photoresist complete removal region are etched to Forming the gate insulating layer including the via hole; ashing the first photoresist layer to thin the photoresist located in the completely remaining region of the first photoresist, and located at the The photoresist of the first photoresist partial removal region is completely removed; the semiconductor layer located in the first photoresist partial removal region is etched to
  • the gate insulating material layer before forming the gate insulating material layer, including: forming a buffer material layer on the second surface of the base substrate, wherein the insulating material layer and the semiconductor layer are patterned in one step
  • the step of forming the gate insulating layer and the active layer by the process includes forming a buffer layer and the gate insulating layer by using a one-step patterning process on the buffer material layer and the insulating material layer.
  • forming the source, the drain, and the common electrode includes: forming a first conductive material layer on a second surface of the base substrate; forming on the first conductive material layer a second conductive material layer; forming a second photoresist layer on the second conductive material layer; patterning the second photoresist layer to form a second photoresist complete retention region, the second photoresist a partial removal region and a second photoresist complete removal region, wherein a thickness of the photoresist in the second photoresist completely remaining region is greater than a thickness of the photoresist in the second photoresist portion removal region;
  • the first conductive material layer and the second conductive material layer located in the second photoresist complete removal region are etched to form a first conductive layer and a second conductive layer, respectively;
  • the glue layer is ashed to thin the photoresist located in the completely remaining region of the second photoresist, and the photoresist located in the second photoresist partial removal region is completely removed
  • the method of fabricating the array substrate further includes: forming a first passivation layer on a side of the common electrode away from the substrate substrate; on a side of the first passivation layer away from the common electrode A pixel electrode is formed.
  • forming the data line further comprising: forming a second passivation layer on a side of the data line away from the base substrate.
  • At least one embodiment of the present disclosure provides a display device including the array substrate of any of the above embodiments.
  • 1A is a partial plan view showing a general array substrate
  • FIG. 1B is a schematic cross-sectional view of the array substrate shown in FIG. 1A taken along line AB;
  • FIG. 1C is a schematic cross-sectional view of the array substrate shown in FIG. 1A taken along line CD;
  • 2A is a partial plan view of an array substrate according to an embodiment of the present disclosure
  • FIG. 2B is a schematic cross-sectional view of the array substrate shown in FIG. 2A taken along line AB;
  • FIG. 2C is a schematic cross-sectional view of the array substrate shown in FIG. 2A taken along line CD;
  • FIG. 3 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • 4A-4Q are schematic diagrams showing a partial structure of an array substrate fabricated in various process stages according to an embodiment of the present disclosure.
  • FIG. 1A is a partial plan view showing a general array substrate of a high-intensity high-frequency field switching (HADS) technology
  • FIG. 1B is a cross-sectional view of the array substrate shown in FIG. 1C is a schematic cross-sectional view of the array substrate shown in FIG. 1A taken along line CD.
  • the array substrate includes a gate insulating layer 10, a data line 16 on a side of the gate insulating layer 10 away from the substrate substrate (not shown), and a portion covering the data line 16.
  • a passivation layer 11 an organic film layer (for example, a resin layer) 12 on a side of the first passivation layer 11 away from the gate insulating layer 10, and a common electrode on a side of the organic film layer 12 away from the gate insulating layer 10.
  • the common electrode and other structures are not shown in FIG. 1A, and the common electrode is a plate electrode covering at least a part of the data lines.
  • FIG. 1C employs a resin layer 12 between the data line 16 and the common electrode 13 to reduce the parasitic capacitance generated between the common electrode 13 and the data line 16, thereby improving the quality of the display device.
  • a gate insulator mask is added to the fabrication process of the array substrate to improve the fabrication yield.
  • the inventors of the present application found that the increased gate insulating mask process leads to an increase in the number of masks in the fabrication process of the array substrate, that is, the use of a seven-step patterning process increases the number of masks. It has an impact on productivity.
  • Embodiments of the present disclosure provide an array substrate, a method of fabricating the same, and a display device.
  • the array substrate includes: a substrate substrate including first and second surfaces opposite to each other; and a through hole penetrating the substrate from the first surface to the second surface; and a data line on the first surface of the substrate The data line is at least partially filled in the via hole; the thin film transistor is disposed on the second surface of the base substrate, and the thin film transistor includes a source and a drain, and the source is electrically connected to the data line.
  • the data lines and the common electrodes in the array substrate are respectively disposed on opposite sides of the base substrate, which can effectively reduce signal crosstalk between the data lines and the common electrodes, and minimize parasitic capacitance formed between the data lines and the common electrodes. In order to improve the picture quality of the display device, the process steps can also be saved.
  • FIG. 2A is a partial plan view of an array substrate according to an embodiment of the present disclosure.
  • FIG. 2B is a cross-sectional view of the array substrate shown in FIG. 2A taken along line AB
  • FIG. 2A is a schematic cross-sectional view of the array substrate taken along line CD.
  • the array substrate includes a base substrate 100 including first and second surfaces 101 and 102 facing each other in the Y direction, and a substrate 100 passing through the first surface 101. The through hole 103 of the second surface 102 is reached.
  • the array substrate further includes a data line 200 on the first surface 101 of the base substrate 100.
  • the data line 200 is at least partially filled in the through hole 103, that is, the data line 200 passes through the through hole 103 to the base substrate 100.
  • the two surfaces 102 extend, that is, a portion of the data line 200 penetrates the base substrate 100 through the through holes 103.
  • the data line 200 extends in a direction perpendicular to the XY plane.
  • the array substrate further includes a thin film transistor 300 on the second surface 102 of the base substrate 100, that is, the data line 200 and the thin film transistor 300 are respectively located on both sides of the base substrate 100 in the Y direction, and the thin film transistor 300 includes a source.
  • the terminal 310 and the drain 320 are electrically connected to the data line 200, that is, the source 310 may be electrically connected to a portion of the data line 200 passing through the through hole 103.
  • the Y direction here refers to a direction perpendicular to the principal plane of the base substrate 100.
  • the array substrate further includes a buffer layer 800 on the second surface 102 of the base substrate 100 , that is, the buffer layer 800 is located on the substrate substrate 100 away from the data line 200 . side.
  • the thin film transistor 300 further includes a gate 340 on a side of the buffer layer 800 away from the substrate 100.
  • the thin film transistor 300 further includes a gate insulating layer 330 covering the gate 340 , and the gate insulating layer 330 includes a via 331 .
  • the buffer layer 800 between the gate insulating layer 330 and the base substrate 100 also includes via holes, and the via holes 331 included in the gate insulating layer 330 and the via holes included in the buffer layer 800 are patterned in the same step. The same via formed in the middle.
  • the source 310 is electrically connected to the data line 200 through the via 331, that is, the orthographic projection of the via 331 on the base substrate 100 at least partially coincides with the via 103 on the base substrate 100, and thus, the data line 200 passes.
  • a portion of the via 103 extending toward the second surface 102 of the base substrate 100 is exposed by the via 331 of the gate insulating layer 330 such that the source 310 can be electrically connected to the data line 200 through the via 331.
  • the array substrate further includes: a common electrode 400 on the second surface 102 of the base substrate 100 , that is, the common electrode 400 is located at the gate insulating layer 330 away from the data line 200 .
  • the common electrode is not shown in FIG. 2A, and the common electrode is a plate electrode covering at least a part of the data line.
  • the common electrode 400 is disposed directly on the gate insulating layer 330, that is, no other film layer is included between the common electrode 400 and the gate insulating layer 330.
  • the array substrate provided in this embodiment is mainly applied to a High Advanced-Super Dimensional Switching (HADS) product, and therefore, a common electrode included in the array substrate.
  • 400 is a transparent conductive layer of the entire surface, and the embodiment includes but is not limited thereto.
  • the material of the common electrode 400 may include a transparent conductive oxide.
  • the material of the common electrode 400 may include a combination of at least one of indium tin oxide, indium zinc oxide, zinc oxide, indium oxide, and indium gallium oxide, which is not limited in the embodiment of the present invention.
  • the material of the common electrode 400 may also include a metal material.
  • the orthographic projection of data line 200 on substrate substrate 100 at least partially overlaps the orthographic projection of common electrode 400 on substrate substrate 100, such that common electrode 400 can be on data line 200.
  • the signal is shielded to prevent the signal of the data line 200 from affecting the deflection of the liquid crystal molecules in the display device, thereby affecting the display.
  • the aperture ratio of the display device can also be increased.
  • the overlap between the common electrode 400 and the data line 200 causes parasitic capacitance (Cdc) and crosstalk of signals to occur between the two.
  • the embodiment of the present disclosure sets the data line and the common electrode on opposite sides of the substrate, respectively, which can effectively avoid signal crosstalk between the data line and the common electrode, and minimize the parasitic capacitance formed between the data line and the common electrode. Reducing power consumption and improving the picture quality of the display device, and also saving the resin process and the mask patterned separately for the gate insulating layer, thereby saving the mask process steps and helping to improve Craftsmanship.
  • the source The pole 310 and the drain 320 include a first conductive layer 311 and a second conductive layer 312 which are sequentially stacked, and the first conductive layer 311 and the second conductive layer 312 have the same shape and size, that is, the first conductive layer 311 is on the substrate.
  • the orthographic projection on the substrate 100 completely coincides with the orthographic projection of the second conductive layer 312 on the substrate substrate 100.
  • the material of the first conductive layer 311 and the common electrode 400 are the same transparent conductive material, that is, the first conductive layer 311 included in the source 310 and the drain 320 is formed with the common electrode 400.
  • the source 310, the drain 320, and the common electrode 400 are formed through a one-step patterning process. Therefore, in the embodiment of the present disclosure, a mask is used to fabricate the source and drain electrodes and the common electrode, which saves the process steps.
  • the material of the first conductive layer 311 may include a transparent conductive oxide or a metal material or the like.
  • the material of the second conductive layer 312 may include a copper material, and the embodiment includes but is not limited thereto.
  • the display area of the array substrate further includes a first passivation layer 500 on a side of the common electrode 400 away from the base substrate 100, and the first passivation layer 500 is away from the common electrode 400.
  • the pixel electrode 600 on one side and the pixel electrode 600 are electrically connected to the drain 320 of the thin film transistor 300.
  • the pixel electrode 600 in this embodiment is a strip electrode.
  • the array substrate further includes: a second passivation layer 700 on a side of the data line 200 away from the base substrate 100, the second passivation layer 700 is used to protect the The data line 200 of the first surface 101 of the base substrate 100.
  • the second passivation layer 700 may include an inorganic material such as a metal oxide, a metal sulfide, or a metal nitride, which is not limited in this embodiment.
  • the metal oxide may include calcium oxide, zinc oxide, copper oxide, titanium dioxide, tin dioxide, etc.
  • the metal sulfide may include iron sulfide, copper sulfide, zinc sulfide, tin disulfide, etc.
  • the metal nitride may include silicon nitride , aluminum nitride, etc., this embodiment includes but is not limited thereto.
  • the second passivation layer 700 has a thickness in the Y direction of 500-3000 angstroms, and the embodiment includes but is not limited thereto.
  • the second passivation layer 700 has a thickness of 1000 angstroms.
  • FIG. 3 is a schematic flow chart of a method for fabricating an array substrate according to the embodiment.
  • FIGS. 4A-4Q are various stages of the process provided by the embodiment.
  • S201 providing a base substrate including a first surface and a second surface opposite to each other, and a through hole penetrating the substrate from the first surface to the second surface.
  • the material of the base substrate may include one or more of glass, polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, and the embodiment includes but is not limited thereto.
  • the base substrate 100 includes a first surface 101 and a second surface 102 which are opposed to each other in the Y direction, where the Y direction is a direction perpendicular to the principal plane of the base substrate 100.
  • providing a substrate may include forming a via 103 on the substrate substrate 100.
  • the via hole 103 formed on the base substrate 100 penetrates the base substrate 100 in the Y direction.
  • the through hole 103 may be formed by laser cutting or the like, which is not limited in this embodiment.
  • a data line 200 is patterned on the first surface 101 of the base substrate 100 by a mask process, and a portion of the formed data line 200 penetrates the base substrate 100 through the via 103.
  • the data line 200 extends in a direction perpendicular to the XY plane.
  • the material of the data line 200 may include one or a combination of aluminum, platinum, silver, gold, nickel, chromium, copper, and the like, and the embodiment includes but is not limited thereto.
  • a second passivation layer 700 is formed on a side of the data line 200 away from the substrate 100, and the formed second passivation layer 700 is used to protect the first substrate 100.
  • Data line 200 of surface 101 is shown in FIG. 4C.
  • the second passivation layer 700 may include an inorganic material such as a metal oxide, a metal sulfide, or a metal nitride, which is not limited in this embodiment.
  • the metal oxide may include calcium oxide, zinc oxide, copper oxide, titanium dioxide, tin dioxide, etc.
  • the metal sulfide may include iron sulfide, copper sulfide, zinc sulfide, tin disulfide, etc.
  • the metal nitride may include silicon nitride , aluminum nitride, etc., this embodiment includes but is not limited thereto.
  • the thickness of the second passivation layer 700 in the Y direction is 500-3000 angstroms, and the embodiment includes but is not limited thereto.
  • the second passivation layer 700 has a thickness of 1000 angstroms.
  • a buffer material layer 801 is formed on the second surface 102 of the base substrate 100, that is, a buffer material layer 801 is deposited on a side of the base substrate 100 away from the data line 200.
  • the material of the buffer material layer 801 may include silicon nitride or the like, and the embodiment includes but is not limited thereto.
  • the thickness of the buffer material layer 801 in the Y direction is 500-1000 angstroms, and the embodiment includes but is not limited thereto.
  • S203 forming a thin film transistor on the second surface of the base substrate, the thin film transistor including a source and a drain, and the source is electrically connected to the data line.
  • a gate 340 is formed on the second surface 102 of the base substrate 100 using a mask patterning process, that is, a gate is formed on a side of the buffer material layer 801 away from the substrate substrate 100. Extreme 340.
  • an insulating material layer 332 and a semiconductor layer 351 are sequentially formed on the gate 340.
  • an insulating material layer 332 is deposited on the gate 340 by chemical vapor deposition to cover the gate 340.
  • the insulating material layer 332 may include a material such as an oxide, a nitride, or an oxynitride, which is not limited in this embodiment.
  • the buffer layer, the gate insulating layer, and the active layer in this embodiment are formed by a one-step patterning process, where the one-step patterning process refers to the buffer layer, the gate insulating layer, and the active layer using the same mask. An exposure is formed.
  • a first photoresist layer 901 is formed on the semiconductor layer 351, and the photoresist layer is patterned by a halftone mask process or a gray tone mask process to form different layers as shown.
  • a first photoresist pattern of thickness For example, a first photoresist pattern having a stepped coating layer formed by photolithography using a halftone mask, a halftone mask portion that shields ultraviolet rays, a halftone transmission portion that partially transmits ultraviolet rays using a phase shift material, and a completely It is composed of a completely transmissive portion that transmits ultraviolet light.
  • the first photoresist pattern includes a first photoresist complete retention region P1 having different thicknesses, a first photoresist partial removal region P2, and a first photoresist complete removal region formed by photolithography using a halftone mask. P3.
  • the first photoresist layer 901 is not covered on the semiconductor layer 351 where the via holes are to be formed, that is, the semiconductor layer 351 at a position where the via holes are to be formed is located in the first photoresist complete removal region P3.
  • the first photoresist layer 901 is not covered on at least the semiconductor layer 351 directly above the via 103.
  • the thickness of the first photoresist layer 901 at a position where the active layer pattern is to be formed is larger than the thickness of the first photoresist layer 901 at a position where the active layer pattern is not formed, that is, the active layer pattern is to be formed.
  • the position is located in the first photoresist complete retention region P1, and the position where the active layer pattern is not formed is located in the first photoresist partial removal region P2.
  • the semiconductor layer 351, the insulating material layer 332, and the buffer material layer 801 are patterned to form a gate insulating layer 330 including vias 331 and a buffer layer 800, that is, a buffer layer in this embodiment. 800 and gate insulating layer 330 are formed by a one-step patterning process.
  • the orthographic projection of the formed via 331 on the base substrate 100 at least partially coincides with the via 103 on the base substrate 100, and therefore, the portion of the data line 200 extending through the via 103 to the second surface 102 of the base substrate 100
  • the via 331 of the gate insulating layer 330 is exposed.
  • the first photoresist layer 901 is subjected to ashing treatment to thin the first photoresist layer 901 at a position where the active layer pattern is to be formed, and the first light at other positions.
  • the engraved layer 901 is completely ashed, that is, the first photoresist layer 901 is ashed to reduce the photoresist located in the first photoresist completely remaining region P1, and is removed in the first photoresist portion.
  • the photoresist of the region P2 is completely removed.
  • the semiconductor layer 351 not covered by the first photoresist layer 901 is etched to form an active layer pattern.
  • the first photoresist layer 901 on the active layer pattern is peeled off to form the active layer 350. Therefore, the gate insulating layer and the active layer of the present embodiment are formed by a one-step patterning process, and the one-step patterning process employs a photoresist pattern layer formed by a halftone mask process or a gray tone process.
  • the source, the drain, and the common electrode provided in this embodiment are formed by a one-step patterning process, where the one-step patterning process refers to the source, the drain, and the common electrode being composed of the first conductive material layer and the second conductive material.
  • the layers are formed by one exposure using the same mask.
  • forming the array substrate further includes: forming a first conductive material layer 3110 on the gate insulating layer 330 and the active layer 350, and leaving the first conductive material layer 3110 away from the gate insulating layer One side of 330 forms a second layer of conductive material 3120.
  • the material of the first conductive material layer 3110 includes a transparent conductive material or a metal material or the like.
  • the material of the first conductive material layer 3110 may include a transparent conductive oxide.
  • the material of the first conductive material layer 3110 may include a combination or at least one of indium tin oxide, indium zinc oxide, zinc oxide, indium oxide, and indium gallium oxide, which is not limited in the embodiment of the present invention.
  • the first conductive material layer 3110 is made of a metal material, the first conductive material layer 3110 is made thin to make the metal material layer a transparent conductive layer.
  • a second photoresist layer 902 is formed on the second conductive material layer 3120, and the second photoresist layer 902 is patterned by a halftone mask process or a gray tone mask process to form, for example, a second photoresist pattern having different thicknesses, that is, patterning the second photoresist layer 902 to form a second photoresist complete retention region P4, a second photoresist partial removal region P5, and The second photoresist completely removes the region P6, and the thickness of the photoresist in the second photoresist complete retention region P4 is greater than the thickness of the photoresist in the second photoresist portion removal region P5.
  • a second photoresist complete retention region P4 is formed in a region where a source drain is to be formed
  • a second photoresist partial removal region P5 is formed in a region where a common electrode is to be formed, except for a source drain and a common electrode to be formed.
  • the other regions form the second photoresist complete removal region P6.
  • the first conductive material layer 3110 and the second conductive material layer 3120 are patterned to expose a portion of the active layer 350 and a portion of the gate insulating layer 330, that is, the second photoresist is completely removed.
  • the first conductive material layer 3110 and the second conductive material layer 3120 of the region P6 are etched to form the first conductive layer 311 and the second conductive layer 312, respectively.
  • the first conductive layer 311 and the second conductive layer 312 in this embodiment may be formed by etching in the same step etching process, or may be formed by step etching, which is not limited in this embodiment.
  • the second photoresist layer 902 is subjected to ashing treatment to thin the second photoresist layer 902 located at the position where the source and drain patterns are to be formed, which is located at the common electrode to be formed.
  • the second photoresist layer 902 at the position is completely ashed, that is, the second photoresist layer 902 is ashed to thin the photoresist in the second photoresist completely remaining region P4, and is located at the second The photoresist of the photoresist partial removal region P5 is completely removed.
  • the second conductive layer 312 not covered by the second photoresist layer 902 is etched to remove the exposed second conductive layer 312, thereby forming a common body including only the first conductive layer 311.
  • the electrode 400 that is, the second conductive layer 312 located in the second photoresist partial removal region P5 is etched to remove the second conductive layer 312, thereby forming the common electrode 400.
  • the second photoresist layer 902 on the pattern of the source and drain electrodes is stripped to form the source 310 and the drain 320, that is, the light that peels off the second photoresist completely remaining region P4.
  • the glue is formed to form the source 310 and the drain 320, that is, the source 310 and the drain 320 are formed by one exposure process by using the same mask for the two layers of the conductive material.
  • the source 310 is electrically connected to the data line 200 of the first surface 101 of the base substrate 100 through the via 331.
  • a gap between the common electrode 400 and the drain 320 serves to insulate the two from each other.
  • the source, the drain and the common electrode of the present embodiment are formed by a one-step patterning process, and the first conductive layer included in the source and drain electrodes is in the same layer as the common electrode, and the materials of the two are the same.
  • the transparent conductive material, that is, the first conductive layer and the common electrode included in the source drain are formed by the same conductive material layer through the same mask patterning through one exposure process.
  • the material of the active layer 350 includes indium zinc oxide
  • the material of the second conductive layer 312 of the source 310 and the drain 320 includes copper.
  • the etching solution The active layer 350 is also etched while etching the second conductive layer 312. Therefore, when the material of the active layer 350 includes indium zinc oxide, the source 310 and the drain 320 include The material of the two conductive layers 312 needs to be selected from a copper material.
  • the method of fabricating the array substrate further includes patterning a first passivation layer 500 on a side of the common electrode 400 away from the substrate 100 using a mask process, and using a mask process.
  • the pixel electrode 600 is patterned on the side of the first passivation layer 500 away from the common electrode 400, and the pixel electrode 600 is electrically connected to the drain 320 included in the thin film transistor 300.
  • the pixel electrode 600 in this embodiment is a strip electrode.
  • the method for fabricating the array substrate provided by the present embodiment can effectively avoid signal crosstalk between the data line and the common electrode, with respect to the fabrication process of the array substrate including the gate insulating layer mask process.
  • the parasitic capacitance formed between the data line and the common electrode is minimized, the power consumption is reduced, and the process steps of the resin process and the gate insulating layer mask process are also saved.
  • the array substrate includes a bottom gate type thin film transistor as an example, but is not limited thereto.
  • the array substrate may further include a top gate type thin film transistor, that is, a one-step patterning process is formed on the buffer layer.
  • the source/drain electrode and the common electrode sequentially form a gate insulating layer, a gate electrode, a passivation layer, and a pixel electrode on the source/drain electrode and the common electrode.
  • An embodiment of the present disclosure provides a display device, which includes the array substrate according to any one of the above embodiments. Therefore, the display device can effectively avoid signal crosstalk between the data line and the common electrode, and the data line is The parasitic capacitance formed between the common electrode and the common electrode is minimized, which reduces power consumption, thereby improving the picture quality of the display device.
  • the display device may be a liquid crystal display device and any product or component having a display function such as a television, a digital camera, a mobile phone, a wristwatch, a tablet computer, a notebook computer, a navigator, or the like including the display device, and the embodiment is not limited thereto.
  • the display device is a display device using a High Open-Super Dimensional Switching (HADS) technology.
  • HADS High Open-Super Dimensional Switching

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Abstract

一种阵列基板及其制作方法、显示装置。该阵列基板包括：衬底基板(100)，包括彼此相对的第一表面(101)和第二表面(102)、以及从第一表面(101)贯通衬底基板(100)到达第二表面(102)的通孔(103)；位于衬底基板(100)的第一表面(101)上的数据线(200)，数据线(200)至少部分填充在通孔(103)中；位于衬底基板(100)的第二表面(102)上的薄膜晶体管(300)，薄膜晶体管(300)包括源极(310)和漏极(320)，源极(310)与数据线(200)电连接。

Description

阵列基板及其制作方法、显示装置
本申请要求于2017年11月10日递交的中国专利申请第201711105473.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开至少一个实施例涉及一种阵列基板及其制作方法、显示装置。
背景技术
一般生产具有高开口率高级超维场转换(High Advanced-Super Dimensional Switching,HADS)特性的产品包括有机膜技术，有机膜技术的应用，可以明显减小公共电极与数据线之间的寄生电容，从而可以降低功耗。
发明内容
本公开的至少一实施例提供一种阵列基板及其制作方法、显示装置。该阵列基板，包括：衬底基板，包括彼此相对的第一表面和第二表面、以及从所述第一表面贯通所述衬底基板到达所述第二表面的通孔；位于所述衬底基板的第一表面上的数据线，所述数据线至少部分填充在所述通孔中；位于所述衬底基板的第二表面上的薄膜晶体管，所述薄膜晶体管包括源极和漏极，所述源极与所述数据线电连接。
在一些示例中，阵列基板还包括：位于所述衬底基板的第二表面上的公共电极。
在一些示例中，所述数据线在所述衬底基板上的正投影与所述公共电极在所述衬底基板上的正投影至少部分交叠。
在一些示例中，沿垂直于所述衬底基板第二表面且从靠近所述第二表面向远离所述第二表面的方向，所述源极和漏极包括依次层叠的第一导电层与第二导电层，所述第一导电层在所述衬底基板上的正投影与所述第二导电层在所述衬底基板上的正投影完全重合。
在一些示例中，所述第一导电层的材料与所述公共电极的材料为相同的透明导电材料，且所述第一导电层与所述公共电极同层设置。
在一些示例中，阵列基板还包括：位于所述公共电极远离所述衬底基板的一侧的第一钝化层；位于所述第一钝化层远离所述公共电极的一侧的像素电极。
在一些示例中，所述薄膜晶体管还包括栅极绝缘层，所述栅极绝缘层包括过孔，所述源极通过所述过孔与所述数据线电连接。
在一些示例中，所述公共电极直接设置在所述栅极绝缘层上。
在一些示例中，阵列基板还包括：位于所述数据线远离所述衬底基板的一侧的第二钝化层。
本公开的至少一实施例提供一种阵列基板的制作方法，包括：提供衬底基板，所述衬底基板包括彼此相对的第一表面和第二表面，以及从所述第一表面贯通所述衬底基板到达所述第二表面的通孔；在所述衬底基板的第一表面上形成数据线，所述数据线至少部分填充在所述通孔中；在所述衬底基板的第二表面上形成薄膜晶体管，形成所述薄膜晶体管包括形成源极和漏极，所述源极与所述数据线电连接。
在一些示例中，所述提供衬底基板包括：在所述衬底基板上形成所述通孔。
在一些示例中，阵列基板的制作方法还包括：在所述衬底基板的第二表面上形成公共电极，其中，所述源极、所述漏极以及所述公共电极通过一步图案化工艺形成。
在一些示例中，形成所述薄膜晶体管还包括：在所述衬底基板的第二表面上依次形成绝缘材料层和半导体层；对所述绝缘材料层和所述半导体层采用一步图案化工艺形成栅极绝缘层以及有源层，其中，所述栅极绝缘层包括过孔，所述源极通过所述过孔与所述数据线电连接。
在一些示例中，对所述绝缘材料层和所述半导体层采用一步图案化工艺形成栅极绝缘层以及有源层的步骤包括：在所述半导体层上形成第一光刻胶层；对所述第一光刻胶层图案化以形成第一光刻胶完全保留区、第一光刻胶部分去除区以及第一光刻胶完全去除区，其中，所述第一光刻胶完全保留区中光刻胶的厚度大于所述第一光刻胶部分去除区中光刻胶的厚度；对位于所述第一光刻胶完全去除区的所述绝缘材料层和所述半导体层刻蚀以形成包括所述过孔的所述栅极绝缘层；对所述第一光刻胶层灰化处理以使位于所述第一光刻胶完全保留区的光刻胶减薄，且位于所述第一光刻胶部分去除区的光刻胶完全去除；对位于所述第一光刻胶部分去除区的所述半导体层进行刻蚀以形成所述有源 层。
在一些示例中，在形成所述栅极绝缘材料层之前包括：在所述衬底基板的第二表面上形成缓冲材料层，其中，对所述绝缘材料层和所述半导体层采用一步图案化工艺形成栅极绝缘层以及有源层的步骤包括：对所述缓冲材料层与所述绝缘材料层采用一步图案化工艺形成了缓冲层以及所述栅极绝缘层。
在一些示例中，形成所述源极、所述漏极以及所述公共电极包括：在所述衬底基板的第二表面上形成第一导电材料层；在所述第一导电材料层上形成第二导电材料层；在所述第二导电材料层上形成第二光刻胶层；对所述第二光刻胶层图案化以形成第二光刻胶完全保留区、第二光刻胶部分去除区以及第二光刻胶完全去除区，其中，所述第二光刻胶完全保留区中光刻胶的厚度大于所述第二光刻胶部分去除区中光刻胶的厚度；对位于所述第二光刻胶完全去除区的所述第一导电材料层和所述第二导电材料层进行刻蚀以分别形成第一导电层和第二导电层；对所述第二光刻胶层灰化处理以使位于所述第二光刻胶完全保留区的光刻胶减薄，且位于所述第二光刻胶部分去除区的光刻胶完全去除；对位于所述第二光刻胶部分去除区的所述第二导电层进行刻蚀以除去所述第二导电层，从而形成所述公共电极；剥离所述第二光刻胶完全保留区的光刻胶以形成所述源极和所述漏极。
在一些示例中，阵列基板的制作方法还包括：在所述公共电极远离所述衬底基板的一侧形成第一钝化层；在所述第一钝化层远离所述公共电极的一侧形成像素电极。
在一些示例中，在形成所述数据线之后还包括：在所述数据线远离所述衬底基板的一侧形成第二钝化层。
本公开的至少一实施例提供一种显示装置，包括上述任一实施例所述的阵列基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一般的阵列基板的局部平面示意图；
图1B为图1A所示的阵列基板沿AB线所截的截面示意图；
图1C为图1A所示的阵列基板沿CD线所截的截面示意图；
图2A为本公开一实施例提供的阵列基板的局部平面示意图；
图2B为图2A所示的阵列基板沿AB线所截的截面示意图；
图2C为图2A所示的阵列基板沿CD线所截的截面示意图；
图3为本公开一实施例提供的阵列基板的制作方法的流程示意图；
图4A-图4Q为本公开一实施例提供的各个工艺阶段制作的阵列基板的局部结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
图1A为一般的应用高开口率高级超维场转换(High Advanced-Super Dimensional Switching，HADS)技术的阵列基板的局部平面示意图，图1B为图1A所示的阵列基板沿AB线所截的截面示意图，图1C为图1A所示的阵列基板沿CD线所截的截面示意图。如图1A-图1C所示，该阵列基板包括栅极绝缘层10、位于栅极绝缘层10远离衬底基板(图中未示出)的一侧的数据线16、覆盖数据线16的第一钝化层11、位于第一钝化层11远离栅极绝缘层10的一侧的有机膜层(例如树脂层)12、位于有机膜层12远离栅极绝缘层10的一侧的公共电极13、位于公共电极13远离栅极绝缘层10的一侧的第二钝化层14以及像素电极15。为了清楚的示意出数据线等结构，图1A中没有示出公共电极及其他结构，公共电极为覆盖至少部分数据线的板状电极。
由于在垂直于衬底基板的方向上，公共电极13与数据线16有交叠，因此， 在公共电极13与数据线16之间会产生寄生电容，导致显示装置的功耗过高，影响显示装置的画面品质。由此图1C采用在数据线16与公共电极13之间增加树脂层(resin)12以减小公共电极13与数据线16之间产生的寄生电容，从而提高显示装置的品质。此外，该阵列基板的制作工艺中还增加了栅极绝缘层掩模工艺(gate insulator mask)以提升制作良率。
在研究中，本申请的发明人发现：增加的栅极绝缘层掩模工艺会导致阵列基板的制作工艺中增加了掩模板的数量，即，采用7步图案化工艺会增加掩模板的数量，对生产性造成影响。
本公开的实施例提供一种阵列基板及其制作方法、显示装置。该阵列基板包括：衬底基板，包括彼此相对的第一表面和第二表面、以及从第一表面贯通衬底基板到达第二表面的通孔；位于衬底基板的第一表面上的数据线，数据线至少部分填充在通孔中；位于衬底基板的第二表面上的薄膜晶体管，薄膜晶体管包括源极和漏极，源极与数据线电连接。该阵列基板中的数据线与公共电极分别设置在衬底基板相对的两侧，既可以有效降低数据线与公共电极之间的信号串扰，将数据线与公共电极之间形成的寄生电容最小化，从而提升显示装置的画面品质，还可以节省工艺步骤。
下面结合附图对本公开实施例提供的阵列基板及其制作方法、显示装置进行描述。
本公开的实施例提供一种阵列基板，图2A为本公开一实施例提供的阵列基板的局部平面示意图，图2B为图2A所示的阵列基板沿AB线所截的截面示意图，图2C为图2A所示的阵列基板沿CD线所截的截面示意图。如图2A-图2C所示，该阵列基板包括衬底基板100，衬底基板100包括沿Y方向彼此相对的第一表面101和第二表面102、以及从第一表面101贯通衬底基板100到达第二表面102的通孔103。该阵列基板还包括位于衬底基板100的第一表面101上的数据线200，数据线200至少部分填充在通孔103中，也就是，数据线200通过通孔103向衬底基板100的第二表面102延伸，即，数据线200的一部分通过通孔103贯通衬底基板100。例如，数据线200沿垂直于XY面的方向延伸。该阵列基板还包括位于衬底基板100的第二表面102上的薄膜晶体管300，即，数据线200与薄膜晶体管300分别位于衬底基板100的沿Y方向的两侧，且薄膜晶体管300包括源极310和漏极320，源极310与数据线200电连接，即，源极310可以与贯通通孔103的一部分数据线200电连接。这里 的Y方向指垂直于衬底基板100的主平面的方向。
在一些示例中，如图2A-图2C所示，阵列基板还包括位于衬底基板100的第二表面102上的缓冲层800，即，缓冲层800位于衬底基板100远离数据线200的一侧。薄膜晶体管300还包括位于缓冲层800的远离衬底基板100一侧的栅极340。
在一些示例中，如图2A-图2C所示，薄膜晶体管300还包括覆盖栅极340的栅极绝缘层330，栅极绝缘层330包括过孔331。例如，位于栅极绝缘层330与衬底基板100之间的缓冲层800也包括过孔，且栅极绝缘层330包括的过孔331与缓冲层800包括的过孔是在同一步图案化工艺中形成的同一个过孔。并且，源极310通过过孔331与数据线200电连接，即，过孔331在衬底基板100上的正投影与衬底基板100上的通孔103至少部分重合，因此，数据线200通过通孔103向衬底基板100的第二表面102延伸的部分被栅极绝缘层330的过孔331暴露出来，以使源极310可以通过过孔331与数据线200实现电连接。
在一些示例中，如图2A-图2C所示，阵列基板还包括：位于衬底基板100的第二表面102上的公共电极400，即，公共电极400位于栅极绝缘层330远离数据线200的一侧。为了清楚的示意出数据线等结构，图2A中没有示出公共电极，公共电极为覆盖至少部分数据线的板状电极。
在一些示例中，如图2A-图2C所示，公共电极400直接设置在栅极绝缘层330上，即，公共电极400与栅极绝缘层330之间不包括其他膜层。
例如，如图2A-图2C所示，本实施例提供的阵列基板主要应用于高开口率高级超维场转换(High Advanced-Super Dimensional Switching，HADS)产品，因此，阵列基板中包括的公共电极400为整面的透明的导电层，本实施例包括但不限于此。例如，公共电极400的材料可以包括透明导电氧化物。例如，公共电极400的材料可以包括氧化铟锡、氧化铟锌、氧化锌、氧化铟和氧化铟镓中的组合或至少一种，本发明实施例对此不作限制。例如，公共电极400的材料还可以包括金属材料。
在一些示例中，如图2C所示，数据线200在衬底基板100上的正投影与公共电极400在衬底基板100上的正投影至少部分交叠，因此公共电极400可以对数据线200的信号进行屏蔽，以防止数据线200的信号影响显示装置中液晶分子的偏转，进而影响显示。在这种情况下，由于显示装置中的彩膜基板上的黑矩阵可以被最小化，因此还可以增加显示装置的开口率。
一般在垂直于衬底基板100的方向上，公共电极400与数据线200之间存在交叠部分会导致两者之间会产生寄生电容(Cdc)以及信号的串扰。本公开的实施例将数据线与公共电极分别设置在衬底基板相对的两侧，既可以有效避免数据线与公共电极之间的信号串扰，将数据线与公共电极之间形成的寄生电容最小化，从而降低了功耗并提升了显示装置的画面品质，还可以节省树脂层(resin)工艺以及对栅极绝缘层单独图案化的掩模板，因此节省了掩模工艺步骤，有助于提升工艺性。
在一些示例中，如图2B所示，沿垂直于衬底基板100的第二表面102且从靠近第二表面102向远离第二表面102的方向，即沿图中所示的Y方向，源极310和漏极320包括依次层叠的第一导电层311与第二导电层312，第一导电层311与第二导电层312的形状及尺寸均相同，即，第一导电层311在衬底基板100上的正投影与第二导电层312在衬底基板100上的正投影完全重合。
在一些示例中，如图2B所示，第一导电层311与公共电极400的材料为相同的透明导电材料，即，源极310和漏极320包括的第一导电层311与公共电极400形成在同一层，且源极310、漏极320以及公共电极400经过一步图案化工艺形成，因此，本公开的实施例中采用一张掩模板来制作源漏极和公共电极，节省了工艺步骤。
例如，第一导电层311的材料可以包括透明导电氧化物或者金属材料等。
例如，第二导电层312的材料可以包括铜材料，本实施例包括但不限于此。
在一些示例中，如图2B所示，阵列基板的显示区还包括位于公共电极400远离衬底基板100的一侧的第一钝化层500，以及位于第一钝化层500远离公共电极400的一侧的像素电极600，像素电极600与薄膜晶体管300的漏极320电连接。例如，本实施例中的像素电极600为条状电极。
在一些示例中，如图2A-图2C所示，阵列基板还包括：位于数据线200远离衬底基板100的一侧的第二钝化层700，该第二钝化层700用于保护位于衬底基板100的第一表面101的数据线200。
例如，第二钝化层700可以包括金属氧化物、金属硫化物或金属氮化物等无机材料，本实施对此不作限制。例如，金属氧化物可以包括氧化钙、氧化锌、氧化铜、二氧化钛、二氧化锡等；金属硫化物可以包括硫化铁、硫化铜、硫化锌、二硫化锡等；金属氮化物可以包括氮化硅、氮化铝等，本实施例包括但不限于此。
例如，第二钝化层700在沿Y方向的厚度为500-3000埃，本实施例包括但不限于此。例如，第二钝化层700的厚度为1000埃。
本公开的另一实施例提供了一种阵列基板的制作方法，图3示出了本实施例提供的阵列基板的制作方法的流程示意图，图4A-图4Q为本实施例提供的各个工艺阶段制作的阵列基板的局部结构示意图。如图3和图4A-图4Q所示，该阵列基板的制作方法包括：
S201：提供衬底基板，衬底基板包括彼此相对的第一表面和第二表面，以及从第一表面贯通衬底基板到达第二表面的通孔。
例如，衬底基板的材料可以包括玻璃、聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜中的一种或多种，本实施例包括但不限于此。
例如，如图4A所示，衬底基板100包括沿Y方向彼此相对的第一表面101和第二表面102，这里的Y方向为垂直于衬底基板100的主平面的方向。
例如，如图4A所示，提供衬底基板可以包括在衬底基板100上形成通孔103。
例如，如图4A所示，在衬底基板100上形成的通孔103沿Y方向贯通衬底基板100。例如，可以采用激光切割等方式形成通孔103，本实施例对此不作限制。
S202：在衬底基板的第一表面上形成数据线，数据线至少部分填充在通孔中。
例如，如图4B所示，采用掩模工艺，在衬底基板100的第一表面101上图案化形成数据线200，形成的数据线200的一部分通过通孔103贯通衬底基板100。例如，数据线200沿垂直于XY平面的方向延伸。
例如，数据线200的材料可以包括铝、铂、银、金、镍、铬和铜等中的一种或几种的组合，本实施例包括但不限于此。
在一些示例中，如图4C所示，在数据线200远离衬底基板100的一侧形成第二钝化层700，形成的第二钝化层700用于保护位于衬底基板100的第一表面101的数据线200。
例如，第二钝化层700可以包括金属氧化物、金属硫化物或金属氮化物等无机材料，本实施对此不作限制。例如，金属氧化物可以包括氧化钙、氧化锌、氧化铜、二氧化钛、二氧化锡等；金属硫化物可以包括硫化铁、硫化铜、硫化锌、二硫化锡等；金属氮化物可以包括氮化硅、氮化铝等，本实施例包括但不 限于此。
例如，第二钝化层700沿Y方向的厚度为500-3000埃，本实施例包括但不限于此。例如，第二钝化层700的厚度为1000埃。
在一些示例中，如图4D所示，在衬底基板100的第二表面102上形成缓冲材料层801，即，在衬底基板100远离数据线200的一侧沉积缓冲材料层801。
例如，如图4D所示，缓冲材料层801的材料可以包括氮化硅等，本实施例包括但不限于此。例如，缓冲材料层801沿Y方向的厚度为500-1000埃，本实施例包括但不限于此。
S203：在衬底基板的第二表面上形成薄膜晶体管，薄膜晶体管包括源极和漏极，源极与数据线电连接。
在一些示例中，如图4E所示，在衬底基板100的第二表面102上采用掩模图案化工艺形成栅极340，即，在缓冲材料层801远离衬底基板100的一侧形成栅极340。
在一些示例中，如图4F所示，在栅极340上依次形成绝缘材料层332以及半导体层351。
例如，在栅极340上利用化学气相沉积法沉积绝缘材料层332以覆盖栅极340。例如，绝缘材料层332可以包括氧化物、氮化物或氮氧化合物等材料，本实施例对此不作限制。
例如，本实施例中的缓冲层、栅极绝缘层以及有源层是通过一步图案化工艺形成的，这里的一步图案化工艺指缓冲层、栅极绝缘层以及有源层利用同一个掩模板进行一次曝光形成。
例如，如图4G所示，在半导体层351上形成第一光刻胶层901，利用半色调掩模工艺或者灰色调掩模工艺对光刻胶层图案化以形成如图所示的具有不同厚度的第一光刻胶图案。例如，可以通过利用半色调掩模的光刻形成具有台阶敷层的第一光刻胶图案，半色调掩模由遮蔽紫外线的遮蔽部分，利用相移材料部分透射紫外线的半色调透射部分以及完全透射紫外线的完全透射部分构成。第一光刻胶图案包括具有不同厚度的第一光刻胶完全保留区P1、第一光刻胶部分去除区P2以及通过利用半色调掩模的光刻形成的第一光刻胶完全去除区P3。
例如，在待形成过孔的位置的半导体层351上没有覆盖第一光刻胶层901，即，待形成过孔的位置的半导体层351位于第一光刻胶完全去除区P3。例如， 至少在通孔103正上方的半导体层351上没有覆盖第一光刻胶层901。例如，在待形成有源层图案的位置的第一光刻胶层901的厚度大于不形成有源层图案的位置的第一光刻胶层901的厚度，即，待形成有源层图案的位置位于第一光刻胶完全保留区P1，不形成有源层图案的位置位于第一光刻胶部分去除区P2。
例如，如图4H所示，对半导体层351、绝缘材料层332以及缓冲材料层801图案化后形成包括过孔331的栅极绝缘层330以及缓冲层800，即，本实施例中的缓冲层800与栅极绝缘层330通过一步图案化工艺形成。形成的过孔331在衬底基板100上的正投影与衬底基板100上的通孔103至少部分重合，因此，数据线200通过通孔103向衬底基板100的第二表面102延伸的部分被栅极绝缘层330的过孔331暴露出来。
例如，如图4I所示，对第一光刻胶层901进行灰化处理，使位于待形成有源层图案的位置的第一光刻胶层901减薄，而位于其他位置的第一光刻胶层901完全灰化除去，即，对第一光刻胶层901灰化处理以使位于第一光刻胶完全保留区P1的光刻胶减薄，且位于第一光刻胶部分去除区P2的光刻胶完全去除。
例如，如图4J所示，对没有被第一光刻胶层901覆盖的半导体层351进行刻蚀以形成有源层图案。
例如，如图4K所示，剥离位于有源层图案上的第一光刻胶层901以形成有源层350。因此，本实施例的栅极绝缘层和有源层通过一步图案化工艺形成，并且该一步图案化工艺采用了通过半色调掩模工艺或者灰色调工艺形成的光刻胶图案层。
例如，本实施例提供的源极、漏极以及公共电极通过一步图案化工艺形成的，这里的一步图案化工艺指源极、漏极以及公共电极由对第一导电材料层和第二导电材料层利用同一个掩模板进行一次曝光形成。
在一些示例中，如图4L所示，形成阵列基板还包括：在栅极绝缘层330以及有源层350上形成第一导电材料层3110，以及在第一导电材料层3110远离栅极绝缘层330的一侧形成第二导电材料层3120。
例如，第一导电材料层3110的材料包括透明导电材料或者金属材料等。例如，第一导电材料层3110的材料可以包括透明导电氧化物。例如，第一导电材料层3110的材料可以包括氧化铟锡、氧化铟锌、氧化锌、氧化铟和氧化铟镓中的组合或至少一种，本发明实施例对此不作限制。当第一导电材料层 3110选用金属材料时，该第一导电材料层3110制作的很薄以使金属材料层成为透明导电层。
例如，如图4M所示，在第二导电材料层3120上形成第二光刻胶层902，利用半色调掩模工艺或者灰色调掩模工艺对第二光刻胶层902图案化以形成如图所示的具有不同厚度的第二光刻胶图案，即，对第二光刻胶层902图案化以形成第二光刻胶完全保留区P4、第二光刻胶部分去除区P5以及第二光刻胶完全去除区P6，第二光刻胶完全保留区P4中光刻胶的厚度大于第二光刻胶部分去除区P5中光刻胶的厚度。
例如，在待形成源漏极的区域形成第二光刻胶完全保留区P4，在待形成公共电极的区域形成第二光刻胶部分去除区P5，在除待形成源漏极和公共电极的其他区域形成第二光刻胶完全去除区P6。
例如，如图4N所示，对第一导电材料层3110和第二导电材料层3120图案化以暴露部分有源层350以及部分栅极绝缘层330，即，对位于第二光刻胶完全去除区P6的第一导电材料层3110和第二导电材料层3120进行刻蚀以分别形成第一导电层311和第二导电层312。本实施例中的第一导电层311与第二导电层312可以在同一步刻蚀工艺中刻蚀形成，也可以分步刻蚀形成，本实施例对此不作限制。
例如，如图4O所示，对第二光刻胶层902进行灰化处理，使位于待形成源极和漏极图案的位置的第二光刻胶层902减薄，位于待形成公共电极的位置的第二光刻胶层902完全灰化除去，即，对第二光刻胶层902灰化处理以使位于第二光刻胶完全保留区P4的光刻胶减薄，且位于第二光刻胶部分去除区P5的光刻胶完全去除。
例如，如图4P所示，对没有被第二光刻胶层902覆盖的第二导电层312进行刻蚀以除去被暴露的第二导电层312，从而形成仅包括第一导电层311的公共电极400，即，对位于第二光刻胶部分去除区P5的第二导电层312进行刻蚀以除去第二导电层312，从而形成公共电极400。
例如，如图4Q所示，剥离位于源极和漏极的图案上的第二光刻胶层902以形成源极310和漏极320，即，剥离第二光刻胶完全保留区P4的光刻胶以形成源极310和漏极320，也就是源极310和漏极320通过对两层导电材料层利用同一个掩模板，经过一次曝光工艺形成。源极310通过过孔331与位于衬底基板100的第一表面101的数据线200实现电连接。在公共电极400与漏极320 之间的间隙用于使两者彼此绝缘。由上述步骤可知，本实施例的源极、漏极以及公共电极通过一步图案化工艺形成，并且源漏极包括的第一导电层与公共电极位于同一层，且两者的材料均为相同的透明导电材料，即源漏极包括的第一导电层与公共电极由同一导电材料层经过同一掩模板图案化经过1次曝光工艺形成。
例如，有源层350的材料包括铟稼锌氧化物，源极310和漏极320的第二导电层312的材料包括铜。由于在对第二导电层312进行刻蚀以形成源极和漏极的过程中，如果第二导电层312采用铝材料，且有源层350的材料包括铟稼锌氧化物，则刻蚀液在对第二导电层312进行刻蚀的同时也会对有源层350进行刻蚀，因此，在有源层350的材料包括铟稼锌氧化物时，源极310和漏极320包括的第二导电层312的材料需要选择铜材料。
在一些示例中，如图2B所示，制作阵列基板的方法还包括采用掩模工艺，在公共电极400远离衬底基板100的一侧图案化形成第一钝化层500，以及采用掩模工艺，在第一钝化层500远离公共电极400的一侧图案化形成像素电极600，像素电极600与薄膜晶体管300包括的漏极320电连接。例如，本实施例中的像素电极600为条状电极。
因此，由上述工艺步骤可知，相对于包括栅极绝缘层掩模工艺的阵列基板的制作工艺，本实施例提供的阵列基板的制作方法既能够有效避免数据线与公共电极之间的信号串扰，将数据线与公共电极之间形成的寄生电容最小化，降低了功耗的基础上，而且还节省了树脂工艺及栅极绝缘层掩模工艺的工艺步骤。
本公开的实施例中以阵列基板包括底栅型薄膜晶体管为例进行描述，但不限于此，例如，阵列基板还可以包括顶栅型薄膜晶体管，即，在缓冲层上采用一步图案化工艺形成源漏电极以及公共电极，在源漏电极以及公共电极上依次形成栅极绝缘层、栅极、钝化层以及像素电极。
本公开一实施例提供一种显示装置，该显示装置包括上述实施例中任一项所述的阵列基板，因此，该显示装置可以有效避免数据线与公共电极之间的信号串扰，将数据线与公共电极之间形成的寄生电容最小化，降低了功耗，从而提升了显示装置的画面品质。
例如，该显示装置可以为液晶显示装置以及包括该显示装置的电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产 品或者部件，本实施例不限于此。
例如，该显示装置为应用高开口率高级超维场转换(High Advanced-Super Dimensional Switching，HADS)技术的显示装置。
有以下几点需要说明：
(1)除非另作定义，本公开实施例以及附图中，同一标号代表同一含义。
(2)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(3)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种阵列基板，包括：
    衬底基板，包括彼此相对的第一表面和第二表面、以及从所述第一表面贯通所述衬底基板到达所述第二表面的通孔；
    位于所述衬底基板的第一表面上的数据线，所述数据线至少部分填充在所述通孔中；
    位于所述衬底基板的第二表面上的薄膜晶体管，所述薄膜晶体管包括源极和漏极，所述源极与所述数据线电连接。
  2. 根据权利要求1所述的阵列基板，还包括：
    位于所述衬底基板的第二表面上的公共电极。
  3. 根据权利要求2所述的阵列基板，其中，所述数据线在所述衬底基板上的正投影与所述公共电极在所述衬底基板上的正投影至少部分交叠。
  4. 根据权利要求2或3所述的阵列基板，其中，沿垂直于所述衬底基板的第二表面且从靠近所述第二表面向远离所述第二表面的方向，所述源极和漏极包括依次层叠的第一导电层与第二导电层，所述第一导电层在所述衬底基板上的正投影与所述第二导电层在所述衬底基板上的正投影完全重合。
  5. 根据权利要求4所述的阵列基板，其中，所述第一导电层的材料与所述公共电极的材料为相同的透明导电材料，且所述第一导电层与所述公共电极同层设置。
  6. 根据权利要求2-5任一项所述的阵列基板，还包括：
    位于所述公共电极远离所述衬底基板的一侧的第一钝化层；
    位于所述第一钝化层远离所述公共电极的一侧的像素电极。
  7. 根据权利要求1-6任一项所述的阵列基板，其中，所述薄膜晶体管还包括栅极绝缘层，所述栅极绝缘层包括过孔，所述源极通过所述过孔与所述数据线电连接。
  8. 根据权利要求1-7任一项所述的阵列基板，还包括：
    位于所述数据线远离所述衬底基板的一侧的第二钝化层。
  9. 一种阵列基板的制作方法，包括：
    提供衬底基板，所述衬底基板包括彼此相对的第一表面和第二表面，以及从所述第一表面贯通所述衬底基板到达所述第二表面的通孔；
    在所述衬底基板的第一表面上形成数据线，所述数据线至少部分填充在所述通孔中；
    在所述衬底基板的第二表面上形成薄膜晶体管，形成所述薄膜晶体管包括形成源极和漏极，所述源极与所述数据线电连接。
  10. 根据权利要求9所述的阵列基板的制作方法，其中，所述提供衬底基板包括：
    在所述衬底基板上形成所述通孔。
  11. 根据权利要求9或10所述的阵列基板的制作方法，还包括：
    在所述衬底基板的第二表面上形成公共电极，
    其中，所述源极、所述漏极以及所述公共电极通过一步图案化工艺形成。
  12. 根据权利要求9-11任一项所述的阵列基板的制作方法，其中，形成所述薄膜晶体管还包括：
    在所述衬底基板的第二表面上依次形成绝缘材料层和半导体层；
    对所述绝缘材料层和所述半导体层采用一步图案化工艺形成栅极绝缘层以及有源层，
    其中，所述栅极绝缘层包括过孔，所述源极通过所述过孔与所述数据线电连接。
  13. 根据权利要求12所述的阵列基板的制作方法，其中，对所述绝缘材料层和所述半导体层采用一步图案化工艺形成栅极绝缘层以及有源层的步骤包括：
    在所述半导体层上形成第一光刻胶层；
    对所述第一光刻胶层图案化以形成第一光刻胶完全保留区、第一光刻胶部分去除区以及第一光刻胶完全去除区，其中，所述第一光刻胶完全保留区中光刻胶的厚度大于所述第一光刻胶部分去除区中光刻胶的厚度；
    对位于所述第一光刻胶完全去除区的所述绝缘材料层和所述半导体层刻蚀以形成包括所述过孔的所述栅极绝缘层；
    对所述第一光刻胶层灰化处理以使位于所述第一光刻胶完全保留区的光刻胶减薄，且位于所述第一光刻胶部分去除区的光刻胶完全去除；
    对位于所述第一光刻胶部分去除区的所述半导体层进行刻蚀以形成所述有源层。
  14. 根据权利要求12或13所述的阵列基板的制作方法，其中，在形成所 述绝缘材料层之前包括：
    在所述衬底基板的第二表面上形成缓冲材料层，其中，对所述绝缘材料层和所述半导体层采用一步图案化工艺形成栅极绝缘层以及有源层的步骤包括：对所述缓冲材料层与所述绝缘材料层采用一步图案化工艺形成了缓冲层以及所述栅极绝缘层。
  15. 根据权利要求11所述的阵列基板的制作方法，其中，形成所述源极、所述漏极以及所述公共电极包括：
    在所述衬底基板的第二表面上形成第一导电材料层；
    在所述第一导电材料层上形成第二导电材料层；
    在所述第二导电材料层上形成第二光刻胶层；
    对所述第二光刻胶层图案化以形成第二光刻胶完全保留区、第二光刻胶部分去除区以及第二光刻胶完全去除区，其中，所述第二光刻胶完全保留区中光刻胶的厚度大于所述第二光刻胶部分去除区中光刻胶的厚度；
    对位于所述第二光刻胶完全去除区的所述第一导电材料层和所述第二材料导电层进行刻蚀以分别形成第一导电层和第二导电层；
    对所述第二光刻胶层灰化处理以使位于所述第二光刻胶完全保留区的光刻胶减薄，且位于所述第二光刻胶部分去除区的光刻胶完全去除；
    对位于所述第二光刻胶部分去除区的所述第二导电层进行刻蚀以除去所述第二导电层，从而形成所述公共电极；
    剥离所述第二光刻胶完全保留区的光刻胶以形成所述源极和所述漏极。
  16. 根据权利要求9-15任一项所述的阵列基板的制作方法，其中，在形成所述数据线之后包括：
    在所述数据线远离所述衬底基板的一侧形成第二钝化层。
  17. 一种显示装置，包括权利要求1-8任一项所述的阵列基板。
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