WO2018120691A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2018120691A1
WO2018120691A1 PCT/CN2017/090363 CN2017090363W WO2018120691A1 WO 2018120691 A1 WO2018120691 A1 WO 2018120691A1 CN 2017090363 W CN2017090363 W CN 2017090363W WO 2018120691 A1 WO2018120691 A1 WO 2018120691A1
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WIPO (PCT)
Prior art keywords
color filter
layer
filter pattern
pattern
switching element
Prior art date
Application number
PCT/CN2017/090363
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English (en)
French (fr)
Inventor
郭志轩
王凤国
武新国
刘弘
王子峰
李元博
李峰
马波
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/747,687 priority Critical patent/US10424669B2/en
Publication of WO2018120691A1 publication Critical patent/WO2018120691A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/136222—Colour filters incorporated in the active matrix substrate
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    • G02—OPTICS
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • Embodiments of the present disclosure relate to an array substrate, a method of manufacturing the same, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • Embodiments of the present disclosure provide an array substrate, a manufacturing method thereof, and a display device for eliminating the resin layer of the prior art, saving cost, and simplifying the process flow.
  • An array substrate provided by an embodiment of the present disclosure includes: a substrate; a first conductive layer on the substrate, including a source of the switching element; and a color filter on the first conductive layer a layer of the color filter adjacent to the source of the switching element in a direction perpendicular to the substrate.
  • the array substrate further includes: a second conductive layer on the color filter layer, including a common electrode, wherein the color filter is in a direction perpendicular to the substrate The layer also abuts the common electrode.
  • the first conductive layer further includes a data line connected to a source of the switching element
  • the second conductive layer further includes a common line connected to the common electrode
  • the color filter The layer is configured to electrically isolate the data line from the common line at an intersection of the data line and the common line.
  • the color filter layer includes adjacent first color filter patterns and second color filter patterns, and is located in the first color filter pattern and the second color filter pattern And an opening portion of the color filter layer, wherein the color of the first color filter pattern and the second color filter pattern are different
  • the first conductive layer further includes a drain of the switching element, Opening the exposed portion A portion of the drain, the drain of the switching element is coincident with the first color filter pattern and the second color filter pattern in a direction perpendicular to the base substrate.
  • the array substrate further includes: a passivation layer on the second conductive layer; and a pixel electrode layer on the passivation layer, wherein a via hole is formed in the passivation layer The via hole is located directly above a portion of the drain exposed by the opening portion, and the pixel electrode layer is connected to a drain of the switching element through the via hole.
  • the first conductive layer further includes a data line connected to a source of the switching element, at least a portion of an interface of the first color filter pattern and the second color filter pattern being located Directly above the data line.
  • At least a portion of the interface of the first color filter pattern and the second color filter pattern is located directly above the data line.
  • the color filter layer further includes a third color filter pattern adjacent to the first color filter pattern and having a different color, and a gate line connected to a gate of the switching element, Wherein at least a portion of the interface of the first color filter pattern and the third color filter pattern is located directly above the gate line.
  • the material of the color filter layer is a photoresist resin.
  • Another embodiment of the present disclosure provides a display device including any of the above array substrates.
  • a further embodiment of the present disclosure provides a method of fabricating an array substrate, comprising: forming a first conductive layer on a base substrate, the first conductive layer including a source of the switching element; and forming on the first conductive layer a color filter layer, wherein the color filter layer abuts the source of the switching element in a direction perpendicular to the substrate.
  • the manufacturing method further includes forming a second conductive layer on the color filter layer, including a common electrode, wherein the color filter is in a direction perpendicular to the substrate The layer also abuts the common electrode.
  • the first conductive layer further includes a data line connected to a source of the switching element
  • the second conductive layer further includes a common line connected to the common electrode
  • the color filter The layer is configured to electrically isolate the data line from the intersection of the data line and the common line Altogether.
  • forming a color filter layer on the first conductive layer includes:
  • first color filter pattern layer and a second color filter pattern layer of different colors Forming a first color filter pattern layer and a second color filter pattern layer of different colors on the first conductive layer, wherein the first color filter pattern layer and the second color filter pattern layer are adjacent to each other at an interface And having no gap; and removing a portion of at least one of the first color filter pattern layer and the second color filter pattern layer at an interface thereof to form the first color filter pattern and the first a second color filter pattern layer and an opening portion between the first color filter pattern and the second color filter pattern and penetrating through the color filter layer, wherein the first conductive layer further Including a drain of the switching element, the opening portion exposing a portion of the drain, a drain of the switching element and the first color filter pattern in a direction perpendicular to the substrate substrate And the second color filter pattern is coincident.
  • the manufacturing method further includes: forming a passivation layer on the second conductive layer; and forming a pixel electrode layer on the passivation layer, wherein a via hole is formed in the passivation layer The via hole is located directly above a portion of the drain exposed by the opening portion, and the pixel electrode layer is connected to a drain of the switching element through the via hole.
  • the material of the color filter layer is a photoresist resin, and at least one of removing the first color filter pattern layer and the second color filter pattern layer is performed by exposure and development. Part of its interface.
  • the manufacturing method further includes: pairing the first filter The color pattern layer and the second color filter pattern layer are baked.
  • the first conductive layer further includes a data line connected to a source of the switching element, at least a portion of an interface of the first color filter pattern and the second color filter pattern being located Directly above the data line.
  • At least a portion of the interface of the first color filter pattern and the second color filter pattern is located directly above the data line.
  • the color filter layer further includes a third color filter pattern adjacent to the first color filter pattern and having a different color, and a gate line connected to a gate of the switching element Its At least a portion of an interface of the first color filter pattern and the third color filter pattern is located directly above the gate line.
  • the manufacturing process can be simplified to reduce the thickness of the display device.
  • 1 is a schematic structural view of a display panel
  • FIG. 2 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure
  • FIG. 9 are cross-sectional structural views of different stages of a fabrication process of an array substrate according to Embodiment 1 of the present disclosure.
  • FIG. 10 is a schematic cross-sectional structural view of a display panel according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic cross-sectional structural view of an array substrate according to Embodiment 2 of the present disclosure.
  • FIG. 12 is a schematic diagram of a planar structure of an array substrate according to an embodiment of the present disclosure.
  • a low temperature poly-Silicon (LTPS) product in a thin film transistor liquid crystal display panel includes an array substrate 100 and a color filter substrate 101 disposed opposite to each other, and between the array substrate 100 and the color filter substrate 101.
  • the liquid crystal layer 111 wherein the array substrate 100 includes a data line 103 on the base substrate 102, a resin layer 107 on the data line 103, a common electrode 104 on the resin layer 107, and an insulating layer on the common electrode 104.
  • the resin layer 107 is used as a flat layer to block the data line metal layer and the public
  • the signal crosstalk between the common electrodes and the color filter pattern are coated on the side of the color filter substrate 101, so that the thickness of the display panel is increased, and the material is wasted, resulting in complicated process flow.
  • the embodiments of the present disclosure provide an array substrate, a manufacturing method thereof, and a display device, which are used to save the resin layer in the above technical solution, save cost, and simplify the process flow.
  • an embodiment of the present disclosure provides a method for manufacturing an array substrate, including:
  • the color filter pattern of the embodiment of the present disclosure includes a red color filter pattern, a green color filter pattern, and a blue color filter pattern.
  • the color filter pattern may further include other colors in actual production.
  • the color filter pattern such as: may also include a yellow color filter pattern.
  • the following embodiments of the present disclosure are described by way of example only in which the color filter pattern includes a red color filter pattern, a green color filter pattern, and a blue color filter pattern.
  • the method since the method has a plurality of color filter patterns arranged in an array on the source and the drain, the adjacent two color filter patterns are adjacent and have no gap therebetween.
  • the color filter pattern formed by the embodiment of the present disclosure can play a flat role and can block signal crosstalk between the source and drain metal layers and the subsequently fabricated common electrode, and thus, the embodiment of the present disclosure can save Going to the resin layer of the prior art, saving cost and simplifying the process flow; in addition, since the color filter pattern in the preset area at the interface of the adjacent two color filter patterns is exposed and developed by the embodiment of the present disclosure, the removal is performed.
  • the color filter pattern in the preset area can separate the color filter patterns of different colors, and the color mixing between the color filter patterns can be avoided.
  • the color filter pattern is formed in the embodiment of the present disclosure. On the array substrate side, the thickness of the display panel can be reduced.
  • the thin film transistor included in the array substrate of the embodiment of the present disclosure may be a bottom gate type thin film transistor or a top gate type thin film transistor.
  • the thin film transistor may be a side gate type thin film transistor.
  • the embodiment of the present disclosure mainly introduces a top gate type thin film transistor and a bottom gate type thin film transistor as an example.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • Embodiment 1 of the present disclosure describes an example in which a thin film transistor included in an array substrate is a top gate type thin film transistor.
  • the embodiment of the present disclosure further includes: forming a light shielding layer 301 on the substrate substrate 102 by a patterning process, and patterning in the embodiment of the present disclosure.
  • the process includes coating, exposing, developing, and removing some or all of the photoresist.
  • a metal layer is deposited on the base substrate 102, and then the metal layer is exposed and developed to form a pattern of the light shielding layer, and then the metal layer is wet etched, and finally the remaining photoresist is removed to form a blackout.
  • the base substrate 102 of the embodiment of the present disclosure may be a glass substrate, a quartz substrate, or a flexible substrate.
  • the metal layer deposited in the embodiment of the present disclosure may be molybdenum (Mo), aluminum (Al), or nickel (Ni). Any single metal layer of the same may be a composite metal layer formed by combining any metal.
  • a buffer layer 302 is formed on the light shielding layer 301, and a semiconductor active layer 304 is formed on the buffer layer 302 by a patterning process.
  • the semiconductor active layer 304 in the embodiment of the present disclosure is a low temperature polysilicon semiconductor active layer.
  • an amorphous silicon layer is deposited on the buffer layer 302, and then the amorphous silicon layer is exposed and developed to form a pattern of the semiconductor active layer, and then the amorphous silicon layer is dry etched and finally removed. The remaining photoresist is subjected to an excimer laser annealing treatment on the formed amorphous silicon layer to form a semiconductor active layer 304.
  • a first insulating layer 303 is formed on the semiconductor active layer 304, and a gate electrode 305 is formed on the first insulating layer 303 by a patterning process.
  • a metal layer is deposited on the first insulating layer 303, and then the metal layer is exposed and developed to form a pattern of the gate electrode, and then the metal layer is wet etched, and finally the remaining photoresist is removed.
  • the gate layer 305 is formed.
  • the metal layer deposited in the embodiment of the present disclosure may be any single metal layer of molybdenum (Mo), aluminum (Al), nickel (Ni), or the like, or may be a composite metal layer formed by combining any metal.
  • a second insulating layer 306 is formed on the gate 305 by a patterning process.
  • the material of the second insulating layer 306 may be the same as or different from the material of the first insulating layer 303, and the second insulating layer 306 may be silicon oxide or silicon nitride, or silicon oxide and silicon nitride. Combination material.
  • an insulating film layer is deposited on the gate 305, and then the insulating film layer is exposed and developed to form a pattern of the second insulating layer, and then the insulating film layer is dry etched to finally remove the remaining light.
  • the second insulating layer 306 is formed by engraving.
  • the source 307 and the drain 308 are formed on the second insulating layer 306 by a patterning process.
  • the materials of the source 307 and the drain 308 of the embodiment of the present disclosure may be made of the same material as the gate 305. Of course, different materials may also be used. In order to save material cost, for example, the materials of the source 307 and the drain 308 are the same as the material of the gate 305.
  • a metal layer may be deposited on the second insulating layer 306, and then the metal layer is exposed and developed to form a pattern of the source 307 and the drain 308, and then the metal layer is wet or dry etched. Finally, the remaining photoresist is removed to form source 307 and drain 308.
  • a red resin layer 400 is formed on the source 307 and the drain 308.
  • the red photoresist resin layer 400 can be formed by spin coating or the like, and the red photoresist resin layer 400 can be formed. Exposure and development, the direction of the black arrow in the figure indicates the direction of light propagation during exposure, and the material characteristics of the red photoresist resin layer 400 of the embodiment of the present disclosure are the same as those of the resin layer 107 of FIG.
  • the spin coating thickness of the photoresist resin layer 400 may be the same as the thickness of the resin layer 107 of FIG. 1, and after development, a red color filter pattern 401 corresponding to the sub-pixel unit is formed, as shown in FIG.
  • a green color filter pattern 402 and a blue color filter pattern 403, a red color filter pattern 401, and a green color filter pattern 402 are formed on the source 307 and the drain 308 by the same method. There is no gap between the blue color filter pattern 403 and the red color filter pattern 401, the green color filter pattern 402, and the blue color filter pattern 403 are formed above the drain 308.
  • a green photoresist resin layer is spin-coated on the base substrate on which the red color filter pattern 401 is formed, and the green photoresist resin layer is exposed and developed to form a green color filter corresponding to the sub-pixel unit.
  • the pattern 402, the green color filter pattern 402 and the red color filter pattern 401 are adjacent and have no gap;
  • a blue photoresist resin layer is spin-coated on the base substrate on which the green color filter pattern 402 is formed,
  • the blue photoresist resin layer is exposed and developed to form a blue color filter pattern 403 corresponding to the sub-pixel unit, and the blue color filter pattern 403 and the green color filter pattern 402 are adjacent to each other without a gap.
  • the red color filter pattern 401 and the green color filter pattern 402 in the preset area at the interface of the red color filter pattern 401 and the green color filter pattern 402 are exposed and developed, and are green.
  • the green color filter pattern 402 and the blue color filter pattern 403 in the preset area at the interface of the color filter pattern 402 and the blue color filter pattern 403 are exposed and developed, and the direction of the black arrow in the figure indicates the light during the exposure.
  • the direction of the spread is set according to actual production needs, as long as the hole formed after development can be ensured that the subsequently fabricated pixel electrode can be connected to the drain, and the spacing between the color filter patterns can be avoided.
  • the color of the cross can occur.
  • a hole H penetrating through the red color filter pattern 401 and the green color filter pattern 402 is formed between the adjacent red color filter patterns 401 and the green color filter patterns 402 after development (example of the opening portion) a portion of the drain 308 is exposed at the hole position, and a hole penetrating the green color filter pattern 402 and the blue color filter pattern 403 is formed between the adjacent green color filter pattern 402 and the blue color filter pattern 403 A portion of the drain 308 is exposed at the location of the hole.
  • the embodiment of the present disclosure further includes: after exposing and developing the color photoresist
  • the resin layer is baked in a preset temperature range to achieve the effect of curing, and the preset temperature of the embodiment of the present disclosure is set according to actual production needs.
  • the red color filter pattern 401, the green color filter pattern 402, and the blue color filter pattern 403 shown in FIG. 8 are baked at 240 ° C for 40 minutes.
  • the dielectric constant of the color filter pattern of the embodiment of the present disclosure is very close to the dielectric constant of the organic insulating film, so the crosstalk between the source 307 and the drain 308 and the subsequently fabricated pixel electrode and the common electrode is also small, and does not affect the array.
  • the embodiment of the present disclosure effectively utilizes the specificity of the metal layer wiring of the source 307 and the drain 308 and the specificity of the light blocking, so that the wiring of the metal layers of the source 307 and the drain 308 functions as an occlusion.
  • the common electrode 901 is formed on the red color filter pattern 401, the green color filter pattern 402, and the blue color filter pattern 403 by a patterning process, and passivation is performed on the common electrode 901 by a patterning process.
  • Layer 902, a pixel electrode 903 is formed on the passivation layer 902 by a patterning process, and the pixel electrode 903 is electrically connected to the exposed drain 308.
  • the manufacturing method of the common electrode 901, the passivation layer 902, and the pixel electrode 903 of the embodiment of the present disclosure may be the same as the prior art, and details are not described herein again.
  • the material of the common electrode of the embodiment of the present disclosure may be the same as or different from the material of the pixel electrode.
  • the material of the common electrode is the same as that of the pixel electrode, and may be a single layer film of indium tin oxide or indium zinc oxide, or a composite film layer of indium tin oxide and indium zinc oxide.
  • the pixel electrode 903 may be first formed on the red color filter pattern 401, the green color filter pattern 402, and the blue color filter pattern 403 by a patterning process, and then fabricated on the pixel electrode 903 by a patterning process.
  • the passivation layer 902 is formed on the passivation layer 902 by a patterning process.
  • the manufacturing method of the common electrode 901, the passivation layer 902, and the pixel electrode 903 can also be the same as the prior art, and details are not described herein. .
  • an embodiment of the present disclosure provides a display panel including an array substrate 100' provided in an embodiment of the present disclosure, an opposite substrate 1000 disposed opposite the array substrate 100, and disposed therebetween.
  • the liquid crystal layer 111 In the cross-sectional structure of the array substrate 100' shown in Fig. 10, the data line 103, the color filter layer 108', the common line 104, the insulating layer 105, and the pixel electrode layer 106 are sequentially formed on the base substrate 102.
  • other layer structures may be formed between the base substrate 102 and the data lines 103.
  • the data line 103 is, for example, the same material as the source and drain of the thin film transistor.
  • the data line 103 is formed integrally with, for example, a source of a thin film transistor. Referring to Fig. 10, for example, color filter layer 108' electrically isolates common line 104 and data line 103 at intersections of common line 104 and data line 103. In addition to being capable of transmitting data signals and/or touch signals, the data lines in the embodiments of the present disclosure can block the backlight and function as a light blocking function of the black matrix.
  • the color filter layer 108' may include a black matrix portion 1001 formed at an intersection of the common line 104 and the data line 103.
  • the color filter pattern 108' of the embodiment of the present disclosure is located on the array substrate, and the display panel is not affected by the alignment error of the upper and lower substrates, thereby reducing the occurrence of light leakage and cross-color defects.
  • the embodiment of the present disclosure passes through FIG. 7 and The recessed portion of the black matrix portion 1001 directly above the data line 103 formed by the step of FIG. 8 enables the formation of a smaller-sized black matrix portion, which in turn can increase the aperture ratio of the display panel.
  • the first conductive layer L1 includes a data line 103, a source 307 and a drain 308 of the thin film transistor.
  • the second conductive layer L2 includes a common electrode 901 and a common line 104 connected thereto.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the second embodiment of the present disclosure is described by taking a thin film transistor including an array substrate as a bottom gate type thin film transistor as an example.
  • the embodiment of the present disclosure fabricates a source on the base substrate 102 by a patterning process.
  • the method further includes: forming a gate electrode 305 on the substrate substrate 102 by a patterning process; forming a first insulating layer 303 on the gate electrode 305, and fabricating a semiconductor active on the first insulating layer 303 by a patterning process Layer 304; a second insulating layer 306 is formed on the semiconductor active layer 304 by a patterning process.
  • the manufacturing method of the gate electrode 305, the first insulating layer 303, the semiconductor active layer 304, and the second insulating layer 306 of the embodiment of the present disclosure may be the same as the prior art, and details are not described herein again.
  • the source 307 and the drain 308 are formed on the second insulating layer 306 by a patterning process.
  • the manufacturing method of the source 307 and the drain 308 is the same as that of the first embodiment of the present disclosure, and details are not described herein again.
  • a red color filter pattern 401, a green color filter pattern 402, and a blue color filter pattern 403, a red color filter pattern 401, a green color filter pattern 402, and blue are formed on the source 307 and the drain 308.
  • the manufacturing method of the color filter pattern 403 is the same as that of the first embodiment of the present disclosure, and details are not described herein again.
  • the common electrode 901 is formed on the red color filter pattern 401, the green color filter pattern 402, and the blue color filter pattern 403 by a patterning process, and passivation is performed on the common electrode 901 by a patterning process.
  • the layer 902 is formed on the passivation layer 902 by a patterning process.
  • the manufacturing method of the common electrode 901, the passivation layer 902 and the pixel electrode 903 in the embodiments of the present disclosure may be the same as the prior art, and details are not described herein again.
  • the first conductive layer L1 includes a data line 103, a source 307 and a drain 308 of the thin film transistor.
  • the second conductive layer L2 includes a common electrode 901 and a common line 104 connected thereto.
  • the pixel electrode 903 may be first formed on the red color filter pattern 401, the green color filter pattern 402, and the blue color filter pattern 403 by a patterning process, and then fabricated on the pixel electrode 903 by a patterning process.
  • the passivation layer 902 is formed on the passivation layer 902 by a patterning process.
  • the manufacturing method of the common electrode 901, the passivation layer 902, and the pixel electrode 903 can be the same as the prior art, and details are not described herein again.
  • an embodiment of the present disclosure further provides an array substrate including a source 307 and a drain 308 on a substrate substrate 102, and a source 307 and a drain.
  • a plurality of arrays of color filter patterns red color filter pattern 401, green color filter pattern 402, and blue color filter pattern 403 on each of 308, each color filter pattern and sub-pixel unit of the array substrate
  • a gap penetrating through the color filter pattern exists in a preset area between adjacent two color filter patterns, and a part of the drain 308 is exposed at a gap position corresponding to the position of the drain 308.
  • the array substrate of the embodiment of the present disclosure includes, for example, a light shielding layer 301, a buffer layer 302, a semiconductor active layer 304, a first insulating layer 303, and a gate 305, which are sequentially disposed on the substrate substrate 102.
  • the array substrate of the embodiment of the present disclosure may further include: a light shielding layer 301, a buffer layer 302, a semiconductor active layer 304, a first insulating layer 303, a gate electrode 305, and a second insulating layer 306, which are sequentially disposed on the substrate.
  • the array substrate of the embodiment of the present disclosure includes: a gate electrode 305 sequentially disposed on the substrate substrate 102 , a first insulating layer 303 , a semiconductor active layer 304 , a second insulating layer 306 , and a source 307 . And a drain 308, a color filter pattern (a red color filter pattern 401, a green color filter pattern 402, and a blue color filter pattern 403), a common electrode 901, a passivation layer 902, and a pixel electrode 903.
  • the array substrate of the embodiment of the present disclosure may further include: a gate electrode 305 sequentially disposed on the substrate substrate 102, a first insulating layer 303, a semiconductor active layer 304, a second insulating layer 306, a source 307, and a drain 308.
  • a color filter pattern (a red color filter pattern 401, a green color filter pattern 402, and a blue color filter pattern 403), a pixel electrode 903, a passivation layer 902, and a common electrode 901.
  • the gate line GL, the common line CL, and the data line DL define four sub-pixel units.
  • a thin film transistor TFT (as an example of a switching element) and a sub-pixel electrode PX are included in each sub-pixel unit.
  • a simplified explanation is shown in which the common electrodes in the respective sub-pixel units are not shown.
  • the source of the thin film transistor TFT is connected to the gate line GL, the source is connected to the data line DL, and the drain is connected to the pixel electrode PX.
  • the thin film transistor TFT is shown with its drain. Referring to FIG.
  • the lower right and upper left sub-pixel units further include, for example, a red color filter pattern P1; the lower left sub-pixel unit further includes, for example, a green color filter pattern P2; and the upper right sub-pixel unit includes, for example, a blue filter.
  • Color pattern P3 The red color filter pattern P1 and the green color filter pattern P2 are formed with an opening H directly above the drain of the TFT. The opening portion H exposes a portion of the drain.
  • the embodiment of the present disclosure further provides a display device, which includes the above array substrate provided by the embodiment of the present disclosure, and the display device may be a liquid crystal panel, a liquid crystal display, a liquid crystal television, or an organic light emitting diode ( Organic Light Emitting Diode, OLED) Display devices such as panels, OLED displays, OLED TVs or electronic paper.
  • a display device which includes the above array substrate provided by the embodiment of the present disclosure, and the display device may be a liquid crystal panel, a liquid crystal display, a liquid crystal television, or an organic light emitting diode ( Organic Light Emitting Diode, OLED) Display devices such as panels, OLED displays, OLED TVs or electronic paper.
  • OLED Organic Light Emitting Diode
  • the embodiments of the present disclosure provide a method for fabricating an array substrate, comprising: fabricating a source and a drain on a substrate by a patterning process; and forming a plurality of arrays of color filters on the source and the drain.
  • a color filter pattern corresponding to the sub-pixel unit of the array substrate adjacent two color filter patterns are adjacent and have no gap; and a preset area is disposed at an interface between adjacent two color filter patterns The color filter pattern is exposed and developed to remove the color filter pattern in the predetermined area, and a portion of the drain is exposed at a position corresponding to the drain.
  • the method has a plurality of color filter patterns arranged in an array on the source and the drain, the adjacent two color filter patterns are adjacent and have no gap therebetween, and thus the color filter formed by the embodiment of the present disclosure is formed.
  • the pattern can play a flat role and can block signal crosstalk between the source and drain metal layers and the subsequently fabricated common electrode. Therefore, the embodiment of the present disclosure can omit the prior art resin layer, saving cost and simplifying a process flow; in addition, since the color filter pattern in the preset area at the interface of the adjacent two color filter patterns is exposed and developed by the embodiment of the present disclosure, the color filter pattern in the preset area is removed, Therefore, the color filter patterns of different colors can be separated, and the color mixture between the color filter patterns can be avoided.
  • the color filter pattern is formed on the array substrate side, and the thickness of the display panel can be reduced. .

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Abstract

一种阵列基板(100)及其制造方法、显示装置。阵列基板(100)包括：衬底基板(102)；位于衬底基板(102)上的第一导电层(L1)，包括开关元件(TFT)的源极(307)；以及位于第一导电层(L1)上的彩色滤色器层(108')，其中，在垂直于衬底基板(102)的方向上，彩色滤色器层(108')邻接开关元件(TFT)的源极(307)。这样，用以简化工艺流程且减少显示装置的厚度。

Description

阵列基板及其制造方法、显示装置 技术领域
本公开的实施例涉及一种阵列基板及其制造方法、显示装置。
背景技术
薄膜晶体管液晶显示面板(Thin Film Transistor Liquid Crystal Display，TFT-LCD)是目前常用的平板显示器，液晶显示面板以其体积小、功耗低、无辐射、分辨率高等优点，被广泛地应用于现代数字信息化设备中。
发明内容
本公开实施例提供了一种阵列基板及其制造方法、显示装置，用以省去现有技术的树脂层，节约成本，简化工艺流程。
本公开实施例提供的一种阵列基板，包括：衬底基板；位于所述衬底基板上的第一导电层，包括开关元件的源极；以及位于所述第一导电层上的彩色滤色器层，其中，在垂直于所述衬底基板的方向上，所述彩色滤色器层邻接所述开关元件的所述源极。
在一个示例中，所述阵列基板还包括：位于所述彩色滤色器层上的第二导电层，包括公共电极，其中，在垂直于所述衬底基板的方向上，所述彩色滤色器层还邻接所述公共电极。
在一个示例中，所述第一导电层还包括与所述开关元件的源极连接的数据线，所述第二导电层还包括与所述公共电极连接的公共线，所述彩色滤色器层构造为在所述数据线与所述公共线的交叉处电性隔离述数据线与所述公共线。
在一个示例中，所述彩色滤色器层包括相邻的第一滤色器图案和第二滤色器图案，以及位于所述第一滤色器图案和所述第二滤色器图案之间且贯穿所述彩色滤色器层的开口部，其中，第一滤色器图案和第二滤色器图案的颜色不同，所述第一导电层还包括所述开关元件的漏极，所述开口部暴露出所 述漏极的一部分，在垂直于所述衬底基板的方向上，所述开关元件的漏极与所述第一滤色器图案和所述第二滤色器图案重合。
在一个示例中，所述阵列基板还包括：位于所述第二导电层上的钝化层；以及位于所述钝化层上的像素电极层，其中，所述钝化层中形成有过孔，所述过孔位于所述漏极的被所述开口部暴露的部分的正上方，所述像素电极层通过所述过孔与所述开关元件的漏极相连。
在一个示例中，所述第一导电层还包括与所述开关元件的源极连接的数据线，所述第一滤色器图案和所述第二滤色器图案的交界面的至少一部分位于所述数据线的正上方。
在一个示例中，所述第一滤色器图案和所述第二滤色器图案的交界面的至少一部分位于所述数据线的正上方。
在一个示例中，所述彩色滤光器层还包括与所述第一滤色器图案相邻且颜色不同的第三滤色器图案，以及与所述开关元件的栅极连接的栅线，其中，所述第一滤色器图案和所述第三滤色器图案的交界面的至少一部分位于所述栅线的正上方。
在一个示例中，所述彩色滤光器层的材料为光刻胶树脂。
本公开另一实施例提供一种显示装置，包括上述任一项阵列基板。
本公开又一实施例提供一种阵列基板的制造方法，包括：在衬底基板上形成第一导电层，该第一导电层包括开关元件的源极；以及在所述第一导电层上形成彩色滤色器层，其中，在垂直于所述衬底基板的方向上，所述彩色滤色器层邻接所述开关元件的所述源极。
在一个示例中，所述制造方法还包括：在所述彩色滤色器层上形成第二导电层，包括公共电极，其中，在垂直于所述衬底基板的方向上，所述彩色滤色器层还邻接所述公共电极。
在一个示例中，所述第一导电层还包括与所述开关元件的源极连接的数据线，所述第二导电层还包括与所述公共电极连接的公共线，所述彩色滤色器层构造为在所述数据线与所述公共线的交叉处电性隔离述数据线与所述公 共线。
在一个示例中，在所述第一导电层上形成彩色滤色器层包括：
在所述第一导电层上形成颜色不同的第一滤色器图案层和第二滤色器图案层，其中第一滤色器图案层和第二滤色器图案层在交界面处彼此邻接且无间隙；以及去除所述第一滤色器图案层和所述第二滤色器图案层至少之一在其交界面处的一部分，以形成所述第一滤色器图案和所述第二滤色器图案层以及在位于所述第一滤色器图案和所述第二滤色器图案之间且贯穿所述彩色滤色器层的开口部，其中，所述第一导电层还包括所述开关元件的漏极，所述开口部暴露出所述漏极的一部分，在垂直于所述衬底基板的方向上，所述开关元件的漏极与所述第一滤色器图案和所述第二滤色器图案重合。
在一个示例中，所述制造方法还包括：在所述第二导电层上形成钝化层；以及在所述钝化层上形成像素电极层，其中，所述钝化层中形成有过孔，所述过孔位于所述漏极的被所述开口部暴露的部分的正上方，所述像素电极层通过所述过孔与所述开关元件的漏极相连。
在一个示例中，所述彩色滤色器层的材料为光刻胶树脂，且通过曝光和显影执行去除所述第一滤色器图案层和所述第二滤色器图案层至少之一在其交界面处的一部分。
在一个示例中，去除所述第一滤色器图案层和所述第二滤色器图案层至少之一在其交界面处的一部分之后，所述制造方法还包括：对所述第一滤色器图案层和所述第二滤色器图案层进行烘烤。
在一个示例中，所述第一导电层还包括与所述开关元件的源极连接的数据线，所述第一滤色器图案和所述第二滤色器图案的交界面的至少一部分位于所述数据线的正上方。
在一个示例中，所述第一滤色器图案和所述第二滤色器图案的交界面的至少一部分位于所述数据线的正上方。
在一个示例中，所述彩色滤色器层还包括与所述第一滤色器图案相邻的且颜色不同的第三滤色器图案，以及与所述开关元件的栅极连接的栅线，其 中，所述第一滤色器图案和所述第三滤色器图案的交界面的至少一部分位于所述栅线的正上方。
这样，可以简化制造工艺减少显示装置的厚度。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为显示面板结构示意图；
图2为本公开实施例提供的一种阵列基板的制造方法流程图；
图3-图9为本公开实施例一提供的一种阵列基板的制作过程的不同阶段的截面结构图；
图10为本公开实施例提供的显示面板的截面结构示意图；
图11为本公开实施例二提供的一种阵列基板的截面结构示意图；
图12为本公开实施例提供的一种阵列基板的平面结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
如图1所示，薄膜晶体管液晶显示面板中的低温多晶硅(Low Temperature Poly-Silicon,LTPS)产品包括相对设置的阵列基板100和彩膜基板101，以及位于阵列基板100和彩膜基板101之间的液晶层111，其中，阵列基板100包括位于衬底基板102上的数据线103、位于数据线103上的树脂层107、位于树脂层107上的公共电极104、位于公共电极104上的绝缘层105、位于绝缘层105上的像素电极106；彩膜基板101包括位于衬底基板102上的彩色滤色器图案108，以及位于相邻的彩色滤色器图案108之间的黑矩阵109。
在上述阵列基板中，用树脂层107充当平坦层，阻隔数据线金属层和公 共电极之间的信号串扰，并在彩膜基板101侧涂布彩色滤色器图案，这样制作不但增加显示面板厚度，而且浪费材料，造成工艺流程复杂。
本公开实施例提供了一种阵列基板及其制造方法、显示装置，用以省去上述技术方案中的树脂层，节约成本，简化工艺流程。
如图2所示，本公开实施例提供了一种阵列基板的制造方法，包括：
S201、通过构图工艺在衬底基板上制作源极和漏极；
S202、在所述源极和所述漏极上制作若干阵列排列的彩色滤色器图案，每一所述彩色滤色器图案与阵列基板的亚像素单元对应，相邻两所述彩色滤色器图案之间邻接且无间隙；
S203、对相邻两所述彩色滤色器图案交界面处预设区域内的彩色滤色器图案进行曝光和显影，去除该预设区域内的彩色滤色器图案，在与所述漏极对应位置处暴露出部分漏极。
例如，本公开实施例的彩色滤色器图案包括红色滤色器图案、绿色滤色器图案和蓝色滤色器图案，当然，在实际生产过程中，彩色滤色器图案还可以包括其它颜色的滤色器图案，如：还可以包括黄色滤色器图案。本公开以下的实施例仅以彩色滤色器图案包括红色滤色器图案、绿色滤色器图案和蓝色滤色器图案为例介绍。
由本公开实施例提供的阵列基板的制造方法，由于该方法在源极和漏极上制作有若干阵列排列的彩色滤色器图案，相邻两彩色滤色器图案之间邻接且无间隙，因此，通过本公开实施例制作形成的彩色滤色器图案能够起到平坦作用，并且能够阻隔源极和漏极金属层与后续制作的公共电极之间的信号串扰，因此，本公开实施例能够省去现有技术的树脂层，节约成本，简化工艺流程；另外，由于本公开实施例对相邻两彩色滤色器图案交界面处预设区域内的彩色滤色器图案进行曝光和显影，去除该预设区域内的彩色滤色器图案，因此能够将不同颜色的滤色器图案分隔开，能够避免彩色滤色器图案之间的混色发生，本公开实施例将彩色滤色器图案制作在阵列基板侧，能够减小显示面板的厚度。
下面结合附图详细介绍本公开实施例提供的阵列基板的制造方法，附图中各膜层厚度和区域大小、形状不反应各膜层的真实比例，目的只是示意说明本公开内容。
例如，本公开实施例的阵列基板包括的薄膜晶体管可以为底栅型的薄膜晶体管，也可以为顶栅型的薄膜晶体管，当然，在实际生产过程中，还可以为其它类型的薄膜晶体管，如：薄膜晶体管可以为侧栅型的薄膜晶体管，本公开实施例主要以顶栅型的薄膜晶体管和底栅型的薄膜晶体管为例进行介绍。
实施例一：
本公开实施例一以阵列基板包括的薄膜晶体管为顶栅型的薄膜晶体管为例进行介绍。
如图3所示，本公开实施例通过构图工艺在衬底基板上制作源极和漏极之前，还包括：在衬底基板102上通过构图工艺制作遮光层301，本公开实施例中的构图工艺包括光刻胶的涂覆、曝光、显影、去除光刻胶的部分或全部过程。例如，在衬底基板102上沉积一层金属层，然后对金属层进行曝光、显影，形成遮光层的图形，之后再对金属层进行湿法刻蚀，最后去除剩余的光刻胶，形成遮光层301。本公开实施例的衬底基板102可以为玻璃基板，也可以为石英基板，还可以为柔性基板，本公开实施例沉积的金属层可以为钼(Mo)、铝(Al)、镍(Ni)等的任一单层金属层，也可以为任意金属组合形成的复合金属层。
如图3所示，接着，在遮光层301上制作缓冲层302，在缓冲层302上通过构图工艺制作半导体有源层304。例如，本公开实施例中的半导体有源层304为低温多晶硅半导体有源层。实施时，在缓冲层302上沉积一层非晶硅层，然后对非晶硅层进行曝光、显影，形成半导体有源层的图形，之后再对非晶硅层进行干法刻蚀，最后去除剩余的光刻胶，并对形成的非晶硅层进行准分子激光退火处理，形成半导体有源层304。
如图3所示，接着，在半导体有源层304上制作第一绝缘层303，在第一绝缘层303上通过构图工艺制作栅极305。实施时，在第一绝缘层303上沉积一层金属层，然后对金属层进行曝光、显影，形成栅极的图形，之后再对金属层进行湿法刻蚀，最后去除剩余的光刻胶，形成栅极305，本公开实施例沉积的金属层可以为钼(Mo)、铝(Al)、镍(Ni)等的任一单层金属层，也可以为任意金属组合形成的复合金属层。
如图3所示，接着，在栅极305上通过构图工艺制作第二绝缘层306， 本公开实施例第二绝缘层306的材料可以与第一绝缘层303的材料相同，也可以不相同，第二绝缘层306可以为氧化硅或氮化硅，也可以为氧化硅和氮化硅的组合材料。实施时，在栅极305上沉积一层绝缘膜层，然后对绝缘膜层进行曝光、显影，形成第二绝缘层的图形，之后再对绝缘膜层进行干法刻蚀，最后去除剩余的光刻胶，形成第二绝缘层306。
如图3所示，接着，在第二绝缘层306上通过构图工艺制作源极307和漏极308，本公开实施例源极307和漏极308的材料可以与栅极305采用相同的材料，当然也可以采用不同的材料，本公开实施例为了节省材料成本，例如，源极307和漏极308的材料与栅极305的材料相同。实施时，可在第二绝缘层306上沉积一层金属层，然后对金属层进行曝光、显影，形成源极307和漏极308的图形，之后再对金属层进行湿法或干法刻蚀，最后去除剩余的光刻胶，形成源极307和漏极308。
如图4所示，接着，在源极307和漏极308上制作一层红色树脂层400，例如可以采用旋涂等方式制作红色光刻胶树脂层400，对红色光刻胶树脂层400进行曝光和显影，图中黑色箭头方向表示曝光过程中光线的传播方向，本公开实施例红色光刻胶树脂层400的材料特性采用与图1中树脂层107的材料特性相同的树脂材料，并且红色光刻胶树脂层400的旋涂厚度可以与图1树脂层107的厚度相同，显影后形成与亚像素单元对应的红色滤色器图案401，如图5所示。
如图6所示，接着，采用同样的方法在源极307和漏极308上形成绿色滤色器图案402和蓝色滤色器图案403，红色滤色器图案401、绿色滤色器图案402和蓝色滤色器图案403之间无间隙，红色滤色器图案401、绿色滤色器图案402和蓝色滤色器图案403的交界处形成在漏极308的上方。
例如，在形成有红色滤色器图案401的衬底基板上旋涂一层绿色光刻胶树脂层，对绿色光刻胶树脂层进行曝光和显影，形成与亚像素单元对应的绿色滤色器图案402，绿色滤色器图案402与红色滤色器图案401之间邻接且无间隙；在形成有绿色滤色器图案402的衬底基板上旋涂一层蓝色光刻胶树脂层，对蓝色光刻胶树脂层进行曝光和显影，形成与亚像素单元对应的蓝色滤色器图案403，蓝色滤色器图案403与绿色滤色器图案402之间邻接且无间隙。
如图7所示，接着，对红色滤色器图案401和绿色滤色器图案402交界面处预设区域内的红色滤色器图案401和绿色滤色器图案402进行曝光和显影，对绿色滤色器图案402和蓝色滤色器图案403交界面处预设区域内的绿色滤色器图案402和蓝色滤色器图案403进行曝光和显影，图中黑色箭头方向表示曝光过程中光线的传播方向。本公开实施例中的预设区域根据实际生产需要设定，只要能够使得显影后形成的孔洞能够确保后续制作的像素电极能够与漏极连接，并且彩色滤色器图案之间产生的间距能够避免串色的发生即可。
如图8所示，显影后在相邻的红色滤色器图案401和绿色滤色器图案402之间形成贯穿红色滤色器图案401和绿色滤色器图案402的孔洞H(开口部的示例)，孔洞位置处暴露出部分漏极308，在相邻的绿色滤色器图案402和蓝色滤色器图案403之间形成贯穿绿色滤色器图案402和蓝色滤色器图案403的孔洞，孔洞位置处暴露出部分漏极308。
例如，本公开实施例在对相邻两彩色滤色器图案交界面处预设区域内的彩色光刻胶树脂层进行曝光和显影之后，还包括：对经过曝光和显影后的彩色光刻胶树脂层在预设温度范围内进行烘烤，达到固化的作用，本公开实施例的预设温度根据实际生产需要设定。如：对图8所示的红色滤色器图案401、绿色滤色器图案402和蓝色滤色器图案403在240℃的情况下烘烤40分钟。
本公开实施例彩色滤色器图案的介电常数非常接近有机绝缘膜的介电常数，因此源极307和漏极308与后续制作的像素电极和公共电极的串扰也很小，不会影响阵列基板原有性能；孔洞使彩色滤色器图案之间产生一定间距，暴露出来的下部漏极也会起到挡光作用。本公开实施例有效利用源极307和漏极308金属层布线较密和挡光的特定，使源极307和漏极308金属层的布线起到遮挡作用。
如图9所示，接着，在红色滤色器图案401、绿色滤色器图案402和蓝色滤色器图案403上通过构图工艺制作公共电极901，在公共电极901上通过构图工艺制作钝化层902，在钝化层902上通过构图工艺制作像素电极903，像素电极903与暴露出来的漏极308电连接。本公开实施例公共电极901、钝化层902和像素电极903的制造方法可与现有技术相同，这里不再赘述。本公开实施例公共电极的材料可以与像素电极的材料相同，也可以不相同。 生产过程中，例如公共电极的材料与像素电极的材料相同，可以为氧化铟锡或氧化铟锌的单层膜层，也可以为氧化铟锡和氧化铟锌的复合膜层。
本公开实施例中，还可以在红色滤色器图案401、绿色滤色器图案402和蓝色滤色器图案403上先通过构图工艺制作像素电极903，然后在像素电极903上通过构图工艺制作钝化层902，在钝化层902上通过构图工艺制作公共电极901，这种情况下公共电极901、钝化层902和像素电极903的制造方法也可与现有技术相同，这里不再赘述。
另外，如图10所示，本公开实施例提供一种显示面板，包括本公开实施例提供的阵列基板100’，与该阵列基板100相对设置的对向基板1000，以及设置在两者之间的液晶层111。图10所示的阵列基板100’的截面结构中，数据线103、彩色滤色器层108’、公共线104、绝缘层105和像素电极层106顺次形成在衬底基板102上。这里，衬底基板102和数据线103之间还可能形成有其他层结构(未示出)。数据线103例如与薄膜晶体管的源极和漏极同层同材料。数据线103例如与薄膜晶体管的源极一体形成。参见图10，例如，彩色滤色器层108’在公共线104和数据线103的交叉位置处电性隔离公共线104和数据线103。本公开实施例中的数据线除了能够传输数据信号和/或触控信号外，还能够遮挡背光源，起到黑矩阵的挡光作用。
参见图10，例如，彩色滤色器层108’可以包括形成在公共线104和数据线103的交叉位置处的黑矩阵部分1001。
本公开实施例的彩色滤色器图案108’位于阵列基板上，显示面板不受上下基板对位误差的影响，减小了漏光和串色不良的产生，另外，本公开实施例通过图7和图8的步骤形成的数据线103正上方的容纳黑矩阵部分1001的凹陷部，从而能够形成的尺寸较小的黑矩阵部分，进而能够提升显示面板的开口率。
例如，在本示例中，第一导电层L1包括数据线103，薄膜晶体管的源极307和漏极308。第二导电层L2包括公共电极901和与其相连的公共线104。
实施例二：
本公开实施例二以阵列基板包括的薄膜晶体管为底栅型的薄膜晶体管为例进行介绍。
如图11所示，本公开实施例通过构图工艺在衬底基板102上制作源极 307和漏极308之前，还包括：在衬底基板102上通过构图工艺制作栅极305；在栅极305上制作第一绝缘层303，在第一绝缘层303上通过构图工艺制作半导体有源层304；在半导体有源层304上通过构图工艺制作第二绝缘层306。本公开实施例栅极305、第一绝缘层303、半导体有源层304和第二绝缘层306的制造方法可以与现有技术相同，这里不再赘述。
如图11所示，接着，在第二绝缘层306上通过构图工艺制作源极307和漏极308，源极307和漏极308的制造方法与本公开实施例一相同，这里不再赘述。接着，在源极307和漏极308上制作红色滤色器图案401、绿色滤色器图案402和蓝色滤色器图案403，红色滤色器图案401、绿色滤色器图案402和蓝色滤色器图案403的制造方法与本公开实施例一相同，这里不再赘述。
如图11所示，接着，在红色滤色器图案401、绿色滤色器图案402和蓝色滤色器图案403上通过构图工艺制作公共电极901，在公共电极901上通过构图工艺制作钝化层902，在钝化层902上通过构图工艺制作像素电极903，本公开实施例公共电极901、钝化层902和像素电极903的制造方法可与现有技术相同，这里不再赘述。
例如，在本示例中，第一导电层L1包括数据线103，薄膜晶体管的源极307和漏极308。第二导电层L2包括公共电极901和与其相连的公共线104。
在另一示例中，还可以在红色滤色器图案401、绿色滤色器图案402和蓝色滤色器图案403上先通过构图工艺制作像素电极903，然后在像素电极903上通过构图工艺制作钝化层902，在钝化层902上通过构图工艺制作公共电极901，这种情况下公共电极901、钝化层902和像素电极903的制造方法可与现有技术相同，这里不再赘述。
基于同样的发明构思，如图9和图11所示，本公开实施例还提供了一种阵列基板，包括位于衬底基板102上的源极307和漏极308，位于源极307和漏极308上的若干阵列排列的彩色滤色器图案(红色滤色器图案401、绿色滤色器图案402和蓝色滤色器图案403)，每一彩色滤色器图案与阵列基板的亚像素单元对应；相邻两彩色滤色器图案之间的预设区域内存在贯穿彩色滤色器图案的间隙，与漏极308位置对应的间隙位置处暴露出部分漏极308。
例如，如图9所示，本公开实施例的阵列基板例如包括：依次位于衬底基板102上的遮光层301、缓冲层302、半导体有源层304、第一绝缘层303、栅极305、第二绝缘层306、源极307和漏极308、彩色滤色器图案(红色滤色器图案401、绿色滤色器图案402和蓝色滤色器图案403)、公共电极901、钝化层902和像素电极903。当然，本公开实施例的阵列基板还可以包括：依次位于衬底基板上的遮光层301、缓冲层302、半导体有源层304、第一绝缘层303、栅极305、第二绝缘层306、源极307和漏极308、彩色滤色器图案(红色滤色器图案401、绿色滤色器图案402和蓝色滤色器图案403)、像素电极903、钝化层902和公共电极901。
例如，如图11所示，本公开实施例的阵列基板包括：依次位于衬底基板102上的栅极305、第一绝缘层303、半导体有源层304、第二绝缘层306、源极307和漏极308、彩色滤色器图案(红色滤色器图案401、绿色滤色器图案402和蓝色滤色器图案403)、公共电极901、钝化层902和像素电极903。当然，本公开实施例的阵列基板还可以包括：依次位于衬底基板102上的栅极305、第一绝缘层303、半导体有源层304、第二绝缘层306、源极307和漏极308、彩色滤色器图案(红色滤色器图案401、绿色滤色器图案402和蓝色滤色器图案403)、像素电极903、钝化层902和公共电极901。
图12中，栅线GL、公共线CL和数据线DL限定了四个亚像素单元。每个亚像素单元中包括薄膜晶体管TFT(作为开关元件的示例)和亚像素电极PX。在图12中，简化说明，各个亚像素单元中的公共电极未示出。薄膜晶体管TFT的源极与栅线GL相连，源极与数据线DL相连，漏极与像素电极PX相连。在图12中，薄膜晶体管TFT以其漏极示出。参见图12，右下方和左上方的亚像素单元例如还包括红色滤色器图案P1；左下方的亚像素单元例如还包括绿色滤色器图案P2；右上方亚像素单元例如还包括蓝色滤色器图案P3。红色滤色器图案P1与绿色滤色器图案P2在TFT的漏极的正上方形成有开口部H。开口部H暴露出漏极的一部分。
基于同样的发明构思，本公开实施例还提供了一种显示装置，该显示装置包括本公开实施例提供的上述阵列基板，该显示装置可以为液晶面板、液晶显示器、液晶电视、有机发光二极管(Organic Light Emitting Diode，OLED) 面板、OLED显示器、OLED电视或电子纸等显示装置。
综上所述，本公开实施例提供一种阵列基板的制造方法，包括：通过构图工艺在衬底基板上制作源极和漏极；在源极和漏极上制作若干阵列排列的彩色滤色器图案，每一彩色滤色器图案与阵列基板的亚像素单元对应，相邻两彩色滤色器图案之间邻接且无间隙；对相邻两彩色滤色器图案交界面处预设区域内的彩色滤色器图案进行曝光和显影，去除该预设区域内的彩色滤色器图案，在与漏极对应位置处暴露出部分漏极。由于该方法在源极和漏极上制作有若干阵列排列的彩色滤色器图案，相邻两彩色滤色器图案之间邻接且无间隙，因此，通过本公开实施例制作形成的彩色滤色器图案能够起到平坦作用，并且能够阻隔源极和漏极金属层和后续制作的公共电极之间的信号串扰，因此，本公开实施例能够省去现有技术的树脂层，节约成本，简化工艺流程；另外，由于本公开实施例对相邻两彩色滤色器图案交界面处预设区域内的彩色滤色器图案进行曝光和显影，去除该预设区域内的彩色滤色器图案，因此能够将不同颜色的滤色器图案分隔开，能够避免彩色滤色器图案之间的混色发生，本公开实施例将彩色滤色器图案制作在阵列基板侧，能够减小显示面板的厚度。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。
本申请要求于2016年12月28日递交的中国专利申请第201611238390.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板；
    位于所述衬底基板上的第一导电层，包括开关元件的源极；以及
    位于所述第一导电层上的彩色滤色器层，
    其中，在垂直于所述衬底基板的方向上，所述彩色滤色器层邻接所述开关元件的所述源极。
  2. 根据权利要求1所述的阵列基板，还包括：
    位于所述彩色滤色器层上的第二导电层，包括公共电极，
    其中，在垂直于所述衬底基板的方向上，所述彩色滤色器层还邻接所述公共电极。
  3. 根据权利要求2所述的阵列基板，其中，所述第一导电层还包括与所述开关元件的源极连接的数据线，所述第二导电层还包括与所述公共电极连接的公共线，所述彩色滤色器层构造为在所述数据线与所述公共线的交叉处电性隔离述数据线与所述公共线。
  4. 根据权利要求1至3中任一项所述的阵列基板，其中，
    所述彩色滤色器层包括相邻的第一滤色器图案和第二滤色器图案，以及位于所述第一滤色器图案和所述第二滤色器图案之间且贯穿所述彩色滤色器层的开口部，其中，第一滤色器图案和第二滤色器图案的颜色不同，
    所述第一导电层还包括所述开关元件的漏极，所述开口部暴露出所述漏极的一部分，
    在垂直于所述衬底基板的方向上，所述开关元件的漏极与所述第一滤色器图案和所述第二滤色器图案重合。
  5. 根据权利要求4所述的阵列基板，还包括：
    位于所述第二导电层上的钝化层；以及
    位于所述钝化层上的像素电极层，
    其中，所述钝化层中形成有过孔，所述过孔位于所述漏极的被所述开口部暴露的部分的正上方，所述像素电极层通过所述过孔与所述开关元件的漏极相连。
  6. 根据权利要求1、2、4和5中任一项所述的阵列基板，其中，所述第一导电层还包括与所述开关元件的源极连接的数据线，所述第一滤色器图案和所述第二滤色器图案的交界面的至少一部分位于所述数据线的正上方。
  7. 根据权利要求3所述的阵列基板，其中，所述第一滤色器图案和所述第二滤色器图案的交界面的至少一部分位于所述数据线的正上方。
  8. 根据权利要求1至7中任一项所述的阵列基板，其中，所述彩色滤光器层还包括与所述第一滤色器图案相邻且颜色不同的第三滤色器图案，以及与所述开关元件的栅极连接的栅线，其中，所述第一滤色器图案和所述第三滤色器图案的交界面的至少一部分位于所述栅线的正上方。
  9. 根据权利要求1至8中任一项所述的阵列基板，其中，所述彩色滤光器层的材料为光刻胶树脂。
  10. 一种显示装置，其中，包括权利要求1至9中任一项所述的阵列基板。
  11. 一种阵列基板的制造方法，包括：
    在衬底基板上形成第一导电层，该第一导电层包括开关元件的源极；以及
    在所述第一导电层上形成彩色滤色器层，
    其中，在垂直于所述衬底基板的方向上，所述彩色滤色器层邻接所述开关元件的所述源极。
  12. 根据权利要求11所述的制造方法，还包括：
    在所述彩色滤色器层上形成第二导电层，包括公共电极，
    其中，在垂直于所述衬底基板的方向上，所述彩色滤色器层还邻接所述公共电极。
  13. 根据权利要求12所述的制造方法，其中，所述第一导电层还包括与 所述开关元件的源极连接的数据线，所述第二导电层还包括与所述公共电极连接的公共线，所述彩色滤色器层构造为在所述数据线与所述公共线的交叉处电性隔离述数据线与所述公共线。
  14. 根据权利要求11至13中任一项所述的制造方法，其中，在所述第一导电层上形成彩色滤色器层包括：
    在所述第一导电层上形成颜色不同的第一滤色器图案层和第二滤色器图案层，其中第一滤色器图案层和第二滤色器图案层在交界面处彼此邻接且无间隙；以及
    去除所述第一滤色器图案层和所述第二滤色器图案层至少之一在其交界面处的一部分，以形成所述第一滤色器图案和所述第二滤色器图案层以及在位于所述第一滤色器图案和所述第二滤色器图案之间且贯穿所述彩色滤色器层的开口部，
    其中，所述第一导电层还包括所述开关元件的漏极，所述开口部暴露出所述漏极的一部分，
    在垂直于所述衬底基板的方向上，所述开关元件的漏极与所述第一滤色器图案和所述第二滤色器图案重合。
  15. 根据权利要求14所述的制造方法，还包括：
    在所述第二导电层上形成钝化层；以及
    在所述钝化层上形成像素电极层，
    其中，所述钝化层中形成有过孔，所述过孔位于所述漏极的被所述开口部暴露的部分的正上方，所述像素电极层通过所述过孔与所述开关元件的漏极相连。
  16. 根据权利要求14或15所述的制造方法，其中，所述彩色滤色器层的材料为光刻胶树脂，且通过曝光和显影执行去除所述第一滤色器图案层和所述第二滤色器图案层至少之一在其交界面处的一部分。
  17. 根据权利要求14至16中任一项所述的制造方法，其中，去除所述第一滤色器图案层和所述第二滤色器图案层至少之一在其交界面处的一部分 之后，所述制造方法还包括：
    对所述第一滤色器图案层和所述第二滤色器图案层进行烘烤。
  18. 根据权利要求11-12和14-17中任一项所述的制造方法，其中，所述第一导电层还包括与所述开关元件的源极连接的数据线，所述第一滤色器图案和所述第二滤色器图案的交界面的至少一部分位于所述数据线的正上方。
  19. 根据权利要求13所述的制造方法，其中，所述第一滤色器图案和所述第二滤色器图案的交界面的至少一部分位于所述数据线的正上方。
  20. 根据权利要求11至19中任一项所述的制造方法，其中，所述彩色滤色器层还包括与所述第一滤色器图案相邻且颜色不同的第三滤色器图案，以及与所述开关元件的栅极连接的栅线，其中，所述第一滤色器图案和所述第三滤色器图案的交界面的至少一部分位于所述栅线的正上方。
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